Cache coherency persistent memory device and method of operation

Abstract

A cache coherency persistent memory (PMEM) device and a method of operating the same are provided, in which the cache coherency PMEM device includes: an input / output (I / O) interface; a volatile memory module; the error correction module can be configured according to an I / O (Input / Output) protocol; a non-volatile memory module; and at least one processor configured to receive a storage command and data corresponding to the storage command from a host device through the I / O interface, control the volatile memory module to store the data based on the storage command, control the error correction module to encode the data to generate encoded data, and control the storage module to store the encoded data based on the encoded data. And controlling the nonvolatile storage module to store the encoded data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 543,389, filed on October 10, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to cache coherent persistent memory (PMEM) devices, and more particularly, to error correction within cache coherent PMEM devices. Background Art

[0004] A persistent memory (PMEM) device may include a device memory and a persistent backend storage device, wherein the device memory may be implemented using a volatile memory device, which may lose data when power supplied to the PMEM device is lost or interrupted, and the persistent backend storage device may be implemented using a non-volatile storage device, which maintains data when power supplied to the PMEM device is lost or interrupted. The persistence of data stored in the device memory may be achieved by dumping or flushing the data from the device memory to the persistent backend storage device.

[0005] In some PMEM designs, there may be a mismatch between the error rate of the device memory and the error rate of the persistent backend storage. In addition, there may be no error protection mechanism (e.g., error detection and correction) between the device memory and the persistent backend storage. Therefore, the overall error rate of the PMEM-based device may not be sufficient to meet the system requirements for the memory. Summary of the invention

[0006] Therefore, embodiments of the present disclosure may provide error correction capabilities between device memory and persistent backend storage included in a PMEM device, which may be sufficient to close the error rate gap between the device memory and the persistent backend storage, thereby allowing for improvement of the overall error rate of the PMEM device.

[0007] In an embodiment, a cache coherent PMEM device may include an I / O interface; a volatile memory module; an error correction module, which is configurable according to an I / O protocol; a non-volatile storage module; and at least one processor, configured to: receive a storage command and data corresponding to the storage command from a host device through the I / O interface according to a cache coherent memory protocol, based on the storage command, control the volatile memory module to store data, control the error correction module to encode the data to generate encoded data, and control the non-volatile storage module to store the encoded data.

[0008] In an embodiment, a cache coherent PMEM device may include an I / O interface; a volatile memory module; an encoder module and a decoder module, the encoder module and the decoder module being configurable according to an I / O protocol; a non-volatile memory module; and at least one processor configured to: control the volatile memory module to store data based on receiving a storage command and data corresponding to the storage command from a host device through the I / O interface according to the cache coherent memory protocol, control the encoder module to encode data to generate encoded data based on detecting at least one of a change in a power state of the cache coherent PMEM device and receiving a refresh command from the host device through the I / O interface according to the I / O protocol, and control the non-volatile memory module to store the encoded data, control the decoder module to decode the encoded data to reconstruct the data, control the volatile memory module to store the data, and provide the data to the host device through the I / O interface based on receiving a load command from the host device through the I / O interface according to the cache coherent memory protocol.

[0009] In an embodiment, a method of operating a cache coherent PMEM device may include: receiving a storage command and data corresponding to the storage command from a host device through an I / O interface according to a cache coherent memory protocol; storing the data in a volatile memory module based on the storage command; encoding the data using an error correction module to generate encoded data, wherein the encoding module is configurable according to the I / O protocol; and storing the encoded data in a non-volatile memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following sections, various aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing an example of a memory system according to an embodiment;

[0012] Figure 2 is a block diagram showing an example of a memory system according to an embodiment;

[0013] Figure 3 is a block diagram illustrating an example of a cache coherent PMEM device according to an embodiment;

[0014] Figure 4A is a block diagram illustrating an example of an error correction module according to an embodiment;

[0015] Figure 4B is a block diagram illustrating an example of an error correction module according to an embodiment;

[0016] Figure 5 is a block diagram showing an example of a nonvolatile storage module according to an embodiment;

[0017] Figure 6 is a flow chart of a process for operating a cache coherent PMEM device according to an embodiment;

[0018] Figure 7 is a flow chart of a process for operating a cache coherent PMEM device according to an embodiment;

[0019] Figure 8 is a flow chart of a process for operating a cache coherent PMEM device according to an embodiment. DETAILED DESCRIPTION

[0020] In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0021] References to "one embodiment" or "an embodiment" throughout this specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) that appear throughout this specification may not necessarily all refer to the same embodiment. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be interpreted as necessarily being preferred or advantageous over other embodiments. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, a singular term may include a corresponding plural form, and a plural term may include a corresponding singular form. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two dimensional", "pre-determined", "pixel-specific", etc.), and capitalized terms (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeable usage should not be considered inconsistent with each other.

[0022] In addition, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures (including component figures) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the size of some elements may be exaggerated relative to other elements. In addition, if deemed appropriate, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements.

[0023] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an", and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] It will be understood that when an element or layer is referred to as being on, "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or coupled to another element or layer, or there can be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] As used herein, the terms "first", "second", etc. are used as labels for the nouns that follow them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. In addition, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same across all embodiments, or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0027] As used herein, the term "module" refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the module. For example, software may be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, an assembly, hardwired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits, either alone or in any combination. Modules may be collectively or individually embodied as circuits forming part of a larger system, such as, but not limited to, an integrated circuit (IC), a system on a chip (SoC), an assembly, and the like.

[0028] A persistent memory (PMEM) device may include a device memory that may be implemented using a volatile memory device, such as a dynamic random access memory (DRAM), and a persistent backend storage device that may be implemented using a non-volatile memory device, such as a NAND flash memory device, e.g., a non-volatile memory express (NVMe) solid-state drive (SSD). Persistence of data stored in the device memory may be achieved by dumping the data from the device memory to the persistent backend storage device. In some PMEM designs, there may be a mismatch between the error rate of the device memory and the error rate of the persistent backend storage device. For example, the uncorrectable bit error rate (UBER) requirement for a consumer SSD may be 10 -15 , and the UBER requirement for enterprise SSD can be 10 -16 , while the UBER requirements of DRAM devices can be several orders of magnitude lower. In addition, there may be no error protection mechanisms (e.g., error detection and correction) between the device memory and the persistent backend storage. Therefore, based on the error rate of the persistent backend storage, the total error rate of the PMEM device may not be sufficient to meet the system requirements for the memory.

[0029] Therefore, embodiments of the present disclosure may provide error correction capabilities between a device memory and a persistent backend storage device included in a PMEM device. For example, a cyclic redundancy check (CRC) scheme may be implemented between the device memory and the persistent backend storage device to achieve comprehensive data protection. As another example, a relatively low-cost error correction code (ECC) scheme may be implemented between the device memory and the persistent backend storage device to allow correction of errors that may occur when data is transferred between the device memory and the persistent backend storage device. According to an embodiment, the error correction capability may be sufficient to close the error rate gap between the device memory and the persistent backend storage device, which may allow the overall error rate of the PMEM device to be improved.

[0030] Figure 1 is a block diagram showing an example of a memory system according to an embodiment. Figure 1As shown in , the memory system 100 may include a host device 110 , a cache coherent PMEM device 120 , and an external power module 130 that may provide power to the cache coherent PMEM device 120 .

[0031] According to an embodiment, the cache coherent PMEM device 120 may operate according to a cache coherence protocol. The cache coherence protocol may allow cache coherence to be maintained in a multi-device or multi-processor system. For example, in some systems, shared data may be stored in multiple different caches, and if the data changes in one cache but not in another cache, the data inconsistency may cause processing errors. Therefore, the cache coherence protocol may be used to maintain data coherence between caches, such as by invalidating or updating a cache based on changes made in other caches.

[0032] The Compute Express Link (CXL) standard may include an example of a cache coherent protocol. CXL may be implemented using three protocols, such as the CXL.io protocol, the CXL.cache protocol, and the CXL.mem protocol, which may be dynamically multiplexed on a peripheral component interconnect express (PCIe) physical layer. The Cx1.io protocol may be based on PCIe and may be used for device discovery, status reporting, virtual to physical address translation, and direct memory access (DMA). The CXL.io protocol may use the non-consistent load-store semantics of PCIe. The CXL.cache protocol may be used by a host device to cache system memory. The CXL.mem protocol may be an example of a cache coherent memory protocol, which may make a CXL memory device attached to a host device cacheable (which may be referred to as a host managed device memory (HDM)), similar to a host memory, resulting in a unified view of the host across HDM and host memory.

[0033] CXL can be used in various types of devices. For example, CXL Type 1 devices may include accelerators, such as intelligent network interface cards (NICs), which use coherent semantics together with PCIe-type direct memory access (DMA) transfers. Therefore, CXL Type 1 devices may only implement CXL.io and CXL.cache protocols. CXL Type 2 devices may include accelerators, such as general purpose graphics processing units (GP-GPUs) and field programmable gate arrays (FPGAs), which have local memory that can be partially mapped to cacheable system memory. These devices can also cache system memory for processing. Therefore, they implement CXL.io, CXL.cache, and CXL.mem protocols. CXL Type 3 devices can be used for memory bandwidth and capacity expansion, and can be used to connect to different memory types, including supporting multiple memory layers attached to a host device. Therefore, CXL Type 3 devices may only implement CXL.io and CXL.mem protocols. According to an embodiment, the cache coherent PMEM device 120 may correspond to a CXL Type 3 device, but the embodiment is not limited thereto.

[0034] The host device 110 may include a central processing unit (CPU) on which an operating system (OS) 111 may operate, and the application 112 may be executed on the OS 111. In addition, the cache coherent PMEM device 120 may include an input / output (I / O) interface 121, a volatile memory module 122, a non-volatile storage module 123, a processor 125, and an internal power module 124. In an embodiment, the processor 125 may control the operation of the cache coherent PMEM device 120. In an embodiment, the volatile memory module 122 may be referred to as a device memory, and the non-volatile storage module 123 may be referred to as a persistent backend storage, but the embodiment is not limited thereto.

[0035] At least one of the host device 110, the OS 111, and the application 112 may send one or more commands to the cache coherent PMEM device 120. For example, the host device 110 may send a command according to the I / O protocol to the cache coherent PMEM device 120. As another example, the host device 110 may send a storage command according to the cache coherent memory protocol to the cache coherent PMEM device 120, and based on receiving the storage command at the I / O interface 121, the processor 125 may control the volatile memory module 122 to store data corresponding to the storage command. Then, the processor 125 may control the non-volatile memory module 123 to receive the data from the volatile memory module 122 and store the data, which may be referred to as flushing or dumping the data to the non-volatile memory module 123. In some embodiments, the I / O protocol may correspond to the CXL.io protocol, and the cache coherent memory protocol may correspond to the CXL.mem protocol, but the embodiment is not limited thereto.

[0036] In an embodiment, if power is not supplied to the volatile memory module 122, data stored in the volatile memory module 122 may be lost, however, data stored in the non-volatile memory module may be maintained even if power is not supplied to the non-volatile memory module 123. Therefore, in some embodiments, data may be refreshed or dumped from the volatile memory module 122 to the non-volatile memory module 123 to ensure that the data is not lost due to a power failure. For example, based on detecting a change in the power state of the cache coherent PMEM device 120, such as an interruption or other failure of the power supplied to the cache coherent PMEM device 120 by the external power module 130, the processor 125 may control the cache coherent PMEM device 120 to use the power supplied by the internal power module 124 to refresh or dump the data from the volatile memory module 122 to the non-volatile memory module 123. As another example, the processor 125 may control the cache coherent PMEM device 120 to refresh or dump data from the volatile memory module 122 to the non-volatile memory module 123 based on the cache coherent PMEM device 120 receiving a refresh command from the host device 110. According to an embodiment, the refresh command may be received according to an I / O protocol. In some embodiments, the refresh command may be a global persistent refresh (GPF) command, but the embodiment is not limited thereto.

[0037] After being stored in the non-volatile memory module 123, the data may be returned to the volatile memory module 122, for example, after the power supplied by the external power module 130 is restored. The host device 110 may send a load command according to the cache coherent memory protocol to the cache coherent PMEM device 120, and based on receiving the load command at the I / O interface 121, the processor 125 may control the volatile memory module 122 to provide the host device 110 with data corresponding to the load command through the I / O interface 121.

[0038] In an embodiment, the volatile memory module 122 may include a random access memory (RAM) device, such as a dynamic RAM (DRAM) device. However, the embodiment is not limited thereto, and according to an embodiment, the volatile memory module 122 may include any type of volatile memory device. In an embodiment, the non-volatile memory device 123 may be a NAND memory device, such as a non-volatile memory express (NVMe) solid state drive (SSD).

[0039] As discussed above, there may be a mismatch or gap between the uncorrectable bit error rate (UBER) requirements of the device memory (e.g., volatile memory module 122) and the persistent backend storage (e.g., non-volatile storage module 123). For example, the UBER of a consumer SSD may be 10 -15 , and the UBER of enterprise SSD can be 10 -16 , while the UBER of DRAM devices can be several orders of magnitude lower. In addition, there may be no error protection mechanism (e.g., error detection and correction) between the device memory and the persistent backend storage. Therefore, based on the UBER of the persistent backend storage, the total UBER of the cache coherent PMEM device 120 may not be sufficient to meet the system requirements for the memory.

[0040] Thus, some embodiments of the present disclosure may provide error correction capabilities between device memory and persistent backend storage included in a cache coherent PMEM device.

[0041] Figure 2 is a block diagram illustrating an example of a storage system according to an embodiment. Figure 3 is a block diagram illustrating an example of a cache coherent PMEM device according to an embodiment. Figure 2As shown in , the memory system 200 may be similar to the memory system 100 discussed above. For example, the memory system 200 may include a host device 110, and the host device 110 includes an OS 111 and an application 112. In addition, a cache coherent PMEM device 220 included in the memory system 200 may include an I / O interface 121, a volatile memory module 122, a non-volatile storage module 123, a processor 125, and an internal power module 124, and the cache coherent PMEM device 220 may receive power supplied by an external power module 130. In some embodiments, the cache coherent PMEM device 220 may correspond to a CXL type 3 device, however, the embodiment is not limited thereto.

[0042] However, if Figure 2 and Figure 3 As shown in , the memory system 200 may be different from the memory system 100 in that the cache coherent PMEM device 220 may further include an error correction module 202 that may communicate with the volatile memory module 122 and the non-volatile storage module 123 .

[0043] When the cache coherent PMEM device 220 moves data from the volatile memory module 122 to the non-volatile memory module 123, for example, when the data is refreshed or dumped from the volatile memory module 122 to the non-volatile memory module 123 based on the detection of a power failure, the processor 125 may control the error correction module 202 to perform a protection process on the data before the data is stored in the non-volatile memory module 123. For example, the processor 125 may control the error correction module 202 to receive data from the volatile memory module 122 and encode the data before controlling the non-volatile memory module 123 to store the encoded data. Then, when the cache coherent PMEM device 220 moves data from the non-volatile memory module 123 to the volatile memory module 122, for example, based on the power failure being corrected, the processor 125 may control the error correction module 202 to receive data from the non-volatile memory module 123 and decode the encoded data in a manner that corrects one or more errors in the received data before controlling the volatile memory module 122 to store the decoded data. For example, the error correction module 202 can apply at least one of a cyclic redundancy check (CRC) coding and an error correction code (ECC) coding to the data to detect and correct errors. For example, the CRC coding can be used to detect errors in the data, and the ECC coding can be used to correct errors in the data, but the embodiment is not limited thereto. Examples of coding and decoding are discussed below.

[0044] In an embodiment, the error correction module 202 may be configurable according to an I / O protocol. For example, the host device 110 may receive a command according to the I / O protocol (in Figure 3 The processor 125 may send a command (shown as an “I / O command” in the figure) to the cache coherent PMEM device 220, and based on receiving the command at the I / O interface 121, the processor 125 may configure one or more parameters of the error correction module 202, for example, by using a configuration command. For example, the processor 125 may control the error correction module 202 to be enabled or disabled, or may configure one or more parameters of the error correction module 202, such as the type of encoding or decoding applied to data by the error correction module 202. An example of a configuration process is discussed below.

[0045] Therefore, according to an embodiment, the cache coherent PMEM device 220 can provide end-to-end or otherwise comprehensive protection for data, and can eliminate or reduce any error rate gap between the volatile memory module 122 (e.g., device memory) and the non-volatile memory module 123 (e.g., persistent backend storage). Therefore, the performance of the cache coherent PMEM device 220 can be improved compared to the cache coherent PMEM device 120 discussed above. For example, the overall UBER of the cache coherent PMEM device 220 can be lower than the overall UBER of the cache coherent PMEM device 120 discussed above.

[0046] Figure 4A is a block diagram showing an example of an error correction module according to an embodiment. Figure 4A As shown, the error correction module 202A may include a CRC module 410 and an ECC module 420. In an embodiment, the CRC module 410 may include a CRC encoder 411 and a CRC decoder 412, and the ECC module 420 may include an ECC encoder 421 and an ECC decoder 422. In an embodiment, the error correction module 202A may be an example of the error correction module 202 discussed above.

[0047] When the cache coherent PMEM device 220 moves data from the volatile memory module 122 to the non-volatile memory module 123, for example, when data is refreshed or dumped from the volatile memory module 122 to the non-volatile memory module 123 based on the detection of a power failure, the CRC encoder 411 may receive the data and perform CRC encoding on the received data to generate CRC-encoded data. Then, the ECC encoder 421 may receive the CRC-encoded data and may perform ECC encoding on the CRC-encoded data to generate ECC-encoded data, which may be stored in the non-volatile memory module 123. In an embodiment, the ECC-encoded data may correspond to the encoded data discussed above with respect to the error correction module 202.

[0048] Then, when the cache coherent PMEM device 220 moves data from the non-volatile memory module 123 to the volatile memory module 122, for example, based on a power failure being corrected, the ECC decoder 422 may receive the ECC-encoded data and perform ECC decoding on the ECC-encoded data to recover or reconstruct the CRC-encoded data. Then, the CRC decoder 412 may receive the CRC-encoded data and perform CRC decoding on the CRC-encoded data to recover or reconstruct the original data, which may then be stored in the volatile memory module 122.

[0049] In an embodiment, the error correction module 202A may be configurable according to an I / O protocol. For example, one or more parameters of at least one of the CRC module 410 and the ECC module 420 may be configured based on a command according to the CRC.io protocol that may be received from the host device 110 at the I / O interface 121. According to an embodiment, the configuration may include enabling or disabling at least one of the CRC module 410 and the ECC module 420, setting the type of CRC encoding and decoding performed by the CRC module 410, setting the type of CRC code or algorithm used by the CRC module 410, setting the type of ECC encoding and decoding performed by the ECC module 420, and setting the type of ECC code or algorithm used by the ECC module 420.

[0050] In an embodiment, the CRC module 410 may apply any type of CRC code or algorithm, such as at least one of CRC-32 and CRC-16, but the embodiment is not limited thereto. In an embodiment, the ECC module 420 may apply any type of ECC code or algorithm, such as at least one of a Bose-Chaudhuri-Hocquenghem (BCH) code, a Reed-Solomon (RS) code, and a polar code.

[0051] For example, a command according to the I / O protocol may include a value of a CRC option and a value of an ECC option. Based on receiving a command according to the I / O protocol at the I / O interface 121, the processor 125 may check the value of the CRC option and the value of the ECC option in the command, and may configure the error correction module 202A accordingly.

[0052] Examples of possible values ​​for the CRC option and the ECC option are provided below:

[0053] CRC option = {0: disable, 1: CRC-16, 2: CRC-32}

[0054] ECC option = {0: disable, 1: BCH}

[0055] According to the above example, based on a command according to the I / O protocol with a value of zero ('0') for the CRC option, the processor 125 may configure the CRC module 410 to be disabled. Based on a command according to the I / O protocol with a value of one ("1") for the CRC option, the processor 125 may configure the CRC module 410 to apply CRC-16 encoding and decoding. Based on a command according to the I / O protocol with a value of two '(2') for the CRC option, the processor 125 may configure the CRC module 410 to apply CRC-32 encoding and decoding.

[0056] Similarly, according to the above example, based on a command according to the I / O protocol with a value of zero ('0') for the ECC option, the processor 125 may configure the ECC module 420 to be disabled. Based on a command according to the I / O protocol with a value of one ("1") for the ECC option, the processor 125 may configure the ECC module 420 to apply BCH encoding and decoding.

[0057] However, the embodiments are not limited thereto, and any value may be used to indicate the configuration of the error correction module 202A.

[0058] According to an embodiment, the cache coherent PMEM device 220 may include reliability, availability, and service (RAS) features. In some embodiments, the RAS features may correspond to CXL RAS features, but embodiments are not limited thereto. For example, the RAS features may also provide CRC and error handling, but these RAS features may be used for link and protocol errors (e.g., link CRC checks). As discussed above, embodiments may involve protecting data transmission between device memory (e.g., volatile memory module 122) and persistent backend storage (e.g., non-volatile storage module 123), which may be orthogonal to the protection provided by the RAS features.

[0059] Figure 4B 2 is a block diagram illustrating an example of an error correction module according to an embodiment. In an embodiment, the error correction module 202B may be an example of the error correction module 202 discussed above. Figure 4B As shown, the error correction module 202B may be similar to the error correction module 202A discussed above, except that the error correction module 202B may include an encoder module 430 and a decoder module 440 instead of the CRC module 410 and the ECC module 420 discussed above. In an embodiment, the encoder module 430 may include a CRC encoder 411 and an ECC encoder 421, and the decoder module 440 may include a CRC decoder 412 and an ECC decoder 422.

[0060] According to an embodiment, the encoding and decoding operations performed by error correction module 202, and, for example, ECC encoding and decoding operations and CRC encoding and decoding operations performed by error correction modules 202A and 202B, may be performed on-the-fly and may have relatively low latency and relatively low computational cost compared to other operations of cache coherent PMEM device 220. For example, the encoding and decoding operations performed by error correction modules 202, 202A, and 202B may not add additional latency overhead to load operations and store operations performed by host device 110 and cache coherent PMEM device 220.

[0061] Figure 5 1 is a block diagram showing an example of a non-volatile storage module according to an embodiment. In an embodiment, the non-volatile storage module 123 may be or may include a NAND storage device, such as an NVMe SSD device. For example, Figure 5 As shown, the non-volatile memory module 123 may include a flash translation layer (FTL) and NAND controller 510 and a NAND module 520. In an embodiment, the FTL and NAND controller 510 may include an ECC module 511.

[0062] In an embodiment, the ECC module 511 may be used by the non-volatile memory module 123 to perform ECC encoding and decoding operations on data received and stored by the non-volatile memory module 123, which may improve the UBER of the non-volatile memory module 123. However, as discussed above, even with the ECC module 511, the UBER of the non-volatile memory module 123 may be higher than the UBER of the volatile memory module 122, and this error rate mismatch or gap may cause the overall UBER of the cache coherent PMEM device 120 to be unsatisfactory.

[0063] Therefore, by adding the error correction module 202 or, for example, the error correction module 202A or the error correction module 202B, the cache coherent PMEM device 220 can close the error rate gap between the non-volatile memory module 123 and the volatile memory module 122, and thus can improve the overall error rate of the cache coherent PMEM device 220 without making any modifications to the non-volatile memory module 123, or, for example, without making any modifications to the FTL and the NAND controller 510.

[0064] In an embodiment, the encoding and decoding operations performed by at least one of the error correction modules 202, 202A, and 202B may have relatively low complexity and computational cost compared to the ECC encoding and decoding operations performed by the ECC module 511. However, the encoding and decoding operations performed by at least one of the error correction modules 202, 202A, and 202B may still be sufficient to reduce or eliminate the error rate gap between the non-volatile storage module 123 and the volatile memory module 122, and thus may improve the overall error rate of the cache coherent PMEM device 220 without adding additional latency to other operations performed by the cache coherent PMEM device 220.

[0065] Figure 6 is a flow chart of a process for operating a cache coherent PMEM device according to an embodiment. In some embodiments, Figure 6 One or more process blocks of may be performed by one or more of the elements discussed above (eg, cache coherent PMEM device 220 and one or more of the elements included therein).

[0066] like Figure 6 As shown, process 600 may include receiving a storage command and data corresponding to the storage command from a host device through an I / O interface according to a cache coherent memory protocol (operation 601). In an embodiment, the host device may correspond to the host device 110 discussed above. In an embodiment, the I / O interface may correspond to the I / O interface 121 discussed above.

[0067] like Figure 6 As further shown in FIG. 6 , process 600 may include storing data in a volatile memory module based on a storage command (operation 602). In an embodiment, the volatile memory module may correspond to the volatile memory module 122 discussed above. For example, the volatile memory module may be used to implement a device memory of a cache coherent PMEM device and may include a DRAM device.

[0068] like Figure 6 As further shown in , process 600 may include encoding the data using an error correction module to generate encoded data, wherein the encoding module is configurable according to the I / O protocol (operation 603). In an embodiment, the error correction module may correspond to at least one of the error correction modules 202, 202A, and 202B discussed above. In an embodiment, the encoding of the data may provide error protection when the data is transferred between the volatile memory device and the non-volatile memory device. For example, the encoding of the data may allow detection and correction of errors that may occur in the data when the data is transferred between the volatile memory device and the non-volatile memory device.

[0069] like Figure 6 As further shown in , process 600 may include storing the encoded data in a non-volatile storage module (operation 604). In an embodiment, the non-volatile storage module may correspond to the non-volatile storage module 123 discussed above. For example, the non-volatile storage module may be used to implement a persistent backend storage device of a cache-coherent PMEM device and may include a NAND device, such as an NVMe SSD.

[0070] In an embodiment, when a power failure occurs, the volatile memory module may not be able to maintain data, however, the non-volatile memory module is able to maintain data even during a power failure. Therefore, in some embodiments, operations 603 and 604 may be used to refresh or dump data from the volatile memory module to the non-volatile memory module. Therefore, in some embodiments, operations 603 and 604 may be performed to ensure the persistence of data stored in the volatile memory module, for example, based on detecting a change in the power state corresponding to the cache coherent PMEM device (e.g., a power failure), or based on receiving a refresh command from a host device through an I / O interface (e.g., according to an I / O protocol).

[0071] Figure 7 is a flow chart of a process for operating a cache coherent PMEM device according to an embodiment. In some embodiments, Figure 7 One or more process blocks of may be performed by one or more of the elements discussed above (eg, cache coherent PMEM device 220 and one or more of the elements included therein).

[0072] like Figure 7 As shown, process 700 may include obtaining encoded data from a non-volatile storage module (operation 701).

[0073] like Figure 7 As further shown in , process 700 may include decoding the encoded data using an error correction module (operation 702). In an embodiment, based on the detected errors, decoding of the data may include reconstructing or restoring the original data.

[0074] like Figure 7 As further shown in FIG. 7 , process 700 may include storing data in a volatile memory module (operation 703 ).

[0075] like Figure 7 As further shown in FIG. 7 , process 700 may include receiving a load command corresponding to data from a host device through an I / O interface according to a cache coherent memory protocol (operation 704 ).

[0076] like Figure 7As further shown in FIG. 7 , process 700 may include providing data to a host device via an I / O interface based on the load command (operation 705 ).

[0077] Figure 8 is a flow chart of a process for operating a cache coherent PMEM device according to an embodiment. In some embodiments, Figure 8 One or more process blocks of may be performed by one or more of the elements discussed above (eg, cache coherent PMEM device 220 and one or more of the elements included therein).

[0078] like Figure 8 As shown, process 800 may include receiving a configuration command according to an I / O protocol from a host device through an I / O interface (operation 801). In an embodiment, the configuration command may include values ​​indicating parameters of the error correction module discussed above.

[0079] like Figure 8 As further shown in FIG. 8 , process 800 may include performing a configuration process on an error correction module (operation 802). In an embodiment, the configuration process may include configuring the error correction module. For example, the configuration process may include enabling the error correction module, disabling the error correction module, and setting at least one of the types of error correction encoding and decoding applied by the error correction module.

[0080] although Figure 6 , Figure 7 and Figure 8 Example blocks of processes 600, 700, and 800 are shown, but in some implementations, processes 600, 700, and 800 may include Figure 6 , Figure 7 and Figure 8 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in. Additionally or alternatively, two or more of the blocks of processes 600, 700, and 800 may be performed in parallel.

[0081] Thus, an embodiment may provide a cache-coherent PMEM device, which may include an error correction module that may perform error correction on data transmitted between a device memory included in the cache-coherent PMEM device and a persistent backend storage device. For example, a CRC scheme may be applied to data transmitted between the device memory and the persistent backend storage device to achieve comprehensive data protection. As another example, a relatively low-cost ECC scheme (such as at least one of a BCH code, an RS code, and a polar code) may be applied to data transmitted between the device memory and the persistent backend storage device. Thus, an embodiment may allow the error rate gap between the device memory and the persistent backend storage device to be reduced or eliminated, and may therefore allow the overall error rate of the cache-coherent PMEM device to be improved.

[0082] Although some embodiments are described above as involving cache-coherent PMEM devices, the embodiments are not limited thereto. For example, embodiments may be used in any device in which a volatile memory device (e.g., a DRAM device) is connected to a non-volatile storage device (e.g., a NAND flash device, such as an NVMe SSD device). For example, at least one of the error correction modules 202, 202A, and 202B may be included in other devices, such as dual-mode CXL-SSD devices and other cache-coherent storage devices.

[0083] The embodiments and operations of the subject matter described in this specification may be implemented in digital electronic circuits, or in computer software, firmware or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, that is, one or more modules of computer program instructions, which are encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or may be included therein. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. The computer storage medium may also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). In addition, the operations described in this specification may be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0084] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as limiting the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may be cut out of the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0085] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0086] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0087] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied over a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

Claims

1. A cache coherent persistent memory (PMEM) device, comprising: Input / output I / O interface; Volatile memory module; an error correction module, the error correction module being configurable according to an I / O protocol; Non-volatile storage module; as well as At least one processor configured to: receiving a storage command and data corresponding to the storage command from a host device through the I / O interface according to a cache coherent memory protocol, Based on the storage command, controlling the volatile memory module to store the data, encoding the data using the error correction module to generate encoded data, and The nonvolatile storage module is controlled to store the encoded data.

2. The cache coherent PMEM device of claim 1, wherein: The at least one processor is further configured to: Obtaining the encoded data from the non-volatile storage module; controlling the error correction module to decode the encoded data to reconstruct the data; controlling the volatile memory module to store the data; receiving a load command corresponding to the data from the host device through the I / O interface according to the cache coherent memory protocol; as well as Based on the load command, the data is provided to the host device through the I / O interface.

3. The cache coherent PMEM device of claim 1 , wherein: The volatile memory module includes a dynamic random access memory DRAM device, and Wherein, the non-volatile storage module includes a non-volatile memory fast NVMe solid-state drive SSD.

4. The cache coherent PMEM device of claim 1, wherein: The error rate of the volatile memory module is lower than the error rate of the non-volatile memory module, and Wherein, an error rate of the cache coherent PMEM device is higher than the error rate of the volatile memory module.

5. The cache coherent PMEM device of claim 1 , wherein: The error correction module comprises: a cyclic redundancy check (CRC) encoder configured to perform CRC encoding on the data based on a CRC code to generate CRC-encoded data; Wherein, the encoded data is generated based on the CRC encoded data.

6. The cache coherent PMEM device of claim 1, wherein: The error correction module comprises: an error correction code (ECC) encoder configured to perform ECC encoding on the data based on an ECC code to generate ECC-encoded data, Wherein, the encoded data includes the ECC encoded data.

7. The cache coherent PMEM device of claim 1, wherein: Based on receiving a configuration command according to the I / O protocol from the host device through the I / O interface, the at least one processor is further configured to perform a configuration process on at least one of a cyclic redundancy check CRC module and an error correction code ECC module included in the error correction module.

8. The cache coherent PMEM device of claim 1, wherein: Based on receiving a configuration command according to the I / O protocol from the host device through the I / O interface, the at least one processor is further configured to perform at least one of the following: enabling at least one of a cyclic redundancy check CRC module and an error correction code ECC module included in the error correction module, setting a type of CRC code corresponding to the CRC module, and setting a type of ECC code corresponding to the ECC module.

9. The cache coherent PMEM device of claim 1, wherein: The at least one processor is further configured to control the error correction module to encode the data and control the non-volatile memory module to store the encoded data based on at least one of detecting a change in a power state of the cache coherent PMEM device and receiving a refresh command from the host device through the I / O interface.

10. A cache coherent persistent memory (PMEM) device, comprising: Input / output I / O interface; Volatile memory module; An encoder module and a decoder module, the encoder module and the decoder module being configurable according to an I / O protocol; Non-volatile storage module; as well as At least one processor configured to: controlling the volatile memory module to store the data based on receiving a storage command and data corresponding to the storage command from a host device through the I / O interface according to a cache coherent memory protocol, controlling the encoder module to encode the data to generate encoded data, and controlling the non-volatile memory module to store the encoded data based on at least one of detecting a change in the power state of the cache coherent PMEM device and receiving a refresh command from the host device through the I / O interface according to the I / O protocol, controlling the decoder module to decode the encoded data to reconstruct the data, controlling the volatile memory module to store the data, and Based on receiving a load command from the host device through the I / O interface according to the cache coherent memory protocol, the data is provided to the host device through the I / O interface.

11. The cache coherent PMEM device of claim 10, wherein: The volatile memory module includes a dynamic random access memory DRAM device, and Wherein, the non-volatile storage module includes a non-volatile memory fast NVMe solid-state drive SSD.

12. The cache coherent PMEM device of claim 10, wherein: The error rate of the volatile memory module is lower than the error rate of the non-volatile memory module, and Wherein, an error rate of the cache coherent PMEM device is higher than the error rate of the volatile memory module.

13. The cache coherent PMEM device according to claim 10, in, The encoder module comprises: a cyclic redundancy check (CRC) encoder configured to perform CRC encoding on the data based on a CRC code to generate CRC-encoded data, wherein the encoded data is generated based on the CRC-encoded data; and Wherein, the decoder module comprises: A CRC decoder is configured to perform CRC decoding on the CRC-encoded data based on the CRC code to obtain the data.

14. The cache coherent PMEM device of claim 10, wherein: The encoder module comprises: an error correction code (ECC) encoder configured to perform ECC encoding on the data based on an ECC code to generate ECC-encoded data, wherein the encoded data includes the ECC-encoded data, and Wherein, the decoder module comprises: The ECC decoder is configured to perform ECC decoding on the ECC-encoded data based on the ECC code to obtain the data.

15. The cache coherent PMEM device of claim 10, wherein: Based on receiving a configuration command according to the I / O protocol from the host device through the I / O interface, the at least one processor is further configured to perform a configuration process on at least one of a cyclic redundancy check CRC module and an error correction code ECC module included in at least one of the encoder module and the decoder module.

16. The cache coherent PMEM device of claim 10, wherein: Based on receiving a configuration command according to the I / O protocol from the host device through the I / O interface, the at least one processor is further configured to perform at least one of the following: enabling at least one of a cyclic redundancy check (CRC) module and an error correction code (ECC) module included in at least one of the encoder module and the decoder module, Setting the type of CRC code corresponding to the CRC module, and Set the type of ECC code corresponding to the ECC module.

17. A method of operating a persistent memory (PMEM) device, the method comprising: receiving a storage command and data corresponding to the storage command from a host device through an input / output (I / O) interface according to a cache coherent memory protocol; Based on the storage command, storing the data in a volatile memory module; encoding the data using an error correction module to generate encoded data, wherein the error correction module is configurable according to an I / O protocol; and The encoded data is stored in a non-volatile storage module.

18. The method according to claim 17, further comprising: Obtaining the encoded data from the non-volatile storage module; decoding the encoded data using the error correction module; storing the data in the volatile memory module; as well as receiving a load command corresponding to the data from the host device through the I / O interface according to the cache coherent memory protocol; Based on the load command, the data is provided to the host device through the I / O interface.

19. The method according to claim 17, wherein: The volatile memory module includes a dynamic random access memory DRAM device, and Wherein, the non-volatile storage module includes a non-volatile memory fast NVMe solid-state drive SSD.

20. The method of claim 17, further comprising: receiving a configuration command according to the I / O protocol from the host device via the I / O interface; as well as A configuration process is performed on at least one of a cyclic redundancy check CRC module and an error correction code ECC module included in the error correction module.

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