Program update method and system for Nor Flash chip including code protection area

Abstract

The present invention discloses a program update method for a Nor Flash chip including a code protection area, which includes obtaining a program update file, erasure configuration information of the current update, storage information of the Nor Flash chip, and configuration information of a first storage area when a program update instruction is received; setting an erasure method for a second storage area according to the erasure configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, and performing an erasure operation on the second storage area according to the erasure method; and after the erasure operation is completed, writing the program update file into the erased rows of the second storage area row by row. According to the erasure configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, the present invention automatically selects a method of erasing row by row or block by block for erasure, which not only optimizes the usage efficiency of the second storage area, the update time and times of the program, but also reduces the interference to the program in the first storage area and reduces the risk of the program in the first storage area.

Description

Technical Field

[0001] The present invention relates to the technical field of Nor Flash memory chips, and particularly to a program update method, system, device and computer-readable storage medium for a Nor Flash chip including a code protection area. Background Art

[0002] In chip products including Nor Flash, Nor Flash is used to store the executable programs of customers. Customers usually have confidentiality requirements for the programs and do not want the developed code to be read by others. Some chip users are software and solution developers (hereinafter referred to as customer A), rather than end customers. They develop some software libraries and then provide secondary software development for end customers (hereinafter referred to as customer B). The software developed by customer A is expected to support customer B's use, that is, to support customer B in executing the software code developed by customer A, but customer A does not want customer B to be able to directly view (read) the code content developed by customer A. This is usually referred to as a Nor Flash chip including a code protection area.

[0003] For a Nor Flash chip including a code protection area, usually after customer A develops the software library program, the chip and customer A's software library program are packaged together and given to customer B for secondary development. At this time, the program of customer A does not change, and when customer B develops its own program, it will frequently perform erase operations on the Nor Flash in the B program area.

[0004] According to the characteristics of Nor Flash, if customer B needs to modify and update the program, generally, the original data needs to be erased line by line first, and then new data is written. In the case of a large Nor Flash capacity and a large customer B program area, the update time will be very long. At the same time, according to the characteristics of Nor Flash, if customer B frequently erases and writes the program area, it will cause slight disturbance to the program of customer A stored in the code protection area. When the number of erase and write operations is too large, it will damage the software library program of customer A stored in the code protection area.

[0005] Based on this, a new solution is needed. Summary of the Invention

[0006] The main purpose of the present invention is to provide a program update method and system for a Nor Flash chip including a code protection area, aiming at the problems of long update time and the risk of damaging the program in the code protection area existing in the existing program update method for Nor Flash chips including a code protection area.

[0007] To achieve the above object, the present invention provides a program update method for a Nor Flash chip including a code protection area. The Nor Flash chip includes a first storage area and a second storage area, and the first storage area is used to store the code to be protected, including the following steps:

[0008] When receiving a program update instruction, obtain the program update file, the erase configuration information of this update, the storage information of the Nor Flash chip, and the configuration information of the first storage area. The configuration information includes the start storage address and the end storage address of the first storage area;

[0009] According to the erase configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, set the erase method of the second storage area and perform an erase operation on the second storage area according to the erase method; and

[0010] After the erase operation is completed, write the program update file into the erased rows of the second storage area row by row.

[0011] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, setting the erase method of the second storage area and performing an erase operation on the second storage area according to the erase method according to the erase configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area includes:

[0012] According to the storage information of the Nor Flash chip and the configuration information of the first storage area, judge the positional relationship between the first storage area and the second storage area. Among them, when the start storage address of the first storage area is 0, it is determined that the first storage area is above the second storage area; when the end storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is above the first storage area; otherwise, it is determined that the first storage area is in the middle of the second storage area;

[0013] Divide the Nor Flash chip into N erase blocks according to the erase configuration information;

[0014] According to the positional relationship, set the erase method of the second storage area and perform an erase operation on the second storage area according to the erase method.

[0015] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located above the second storage area, according to the positional relationship, the steps of setting the erasing method of the second storage area and performing an erasing operation on the second storage area according to the erasing method include:

[0016] Search for the erasing block to which the end storage address of the first storage area belongs among the N erasing blocks;

[0017] Start performing an erasing operation on the second storage area, wherein, perform a row-by-row erasing operation on the storage rows belonging to the second storage area in the erasing block to which the end storage address of the first storage area belongs, and perform a block-by-block erasing operation on the remaining erasing blocks of the second storage area.

[0018] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located below the second storage area, according to the positional relationship, the steps of setting the erasing method of the second storage area and performing an erasing operation on the second storage area according to the erasing method include:

[0019] Search for the erasing block to which the start storage address of the first storage area belongs among the N erasing blocks;

[0020] Start performing a block-by-block erasing operation on the second storage area, and when reaching the erasing block to which the start storage address of the first storage area belongs, perform a row-by-row erasing operation on the storage rows belonging to the second storage area in the erasing block to which the start storage address of the first storage area belongs.

[0021] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located in the middle of the second storage area, according to the positional relationship, the steps of setting the erasing method of the second storage area and performing an erasing operation on the second storage area according to the erasing method include:

[0022] Search for the erasing block to which the start storage address of the first storage area belongs and the erasing block to which the end storage address of the first storage area belongs among the N erasing blocks;

[0023] Start performing a block-by-block erase operation on the second storage area. When the erase block where the start storage address of the first storage area is located is reached, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block where the start storage address of the first storage area is located. When the erase block where the end storage address of the first storage area is located is reached, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block where the end storage address of the first storage area is located. Perform a block-by-block erase operation on the remaining erase blocks of the second storage area.

[0024] According to another aspect of the present invention, there is also provided a program update system for a Nor Flash chip including a code protection area. The Nor Flash chip includes a first storage area and a second storage area. The first storage area is used to store code that needs to be protected, and includes:

[0025] An acquisition module, configured to acquire a program update file, erase configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area when receiving a program update instruction. The configuration information includes the start storage address and end storage address of the first storage area;

[0026] An erase module, configured to set the erase method of the second storage area according to the erase configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, and perform an erase operation on the second storage area according to the erase method; and

[0027] An update module, configured to write the program update file into the erased rows of the second storage area row by row after the erase operation is completed.

[0028] In the program update system for a Nor Flash chip including a code protection area provided by the present invention, the erase module includes:

[0029] A position relationship determination unit, configured to determine the position relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area. Wherein, when the start storage address of the first storage area is 0, it is determined that the first storage area is located above the second storage area. When the end storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is located above the first storage area. Otherwise, it is determined that the first storage area is located in the middle of the second storage area;

[0030] A division unit, configured to divide the Nor Flash chip into N erase blocks according to the erase configuration information;

[0031] An execution unit, configured to set an erasure mode of the second storage area according to the position relationship and perform an erasure operation on the second storage area according to the erasure mode.

[0032] In the program update system for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located above the second storage area, the execution unit is configured to find the erasure block to which the end storage address of the first storage area belongs among the N erasure blocks, and start performing an erasure operation on the second storage area, where a row-by-row erasure operation is performed on the storage rows belonging to the second storage area in the erasure block to which the end storage address of the first storage area belongs, and a block-by-block erasure operation is performed on the remaining erasure blocks of the second storage area;

[0033] When the first storage area is located below the second storage area, the execution unit is configured to find the erasure block to which the start storage address of the first storage area belongs among the N erasure blocks, start performing a block-by-block erasure operation on the second storage area, and when reaching the erasure block to which the start storage address of the first storage area belongs, perform a row-by-row erasure operation on the storage rows belonging to the second storage area in the erasure block to which the start storage address of the first storage area belongs;

[0034] When the first storage area is located in the middle of the second storage area, the execution unit is configured to find the erasure block to which the start storage address of the first storage area belongs and the erasure block to which the end storage address of the first storage area belongs among the N erasure blocks, start performing a block-by-block erasure operation on the second storage area, where when reaching the erasure block to which the start storage address of the first storage area belongs, perform a row-by-row erasure operation on the storage rows belonging to the second storage area in the erasure block to which the start storage address of the first storage area belongs, when reaching the erasure block to which the end storage address of the first storage area belongs, perform a row-by-row erasure operation on the storage rows belonging to the second storage area in the erasure block to which the end storage address of the first storage area belongs, and perform a block-by-block erasure operation on the remaining erasure blocks of the second storage area.

[0035] The present invention further provides a program update device for a Nor Flash chip including a code protection area, including a processor and a memory, where the memory stores a computer program, and when the computer program is executed by the processor, the steps of the program update method for a Nor Flash chip including a code protection area as described above are implemented.

[0036] The program update system and method for a Nor Flash chip including a code protection area provided by the present invention have the following beneficial effects: According to the erasure configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, the present invention automatically selects the method of erasing line by line or block by block, which not only optimizes the usage efficiency of the second storage area, the update time and frequency of the program, but also reduces the interference to the program in the first storage area and reduces the risk of the program in the first storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings:

[0038] Figure 1 Shown is a partition schematic diagram of a Nor Flash chip including a code protection area applied by the present invention;

[0039] Figure 2 Shown is a flowchart of a program update method for a Nor Flash chip including a code protection area provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] For the convenience of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. The typical embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0042] Figure 1 Shown is a partition schematic diagram of a Nor Flash chip including a code protection area applied by the present invention. As Figure 1 shown, the Nor Flash chip includes a first storage area for storing the program of customer A and a second storage area for storing the program of customer B. The program of customer A is the code that needs to be protected when performing program update.

[0043] Figure 2The following is a flowchart of a program update method for a Nor Flash chip including a code protection area provided by an embodiment of the present invention. As Figure 2 shown, the program update method for the Nor Flash chip including the code protection area includes the following steps:

[0044] Step S1: When receiving a program update instruction, obtain a program update file, erasure configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area, where the configuration information includes the start storage address and end storage address of the first storage area;

[0045] Specifically, in an embodiment of the present invention, when receiving a program update instruction from a processor, obtain the program update file, erasure configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area. Among them, the program update file refers to a file containing new program code, which is usually a binary file. The erasure configuration information for this update refers to the size of the erasure block during this update, that is, the number of rows included in each erasure block. For example, 8 means that when performing block erasure, 8 rows of data are erased at a time. The storage information of the Nor Flash chip refers to the maximum storage address of the Nor Flash chip. For example, Figure 1 the Nor Flash chip in Figure 1 includes a storage area of n rows, and its maximum storage address is n. The configuration information of the first storage area refers to the start storage address and end storage address of the first storage area. For example,

[0046] the start storage address of the first storage area of the Nor Flash chip in

[0047] is 0, and the end storage address is x, that is, the second storage area starts from the (x + 1)-th row. Figure 1In the illustrated example, the program of Customer B can only start using from block2, and a part of the space in block1 cannot be used. Therefore, step S2 includes:

[0048] Step S21: Determine the positional relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area.

[0049] Specifically, in an embodiment of the present invention, the positional relationship between the first storage area and the second storage area is determined by the maximum storage address of the Nor Flash chip, the starting storage address and the ending storage address of the first storage area. That is, when the starting storage address of the first storage area is 0, it is determined that the first storage area is above the second storage area; when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is above the first storage area; otherwise, it is determined that the first storage area is in the middle of the second storage area.

[0050] Step S22: Divide the Nor Flash chip into N erasable blocks according to the erasing configuration information;

[0051] Step S23: Set the erasing method of the second storage area according to the positional relationship and perform an erasing operation on the second storage area according to the erasing method.

[0052] Further, in an embodiment of the present invention, when the first storage area is above the second storage area, only the erasable block where the ending position of the first storage area is located may have an intersection with the erasable block where the starting position of the second storage area is located. That is, in Figure 1 In the illustrated example, the last row of the first storage area where the program of Customer A is located and the first m-1 rows of the second storage area where the program of Customer B is located are divided into block1 together. Perform a row-by-row erasing operation on the first m-1 rows of the second storage area where the program of Customer B is located, and perform a block-by-block erasing operation on the remaining erasable blocks of the second storage area. Therefore, step S23 includes:

[0053] Search for the erasable block to which the ending storage address of the first storage area belongs among the N erasable blocks;

[0054] Start performing an erasing operation on the second storage area, where a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erasable block to which the ending storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erasable blocks of the second storage area.

[0055] Further, in an embodiment of the present invention, when the first storage area is located below the second storage area, only the erase block where the start position of the first storage area is located may intersect with the erase block where the end position of the second storage area is located, that is, the first few rows of the first storage area where the customer A program is located and the last few rows of the second storage area where the customer B program is located are divided into the same erase block. For example, for the erase block block i, perform a block-by-block erase operation on the first i - 1 erase blocks, and perform a row-by-row erase operation on the rows belonging to the second storage area in the i-th erase block. Therefore, step S23 includes:

[0056] Search for the erase block to which the start storage address of the first storage area belongs among the N erase blocks;

[0057] Start performing a block-by-block erase operation on the second storage area. When reaching the erase block to which the start storage address of the first storage area belongs, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs.

[0058] Further, in an embodiment of the present invention, when the first storage area is located in the middle of the second storage area, the erase block where the start position of the first storage area is located may intersect with the erase block where the end position of the second storage area is located, and the erase block where the end position of the first storage area is located may intersect with the erase block where the start position of the second storage area is located. That is, the first few rows of the first storage area where the customer A program is located and the last few rows of the first part of the second storage area where the customer B program is located are divided into the same erase block (for example, erase block block i), and the last few rows of the first storage area where the customer A program is located and the first few rows of the second part of the second storage area where the customer B program is located are divided into the same erase block (for example, erase block block j). Perform a block-by-block erase operation on the first i - 1 erase blocks, perform a row-by-row erase operation on the rows belonging to the second storage area in the i-th erase block and the rows belonging to the second storage area in the j-th erase block, and perform a block-by-block erase operation on the j + 1-th to N-th erase blocks. Step S23 includes:

[0059] Search for the erase block to which the start storage address of the first storage area belongs and the erase block to which the end storage address of the first storage area belongs among the N erase blocks;

[0060] Start performing a block-by-block erase operation on the second storage area. When the erase block where the start storage address of the first storage area is located is reached during the execution, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block where the start storage address of the first storage area is located. When the erase block where the end storage address of the first storage area is located is reached during the execution, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block where the end storage address of the first storage area is located. Perform a block-by-block erase operation on the remaining erase blocks of the second storage area.

[0061] In this embodiment, through the start storage address and / or the end storage address of the first storage area, and it can be known in which erase block this address is located; when updating the program of customer B in the second storage area, it is necessary to first erase the program of customer B. By default, the block-by-block erase method is used. When the start storage address and / or the end storage address are encountered, it is automatically changed to the row-by-row erase method. After completing the erase of the erase block containing the start storage address and / or the end storage address of the program of customer A, it is automatically changed back to the block-by-block erase until the end.

[0062] For example, assume that each block of Nor Flash has 8 rows and the program of customer B has a total of 300 rows; if the row-by-row erase is used and the erase time for each row and each block is 2ms (Nor Flash characteristic, the erase time for row and block is the same), then the erase time required is 300 x 2 = 600ms; if the erase method of automatically selecting row or block is used, then the erase time can be optimized as follows:

[0063] 300 = 37 blocks x 8 + 4 rows

[0064] 37 x 2ms + 4 x 2ms = 82ms

[0065] Only 82ms is required to complete the erase, which is much shorter compared to 600ms.

[0066] At the same time, the number of erase times of the flash is also reduced a lot, from 300 times to 4 + 37 = 41 times. The reduction of the erase times improves the service life of the chip and the reliability of the data.

[0067] Step S3, after the erase operation is completed, write the program update file into the erased rows of the second storage area row by row.

[0068] The present invention adopts an automatic switching method of block-by-block erasure and row-by-row erasure. By mixing block-by-block erasure and row-by-row erasure, compared with completely erasing all rows row by row, the erasure time can be significantly shortened, and the number of erasure times can also be greatly reduced. By reducing the erasure time and the number of erasure times, not only the update efficiency is improved, but also the service life of the Flash chip is effectively extended, thereby improving the durability and data reliability of the chip. According to the positional relationship of the storage areas and the division of the erasure blocks, the erasure method (row by row or block by block) is flexibly selected to maximize the use of the storage space of the Nor Flash chip and optimize the performance. By finely controlling the erasure operation, unnecessary erasure operations are reduced, and the security and stability of the data are improved.

[0069] Correspondingly, the present invention also provides a program update system for a Nor Flash chip including a code protection area. The Nor Flash chip includes a first storage area and a second storage area. The first storage area is used to store the code that needs to be protected, and includes: an acquisition module, configured to acquire a program update file, erasure configuration information of the current update, storage information of the Nor Flash chip, and configuration information of the first storage area when receiving a program update instruction, where the configuration information includes the start storage address and the end storage address of the first storage area; an erasure module, configured to set the erasure method of the second storage area according to the erasure configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, and perform an erasure operation on the second storage area according to the erasure method; and an update module, configured to write the program update file row by row into the erased rows of the second storage area after the erasure operation is completed.

[0070] Further, in an embodiment of the present invention, the erasure module includes: a positional relationship determination unit, configured to determine the positional relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area. Wherein, when the start storage address of the first storage area is 0, it is determined that the first storage area is above the second storage area; when the end storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is above the first storage area; otherwise, it is determined that the first storage area is in the middle of the second storage area; a division unit, configured to divide the Nor Flash chip into N erasure blocks according to the erasure configuration information; an execution unit, configured to set the erasure method of the second storage area according to the positional relationship and perform an erasure operation on the second storage area according to the erasure method.

[0071] Further, in an embodiment of the present invention, when the first storage area is located above the second storage area, the execution unit is configured to find the erasure block to which the end storage address of the first storage area belongs among the N erasure blocks, and start an erasure operation in the second storage area. Among them, a row-by-row erasure operation is performed on the storage rows belonging to the second storage area in the erasure block to which the end storage address of the first storage area belongs, and a block-by-block erasure operation is performed on the remaining erasure blocks of the second storage area. When the first storage area is located below the second storage area, the execution unit is configured to find the erasure block to which the start storage address of the first storage area belongs among the N erasure blocks, start a block-by-block erasure operation in the second storage area, and when reaching the erasure block to which the start storage address of the first storage area belongs, perform a row-by-row erasure operation on the storage rows belonging to the second storage area in the erasure block to which the start storage address of the first storage area belongs. When the first storage area is located in the middle of the second storage area, the execution unit is configured to find the erasure block to which the start storage address of the first storage area belongs and the erasure block to which the end storage address of the first storage area belongs among the N erasure blocks, start a block-by-block erasure operation in the second storage area. Among them, when reaching the erasure block to which the start storage address of the first storage area belongs, perform a row-by-row erasure operation on the storage rows belonging to the second storage area in the erasure block to which the start storage address of the first storage area belongs, when reaching the erasure block to which the end storage address of the first storage area belongs, perform a row-by-row erasure operation on the storage rows belonging to the second storage area in the erasure block to which the end storage address of the first storage area belongs, and perform a block-by-block erasure operation on the remaining erasure blocks of the second storage area.

[0072] An embodiment of the present invention further provides a program update device for a Nor Flash chip including a code protection area, which may include:

[0073] A memory for storing a computer program;

[0074] A processor, when executing the computer program stored in the above-mentioned memory, can implement the following steps:

[0075] When receiving a program update instruction, obtain a program update file, erasure configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area. The configuration information includes the start storage address and end storage address of the first storage area; set the erasure method of the second storage area according to the erasure configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, and perform an erasure operation in the second storage area according to the erasure method; and after the erasure operation is completed, write the program update file into the erased rows of the second storage area row by row.

[0076] An embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps can be implemented;

[0077] When a program update instruction is received, obtain a program update file, erasure configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area. The configuration information includes the starting storage address and the ending storage address of the first storage area; according to the erasure configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, set the erasure method of the second storage area and perform an erasure operation on the second storage area according to the erasure method; and after the erasure operation is completed, write the program update file into the erased rows of the second storage area row by row.

[0078] The computer-readable storage medium may include: various media such as a USB flash drive, a portable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0079] In the specification provided here, a large number of specific details are described. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0080] Similarly, it should be understood that, in order to streamline this disclosure and assist in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting the intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0081] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0082] In addition, those skilled in the art can understand that although some of the embodiments herein include certain features included in other embodiments rather than other features, the combination of the features of different embodiments means that it is within the scope of the present invention and forms different embodiments. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

[0083] Each component embodiment of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components according to the embodiments of the present invention. The present invention can also be implemented as a device or device program (for example, a computer program and a computer program product) for executing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0084] It should be noted that the above embodiments are illustrative of the present invention and not restrictive thereof, and alternative embodiments can be designed by those skilled in the art without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

Claims

1. A program update method for a Nor Flash chip including a code protection area, wherein the Nor Flash chip includes a first storage area and a second storage area, wherein the first storage area is used to store code to be protected, characterized in that: The following steps are involved: Upon receiving a program update instruction, obtaining a program update file, erase configuration information for this update, storage information of the NorFlash chip, and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; According to the erasure configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, setting an erasure mode of the second storage area and performing an erasure operation in the second storage area according to the erasure mode; as well as After the erasing operation is completed, writing the program update file row by row into the erased row of the second storage area; According to the erase configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, setting an erase mode of the second storage area and performing an erase operation in the second storage area according to the erase mode includes: According to the storage information of the Nor Flash chip and the configuration information of the first storage area, determining the positional relationship between the first storage area and the second storage area, wherein when the starting storage address of the first storage area is 0, determining that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the NorFlash chip, determining that the second storage area is located above the first storage area, otherwise, determining that the first storage area is located in the middle of the second storage area; Dividing the Nor Flash chip into N erase blocks according to the erase configuration information; When the first storage area is located above the second storage area: searching the erase block to which the end storage address of the first storage area belongs in the N erase blocks; starting to perform an erase operation in the second storage area, wherein a row-by-row erase operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks in the second storage area; When the first storage area is located below the second storage area: searching the erase block to which the start storage address of the first storage area belongs in the N erase blocks; starting to perform a block-by-block erase operation in the second storage area, when the erase block to which the start storage address of the first storage area belongs is executed, performing a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs; When the first storage area is located in the middle of the second storage area: search the erase block to which the start storage address of the first storage area belongs and the erase block to which the end storage address of the first storage area belongs in the N erase blocks; start to perform a block-by-block erasing operation in the second storage area, wherein, when executing to the erase block to which the start storage address of the first storage area belongs, perform a row-by-row erasing operation on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs, and when executing to the erase block to which the end storage address of the first storage area belongs, perform a row-by-row erasing operation on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and perform a block-by-block erasing operation on the remaining erase blocks in the second storage area.

2. A program update system for a Nor Flash chip including a code protection area, wherein the Nor Flash chip includes a first storage area and a second storage area, wherein the first storage area is used to store code to be protected, wherein: include: an acquisition module, configured to acquire, upon receiving a program update instruction, a program update file, erase configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; An erasing module, configured to set an erasing mode of the second storage area according to the erasing configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, and perform an erasing operation in the second storage area according to the erasing mode; as well as An updating module, configured to write the program update file into the erased row of the second storage area row by row after the erasing operation is completed; The erasing module comprises: a position relationship determination unit, configured to determine the position relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area, wherein when the starting storage address of the first storage area is 0, it is determined that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is located above the first storage area; otherwise, it is determined that the first storage area is located in the middle of the second storage area; A division unit, used for dividing the Nor Flash chip into N erase blocks according to the erase configuration information; an execution unit, configured to set an erasing mode of the second storage area according to the position relationship and perform an erasing operation in the second storage area according to the erasing mode; When the first storage area is located above the second storage area, the execution unit is used to search the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform an erase operation in the second storage area, wherein a row-by-row erase operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks in the second storage area; When the first storage area is located below the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs in the N erase blocks, start to perform a block-by-block erase operation in the second storage area, and when the erase block to which the start storage address of the first storage area belongs is executed, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs; When the first storage area is located in the middle of the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs and the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform a block-by-block erasing operation in the second storage area, wherein, when executing to the erase block to which the start storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs, and when executing to the erase block to which the end storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks in the second storage area.

3. A program update device for a Nor Flash chip including a code protection area, characterized in that: The invention comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the program update method for a Nor Flash chip containing a code protection zone as claimed in claim 1 are implemented.

4. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, characterized in that: When the computer program is executed by a processor, the method according to claim 1 is implemented.

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