Method and device for testing internal parasitic parameters of chip

Abstract

The invention discloses a method for testing internal parasitic parameters of a chip, and discloses a device for implementing the method, and the method for testing the internal parasitic parameters of the chip comprises the steps: obtaining a high-level threshold voltage of a to-be-tested pin; configuring the to-be-tested pin to be in a timer triggering mode; setting a signal output pin to be in a high level, enabling a counter of a timer in the chip to start counting, enabling a voltage value of a parasitic capacitor to rise to a high level threshold voltage, and obtaining a count value of the timer at the moment; changing the resistance value of the adjustable resistor for multiple times and obtaining count values of a plurality of timers; and obtaining the capacitance value of the first equivalent parasitic capacitor according to the parameters. Therefore, the internal parasitic parameters of the chip are measured by means of the pins of the chip, the parasitic parameters conforming to the actual working scene of the chip are obtained, external equipment is not depended on, and the test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a method for testing parasitic parameters inside a chip and a chip. Background Art

[0002] After the chip is designed and manufactured, there will be parasitic resistance and capacitance inside the chip signal path. These parasitic resistance and capacitance values ​​are the parasitic parameters inside the chip. When the chip is used for high-speed communication or fast ADC sampling, the internal parasitic resistance and capacitance need to be comprehensively considered, so it is necessary to provide parasitic parameters that are closer to the actual situation inside the chip. Existing instruments for measuring resistance and capacitance are basically tested when the device is not powered, but the parasitic resistance and capacitance inside the chip will show different values ​​when the chip is powered and not powered, and only the parasitic resistance and capacitance values ​​when the chip is powered are the parasitic parameters closest to the actual situation inside the chip. Therefore, existing technical means cannot provide parasitic parameters that are closest to the actual situation inside the chip. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a method for testing internal parasitic parameters of a chip, which can test the internal parasitic parameters with the help of the pins of the chip itself, so as to measure the parasitic parameters that meet the actual working scenario of the chip.

[0004] The present invention also provides a device for implementing the above-mentioned method for testing the internal parasitic parameters of the chip.

[0005] The present invention also provides a computer-readable storage medium.

[0006] According to a first aspect of the present invention, a method for testing chip internal parasitic parameters is applied to a chip, wherein the chip comprises: a timer, a PWM signal output pin, a GPIO pin, and a first equivalent parasitic capacitor, wherein the PWM signal output pin is electrically connected to the GPIO pin via an adjustable resistor, and the GPIO pin is connected to the first equivalent parasitic capacitor; the method for testing chip internal parasitic parameters comprises:

[0007] Obtaining a high level threshold voltage of the GPIO pin;

[0008] Configuring the GPIO pin to a timer trigger mode;

[0009] The PWM signal output pin is set to a high level, and after the counter of the timer is cleared, the counter of the timer starts counting;

[0010] The PWM signal output pin charges the GPIO pin through the adjustable resistor, so that the voltage value of the first equivalent parasitic capacitor rises to the high-level threshold voltage, and the count value of the timer at this time is obtained;

[0011] Changing the resistance value of the adjustable resistor multiple times, and returning to the step of setting the PWM signal output pin to a high level, and clearing the counter of the timer to zero, and then starting the counter of the timer to count, to obtain multiple count values ​​of the timer;

[0012] The capacitance value of the first equivalent parasitic capacitance is obtained according to the plurality of count values, the output voltage of the PWM signal output pin and the high-level threshold voltage.

[0013] According to some embodiments of the present invention, obtaining the high-level threshold voltage of the GPIO pin includes:

[0014] Setting the GPIO pin to normal input mode;

[0015] Providing a gradually increasing voltage to the GPIO pin;

[0016] When the input value of the GPIO pin is at a high level, the voltage value of the voltage is recorded, and the voltage value is the high level threshold voltage.

[0017] According to some embodiments of the present invention, obtaining the capacitance value of the first equivalent parasitic capacitance according to the plurality of count values, the output voltage of the PWM signal output pin, and the high-level threshold voltage includes:

[0018] Calculate and obtain multiple recognition times of the GPIO pin recognizing a high level according to the multiple count values ​​and the clock value of the timer;

[0019] Substituting the plurality of identification times, the resistance values ​​of the plurality of adjustable resistors, the output voltage of the PWM signal output pin and the high-level threshold voltage into a capacitor charging formula to obtain a first charging equation group;

[0020] The first charging equation group is solved to obtain the capacitance value of the first equivalent parasitic capacitance.

[0021] According to some embodiments of the present invention, when the GPIO pin is an ADC pin with an ADC function, the chip further includes: an equivalent parasitic resistor, a second equivalent parasitic capacitor, the PWM signal output pin is electrically connected to the ADC pin through an adjustable resistor, the ADC pin is connected to the first equivalent parasitic capacitor, the ADC pin is also connected to one end of the equivalent parasitic resistor, and the other end of the equivalent parasitic resistor is connected to the second equivalent parasitic capacitor; the method for testing the internal parasitic parameters of the chip further includes:

[0022] Configuring the ADC pin to analog input mode;

[0023] Set the sampling time setting value of the ADC pin;

[0024] The PWM signal output pin is set to a high level, and after the counter of the timer is cleared, the counter of the timer starts counting, and the ADC pin triggers sampling;

[0025] When the count value of the timer reaches the sampling time setting value, obtaining the sampling voltage of the ADC pin at this time;

[0026] Changing the resistance value of the adjustable resistor multiple times, and returning to the step of configuring the ADC pin to an analog input mode, to obtain multiple sampled voltages;

[0027] The capacitance value of the second equivalent parasitic capacitor and the resistance value of the parasitic resistor are obtained according to the plurality of sampled voltages, the output voltage of the PWM signal output pin and the capacitance value of the first equivalent parasitic capacitor.

[0028] According to some embodiments of the present invention, obtaining the capacitance value of the second equivalent parasitic capacitor and the resistance value of the parasitic resistor according to the plurality of sampled voltages, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitor comprises:

[0029] Substituting the plurality of sampled voltages, the resistance values ​​of the plurality of adjustable resistors, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitor into a capacitor charging formula to obtain a second charging equation group;

[0030] The second charging equation group is solved to obtain the second parasitic capacitance value and the parasitic resistance value.

[0031] According to some embodiments of the present invention, the chip further includes a sampling switch, and the sampling switch is arranged between the ADC pin and the equivalent parasitic resistor. The method for testing the internal parasitic parameters of the chip includes:

[0032] When the sampling switch is disconnected, the GPIO pin does not have an ADC function;

[0033] When the sampling switch is closed, the GPIO pin has an ADC function.

[0034] According to some embodiments of the present invention, the capacitor charging formula is:

[0035]

[0036] Among them, V C (t) is the voltage of the capacitor at time t, V u is the output voltage of the PWM signal output pin, R is the resistance value of the adjustable resistor, and C is the capacitance value of the first equivalent parasitic capacitor.

[0037] According to some embodiments of the present invention, the second charging equation set is:

[0038]

[0039] Among them, Vs is the voltage value of the sampled voltage, Rx is the resistance value of the adjustable resistor, Vout is the output voltage value of the PWM signal output pin, C1 is the capacitance value of the first equivalent parasitic capacitor, C2 is the capacitance value of the second equivalent parasitic capacitor, Ts is the sampling time setting value of the ADC pin, and R1 is the resistance value of the equivalent parasitic resistor.

[0040] According to a device for testing parasitic parameters inside a chip according to a second aspect of the present invention, the chip comprises:

[0041] one or more processors;

[0042] Memory;

[0043] One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the method for testing chip internal parasitic parameters as described in any one of the above embodiments are implemented.

[0044] According to the computer-readable storage medium of the third aspect of the present invention, a computer program is stored thereon, and when the computer program is executed by a processor, the steps of the method for testing the internal parasitic parameters of a chip as described in any one of the above embodiments are implemented.

[0045] The method for testing chip internal parasitic parameters according to an embodiment of the present invention has at least the following beneficial effects: by electrically connecting the PWM signal output pin to the GPIO pin through an adjustable resistor, changing the level of the PWM signal output pin, and recording the corresponding parameters to calculate the capacitance value of the parasitic capacitor, it is possible to measure the chip internal parasitic parameters with the help of the chip's own pins when the chip device is powered on, that is, to obtain parasitic parameters that meet the actual working scenario of the chip without relying on external instruments and equipment, thereby reducing the testing cost.

[0046] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0048] Figure 1 Schematic diagram of the process of the chip internal parasitic parameters testing method according to an embodiment of the present invention;

[0049] Figure 2 for Figure 1 A flowchart of additional steps in the chip internal parasitic parameter testing method when the GPIO pin is an ADC pin with ADC function is shown;

[0050] Figure 3 This is a schematic diagram of electrical connections of GPIO pins without ADC function of a device for testing internal parasitic parameters of a chip according to an embodiment of the present invention;

[0051] Figure 4 for Figure 3 The signal waveform diagram of the GPIO pin without ADC function of the test device of the internal parasitic parameters of the chip is shown;

[0052] Figure 5 This is a schematic diagram of electrical connections of ADC pins with ADC function of a device for testing chip internal parasitic parameters according to an embodiment of the present invention;

[0053] Figure 6 for Figure 5 The signal waveform diagram of the ADC pin of the chip internal parasitic parameter test device with ADC function is shown. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0055] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0056] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0057] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0058] The following is combined with Figure 1-6 , a method and device for testing chip internal parasitic parameters according to an embodiment of the present invention are described in detail.

[0059] Reference Figure 1 and Figure 3 The present invention proposes a chip internal parasitic parameter testing method, which is applied to a chip MCU. The chip MCU includes: a timer, a PWM signal output pin, a GPIO pin and a first equivalent parasitic capacitor C1. The PWM signal output pin is electrically connected to the GPIO pin through an adjustable resistor Rx, and the GPIO pin is connected to the first equivalent parasitic capacitor C1. The chip internal parasitic parameter testing method includes:

[0060] S100: Get the high level threshold voltage VIH of the GPIO pin;

[0061] S200: Configure the GPIO pin to timer trigger mode;

[0062] S300: Set the PWM signal output pin to a high level, and clear the timer counter to zero, so that the timer counter starts counting;

[0063] S400: the PWM signal output pin charges the GPIO pin through the adjustable resistor Rx, so that the voltage value of the first equivalent parasitic capacitor C1 rises to the high level threshold voltage, and the count value Count of the timer at this time is obtained;

[0064] S500: changing the resistance value of the adjustable resistor Rx multiple times, and returning to the step of setting the PWM signal output pin to a high level, and clearing the counter of the timer to zero, and then starting the timer counter to count, to obtain the count values ​​Count of multiple timers;

[0065] S600: Obtaining a capacitance value of a first equivalent parasitic capacitor C1 according to a plurality of count values ​​Count, an output voltage Vout of a PWM signal output pin, and a high-level threshold voltage VIH.

[0066] Specifically, in this embodiment, refer to Figure 3 The PWM signal output pin of the chip MCU is electrically connected to the GPIO pin through an adjustable resistor Rx that is externally welded or detachably electrically connected. The GPIO pin is electrically connected to one end of the first equivalent parasitic capacitor C1 inside the chip MCU. The GPIO pin is also electrically connected to the Schmitt trigger SCHMITT inside the chip. The Schmitt trigger SCHMITT is used to perform signal processing and waveform shaping on the GPIO pin, which can effectively eliminate noise interference and avoid false triggering caused by small fluctuations, thereby improving the quality and stability of the signal. Figure 1 , for the chip internal parasitic parameter measurement method of this embodiment, step S100 is specifically: set the GPIO to the normal input mode, input a gradually increasing voltage to the GPIO pin, and when the input value of the GPIO pin is a high level, record the voltage value of the GPIO pin at this time, which is the high level threshold voltage VIH. For steps S300 and S400, refer to Figure 4 , configure the GPIO pin to the timer trigger mode, set the timer clock value to Clk, at time a, the PWM signal output pin outputs a high level, at the same time, the counter of the timer inside the chip starts counting, and the PWM signal output pin charges the internal circuit of the GPIO pin through the adjustable resistor Rx, that is, charges the first equivalent capacitor C1 electrically connected to the GPIO pin inside the chip MCU, so that the level of one end of the first equivalent capacitor C1 increases synchronously with the level of the GPIO pin at this time. At time b, the voltage of the GPIO pin reaches the high level threshold voltage VIH, and the counter of the timer inside the chip stops counting, and the count value Count is obtained. According to the formula Calculate the time Tx from the time when the PWM signal output pin outputs a high level to the time when the GPIO pin recognizes a high level at time b. Step S500 specifically includes: changing the value of the adjustable resistor Rx to obtain several groups of different adjustable resistor Rx values ​​and corresponding time Tx values ​​from time a to time b. The output voltage of the PWM signal output pin is Vout. According to the charging formula of the capacitor List the equations After mathematical transformation, we get the equation Substitute the resistance values ​​of several different sets of adjustable resistors Rx obtained by changing the value of the adjustable resistor Rx and the corresponding time Tx value from time a to time b, together with the high-level threshold voltage VIH and the output voltage Vout of the PWM signal output pin into the equation The corresponding set of equations is obtained, and the capacitance value of the first equivalent capacitor C1 is calculated by solving the set of equations.

[0067] Reference Figure 1 and Figure 3 Further, in some embodiments of the present invention, step S100: obtaining a high-level threshold voltage VIH of a GPIO pin comprises:

[0068] (1) Set the GPIO pin to normal input mode;

[0069] (2) Provide a gradually increasing voltage to the GPIO pin;

[0070] (3) When the input value of the GPIO pin is a high level, the voltage value of the GPIO pin voltage is recorded, and the voltage value is the high level threshold voltage VIH.

[0071] Specifically, in this embodiment, step S100 is as follows: setting the GPIO to a normal input mode, injecting a gradually increasing voltage into the GPIO pin, and when the input value of the GPIO pin is a high level, recording the voltage value of the GPIO pin at this time, which is the high level threshold voltage VIH.

[0072] Reference Figure 1 Further, in some embodiments of the present invention, step S600: obtaining the capacitance value of the first equivalent parasitic capacitor C1 according to the multiple count values ​​Count, the output voltage Vout of the PWM signal output pin and the high level threshold voltage VIH, comprises:

[0073] (1) Calculating multiple recognition times Tx for the GPIO pin to recognize a high level according to multiple count values ​​Count and a clock value Clk of the timer;

[0074] (2) Substituting multiple identification times Count, multiple resistance values ​​of adjustable resistors Rx, the output voltage Vout of the PWM signal output pin, and the high-level threshold voltage VIH into the capacitor charging formula to obtain a first charging equation group;

[0075] (3) Solve the first charging equation group to obtain the capacitance value of the first equivalent parasitic capacitor C1.

[0076] Specifically, in this embodiment, step (1) is specifically: the parameter multiple count values ​​Count and the timer clock value Clk are substituted into the formula Thus, several groups of different variable resistor Rx resistance values ​​and corresponding time Tx values ​​from time a to time b are obtained.

[0077] Steps (2) and (3) are as follows: Based on the charging formula of the capacitor, list the equation After mathematical transformation, we get the equation Substitute the resistance values ​​of several different sets of adjustable resistors Rx obtained by changing the value of the adjustable resistor Rx and the corresponding time Tx value from time a to time b, together with the high-level threshold voltage VIH and the output voltage Vout of the PWM signal output pin into the equation The corresponding first set of equations is obtained, and the capacitance value of the first equivalent capacitor C1 is calculated by solving the first set of equations. By changing the resistance value of the adjustable resistor Rx, corresponding groups of different time Tx values ​​are formed, thereby forming the form of an equation group, so that the capacitance value of the first equivalent capacitor C1 calculated is more accurate and reliable.

[0078] Reference Figure 2 and Figure 5 Further, in some embodiments of the present invention, when the GPIO pin is an ADC pin with an ADC function, the chip MCU also includes: an equivalent parasitic resistor R1, a second equivalent parasitic capacitor C2, the PWM signal output pin is electrically connected to the ADC pin through an adjustable resistor Rx, the ADC pin is connected to the first equivalent parasitic capacitor C1, the ADC pin is also connected to one end of the equivalent parasitic resistor R1, and the other end of the equivalent parasitic resistor R1 is connected to the second equivalent parasitic capacitor C2; the test method of the internal parasitic parameters of the chip also includes:

[0079] S710: Configure the ADC pin to analog input mode;

[0080] S720: Set the sampling time setting value Ts of the ADC pin;

[0081] S730: Set the PWM signal output pin to a high level, and clear the timer counter to zero, so that the timer counter starts counting, and the ADC pin triggers sampling;

[0082] S740: When the count value of the timer reaches the sampling time setting value Ts, the sampling voltage Vs of the ADC pin at this time is obtained;

[0083] S750: changing the resistance value of the adjustable resistor Rx multiple times, and returning to the step of configuring the ADC pin to the analog input mode to obtain multiple sampling voltages Vs;

[0084] S760: Obtain the capacitance value of the second equivalent parasitic capacitor C2 and the resistance value of the parasitic resistor R1 according to the multiple sampling voltages Vs, the output voltage of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitor C1.

[0085] Specifically, in this embodiment, refer to Figure 5 When the GPIO pin has an ADC function, it is an ADC pin. The ADC pin is connected to the first equivalent parasitic capacitor C1. The ADC pin is also connected to one end of the equivalent parasitic resistor R1 through the sampling switch Ks. The other end of the equivalent parasitic resistor R1 is connected to the second equivalent parasitic capacitor C2. The other end of the equivalent parasitic resistor R1 is also electrically connected to the analog-to-digital conversion module inside the chip MCU. Therefore, when the sampling switch Ks is disconnected, the GPIO pin is a GPIO pin without an ADC function. When the sampling switch Ks is closed, the GPIO pin is an ADC pin with an ADC function. Among them, steps S710 to S760 are additional steps based on the above steps S100 to S600 when the GPIO pin has an ADC function. For steps S730 and S740, refer to Figure 6 At time a, the level of the PWM signal output pin changes from low level to high level, and the ADC pin is charged through the adjustable resistor Rx, that is, the first equivalent parasitic capacitor C1 and the second equivalent parasitic capacitor C2 are charged. At this time, the timer inside the chip MCU starts counting, and the level of the ADC pin gradually increases. At time b, when the technical time of the timer reaches the sampling time setting value Ts, the sampling voltage Vs at this time is recorded. Then, step S750 is executed to change the resistance value of the adjustable resistor Rx, and measure the sampling voltage Vs corresponding to several groups of different resistance values ​​of the adjustable resistor Rx. For example, two groups of data are measured, and the resistance value Rx1 corresponds to the sampling voltage Vs1, and the resistance value Rx2 corresponds to the sampling voltage Vs2. Then, step S760 is executed according to Figure 5 The circuit shown is combined with the capacitor charging equation to list the second charging equation group Then, the resistance value Rx1 and its corresponding sampled voltage Vs1, the resistance value Rx2 and its corresponding sampled voltage Vs2, the first equivalent parasitic capacitance C1 obtained according to steps S100 to S600, and the output voltage Vout of the PWM signal output pin are substituted into the second charging equation to obtain the following second charging equation group:

[0086]

[0087] Solving the equation group, the resistance value of the first equivalent parasitic resistor R1 and the capacitance value of the second equivalent parasitic capacitor C2 are obtained. The parameter value of the parasitic resistor of the ADC pin is the resistance value of the first equivalent parasitic resistor R1, and the parameter value of the parasitic capacitor of the ADC pin is the sum of the capacitance value of the first equivalent parasitic capacitor C1 and the capacitance value of the second equivalent parasitic capacitor C2.

[0088] Reference Figure 2 Further, in some embodiments of the present invention, step S760: obtaining the capacitance value of the second equivalent parasitic capacitor C2 and the resistance value of the parasitic resistor R1 according to the plurality of sampled voltages Vs, the output voltage of the PWM signal output pin and the capacitance value of the first equivalent parasitic capacitor C1, comprises:

[0089] Substituting the multiple sampling voltages Vs, the resistance values ​​Rx of the multiple adjustable resistors, the output voltage Vout of the PWM signal output pin, and the capacitance value of the first equivalent parasitic capacitor into the capacitor charging formula to obtain a second charging equation group;

[0090] The second charging equation group is solved to obtain the second parasitic capacitance value C2 and the parasitic resistance value R1.

[0091] Specifically, in this embodiment, the resistance value of the adjustable resistor Rx is changed, and after measuring the sampling voltage Vs corresponding to several groups of different resistance values ​​of the adjustable resistor Rx, for example, two groups of data are measured, the resistance value Rx1 corresponds to the sampling voltage Vs1, and the resistance value Rx2 corresponds to the sampling voltage Vs2. Figure 5 The circuit shown is combined with the capacitor charging equation to list the second charging equation group Substitute the resistance value Rx1 and its corresponding sampled voltage Vs1, the resistance value Rx2 and its corresponding sampled voltage Vs2, the first equivalent parasitic capacitance C1 obtained according to steps S100 to S600, and the output voltage Vout of the PWM signal output pin into the charging equation to obtain the following second charging equation group:

[0092]

[0093] Solving the second charging equation group, the resistance value of the equivalent parasitic resistor R1 and the capacitance value of the second equivalent parasitic capacitor C2 are obtained. The parameter value of the parasitic resistor of the ADC pin is the resistance value of the first equivalent parasitic resistor R1, and the parameter value of the parasitic capacitor of the ADC pin is the sum of the capacitance value of the first equivalent parasitic capacitor C1 and the capacitance value of the second equivalent parasitic capacitor C2.

[0094] Reference Figure 5Furthermore, in some embodiments of the present invention, the chip MCU further includes a sampling switch Ks, and the sampling switch Ks is arranged between the ADC pin and the equivalent parasitic resistor R1. The method for testing the internal parasitic parameters of the chip further includes:

[0095] When the sampling switch Ks is disconnected, the GPIO pin does not have the ADC function;

[0096] When the sampling switch Ks is closed, the GPIO pin has the ADC function.

[0097] Specifically, in the present embodiment, since the ADC pin is also connected to one end of the equivalent parasitic resistor R1 through the sampling switch Ks, the other end of the equivalent parasitic resistor R1 is connected to the second equivalent parasitic capacitor C2, and the other end of the equivalent parasitic resistor R1 is also electrically connected to the analog-to-digital conversion module ADC inside the chip MCU, when the sampling switch Ks is disconnected, the GPIO pin is a GPIO pin without ADC function, and when the sampling switch Ks is closed, the GPIO pin is an ADC pin with ADC function.

[0098] Furthermore, in some embodiments of the present invention, the above capacitor charging formula is:

[0099]

[0100] Among them, V C (t) is the voltage of the capacitor at time t, V u is the output voltage of the PWM signal output pin, R is the resistance value of the adjustable resistor, and C is the capacitance value of the first equivalent parasitic capacitor.

[0101] Furthermore, in some embodiments of the present invention, the second charging equation group is:

[0102]

[0103] Among them, Vs is the voltage value of the sampling voltage, Rx is the resistance value of the adjustable resistor, Vout is the output voltage value of the PWM signal output pin, C1 is the capacitance value of the first equivalent parasitic capacitor, C2 is the capacitance value of the second equivalent parasitic capacitor, Ts is the sampling time setting value of the ADC pin, and R1 is the resistance value of the equivalent parasitic resistor.

[0104] The present invention also proposes a testing device for chip internal parasitic parameters, wherein the chip MCU includes: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the chip internal parasitic parameters testing method as described above are implemented.

[0105] The present invention also proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for testing the internal parasitic parameters of a chip as described above are implemented.

[0106] It will be appreciated by those skilled in the art that all or part of the steps for implementing the above-mentioned embodiments can be accomplished by hardware, or by a program to instruct the relevant hardware to accomplish, and the program can be stored in a computer-readable storage medium. In the context of the present invention, the computer-readable medium can be considered to be tangible and non-temporary. Non-limiting examples of non-temporary tangible computer-readable media include non-volatile memory circuits (e.g., flash memory circuits, erasable programmable read-only memory circuits, or mask read-only memory circuits), volatile memory circuits (e.g., static random access memory circuits or dynamic random access memory circuits), magnetic storage media (e.g., analog or digital tapes or hard disk drives), and optical storage media (e.g., CDs, DVDs, or Blu-ray discs), etc. The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0107] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present invention. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0108] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A method for testing parasitic parameters inside a chip, characterized in that: Applied to a chip, the chip comprising: a timer, a PWM signal output pin, a GPIO pin and a first equivalent parasitic capacitor, the PWM signal output pin is electrically connected to the GPIO pin through an adjustable resistor, and the GPIO pin is connected to the first equivalent parasitic capacitor; the method for testing the internal parasitic parameters of the chip comprises: Obtaining a high level threshold voltage of the GPIO pin; Configuring the GPIO pin to a timer trigger mode; The PWM signal output pin is set to a high level, and after the counter of the timer is cleared, the counter of the timer starts counting; The PWM signal output pin charges the GPIO pin through the adjustable resistor, so that the voltage value of the first equivalent parasitic capacitor rises to the high-level threshold voltage, and the count value of the timer at this time is obtained; The resistance value of the adjustable resistor is changed multiple times, and the PWM signal output pin is returned to a high level, and after the counter of the timer is cleared, the counter of the timer starts counting, and a plurality of count values ​​of the timer are obtained; The capacitance value of the first equivalent parasitic capacitance is obtained according to the plurality of count values, the output voltage of the PWM signal output pin and the high-level threshold voltage.

2. The method for testing chip internal parasitic parameters according to claim 1, characterized in that: The obtaining of the high level threshold voltage of the GPIO pin comprises: Setting the GPIO pin to normal input mode; Providing a gradually increasing voltage to the GPIO pin; When the input value of the GPIO pin is at a high level, the voltage value of the voltage is recorded, and the voltage value is the high level threshold voltage.

3. The method for testing chip internal parasitic parameters according to claim 1, characterized in that: The obtaining of the capacitance value of the first equivalent parasitic capacitance according to the plurality of count values, the output voltage of the PWM signal output pin and the high level threshold voltage comprises: Calculate and obtain multiple recognition times of the GPIO pin recognizing a high level according to the multiple count values ​​and the clock value of the timer; Substituting the plurality of identification times, the resistance values ​​of the plurality of adjustable resistors, the output voltage of the PWM signal output pin and the high-level threshold voltage into a capacitor charging formula to obtain a first charging equation group; The first charging equation group is solved to obtain the capacitance value of the first equivalent parasitic capacitance.

4. The method for testing chip internal parasitic parameters according to claim 1, characterized in that: When the GPIO pin is an ADC pin with an ADC function, the chip further includes: an equivalent parasitic resistor, a second equivalent parasitic capacitor, the PWM signal output pin is electrically connected to the ADC pin through an adjustable resistor, the ADC pin is connected to the first equivalent parasitic capacitor, the ADC pin is also connected to one end of the equivalent parasitic resistor, and the other end of the equivalent parasitic resistor is connected to the second equivalent parasitic capacitor; the method for testing the internal parasitic parameters of the chip further includes: Configuring the ADC pin to analog input mode; Set the sampling time setting value of the ADC pin; The PWM signal output pin is set to a high level, and after the counter of the timer is cleared, the counter of the timer starts counting, and the ADC pin triggers sampling; When the count value of the timer reaches the sampling time setting value, obtaining the sampling voltage of the ADC pin at this time; Changing the resistance value of the adjustable resistor multiple times, and returning to the step of configuring the ADC pin to an analog input mode, to obtain multiple sampled voltages; The capacitance value of the second equivalent parasitic capacitor and the resistance value of the equivalent parasitic resistor are obtained according to the plurality of sampled voltages, the output voltage of the PWM signal output pin and the capacitance value of the first equivalent parasitic capacitor.

5. The method for testing chip internal parasitic parameters according to claim 4, characterized in that: The obtaining the capacitance value of the second equivalent parasitic capacitor and the resistance value of the parasitic resistor according to the plurality of sampled voltages, the output voltage of the PWM signal output pin and the capacitance value of the first equivalent parasitic capacitor comprises: Substituting the plurality of sampled voltages, the resistance values ​​of the plurality of adjustable resistors, the output voltage of the PWM signal output pin, the sampling time setting value of the ADC pin and the capacitance value of the first equivalent parasitic capacitor into a capacitor charging formula to obtain a second charging equation group; The second charging equation group is solved to obtain the second parasitic capacitance value and the equivalent parasitic resistance value.

6. The method for testing chip internal parasitic parameters according to claim 4, characterized in that: The chip further includes a sampling switch, and the sampling switch is arranged between the ADC pin and the equivalent parasitic resistor. The method for testing the internal parasitic parameters of the chip further includes: When the sampling switch is disconnected, the GPIO pin does not have an ADC function; When the sampling switch is closed, the GPIO pin has an ADC function.

7. The method for testing chip internal parasitic parameters according to claim 3, characterized in that: The capacitor charging formula is: Among them, V C (t) is the voltage of the capacitor at time t, V u is the output voltage of the PWM signal output pin, R is the resistance value of the adjustable resistor, and C is the capacitance value of the first equivalent parasitic capacitor.

8. The method for testing chip internal parasitic parameters according to claim 5, characterized in that: The second charging equation group is: Among them, Vs is the voltage value of the sampled voltage, Rx is the resistance value of the adjustable resistor, Vout is the output voltage value of the PWM signal output pin, C1 is the capacitance value of the first equivalent parasitic capacitor, C2 is the capacitance value of the second equivalent parasitic capacitor, Ts is the sampling time setting value of the ADC pin, and R1 is the resistance value of the equivalent parasitic resistor.

9. A test device for chip internal parasitic parameters, characterized in that: The chip comprises: one or more processors; Memory; One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the method for testing chip internal parasitic parameters as described in any one of claims 1-8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for testing chip internal parasitic parameters as described in any one of claims 1 to 8 are implemented.

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