A high-performance switch shared cache control system

Abstract

The present invention provides a high-performance switch shared cache control system, comprising: multiple port modules, multiple memory allocation modules, multiple memory recovery modules, a dynamic channel allocation module, and an SRAM array; the dynamic channel allocation module enables cross-communication between the port modules, the memory allocation module, the memory recovery module, and the SRAM array; the port modules are responsible for sending and receiving data packets, scheduling the work of other modules, and performing read and write operations on addresses in the SRAM array; the memory allocation module is responsible for allocating memory space addresses to data packets and using a vector mapping mechanism to record the idle or occupied status of the SRAM address space; and the recovery module is responsible for requesting the destination port to read data packets and recovering the memory address space corresponding to the read data packets. The present invention has the beneficial effect of increasing the switching rate of the shared cache switch.

Description

Technical Field

[0001] The present invention relates to the technical field of cache control, and in particular to a high-performance switch shared cache control system. Background Art

[0002] With the rapid development of fifth-generation communication technology and large-scale artificial intelligence models, the importance of intelligent network devices in people's lives has become increasingly prominent. User requirements for network bandwidth, reliability, and stability have also increased accordingly. Currently, data storage and scheduling occupy a large portion of the time and become a major bottleneck in the communication and large-scale model training and inference processes. Therefore, network devices such as switches and routers are urgently needed to have extremely high data storage capabilities. To this end, it is necessary to design a high-bandwidth, multi-port shared cache controller to meet the requirements of modern communication technology.

[0003] In traditional shared-cache switches, the allocation of free SRAM addresses and the recycling of SRAM memory are inefficient. Specifically, after completing a port service, the system must wait for that port to release resources before the next port requiring service can begin. However, ports only require service when reading and writing SRAM. This polling method wastes a significant amount of time while the shared cache is inactive, increasing data transmission latency and reducing overall performance.

[0004] Traditional switches use weighted round-robin (WRR) queue scheduling. This method has the problem that if no queue submits an arbitration request within a certain period, the grant counts for all queues are reset. This weakens the effectiveness of WRR when requests are infrequent, affecting the efficient allocation of bandwidth between queues of different priority levels. Furthermore, if a high-priority queue has unused weight but no new requests arrive for an extended period, this can waste resources and even cause congestion.

[0005] Traditional shared-cache switches often use CrossBar as the switching matrix, offering advantages such as simplicity and flexibility. However, as scale increases, costs and power consumption increase dramatically. In high-speed network environments, switching latency becomes a performance bottleneck. The total bandwidth of a traditional shared-cache switch's internal switching rate = SRAM bit width × frequency × utilization. However, both bit width and frequency are limited by the manufacturing process, while utilization is affected by the time required for port service polling and shared cache storage management. These factors cannot be increased indefinitely. Therefore, they become bottlenecks that limit further increases in the switching rate of shared-cache switches. Summary of the Invention

[0006] The technical problem to be solved by the present invention is: a high-performance switch shared cache control system, aiming to improve the switching rate of the shared cache switch.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: a high-performance switch shared cache control system, including: multiple port modules, multiple memory allocation modules, multiple memory recycling modules, a dynamic channel allocation module and an SRAM array;

[0008] The dynamic channel allocation module is used for cross communication between the port module, the memory allocation module, the memory recovery module and the SRAM array;

[0009] The port module is used for sending and receiving data packets, scheduling the work of other modules, and performing read and write operations on addresses in the SRAM array;

[0010] The memory allocation module is used to allocate memory space addresses for data packets and use a vector mapping mechanism to record the idle state or occupied state of the SRAM address space;

[0011] A memory recovery module is used to request the destination port to read data packets and to recover the memory address space corresponding to the read data packets;

[0012] Among them, the memory recovery module receives the descriptor of the data packet written into the SRAM array from the port module, manages the descriptors through multiple FIFOs with different priorities, and works for the FIFOs through multiple state machine queues. After weighted polling arbitration between the FIFOs, it is determined that all state machine queues work for a certain FIFO after serving it. The state machine queue takes the descriptor and dispatches the port module to read the corresponding data packet through the descriptor. After completion, the descriptor is sent to the memory allocation module to schedule it to clear the occupancy mark of the address space of the data packet corresponding to the descriptor, thereby requesting the destination port to read the data packet and memory recovery.

[0013] Furthermore, the memory recycling module is provided with a weighted round-robin arbiter, a plurality of FIFOs of different priorities and a plurality of state machine queues;

[0014] The FIFO is used to store descriptors of the corresponding level. When the FIFO is not empty, it actively sends a service request signal to the weighted polling arbiter. After receiving at least one valid service request signal, the weighted polling arbiter marks all FIFOs in the request state as pending and starts a round-robin selection process based on the weight ratio. Only one authorization operation is performed on each FIFO marked as pending, and only one opportunity can be obtained in the same round. The selected FIFO is collaboratively completed by all state machine queues to complete the required amount of data retrieval and task scheduling work. After completion, the control right is immediately released and the pending mark of the FIFO is cleared. For the remaining FIFOs that are not selected and still have pending marks, they will continue to participate in polling until all pending marks are cleared. After all pending marks are cleared, the weighted polling arbiter starts a new round of weighted polling.

[0015] Furthermore, when a FIFO is exhausted, a control right release signal is immediately sent to the weighted polling arbiter.

[0016] Furthermore, the register value is dynamically configured through the APB interface to adjust the bandwidth allocated to each FIFO by the weighted polling arbiter, thereby adjusting the weight of each FIFO.

[0017] Furthermore, the memory recycling module also includes a data distributor for storing received data packets into corresponding priority FIFOs according to their priority information.

[0018] Furthermore, the memory recycling module also includes a TAG FIFO for scheduling the state machine queue. Each queue is assigned a TAG value. When the state machine queue is idle and has a data packet or descriptor processing requirement, it applies for the corresponding TAG through fair polling arbitration to obtain work authorization.

[0019] Furthermore, the descriptor includes: source port, destination port, data packet length, priority, module ID, multicast destination port and multicast enable.

[0020] Furthermore, each port module is internally configured with multiple FIFOs for storing data packets, multiple state machine queues, TAG FIFO, fair polling arbiter, data distributor, information vector table and state vector table;

[0021] The data distributor is used to distribute received data packets to the FIFO; the FIFO is used to store data packets; the state machine queue applies to the TAG FIFO for corresponding work authorization through the fair polling arbitrator; the information vector table is used to store the frame header information of the data packet; the state vector table is used to identify the workflow and guide the operation of the state machine by changing the register value in the state vector table after the port module successfully establishes communication with other modules and completes the handshake protocol.

[0022] Furthermore, the frame header information of the data packet includes a source port, a destination port, a data packet length, a priority, a multicast destination port and a multicast enable.

[0023] Furthermore, the dynamic channel allocation module is integrated with a load balancing module and a routing module;

[0024] The dynamic channel allocation module first receives a request from the host and simultaneously obtains the real-time status information of all slaves; the port module acts as the host, and the memory allocation module and memory recovery module act as slaves; based on the real-time status information of the slaves, the dynamic channel allocation module arbitrates the host's request to determine which host to provide service to; after determining which host to provide service to, the load balancing module further arbitrates the idle slaves and allocates the request to the slave that has obtained arbitration authorization; the index of the slave that has obtained arbitration authorization is output to the routing module, and the routing module selects the corresponding line according to the slave index to complete the data transmission between the host and the slave.

[0025] The beneficial effects of the present invention are as follows: the technical solution manages the SRAM array composed of multiple SRAMs in a refined manner through memory space mapping vectors, and performs dynamic memory allocation and recycling after reading and writing data packets, which greatly improves the shared cache utilization rate. All ports can write data packets to any position in the SRAM array through the dynamic channel allocation module. Each port may be at a different position in the workflow, and the port only needs to participate in polling to apply for the bus to read and write SRAM when reading and writing SRAM, which reduces time consumption and greatly improves the total bandwidth. The technical solution of the present invention optimizes the weighted polling scheduling mechanism, solves the problem of resetting the authorization counts of all queues in a period without requests, and solves the problem of resource waste and blocking caused by a long period of no new requests for high-priority queues, thereby improving the effective allocation of bandwidth between queues of different priorities. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the mechanisms shown in these drawings without paying any creative work.

[0027] Figure 1 This is a block diagram of a high-performance switch shared cache control system according to an embodiment of the present invention;

[0028] Figure 2 This is a structural block diagram of a port module according to an embodiment of the present invention;

[0029] Figure 3 This is a structural block diagram of a memory recycling module according to an embodiment of the present invention;

[0030] Figure 4 This is a structural block diagram of a dynamic channel allocation module according to an embodiment of the present invention;

[0031] Figure 5 A block diagram of a global shared cache implementation method according to an embodiment of the present invention;

[0032] Figure 6 A memory space mapping vector block diagram according to an embodiment of the present invention;

[0033] Figure 7 This is a flowchart of a data writing process according to an embodiment of the present invention;

[0034] Figure 8 A flowchart of a data reading process according to an embodiment of the present invention;

[0035] Figure 9 This is a structural diagram of a data packet frame header according to an embodiment of the present invention;

[0036] Figure 10 This is a descriptor structure diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0038] It should be noted that the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0039] like Figure 1 As shown, the embodiments of the present invention are: Figure 1 The overall architecture of a high-performance switch shared cache control system provided by an embodiment of the present invention is presented. The system includes a port module, a memory allocation module, a memory recycling module, a routing module, a dynamic channel allocation module, and an SRAM array.

[0040] In this embodiment, the system is configured with 16 port modules and an SRAM array consisting of 16 SRAM slices. The number of memory allocation modules and memory recycling modules can be parameterized and configured as needed, with a maximum of 16 modules in each configuration. Identical modules operate independently and are not affected by other modules, so each module may be in a different process. Cross-module communication is achieved through the routing module and the dynamic channel allocation module.

[0041] In this embodiment, the system allows all ports to share a unified SRAM array resource to achieve efficient data packet storage and forwarding functions. Whenever any source port receives a new data packet, it will request memory space from the memory allocation module and store the data packet in the SRAM array. Each port module may be in a different workflow and will only participate in arbitration to apply for the bus to read and write the SRAM when it needs to read and write the SRAM. As long as there are data packets in the SRAM array that have not been read by the destination port, the memory recovery module will continuously initiate read requests, aiming to read the data packets stored in the SRAM array from the destination port. The memory recovery module will then initiate a recovery request to release the previously occupied space for subsequent use, thereby ensuring the stable operation of the entire system and efficient use of existing hardware resources.

[0042] The system's external read and write interfaces are located in the port module. When an external data write request arrives, the port module temporarily stores the data packet and concatenates information such as the packet size, priority, and destination port from the frame header to generate a descriptor corresponding to the packet. This descriptor is then sent to the memory allocation module. Based on the descriptor, the memory allocation module searches the shared cache for free memory space that matches the packet size and allocates an address for the packet. Simultaneously, the memory allocation module uses vector mapping to mark the allocated address as occupied. After obtaining the address, the port module writes the data packet to the shared cache. Once the write is complete, the port module sends the descriptor to the memory recycling module. The memory recycling module stores the descriptor in the FIFO and initiates a read request to the port module. After the destination port reads the data packet, the memory recycling module uses the descriptor to communicate with the memory allocation module to clear the vector occupied mark corresponding to the packet in the memory allocation module, thus completing the packet forwarding and memory recycling process.

[0043] Figure 2 The port module structure of the present invention is demonstrated. The port module serves as the interface module for external data read and write between the system and external devices, responsible for sending and receiving data packets, scheduling system workflows, and reading and writing SRAM data. Each port module is internally configured with eight FIFOs for storing data packets, eight state machine queues, a tag FIFO, a fair polling arbiter, a data distributor, an information vector table, and a state vector table.

[0044] The 16-port module has exactly the same structure and function. Each port may be in a different stage of writing or reading data, and they are independent of each other and work in parallel.

[0045] The eight internal state machine queues are scheduled through the tag FIFO. A tag is a marker, and each queue has a unique tag value. Receiving the tag assigned to a queue initiates the state machine, allowing the eight state machine queues to operate in parallel and out of order. The tag FIFO has a depth of eight and stores integers from 0 to 7 as tags. Each queue is associated with a unique tag. For example, state machine queue 0 corresponds to tag 0. When a queue is idle and a packet or descriptor needs to be sent or received, it participates in fair round-robin arbitration to request the corresponding tag from the tag FIFO. Once the tag is received, the state machine is authorized to work, starts, and after completing all states, pushes the tag back into the tag FIFO. This mechanism allows multiple queues to process multiple tasks in parallel and out of order.

[0046] The tag FIFO depth is 8. When the power is on, the 8 data are reset to 8 integers from 0 to 7, which correspond to the tag values ​​of the 8 queues as passes. At the same time, the write pointer in the FIFO is increased by 8. In this way, a full FIFO is obtained after power-on and all 8 tags are in the FIFO.

[0047] In the port module, there are two scenarios in which the state machine queues request tags: First, during a write packet (WP), an external request is sent to the port to write data; second, during a read packet (RP), the memory reclaim module requests the port module to read the corresponding packet descriptor and reclaim the corresponding memory. In both scenarios, the eight queues request tags from the tag FIFO through a fair round-robin arbiter.

[0048] Similarly, the state machine queue returns tags in two situations: First, during a data packet write (WP), the queue returns the tag to the tag FIFO after writing the data packet to the SRAM. Second, during a data packet read (RP), the tag return task begins after the data packet is read from the destination port module. In both cases, the eight queues return the tag by pushing it back to the tag FIFO through a fair polling arbiter.

[0049] When an external request is made to write a data packet, the state machine queue extracts the information of the data packet frame header, such as Figure 9 As shown in the figure, the packet header information, including source port, destination port, packet length, priority, multicast destination port, and multicast enable, is stored in the information vector table constructed by registers. Furthermore, some fields in the packet header information, such as packet length, priority, and destination port, are spliced ​​into descriptors, which are used to schedule other modules to complete packet forwarding and memory recycling functions.

[0050] During the communication process with other modules, additional information is recorded in the information vector table, including address, SRAM ID, memory recovery module ID, memory allocation module ID, ECC warning and ECC error, etc.

[0051] After the port module successfully establishes communication with other modules and completes the handshake protocol, it identifies the workflow and guides the operation of the state machine by changing the register values ​​in the state vector table. The port module is responsible for updating and maintaining the information vector table and the state vector table to manage the queues of the eight state machines and implement a parallel and unordered workflow.

[0052] exist Figure 3The structure and functionality of the memory reclamation module are described in detail in [1]. The core of the memory reclamation module is a set of multiple FIFOs, which store descriptors corresponding to packets that have been written but not yet read. These descriptors instruct the port module to read the corresponding packets and notify the memory allocation module to release the memory space mapping vectors corresponding to these packets, thereby effectively reclaiming and reusing memory resources.

[0053] In this embodiment, each memory recycling module includes: 8 independent FIFOs, each responsible for managing descriptors of corresponding priorities; 8 state machine queues for tracking and processing descriptors; a TAG FIFO for scheduling state machine queue work; a weighted polling arbitrator to ensure that the required bandwidth is allocated to data packets of different priorities; and a data distributor responsible for storing received data packets into the corresponding priority FIFO according to their priority information.

[0054] The FIFO in the memory recycling module features eight priority levels, designed to efficiently receive descriptors from the port modules and improve the quality of service for descriptors of varying priorities. During descriptor reception, the system uses a data selector to accurately assign each descriptor to the FIFO of the corresponding priority level based on its priority information. This mechanism ensures faster processing of high-priority tasks.

[0055] After completing the data packet reading, the memory allocation module is instructed to perform a cleanup operation based on the specific details provided by the descriptor, that is, to clear the occupied mark in the memory space address mapping vector corresponding to the read data packet.

[0056] The memory recycling module also incorporates an optimized arbitration mechanism designed to improve the efficiency and fairness of system resource allocation. The eight FIFOs are arbitrated using an improved weighted round-robin approach. A problem with traditional methods is that if no queue submits an arbitration request within a certain period, the grant counts for all queues are reset. This weakens the effectiveness of weighted round-robin when requests are infrequent, affecting the efficient allocation of bandwidth between queues of different priority levels. Furthermore, if a high-priority queue has unused weights but no new requests arrive for an extended period, this can waste resources and even cause congestion.

[0057] To address this problem, a novel solution is proposed: eight FIFOs with different priorities are configured to store task descriptors of corresponding levels. Non-empty FIFOs actively send request signals to a weighted round-robin arbiter. Upon receiving at least one valid request, the weighted round-robin arbiter marks all currently requesting FIFOs as pending and initiates a round-robin selection process based on weighted proportions. During this process, only those FIFOs marked as pending are granted authorization once in turn; each FIFO receives only one opportunity in each round. The marked FIFOs are granted authorization one by one. Once a FIFO receives authorization, all state machines jointly serve it, extracting descriptors and completing the corresponding task scheduling with other modules. After all state machines jointly obtain the weighted number of descriptors, they terminate service to that FIFO, release control, and clear the pending flag on that FIFO. For the remaining unselected FIFOs still marked as pending, authorization continues until all are processed. When the pending flags on all FIFOs are cleared, a new round of weighted round-robin begins.

[0058] To prevent the entire process from stalling due to insufficient data remaining in a single FIFO to support the scheduled number of operations, a safety measure has been designed. When a FIFO is detected to be exhausted, it immediately sends a release signal to the weighted round-robin arbiter, thus avoiding unnecessary waiting time. Furthermore, the bandwidth allocated to each FIFO can be adjusted based on actual conditions. This function is achieved by dynamically configuring register values ​​through the APB interface, thereby adjusting the weights of each FIFO.

[0059] Figure 4 This section shows the structure of the dynamic channel allocation module, which integrates the load balancing module and the routing module to optimize data transmission between the master and slave devices. The port module, acting as the master, issues a request. The load balancing module and the routing module distribute the request to any single idle channel, which then accesses the corresponding slave, namely the memory allocation module or the memory recycling module.

[0060] In this embodiment, the dynamic channel allocation module first receives a request from the master and simultaneously obtains the status information of all slaves. Based on this status information, the dynamic channel allocation module arbitrates the master's request to determine which master to serve. Once the service target is determined, the load balancing module further arbitrates the idle slaves and assigns the request to the slave that has received arbitration authorization. The selected slave index is then output to the routing module, which selects the corresponding route based on the index, thereby completing the data transmission between the master and slaves.

[0061] The port module obtains a free memory allocation module through the dynamic channel allocation module for its service, and returns the module ID to the port module for recording and storing it in Figure 10 In the descriptor shown, when the descriptor is sent to the memory recycling module, the corresponding memory recycling module and SRAM are found through the routing module according to the ID index, thereby realizing the cross-connection function.

[0062] In this embodiment, the design of the dynamic channel allocation module allows parameterization of the number of memory allocation and memory recycling modules, effectively reducing resource consumption and being particularly suitable for use on resource-constrained hardware platforms.

[0063] like Figure 5 As shown in the figure, the dynamic channel allocation module supports any port module to access any memory allocation module or memory recycling module, so that data packets input from any port can access any SRAM area, achieving the effect of global shared cache, and realizing load balancing, which significantly improves system performance.

[0064] Figure 6This article demonstrates how the memory allocation module manages the SRAM array. Each memory allocation module uses a vector-mapped memory space to record the occupied and idle status of all addresses in a block of SRAM. All memory allocation modules work together to manage the memory space occupied and idle status of the entire SRAM array. Specifically, this management is achieved through a one-to-one mapping relationship between memory space addresses and vectors. Initially, all memory spaces in the SRAM array are empty, and the corresponding mapping vectors are idle. When a port module successfully requests an address allocation, it writes a data packet to the corresponding address in the SRAM array. The memory allocation module then marks the memory space mapping vector for that address as occupied, indicating that the memory space is in use. After the port module reads a data packet from a specific address in the SRAM array, the memory allocation module clears the occupied flag at that address, restoring the address to an idle state. In this way, the memory allocation module effectively manages memory allocation and deallocation, ensuring efficient utilization of the SRAM array.

[0065] After receiving the descriptor from the port module, the memory allocation module first extracts the packet length (len) from the descriptor. It then searches the free mapping vector for a contiguous memory space greater than or equal to len (a power of 2). Once a suitable contiguous memory space is found, the memory allocation module sends the first address of this contiguous memory space to the port module and marks it occupied in the free mapping vector to prevent other packets from writing to it. This ensures stability and security during data transmission and improves overall system performance.

[0066] like Figure 7 、 Figure 8 As shown in the figure, the forwarding process of a data packet in the system is as follows:

[0067] Write data:

[0068] (1) The write data request is initiated externally, and the port module decides whether to accept the request based on the idle state of the internal state machine queue.

[0069] (2) If the state machine is in the idle state, it performs polling arbitration to apply for a tag. The queue that successfully obtains the tag stores the data packet in its corresponding FIFO. It also extracts information from the packet header (including source port, destination port, packet length, priority, multicast destination port, and multicast enable). This information is stored in the information vector table constructed by the register.

[0070] (3) The port module selects a memory allocation module through the dynamic channel allocator and sends a descriptor to the memory allocation module to request the allocation of memory space.

[0071] (4) The memory allocation module queries the free address of the SRAM array based on the packet length carried by the descriptor, and returns the first address of a continuous free memory space to the queue.

[0072] (5) The queue uses the obtained first address to write the data packet into the continuous address space starting with this address.

[0073] (6) After completing the data write operation, the queue sends the descriptor to the memory recycling module for temporary storage, waiting for further processing.

[0074] (7) The queue that has completed writing data goes through the arbitration mechanism and pushes its tag back to the tag FIFO.

[0075] (8) At this point, the entire data writing process ends.

[0076] Read data:

[0077] (1) The data reading process is initiated by the memory recovery module.

[0078] (2) The memory recycling module contains eight FIFOs for storing descriptors. These FIFOs apply for arbitration through weighted round-robin. Once authorized, all state machine queues jointly serve the FIFO. When a state machine applies for a TAG, it will take out a descriptor from the FIFO.

[0079] (3) The state machine queue that obtains the descriptor will apply for fair polling arbitration, obtain the authorized state machine control module interface signal, and send the descriptor to the corresponding port module through the routing module. The specific port module to which it is sent depends on the destination port information in the descriptor, which is completed by the routing module.

[0080] (4) After sending the descriptor, the state machine waits for the response signal from the port module. Receiving the response signal indicates that the data packet has been confirmed to be read from the destination port.

[0081] (5) After receiving the response signal from the port module, the state machine sends the descriptor to the memory allocation module, which schedules the memory allocation module to clear the memory space mark occupied by the data packet corresponding to the descriptor, completing the memory recovery function.

[0082] (6) Finally, the state machine pushes the TAG back into the TAG FIFO, indicating that the state machine has completed a data reading task.

[0083] (7) At this point, the data reading process ends.

[0084] The beneficial effects of the embodiments of the present invention are:

[0085] (1) Each memory allocation module is responsible for managing a specific SRAM area. After the data packet is written, the address is marked as occupied. After the data packet is read, the occupied mark is cleared and the address is restored to the idle state. All memory allocation modules work together to maintain the memory space usage and idle state information of the entire SRAM array. Through this mechanism, not only can we effectively track which parts are currently occupied and which parts are available, but we can also provide accurate data support for subsequent operations. In addition, a dynamic channel allocation module is designed in the system, which allows any port module to flexibly access any memory allocation module according to actual needs, and then obtain any specified memory address resource in the SRAM array. This design allows any external device or internal component to easily perform read and write operations at any location in the SRAM array, truly realizing a global shared cache function. Moreover, among the multiple tasks of each port, only when reading and writing SRAM does it need to request SRAM for its service, which greatly saves time cost and does not cause queue congestion. This method greatly improves the flexibility and efficiency of the overall system, and also significantly enhances the utilization of memory resources. It is particularly important for applications that require high-performance computing and fast response capabilities.

[0086] (2) In order to adapt to platforms of different sizes and reduce the consumption of hardware resources, the present invention adopts an innovative modular architecture design. Specifically, by introducing a routing module and a dynamic channel allocation mechanism, not only is an efficient inter-module interconnection network function achieved, but the number of memory allocation modules and memory recovery modules can also be flexibly adjusted according to actual needs. This design significantly reduces unnecessary hardware resource overhead and improves the scalability and flexibility of the system. In addition, in order to further improve the processing power and efficiency of the system, the present invention specifically considers the load balancing problem. By supporting multiple slave devices (Slave) to provide services for a single master device (Master), the pressure of data processing is effectively dispersed, thereby optimizing the overall performance. This solution not only enhances the robustness of the system, but also ensures that it can maintain stable operation under high concurrency conditions. By adopting the above-mentioned technical means, the present invention greatly reduces the demand for hardware resources while ensuring the efficient operation of the system, providing strong support for the realization of a more economical and efficient solution.

[0087] (3) In order to improve service quality and performance, the present invention proposes an innovative weighted polling arbiter design. The core function of the weighted polling arbiter is to allocate service times to FIFO (first-in-first-out queue) according to different priorities, and all state machine queues can work together to serve the same FIFO. Specifically, the weighted polling arbiter will perform weighted data processing after each authorization and release the authorization after processing. In addition, the present invention also solves the system congestion problem that may be caused when the FIFO is empty. When the FIFO is detected to be empty, an end authorization signal will be issued, thereby avoiding unnecessary waiting and resource waste. Furthermore, the present invention allows the weight of each queue to be adjusted in real time through the APB (Advanced Peripheral Bus) configuration register, so that bandwidth can be dynamically allocated to data packets of different priorities according to actual needs. This flexible configuration method not only enhances the adaptability of the system, but also optimizes the efficiency of resource utilization.

[0088] By implementing this weighted polling mechanism, the present invention effectively avoids the problem of a queue's weight counter not being fully depleted, leading to a continuous wait for the queue to send a request signal, which in turn causes the entire system to be blocked. This improvement significantly improves bus utilization and greatly enhances overall service quality and performance.

[0089] This invention involves an advanced system design that significantly improves system flexibility and efficiency by integrating a tag first-in-first-out (TAG) field (FIFO), an information vector table (MVT), and a state vector table (SVT). This design not only optimizes the processing capabilities of complex tasks but also effectively coordinates the work order between multiple state machine queues, maintaining excellent performance even in the face of highly concurrent tasks. Furthermore, the system supports dynamic adjustment of the work priority of each state machine, enabling it to more intelligently adapt and respond to the needs of different application scenarios, further enhancing its adaptability and practicality.

[0090] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-performance switch shared cache control system, characterized in that: include: Multiple port modules, multiple memory allocation modules, multiple memory recycling modules, dynamic channel allocation module and SRAM array; The dynamic channel allocation module is used for cross communication between the port module, the memory allocation module, the memory recovery module and the SRAM array; The port module is used for receiving and sending data packets, scheduling the work of other modules, and performing read and write operations on addresses in the SRAM array; The memory allocation module is used to allocate memory space addresses for data packets and use a vector mapping mechanism to record the idle state or occupied state of the SRAM address space; A memory recovery module is used to request the destination port to read data packets and to recover the memory address space corresponding to the read data packets; Among them, the memory recovery module receives the descriptor of the data packet written into the SRAM array from the port module, manages the descriptors through multiple FIFOs with different priorities, and works for the FIFOs through multiple state machine queues. After weighted polling arbitration between the FIFOs, it is determined that all state machine queues work for a certain FIFO after serving it. The state machine queue takes the descriptor and dispatches the port module to read the corresponding data packet through the descriptor. After completion, the descriptor is sent to the memory allocation module to schedule it to clear the occupancy mark of the address space of the data packet corresponding to the descriptor, thereby requesting the destination port to read the data packet and memory recovery.

2. The high-performance switch shared cache control system according to claim 1, wherein: The memory recycling module is provided with a weighted polling arbiter, a plurality of FIFOs of different priorities and a plurality of state machine queues; The FIFO is used to store descriptors of the corresponding level. When the FIFO is not empty, it actively sends a service request signal to the weighted polling arbiter. After receiving at least one valid service request signal, the weighted polling arbiter marks all FIFOs in the request state as pending and starts a round-robin selection process based on the weight ratio. Only one authorization operation is performed on each FIFO marked as pending, and only one opportunity can be obtained in the same round. The selected FIFO is collaboratively completed by all state machine queues to complete the required amount of data retrieval and task scheduling work. After completion, the control right is immediately released and the pending mark of the FIFO is cleared. For the remaining FIFOs that are not selected and still have pending marks, they will continue to participate in polling until all pending marks are cleared. After all pending marks are cleared, the weighted polling arbiter starts a new round of weighted polling.

3. The high-performance switch shared cache control system according to claim 2, wherein: When a FIFO is exhausted, a signal to release control is immediately sent to the weighted polling arbiter.

4. The high-performance switch shared cache control system according to claim 3, wherein: The register value is dynamically configured through the APB interface to adjust the bandwidth allocated to each FIFO by the weighted polling arbiter, thereby adjusting the weight of each FIFO.

5. The high-performance switch shared cache control system according to claim 4, characterized in that: The memory recycling module further comprises a data distributor for storing received data packets into corresponding priority FIFOs according to their priority information.

6. The high-performance switch shared cache control system according to claim 5, characterized in that: The memory recycling module also includes a TAG FIFO for scheduling state machine queues. Each queue is assigned a TAG value. When the state machine queue is idle and has a data packet or descriptor processing requirement, it applies for the corresponding TAG through fair polling arbitration to obtain work authorization.

7. The high-performance switch shared cache control system according to any one of claims 1 to 6, wherein: The descriptor includes: source port, destination port, data packet length, priority, module id, multicast destination port and multicast enable.

8. The high-performance switch shared cache control system according to claim 1, wherein: Each port module is internally configured with multiple FIFOs for storing data packets, multiple state machine queues, TAG FIFO, fair polling arbiter, data distributor, information vector table and state vector table; The data distributor is used to distribute received data packets to the FIFO; the FIFO is used to store data packets; the state machine queue is used to fairly poll the arbitrator to apply to the TAG FIFO for corresponding work authorization; the information vector table is used to store the frame header information of the data packet; the state vector table is used to identify the workflow and guide the operation of the state machine by changing the register value in the state vector table after the port module successfully establishes communication with other modules and completes the handshake protocol.

9. The high-performance switch shared cache control system according to claim 8, wherein: The frame header information of the data packet includes source port, destination port, data packet length, priority, multicast destination port and multicast enable.

10. The high-performance switch shared cache control system according to claim 1, wherein: The dynamic channel allocation module is integrated with a load balancing module and a routing module; The dynamic channel allocation module first receives a request from the host and simultaneously obtains the real-time status information of all slaves; the port module acts as the host, and the memory allocation module and memory recovery module act as slaves; Based on the real-time status information of the slaves, the dynamic channel allocation module arbitrates the master's requests to determine which master to serve. After determining which master to serve, the load balancing module further arbitrates the idle slaves and allocates the request to the slave that has obtained arbitration authorization. The slave index that obtains arbitration authorization is output to the routing module, and the routing module selects the corresponding line according to the slave index to complete the data transmission between the host and the slave.

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