Display device and method of providing the same

Abstract

The invention relates to a display device and a method of providing the same. The method includes: providing an active pattern and a gate metal pattern, and inorganic insulating layers respectively between them in a pixel region and each extending to a bending region; providing a first photoresist pattern defining a first opening in the bending region; providing at least one of the etched inorganic layers in the bending region by using a first photoresist pattern; providing a remaining photoresist pattern, the remaining photoresist pattern defining a first remaining opening corresponding to the first opening and a second opening corresponding to a portion of the active pattern; and providing, by using the remaining photoresist pattern, both a contact hole corresponding to the second opening and exposing the portion of the active pattern to the outside of the remaining photoresist pattern, and a portion of the base substrate, a portion of the base substrate corresponds to the first remaining opening and is exposed outside the remaining photoresist pattern.

Description

[0001] Description of the case

[0002] This application is a divisional application of patent application 202110703605.7, filed on June 24, 2021, with the invention name “Display device and method for providing the same”. Technical Field

[0003] Embodiments relate to a display device, and more particularly, to a display device including a curved area and a method of providing the same. Background Art

[0004] The organic light emitting display device emits light by itself without a separate light source, has reduced weight and thickness, and has characteristics suitable for a display device.

[0005] A display panel of an organic light emitting display device may include a flexible base substrate including or formed of a polymer material. Summary of the invention

[0006] Embodiments provide a method for providing or manufacturing a display device, which reduces the number of etching masks.

[0007] Embodiments provide a display device including a curved area.

[0008] According to an embodiment, a method for providing or manufacturing a display device is provided. According to the method, a first inorganic layer is provided on a base substrate including a pixel area and a curved area. A second inorganic layer is provided on the first inorganic layer. An active pattern is provided on the second inorganic layer in the pixel area. A third inorganic layer is provided to cover the active pattern. A first gate metal pattern including a gate electrode is provided on the third inorganic layer. The gate electrode overlaps with the active pattern. A fourth inorganic layer is provided to cover the first gate metal pattern. A second gate metal pattern is provided on the fourth inorganic layer in the pixel area. A fifth inorganic layer is provided to cover the second gate metal pattern. A first photoresist pattern is provided on the fifth inorganic layer. At least one of the inorganic layers is etched below the first opening of the first photoresist pattern in the curved area. The first photoresist pattern is partially removed to form a remaining photoresist pattern, the remaining photoresist pattern including a first remaining opening corresponding to the first opening overlapping the curved area and a second opening overlapping a portion of the active pattern. At least one of the inorganic layer is etched under the first remaining opening and the second opening of the remaining photoresist pattern to form a first contact hole exposing the active pattern and to expose at least a portion of the base substrate in the bent region.

[0009] In an embodiment, the first to fifth inorganic layers may each include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0010] In an embodiment, etching the inorganic layer under the first opening of the first photoresist pattern may remove at least the fifth inorganic layer, the fourth inorganic layer, and the third inorganic layer.

[0011] In an embodiment, etching the inorganic layer under the first opening of the first photoresist pattern may remove at least a portion of the second inorganic layer, the fifth inorganic layer, the fourth inorganic layer, and the third inorganic layer.

[0012] In an implementation, a sum of thicknesses of the inorganic layers etched under the first openings of the first photoresist pattern may be greater than a sum of thicknesses of the inorganic layers etched under the first remaining openings of the remaining photoresist pattern.

[0013] In an embodiment, a first source metal pattern may be provided on the fifth inorganic layer. The first source metal pattern may include a source pattern and a transmission wiring. The source pattern may be electrically contacted with the active pattern through a first contact hole. The transmission wiring may be in the bending region.

[0014] In an implementation, the active pattern may include polysilicon.

[0015] According to an embodiment, a method for providing or manufacturing a display device is provided. According to the method, a first inorganic layer is provided on a base substrate including a pixel area and a curved area. A second inorganic layer is provided on the first inorganic layer. A first active pattern is provided on the second inorganic layer in the pixel area. A third inorganic layer is provided to cover the first active pattern. A first gate metal pattern including a gate electrode is provided on the third inorganic layer. The gate electrode overlaps with the first active pattern. A fourth inorganic layer is provided to cover the first gate metal pattern. A second gate metal pattern is provided on the fourth inorganic layer in the pixel area. A fifth inorganic layer is provided to cover the second gate metal pattern. A second active pattern is provided on the fifth inorganic layer in the pixel area. A sixth inorganic layer is provided to cover the second active pattern. A third gate metal pattern including a second gate electrode is provided on the sixth inorganic layer. The second gate electrode overlaps with the second active pattern. A seventh inorganic layer is provided to cover the third gate metal pattern. A first photoresist pattern is provided on the seventh inorganic layer. At least one of the inorganic layers is etched below the first opening and the second opening of the first photoresist pattern. The first photoresist pattern is partially removed to form a remaining photoresist pattern, the remaining photoresist pattern including a first remaining opening overlapping the bending area, a second remaining opening overlapping a portion of the first active pattern, and a third opening overlapping a portion of the second active pattern. At least one of the inorganic layers is etched under the first remaining opening, the second remaining opening, and the third opening of the remaining photoresist pattern to form a first contact hole exposing the active pattern and a second contact hole exposing the second active pattern.

[0016] According to an embodiment, a display device includes: a base substrate including a pixel region and a bending region, an isolation layer on the base substrate, an active pattern on the isolation layer in the pixel region, a first insulating layer covering the active pattern, a first gate metal pattern on the first insulating layer and including a gate electrode overlapping the active pattern, a second insulating layer covering the first gate metal pattern, a second gate metal pattern on the second insulating layer in the pixel region, a third insulating layer covering the second gate metal pattern, a source metal pattern on the third insulating layer, a through-hole insulating layer on the source metal pattern, and an organic light emitting diode on the through-hole insulating layer. The inorganic layer is excluded in the bending region. The side surfaces of the vertically stacked inorganic layers are connected to each other at the boundary of the bending region, thereby providing a straightly extending side surface.

[0017] According to an embodiment, the inorganic layer in the pixel region and the bent region may be removed by the same photolithography process. Therefore, an additional photolithography process for separately etching the inorganic layer in the bent region may be removed.

[0018] In addition, since the stacked structure of the inorganic layer can have a straightly extending side surface at the boundary between the bending area and the area adjacent to the bending area without a protrusion protruding in the lateral direction, the size of the peripheral area (e.g., non-display area) can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0020] Figure 1 is a cross-sectional view illustrating an embodiment of a display device.

[0021] Figure 2 It is a plan view illustrating an embodiment of a display device.

[0022] Figure 3A , Figure 3B , Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B and Figure 8C A cross-sectional view illustrating an embodiment of a method for providing or manufacturing a display device.

[0023] Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A and 15B A cross-sectional view illustrating an embodiment of a method for providing or manufacturing a display device. DETAILED DESCRIPTION

[0024] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0025] It will be understood that when an element is referred to as being associated with another element, such as being "on" another element, it can be directly on the other element, or intervening elements may exist between them. Conversely, when an element is referred to as being associated with another element, such as being "directly" "on" another element, there are no intervening elements.

[0026] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this article, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0027] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, "a", "an", "the" and "at least one" do not represent a limitation on quantity, and are intended to include the singular and the plural, unless the context clearly indicates otherwise. For example, "element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be understood to limit "one" or "a kind of". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be further understood that the terms "comprises" and / or "comprising" or "includes" and / or "including" when used in this specification indicate the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0028] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top", can be used in this article to describe the relationship between one element and another element as illustrated in the figure. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation described in the figure. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, the term "lower" can cover both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0029] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0031] Embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments. Thus, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but rather should include deviations in shapes, for example, caused by manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated acute angles may be rounded. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the invention.

[0032] The display device 100 may be designed to include a bending area BA where the display device 100 is bendable. The inorganic layer may be omitted in the bending area BA to reduce or effectively prevent the inorganic layer from being broken due to bending stress applied to the bending area BA.

[0033] Hereinafter, the display device 100 and a method of providing or manufacturing the display device 100 will be described with reference to the accompanying drawings.

[0034] Figure 1 is a cross-sectional view illustrating an embodiment of a display device 100 . Figure 1 The display device 100 including the bending area BA and the connection area CA and being folded or bent may be illustrated. Figure 2 is a plan view illustrating an embodiment of the display device 100 . Figure 2 The display device 100 including the bending area BA and the connection area CA and unfolded in a plan view may be illustrated.

[0035] refer to Figure 1 and Figure 2 , the display device 100 includes a display area DA and a peripheral area PA adjacent to the display area DA. The display area DA may include a plurality of pixels or a pixel area PX (including a plurality of pixel areas PX). In an embodiment, a light emitting element and a driving element electrically connected to the light emitting element may be provided in each of the plurality of pixel areas PX. In a plan view, the peripheral area PA may surround at least a portion of the display area DA.

[0036] The display device 100 may further include a bending area BA and a connection area CA. The bending area BA may extend from one side of the peripheral area PA. The bending area BA may be a plane area of ​​the display device 100 where the display device 100 and its various layers are bendable. Figure 1, the curved display device 100 may bend the bending area BA downward along the thickness direction of the display device 100. The connection area CA may extend from the bending area BA and extend in a direction away from the display area DA. The peripheral area PA (e.g., non-display area) may include the connection area CA and the bending area BA, but is not limited thereto. Various layers and elements in the final form of the display device 100 or in an intermediate structure for providing the display device 100 may include the display area DA, the peripheral area PA, the bending area BA, and / or the connection area CA corresponding to those described above for the display device 100.

[0037] refer to Figure 1 , the display device 100 bent at the bending area BA has the connection area CA disposed below the display area DA and / or the peripheral area PA. Figure 2 , the unfolded display device 100 has the bending area BA disposed between the display area DA and the connection area CA. The bending area BA may connect the connection area CA to the peripheral area PA and / or the display area DA.

[0038] The display device 100 may be electrically connected to the driving device at the connection area CA. The connection pad PD may be provided in plurality in the connection area CA, including a plurality of connection pads PD. The connection pad PD may receive a driving signal or a power supply voltage from outside the display device 100. The connection pad PD may receive a driving signal or a power supply voltage from a driving device outside the display device 100.

[0039] The display device 100 may include a transmission wiring TL (including a plurality of transmission wirings TL) provided in a plurality. The transmission wiring TL may be in the bending area BA and may extend from the bending area BA to the connection area CA, the peripheral area PA and / or the display area DA. The connection pad PD may be electrically connected to the transmission wiring TL provided in the bending area BA and the peripheral area PA. The transmission wiring TL may transmit a driving signal or a power supply voltage to the pixel area PX in the display area DA. In an embodiment, the method may include providing a transmission wiring TL through which an electrical signal is provided from the outside of the bending area BA to the pixel area PX. In addition, the transmission wiring TL may transmit a driving signal to a driving circuit provided in the peripheral area PA. In an embodiment, for example, the transmission wiring TL may extend along a first direction DR1 in the bending area BA. The transmission wiring TL may be arranged along a second direction DR2 intersecting the first direction DR1. The thickness direction may be defined along a third direction intersecting each of the first direction DR1 and the second direction DR2.

[0040] Figure 3A , Figure 3B , Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B and Figure 8C is a cross-sectional view illustrating an embodiment of a method for providing or manufacturing the display device 100 . Figure 3A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A An enlarged cross-sectional view of an embodiment of a pixel region PX of the display device 100 may be illustrated. Figure 3B , Figure 4 , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 8C An enlarged cross-sectional view of an embodiment of the bending area BA of the display device 100 may be illustrated.

[0041] refer to Figure 3A and Figure 3B , an isolation layer 112 and a buffer layer 114 are provided or formed on a base substrate 110 .

[0042] The base substrate 110 may include at least one polymer film. The polymer film may include polyethylene terephthalate, polyethylene naphthalate, polyether ketone, polycarbonate, polyarylate, polyether sulfone, polyimide, or a combination thereof. In an embodiment, for example, the base substrate 110 may include at least two polymer films and an inorganic isolation layer disposed therebetween.

[0043] The isolation layer 112 and the buffer layer 114 may include an inorganic material (e.g., an inorganic isolation layer and an inorganic buffer layer). In an embodiment, for example, the isolation layer 112 and the buffer layer 114 may each include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may have a single-layer structure or a multi-layer structure. In an embodiment, the isolation layer 112 may include silicon oxide, and the buffer layer 114 may have a stacked structure including a lower layer including silicon nitride and an upper layer including silicon oxide.

[0044] An active pattern AP and a first insulating layer 120 covering the active pattern AP are provided or formed on the buffer layer 114. A first gate metal pattern including a first gate electrode GE1 and a second gate electrode GE2 is provided or formed on the first insulating layer 120. The first gate electrode GE1 and the second gate electrode GE2 may be in the same layer among the layers on the base substrate 110. Since they are in the same layer, the elements or features may be corresponding patterns of the same material layer. Regarding the first gate metal pattern, for example, the first gate electrode GE1 and the second gate electrode GE2 may be corresponding parts of the same first gate metal layer.

[0045] In an embodiment, for example, the active pattern AP may include polycrystalline silicon (poly-Si). In an embodiment, for example, an amorphous silicon layer may be provided or formed on the buffer layer 114 and then crystallized to provide or form a poly-Si layer.

[0046] In an embodiment, for example, the amorphous silicon layer may be provided or formed by sputtering, low pressure chemical vapor deposition ("LPCVD"), plasma enhanced chemical vapor deposition ("PECVD"), etc. The amorphous silicon layer may be crystallized by excimer laser annealing ("ELA"), sequential lateral solidification ("SLS"), etc.

[0047] The polysilicon layer may be patterned by photolithography or the like to provide or form a semiconductor pattern.

[0048] At least a portion of the semiconductor pattern may be doped with impurities. In an embodiment, the semiconductor pattern may be doped with p-type impurities such as boron, etc. However, the embodiment is not limited thereto. In an embodiment, for example, the semiconductor pattern may be doped with n-type impurities such as phosphorus or arsenic, etc. In an embodiment, for example, the semiconductor pattern may have different concentrations of n-type impurities in different portions.

[0049] In an implementation, for example, after providing or forming the first gate metal pattern on the first insulating layer 120 , the semiconductor pattern may be doped by using the first gate metal pattern or a photoresist pattern on the first gate metal pattern as a mask.

[0050] As a result, a portion of the semiconductor pattern that does not overlap with the first gate metal pattern may be doped with impurities to form a doped region. In an embodiment, for example, the active pattern AP as a doped semiconductor pattern may include a first channel region C1 overlapping or corresponding to the first gate electrode GE1 and a second channel region C2 overlapping or corresponding to the second gate electrode GE2. The doped portion of the active pattern AP may define a source region and a drain region. In an embodiment, for example, the active pattern AP may include a first source region S1, a first drain region D1, a second source region S2, and a second drain region D2, which are adjacent to the first channel region C1 and the second channel region C2. However, the embodiment is not limited thereto. In an embodiment, for example, depending on the configuration of the pixel circuit of the pixel area PX, the active pattern AP may include at least three channel regions, at least three source regions, and at least three drain regions. The pixel circuit may include a gate electrode, a source electrode, and a drain electrode, as well as an active pattern AP, but is not limited thereto. In an embodiment, the pixel circuit may include an active pattern AP, a first gate metal pattern corresponding to the active pattern AP, and a second gate metal pattern in sequence from the base substrate 110.

[0051] The first insulating layer 120 may include an inorganic material (e.g., a first inorganic insulating layer) and may have a single-layer structure or a multi-layer structure. In an embodiment, for example, the first insulating layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, the first insulating layer 120 may include an insulating metal oxide, such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. In an embodiment, the first insulating layer 120 may include silicon oxide. The first insulating layer 120 may be referred to as a first gate insulating layer.

[0052] In an embodiment, for example, a first gate metal layer is provided or formed on the first insulating layer 120, and then patterned to provide or form a first gate metal pattern including a first gate electrode GE1 and a second gate electrode GE2. A second insulating layer 130 is provided or formed on the first gate metal pattern. A second gate metal layer is provided or formed on the second insulating layer 130, and then patterned to form a second gate metal pattern including a capacitor pattern CP (e.g., a capacitor electrode). A third insulating layer 140 is provided or formed on the second gate metal pattern.

[0053] The first gate metal layer and the second gate metal layer may each include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. In an embodiment, for example, the first gate metal layer and the second gate metal layer may each include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0054] In an embodiment, for example, at least a portion of the capacitor pattern CP may define a capacitor electrode of a storage capacitor. The second gate metal pattern may further include a signal wiring through which an electrical signal such as an initialization signal or a shielding pattern, etc., is transmitted.

[0055] The second insulating layer 130 and the third insulating layer 140 may each include an inorganic material (e.g., a second inorganic insulating layer and a third inorganic insulating layer), and may have a single-layer structure or a multi-layer structure. In an embodiment, for example, the second insulating layer 130 and the third insulating layer 140 may each include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, the second insulating layer 130 and the third insulating layer 140 may each include an insulating metal oxide, such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. In an embodiment, the second insulating layer 130 may include silicon nitride, and the third insulating layer 140 may include a lower layer including silicon oxide and an upper layer including silicon nitride, the upper layer being farther from the base substrate 110 than the lower layer. The second insulating layer 130 may be referred to as a second gate insulating layer, and the third insulating layer 140 may be referred to as a first interlayer insulating layer.

[0056] A first photoresist pattern PR1 is provided or formed on the third insulating layer 140. Figure 3A , the first photoresist pattern PR1 may include a first portion A1 and a second portion A2, which have different thicknesses from each other and are both disposed in the pixel region PX. In an embodiment, for example, the second portion A2 may overlap or correspond to a portion of the active pattern AP. The second thickness of the first photoresist pattern PR1 at the second portion A2 may be less than the first thickness at the first portion A1. The first photoresist pattern PR1 may include an upper surface in the first portion A1 and the second portion A2, which is farthest from the base substrate 110. The upper surface of the first photoresist pattern PR1 at the second portion A2 may be closer to the base substrate 110 than the upper surface at the first portion A1.

[0057] One or more of the above-mentioned layers may extend from the pixel area PX to the peripheral area PA, the bending area BA, and the connection area CA. Figure 3B , combined with Figure 3A , the isolation layer 112 , the buffer layer 114 , the first insulating layer 120 , the second insulating layer 130 , and the third insulating layer 140 may be disposed in the bending area BA.

[0058] The solid portion of the first photoresist pattern PR1 may not be disposed in the bending area BA (e.g., may be excluded from the bending area BA). In an embodiment, for example, the first photoresist pattern PR1 may include or define a first opening OP1 that overlaps or corresponds to the bending area BA. Therefore, the upper surface of the third insulating layer 140 may be exposed outside the first photoresist pattern PR1 at the bending area BA.

[0059] The first photoresist pattern PR1 having different thicknesses may be provided or formed by using half-tone exposure.

[0060] In an embodiment, the isolation layer 112, the buffer layer 114, the first insulating layer 120, the second insulating layer 130 and the third insulating layer 140 may be respectively referred to as a first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer and a fifth inorganic layer, or collectively referred to as inorganic layers.

[0061] refer to Figure 4, in a first etching process (e.g., a first inorganic layer etching process), an inorganic layer is etched in the bending area BA by using the first photoresist pattern PR1. In an embodiment, for example, the inorganic layer may be etched by a dry etching process. One or more inorganic layers may be etched at the same time (e.g., simultaneously), but is not limited thereto. In an embodiment, the method may include: at a first opening OP1, providing at least one of the inorganic layers etched in the bending area BA by a first inorganic layer etching process using the first photoresist pattern PR1 as a first mask.

[0062] The etching depth may be adjusted as needed. In an embodiment, the third insulating layer 140, the second insulating layer 130, and the first insulating layer 120 may be removed in the bending area BA. However, the embodiment is not limited thereto. The inorganic layer removed may vary depending on the original thickness of the inorganic layer and the etching depth. Figure 4 In this regard, for example, a thickness portion of the first insulating layer 120 may be retained in the bending area BA by etching, or a thickness portion of the buffer layer 114 may be further removed in the bending area BA. In an embodiment, for example, the sum of the thicknesses of the inorganic layers removed in the bending area BA may be approximately to about The sum of the removed thicknesses may define the etching depth. The etching depth may be adjusted depending on the etching depth of a subsequent second etching process.

[0063] refer to Figure 5A and Figure 5B , the first photoresist pattern PR1 may be partially removed to form a remaining photoresist pattern PR1', as shown by the solid line and the dotted line. In an embodiment, for example, the thickness portion of the first photoresist pattern PR1 may be completely reduced by an ashing process or the like. As a result, the first photoresist pattern PR1 at the second portion A2 may be completely removed, thereby providing or forming a second opening OP2 (e.g., a second remaining opening) overlapping or corresponding to a portion of the active pattern AP, and exposing the third insulating layer 140 to the outside of the first photoresist pattern PR1. In addition, the remaining photoresist pattern PR1' includes a first opening OP1' (e.g., a first remaining opening) having substantially the same planar shape as the first opening OP1' of the first photoresist pattern PR1.

[0064] refer to Fig. 6A and Figure 6B In the second etching process (eg, second inorganic layer etching process), the first etched inorganic layer is further etched in the bending area BA and the pixel area PX by using the remaining photoresist pattern PR1' as a remaining mask. In an embodiment, for example, the inorganic layer may be etched by a dry etching process.

[0065] In an embodiment, for example, the buffer layer 114 and the isolation layer 112 may be removed at the first opening OP1' in the bending area BA so that the upper surface of the base substrate 110 may be exposed outside the remaining photoresist pattern PR1', the third insulating layer 140, the second insulating layer 130, the first insulating layer 120, the buffer layer 114, and the isolation layer 112. In addition, the third insulating layer 140, the second insulating layer 130, and the first insulating layer 120 may be removed in the pixel area PX at the second opening OP2, thereby forming a first contact hole CT1 that exposes a portion of the active pattern AP outside the third insulating layer 140, the second insulating layer 130, and the first insulating layer 120. In an embodiment, the method may include providing a contact hole corresponding to the second opening OP2 and exposing this portion of the active pattern AP to the outside of the remaining photoresist pattern PR1', and a portion of the base substrate 110 in the bending area BA corresponding to the first remaining opening and exposed to the outside of the remaining photoresist pattern PR1' through a second inorganic layer etching process using the remaining photoresist pattern PR1' as a remaining mask.

[0066] In an embodiment, the sum of the thicknesses of the inorganic layers removed in the bending area BA in the second etching process may be less than the sum of the thicknesses of the inorganic layers removed in the bending area BA in the first etching process. In an embodiment, for example, the sum of the thicknesses of the inorganic layers removed in the bending area BA in the second etching process may be about 100 nm. to about In an embodiment, a second inorganic layer etching process using the remaining photoresist pattern PR1' as a remaining mask includes removing the sum of the inorganic layer thicknesses at the first remaining openings, and a first inorganic layer etching process using the first photoresist pattern PR1 as a first mask includes removing the sum of the inorganic layer thicknesses at the first opening OP1' which is greater than the sum of the inorganic layer thicknesses at the first remaining openings.

[0067] In an embodiment, the inorganic layer may be removed in the curved area BA by using a substantially identical mask (e.g., in the form of a photoresist pattern). Therefore, the side surfaces of the inorganic layer may be substantially continuously connected to each other at the boundary between the curved area BA and the area adjacent to the curved area BA (e.g., the peripheral area PA and the connection area CA). Therefore, the stacked structure of the inorganic layer may form a straightly extending side surface at the boundary without a protrusion protruding in the lateral direction. The side surfaces of the inorganic layer at the curved area BA may be coplanar with each other. The side surfaces of the inorganic layer at the curved area BA may form an inner angle (e.g., a taper angle) relative to the base substrate 110. In an embodiment, for example, the taper angle of the stacked structure including the coplanar side surfaces of the inorganic layer may be about 70 degrees (°) to about 90° or about 80° to about 90°. In an embodiment, each of the inorganic isolation layer, the first inorganic insulating layer, the second inorganic insulating layer, and the third inorganic insulating layer extends from the pixel area PX to define the inorganic layer in the peripheral area PA. A portion of the inorganic layer in the peripheral area PA is excluded in the curved area BA to define a remaining portion of the inorganic layer in the peripheral area PA. The remaining portion of the inorganic layer in the peripheral area PA defines side surfaces of the inorganic layer, which are coplanar and connected to each other at the boundary of the curved area BA formed with the remaining portion of the peripheral area PA. The side surfaces of the inorganic layer form a taper angle with the base substrate 110.

[0068] refer to Fig. 7A and Figure 7B , after removing the remaining photoresist pattern PR1', a source metal pattern is provided or formed on the third insulating layer 140. The source metal pattern may include a source pattern SP (e.g., a source electrode) and a transmission wiring TL. The source pattern SP and the transmission wiring TL may be in the same layer as each other. The source pattern SP may be in electrical contact with the active pattern AP through the first contact hole CT1 in the pixel area PX. The transmission wiring TL may be disposed in the bending area BA. The source metal pattern may further include a drain pattern electrically contacting the drain region of the active pattern AP to transmit an electrical signal (e.g., a driving voltage) to a light emitting diode as a light emitting element in the pixel area PX.

[0069] In an embodiment, the source pattern SP may be a power wiring that transmits a power supply voltage as an electrical signal. However, the embodiment is not limited thereto. In an embodiment, for example, the source pattern SP may be a data line that transmits a data signal as an electrical signal, or a connection pattern that transmits a source signal or a source voltage as an electrical signal.

[0070] In an embodiment, for example, a source metal layer is provided or formed on the third insulating layer 140 and then patterned to form a source metal pattern. In an embodiment, for example, the source metal pattern may include a metal, a metal alloy, a metal nitride, or a conductive metal oxide, etc. In an embodiment, for example, the source metal layer may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0071] refer to Fig. 8A , a fourth insulating layer 150 is provided or formed to cover the source metal pattern. In an embodiment, for example, the fourth insulating layer 150 may include an organic insulating material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, or epoxy resin. The fourth insulating layer 150 may be referred to as a through-hole insulating layer or an organic insulating layer.

[0072] The first electrode EL1 of the organic light emitting diode 200 and the pixel defining layer PXL may be provided or formed on the fourth insulating layer 150 .

[0073] The first electrode EL1 may be used as an anode of the organic light emitting diode 200. In an embodiment, for example, the first electrode EL1 may be provided or formed as a transmissive electrode or a reflective electrode according to the emission type of the display device 100. When the first electrode EL1 is a transmissive electrode, the first electrode EL1 may include indium tin oxide, indium zinc oxide, zinc tin oxide, indium oxide, zinc oxide, or tin oxide, etc. When the first electrode EL1 is a reflective electrode, the first electrode EL1 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or a combination thereof, and may have a stacked structure, which further includes a material that can be used for a transmissive electrode.

[0074] The pixel defining layer PXL may include or define an opening exposing at least a portion of the first electrode EL1 to the outside of the pixel defining layer PXL. In an implementation, for example, the pixel defining layer PXL may include an organic insulating material.

[0075] An organic light emitting layer OL of the organic light emitting diode 200 is provided or formed on the first electrode EL1. The organic light emitting layer OL may include at least an emission layer, and may further include at least one of a hole injection layer ("HIL"), a hole transport layer ("HTL"), an electron transport layer ("ETL"), and an electron injection layer ("EIL").

[0076] In an embodiment, the organic light emitting layer OL may emit red light, green light, or blue light. In an embodiment, the organic light emitting layer OL may emit white light. The organic light emitting layer OL emitting white light may have a multilayer structure including a red emission layer, a green emission layer, and a blue emission layer, or a single layer structure including a combination of a red emission material, a green emission material, and a blue emission material.

[0077] In an implementation, for example, the organic light emitting layer OL may be provided or formed by a screen printing method, an inkjet printing method, a vacuum deposition method, or the like.

[0078] The second electrode EL2 of the organic light emitting diode 200 is provided or formed on the organic light emitting layer OL. In an embodiment, the second electrode EL2 may be used as a cathode of the organic light emitting diode 200. In an embodiment, for example, the second electrode EL2 may be provided or formed as a transmissive electrode or a reflective electrode according to an emission type of the display device 100. In an embodiment, for example, when the second electrode EL2 is a reflective electrode, the second electrode EL2 may include a metal, a metal alloy, a metal nitride, a metal fluoride, a conductive metal oxide, or a combination thereof.

[0079] In an embodiment, for example, the second electrode EL2 may continuously extend across a plurality of pixel areas PX in the display area DA. In an embodiment, a capping layer and / or a barrier layer may be provided or formed on the second electrode EL2.

[0080] Thereafter, an encapsulation layer 210 may be provided or formed on the organic light emitting diode 200. The encapsulation layer 210 may have a stack structure of inorganic thin films 212 and 216 and an organic thin film 214.

[0081] In an implementation, for example, the organic thin film 214 may include a cured polymer resin such as poly (meth)acrylate or epoxy resin, or the like.

[0082] In an implementation, for example, the inorganic thin films 212 and 216 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof.

[0083] refer to Figure 8B, a filling member FL may be provided or formed to cover the transmission wiring TL in the bending area BA and fill the plane area from which the inorganic layer is removed. In an embodiment, for example, a filling member FL may be provided or formed in a process of providing or forming the fourth insulating layer 150 so that the filling member FL may include the same material as the fourth insulating layer 150. The fourth insulating layer 150 and the filling member FL may be in the same layer as each other. In an embodiment, at least a portion of the filling member FL may be provided or formed in a process of providing or forming the pixel defining layer PXL so that at least a portion of the filling member FL may include the same material as the pixel defining layer PXL. That is, the filling member FL may be in the same layer as the pixel defining layer PXL.

[0084] In an embodiment, if Figure 8C , a filling member FL including an organic material may be provided under the transmission wiring TL to fill the opening in the bending area BA. A protective layer PL may be further provided or formed to cover the transmission wiring TL. In an embodiment, for example, the filling member FL may be provided or formed in a separate process that is different from each of the processes of providing or forming the fourth insulating layer 150 and the pixel defining layer PXL. The protective layer PL may be provided or formed in the process of providing or forming the fourth insulating layer 150 or the pixel defining layer PXL.

[0085] In an embodiment, the thickness portion of the inorganic layer disposed in the pixel area PX and in the bending area BA may be removed simultaneously, such as by the same photolithography process. Therefore, an additional photolithography process for separately etching the inorganic layer in the bending area BA may be omitted.

[0086] In addition, since the stacked structure of the inorganic layer can define coplanar side surfaces at the boundary between the bending area BA and the area adjacent to the bending area BA without protrusions protruding in the lateral direction, the size of the peripheral area PA (e.g., non-display area) can be significantly reduced.

[0087] Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A and Fig. 15B is a cross-sectional view illustrating an embodiment of a method for providing or manufacturing the display device 100 . Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A An enlarged cross-sectional view of a pixel area PX of the display area DA may be shown, and Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 14C and Fig. 15B An enlarged cross-sectional view of the bending area BA and an area adjacent thereto may be shown.

[0088] refer to Fig. 9A and Fig. 9B , an isolation layer 112 and a buffer layer 114 are provided or formed on a base substrate 110 .

[0089] The first active pattern AP1 and a first insulating layer 120 covering the first active pattern AP1 are provided or formed on the buffer layer 114. A first gate metal pattern including a first gate electrode GE1 is provided or formed on the first insulating layer 120. In an embodiment, the first active pattern AP1 may include polycrystalline silicon (poly-Si).

[0090] In an embodiment, for example, the first active pattern AP1 may include a first channel region C1 overlapping the first gate electrode GE1, a first source region S1, and a first drain region D1. The first source region S1 and the first drain region D1 are adjacent to the first channel region C1 at opposite sides thereof, respectively.

[0091] In an embodiment, a first gate metal layer is provided or formed on the first insulating layer 120 and then patterned to form a first gate metal pattern including a first gate electrode GE1. A second insulating layer 132 is provided or formed on the first gate metal pattern. A second gate metal layer is provided or formed on the second insulating layer 132 and then patterned to form a second gate metal pattern including a capacitor pattern CP.

[0092] The second gate metal pattern may further include a bottom gate pattern BP. The capacitor pattern CP and the bottom gate pattern BP may be in the same layer. The bottom gate pattern BP may overlap with the second channel region C2 of the second active pattern AP2 disposed on the bottom gate pattern BP. The bottom gate pattern BP may block light entering from the lower surface of the second channel region C2 to reduce or effectively prevent degradation of the characteristics of the driving element including the second channel region C2. In an embodiment, for example, an electrical signal identical to a gate signal applied to the second gate electrode GE2 may be applied to the bottom gate pattern BP.

[0093] A third insulating layer 134 is provided or formed on the second gate metal pattern. A second active pattern AP2 is provided or formed on the third insulating layer 134. A fourth insulating layer 136 is provided or formed to cover the second active pattern AP2. A third gate metal pattern is provided or formed on the fourth insulating layer 136. A fifth insulating layer 142 is provided or formed to cover the third gate metal pattern.

[0094] The second active pattern AP2 includes a metal oxide semiconductor. In an embodiment, for example, the second active pattern AP2 may include a two-component compound (AB x ), ternary compounds (AB x C y ) or four-component compound (AB x C y D z ), which contains indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr) and / or magnesium (Mg). For example, the second active pattern AP2 may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO) or indium gallium tin oxide (IGTO), etc.

[0095] The third gate metal pattern may include a second gate electrode GE2 overlapping or corresponding to the second channel region C2 of the second active pattern AP2. The third gate metal pattern may include substantially the same material as the first gate metal pattern or the second gate metal pattern.

[0096] In an embodiment, for example, an oxide semiconductor pattern may be provided or formed on the third insulating layer 134. A fourth insulating layer 136 may be provided or formed to cover the oxide semiconductor pattern. A third gate metal pattern including a second gate electrode GE2 partially overlapping the oxide semiconductor pattern may be provided or formed on the fourth insulating layer 136. The oxide semiconductor pattern may be partially doped by using the second gate electrode GE2 or a photoresist pattern on the second gate electrode GE2 as a mask, thereby providing or forming a second source region S2 and a second drain region D2.

[0097] The first insulating layer 120, the second insulating layer 132, the third insulating layer 134, the fourth insulating layer 136, and the fifth insulating layer 142 may each include an inorganic material and may have a single-layer structure or a multi-layer structure. In an embodiment, for example, the first insulating layer 120, the second insulating layer 132, the third insulating layer 134, the fourth insulating layer 136, and the fifth insulating layer 142 may each include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, the first insulating layer 120, the second insulating layer 132, the third insulating layer 134, the fourth insulating layer 136, and the fifth insulating layer 142 may each include an insulating metal oxide, such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof.

[0098] In an embodiment, the first insulating layer 120 may include silicon oxide. The second insulating layer 132 may include silicon nitride, and the third insulating layer 134 may include a lower layer including silicon nitride and an upper layer including silicon oxide. The fourth insulating layer 136 may include silicon oxide, and the fifth insulating layer 142 may include a lower layer including silicon oxide and an upper layer including silicon nitride.

[0099] A first photoresist pattern PR1 is provided or formed on the fifth insulating layer 142. Fig. 9A , the first photoresist pattern PR1 may include a first portion A1 and a second portion A2, the first portion A1 and the second portion A2 having different thicknesses and disposed in the pixel region PX. In an embodiment, for example, the second portion A2 may overlap or correspond to a portion of the second active pattern AP2, and a height of an upper surface of the first photoresist pattern PR1 at the second portion A2 from a reference (such as an upper surface of the base substrate 110) may be less than a height of an upper surface of the first photoresist pattern PR1 at the first portion A1 from the reference. In addition, the first photoresist pattern PR1 may include or define a second opening OP2, which overlaps or corresponds to a portion of the first active pattern AP1 in the pixel region PX.

[0100] refer to Fig. 9B , the isolation layer 112, the buffer layer 114, the first insulating layer 120, the second insulating layer 132, the third insulating layer 134, the fourth insulating layer 136 and the fifth insulating layer 142 may each extend from the pixel area PX to define a corresponding extension portion disposed in the bending area BA.

[0101] The solid portion of the first photoresist pattern PR1 may not be disposed in the bending area BA. In an embodiment, for example, the first photoresist pattern PR1 may include or define a first opening OP1 overlapping the bending area BA. Therefore, the upper surface of the fifth insulating layer 142 may be exposed outside the first photoresist pattern PR1 at the bending area BA.

[0102] The first photoresist pattern PR1 having different thicknesses may be provided or formed by using half-tone exposure.

[0103] In an embodiment, the isolation layer 112, the buffer layer 114, the first insulating layer 120, the second insulating layer 132, the third insulating layer 134, the fourth insulating layer 136 and the fifth insulating layer 142 may be respectively referred to as a first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer, a fifth inorganic layer, a sixth inorganic layer and a seventh inorganic layer, or collectively referred to as inorganic layers.

[0104] refer to Fig. 10A and Fig. 10B In the first etching process, the inorganic layer is etched in the bending area BA at the first opening OP1 and in the pixel area PX at the second opening OP2 by using the first photoresist pattern PR1 as a first mask. In an embodiment, for example, the inorganic layer may be etched by a dry etching process.

[0105] The etching depth may be adjusted as needed. In an embodiment, the thickness portion of the fifth insulating layer 142 and the fourth insulating layer 136 may be removed in the bending area BA at the first opening OP1 and in the pixel area PX at the second opening OP2. In an embodiment, the first inorganic layer etching process using the first photoresist pattern PR1 as a first mask may further provide the following two: the bending area BA excluding the seventh inorganic layer and the sixth inorganic layer at the first opening OP1, and the seventh inorganic layer and the sixth inorganic layer excluded at the second opening OP2. However, the embodiment is not limited thereto.

[0106] The removed thickness of the inorganic layer may vary depending on the original thickness of the inorganic layer and / or the etching depth. Fig. 10A and Fig. 10B In this embodiment, for example, a thickness portion of the fourth insulating layer 136 may remain in the bending area BA and the pixel area PX instead of being completely removed, or a thickness portion of the third insulating layer 134 may be further removed in the bending area BA and the pixel area PX. In an embodiment, for example, the sum of the thickness of the removed portion of the inorganic layer in the first etching process may be about to about The etching depth may be adjusted depending on the etching depth of the subsequent second etching process.

[0107] refer to Fig.11A and Fig. 11B, the first photoresist pattern PR1 may be partially removed to form a remaining photoresist pattern PR1'. In an embodiment, for example, a thickness portion of the first photoresist pattern PR1 may be completely reduced by an ashing process, etc. As a result, the first photoresist pattern PR1 at the second portion A2 may be completely removed, thereby providing or forming a third opening OP3, the third opening OP3 overlapping a portion of the second active pattern AP2, and exposing the fifth insulating layer 142 to the outside of the remaining photoresist pattern PR1'. The remaining photoresist pattern PR1' may include or define a first opening OP1' and a second opening OP2', which have substantially the same planar shape as the first opening OP1 and the second opening OP2 of the first photoresist pattern PR1. In an embodiment, the remaining photoresist pattern PR1' may define a first remaining opening corresponding to the first opening OP1 in the bending area BA, a second remaining opening corresponding to the second opening OP2 in the pixel area PX, and a third opening OP3' corresponding to a portion of the second active pattern AP2 in the pixel area PX and extending to the inorganic layer in the pixel area PX.

[0108] refer to Fig. 12A and Fig. 12B In the second etching process, the first etched inorganic layer is further etched at the first opening OP1', the second opening OP2', and the third opening OP3' in the bending area BA and in the pixel area PX by using the remaining photoresist pattern PR1' as a remaining mask. In an embodiment, for example, the inorganic layer may be etched by a dry etching process.

[0109] In an embodiment, for example, the third insulating layer 134, the second insulating layer 132, and the first insulating layer 120 may be completely removed in the bending area BA at the first opening OP1', and at least a portion of the buffer layer 114 may be further removed. However, the embodiment is not limited thereto. In an embodiment, for example, the etching depth may be increased to further remove at least a portion of the isolation layer 112.

[0110] In addition, the third insulating layer 134, the second insulating layer 132 and the first insulating layer 120 can be removed in the pixel area PX at the second opening OP2' to form a first contact hole CT1, which exposes a portion of the first active pattern AP1 to the outside of the remaining photoresist pattern PR1', the fifth insulating layer 142, the fourth insulating layer 136, the third insulating layer 134, the second insulating layer 132 and the first insulating layer 120.

[0111] In addition, the fifth insulating layer 142 and the fourth insulating layer 136 may be removed in the pixel area PX at the third opening OP3' to form a second contact hole CT2 that exposes a portion of the second active pattern AP2 outside the remaining photoresist pattern PR1', the fifth insulating layer 142, and the fourth insulating layer 136. In an embodiment, the method may further include providing each of the following by a second inorganic layer etching process using the remaining photoresist pattern PR1' as a remaining mask: at least one of the inorganic layers at the first remaining opening, the at least one of the inorganic layers being etched to define the remaining inorganic layer in the bending area BA; the first contact hole CT1 that corresponds to the second opening OP2' and exposes the first active pattern AP1 outside the remaining photoresist pattern PR1'; and the second contact hole CT2 that corresponds to the third opening OP3' and exposes the second active pattern AP2 outside the remaining photoresist pattern PR1'.

[0112] refer to Fig.13A and Fig. 13B , after removing the remaining photoresist pattern PR1 ′, a first source metal pattern is provided or formed on the fifth insulating layer 142 .

[0113] The first source metal pattern may include a first drain pattern DP1 (e.g., a first drain electrode), a source pattern SP, and a second drain pattern DP2 (e.g., a second drain electrode). The first drain pattern DP1 may be in electrical contact with the first active pattern AP1 at or through the first contact hole CT1 in the pixel region PX. The source pattern SP and the second drain pattern DP2 may be in electrical contact with the second active pattern AP2 at or through the second contact hole CT2 in the pixel region PX.

[0114] In an embodiment, for example, the first drain pattern DP1 may be in electrical contact with the first drain region D1 of the first active pattern AP1 to transmit a driving voltage to the light emitting diode. In an embodiment, for example, the source pattern SP may transmit a source signal (such as an initialization voltage) as an electrical signal. In an embodiment, for example, the second drain pattern DP2 may be electrically connected to the second gate electrode GE2 or the second drain region D2.

[0115] The first source metal pattern may further include a first transfer pattern TP1 and a second transfer pattern TP2. The first transfer pattern TP1 may be disposed in the connection area CA. The second transfer pattern TP2 may be disposed in the peripheral area PA. The first transfer pattern TP1 in the connection area CA may transmit a drive signal or a power supply voltage as an electrical signal to a transfer wiring TL provided or formed in the bending area BA. The second transfer pattern TP2 in the peripheral area PA may transmit a drive signal or a power supply voltage as an electrical signal from the transfer wiring TL in the bending area BA to the pixel area PX in the display area DA.

[0116] In an embodiment, for example, a first source metal layer is provided or formed on the fifth insulating layer 142. A second photoresist pattern PR2 is provided or formed on the first source metal layer. The second photoresist pattern PR2 may have a planar shape corresponding to the first source metal pattern. Therefore, the second photoresist pattern PR2 may not be disposed in the bending area BA (e.g., excluded from the bending area BA).

[0117] The first source metal layer is etched by using the second photoresist pattern PR2 as a second mask to provide or form a first source metal pattern. In an embodiment, the first source metal layer may be etched by a dry etching process. The first drain pattern DP1, the source pattern SP, the second drain pattern DP2, the first transfer pattern TP1, and the second transfer pattern TP2 may be in the same layer as each other.

[0118] refer to Fig. 13B , when etching the first source metal layer, the remaining inorganic layer in the bending area BA may be further etched. In an embodiment, for example, after removing the first source metal layer in the bending area BA, at least a portion of the thickness of the isolation layer 112 may be removed by overetching. The overetching (time) may be increased to completely remove the isolation layer 112 in the bending area BA. However, the overetching is performed so as to prevent or minimize damage to the fifth insulating layer 142 in the pixel area PX. In an embodiment, for example, the etching depth of the inorganic layer by overetching may be about to about

[0120] refer to Fig.14A and Fig. 14B , remove the second photoresist pattern PR2, and provide or form a sixth insulating layer 152 to cover the first source metal pattern. The sixth insulating layer 152 may include an organic insulating material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, or epoxy resin. The sixth insulating layer 152 may be referred to as a first through hole insulating layer or a first organic insulating layer.

[0121] A filling member FL may be provided or formed in the bending area BA to fill the area where the inorganic layer is removed. In an embodiment, the first organic insulating layer may define a filling member FL that fills the entire area in the bending area BA in which a portion of the remaining inorganic layer is removed. The filling member FL may include an organic material. In an embodiment, for example, the filling member FL may be provided or formed in a process of providing or forming the sixth insulating layer 152 so that the filling member FL may include the same material as the sixth insulating layer 152. The sixth insulating layer 152 and the filling member FL may be in the same layer as each other.

[0122] A second source metal pattern is provided or formed on the sixth insulating layer 152. In an embodiment, for example, the second source metal pattern may include a connection electrode CE electrically contacting the first drain pattern DP1 at a contact hole in the sixth insulating layer 152. In addition, the second source metal pattern may further include a power wiring PL that transmits a power voltage as an electrical signal. In an embodiment, for example, the second source metal pattern may include the same material as the first source metal pattern.

[0123] refer to Fig. 14B The second source metal pattern may further include a transmission wiring TL disposed in the bending area BA. The transmission wiring TL may be disposed on the filling member FL and may be electrically connected to the transmission patterns TP1 and TP2 disposed in the connection area CA and the peripheral area PA, respectively.

[0124] refer to Fig. 14B , a portion of the isolation layer 112 may remain in the bending area BA. However, the embodiment is not limited thereto. Fig. 14C , for example, the bending area BA may exclude all remaining inorganic layers (e.g., the isolation layer 112) in the bending area BA. When the isolation layer 112 is completely removed in the bending area BA by over-etching in the process of providing or forming the first source metal pattern, the filling member FL may contact the base substrate 110. When in contact, the elements may form an interface therebetween.

[0125] refer to Fig.15A A seventh insulating layer 162 is provided or formed to cover the second source metal pattern. The seventh insulating layer 162 includes an organic insulating material. The seventh insulating layer 162 may be referred to as a second through hole insulating layer or a second organic insulating layer.

[0126] The first electrode EL1 and the pixel defining layer PXL of the organic light emitting diode 200 are provided or formed on the seventh insulating layer 162. The organic light emitting layer OL of the organic light emitting diode 200 is provided or formed on the first electrode EL1. The second electrode EL2 of the organic light emitting diode 200 is provided or formed on the organic light emitting layer OL.

[0127] An encapsulation layer 210 may be formed on the organic light emitting diode 200. In an embodiment, for example, the encapsulation layer 210 may have a stacked structure including inorganic thin films 212 and 216 and an organic thin film 214. In an embodiment, the pixel circuit may include, from the base substrate 110, a first active pattern AP1, a first gate metal pattern corresponding to the first active pattern AP1, a second gate metal pattern, a second active pattern AP2 corresponding to the second gate metal pattern, and a third gate metal pattern.

[0128] refer to Fig. 15B , a protection layer PL may be provided or formed to cover the transmission wiring TL in the bending area BA. The protection layer PL may include an organic material. In an embodiment, for example, a protection layer PL may be provided or formed in a process of forming the seventh insulating layer 162 so that the protection layer PL may include the same material as the seventh insulating layer 162 and may be in the same layer as the seventh insulating layer 162. In an embodiment, at least a portion of the protection layer PL may be provided or formed in a process of providing or forming the pixel defining layer PXL so that the protection layer PL may include the same material as the pixel defining layer PXL and may be in the same layer as the pixel defining layer PXL.

[0129] According to an embodiment, the thickness portion of the inorganic layer disposed in the pixel region PX and in the bending region BA may be excluded or removed by the same photolithography process. The remaining thickness portion of the inorganic layer may be removed by over-etching in a subsequent etching process. Therefore, an additional photolithography process for etching the inorganic layer in the bending region BA alone may be removed.

[0130] The embodiments may be applied to various display devices. One or more embodiments may be applied to a vehicle display device, a ship display device, an aircraft display device, a portable communication device, a display device for display or for information transmission, a medical display device, etc.

[0131] The foregoing is an illustration of an embodiment and should not be construed as limiting it. Although embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and features of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the present invention, as set forth in the appended claims and their equivalents.

Claims

1. A method for providing a display device, the method comprising: providing a base substrate including a bending area and a display area, the base substrate being bendable at the bending area, and the display area including a pixel area; In the pixel region there is provided: A pixel circuit, the pixel circuit comprising, in order from the base substrate: a first active pattern, a first gate metal pattern corresponding to the first active pattern, a second gate metal pattern, a second active pattern corresponding to the second gate metal pattern, and a third gate metal pattern; a first inorganic layer and a second inorganic layer between the base substrate and the first active pattern; a third inorganic layer between the first active pattern and the first gate metal pattern; a fourth inorganic layer between the first gate metal pattern and the second gate metal pattern; a fifth inorganic layer between the second gate metal pattern and the second active pattern; a sixth inorganic layer between the second active pattern and the third gate metal pattern; and a seventh inorganic layer covering the third gate metal pattern, in: The first to seventh inorganic layers in the pixel region define an inorganic layer in the pixel region, and Each of the first to seventh inorganic layers in the pixel region extends to the bending region to define an inorganic layer in the bending region; A first photoresist pattern is provided on the seventh inorganic layer in the pixel region and the bending region, the first photoresist pattern defining: a first opening corresponding to the bending region and extending to the inorganic layer in the bending region, and a second opening corresponding to a portion of the second active pattern and extending to the inorganic layer in the pixel region; The first inorganic layer etching process using the first photoresist pattern as a first mask provides both of the following: at least one of the inorganic layers etched in the curved region at the first opening, and at least one of the inorganic layers etched in the pixel region at the second opening; Providing a remaining photoresist pattern by reducing a thickness of the first photoresist pattern in the pixel region and the bending region, the remaining photoresist pattern defining: a first remaining opening, the first remaining opening corresponding to the first opening in the bending region, a second remaining opening, the second remaining opening corresponding to the second opening in the pixel area, and a third opening corresponding to a portion of the second active pattern in the pixel area and extending to the inorganic layer in the pixel area; and Each of the following is provided by a second inorganic layer etching process using the remaining photoresist pattern as a remaining mask: at least one of the inorganic layers at the first remaining opening, the at least one of the inorganic layers being etched to define a remaining inorganic layer in the curved region, a first contact hole corresponding to the second opening and exposing the first active pattern outside the remaining photoresist pattern, and A second contact hole corresponds to the third opening and exposes the second active pattern outside the remaining photoresist pattern. 2 . The method of claim 1 , wherein the first to seventh inorganic layers each include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

3. The method of claim 1, wherein the first inorganic layer etching process using the first photoresist pattern as the first mask further provides both of the following: At the first opening, the bending regions of the seventh inorganic layer and the sixth inorganic layer are excluded, and The seventh inorganic layer and the sixth inorganic layer are excluded at the second opening.

4. The method of claim 1, further comprising: provided in the bending region and the pixel region, a first source metal layer on the seventh inorganic layer, and a second photoresist pattern on the first source metal layer; as well as By etching the first source metal layer using the second photoresist pattern as a second mask, both of the following are provided: a first source metal pattern, and The bent region excludes at least a portion of the remaining inorganic layer in the bent region. The method of claim 4 , wherein the curved region excludes all of the remaining inorganic layer in the curved region.

6. The method of claim 4, wherein the first source metal pattern comprises: a drain pattern electrically connected to the first active pattern at the first contact hole, and A source pattern electrically connected to the second active pattern at the second contact hole.

7. The method of claim 4, further comprising: providing a first organic insulating layer covering the first source metal pattern; and A second source metal pattern is provided on the first organic insulating layer.

8. The method of claim 7, wherein: The first organic insulating layer defines a filling member that fills the entire region in the bent region from which the at least a portion of the remaining inorganic layer is removed, and The second source metal pattern includes a transmission wiring that covers the filling member in the bending region, and an electrical signal is provided from outside the bending region to the pixel region through the transmission wiring.

9. The method of claim 1, wherein: The first active pattern includes polysilicon, and The second active pattern includes metal oxide.

10. A display device, comprising: A base substrate, the base substrate comprising: A display area including pixel areas, and a peripheral region adjacent to the display region and including a bending region at which the base substrate is bendable, the bending region forming a boundary with a remaining portion of the peripheral region; In the pixel area, the pixel circuit includes an active pattern, a first gate metal pattern corresponding to the active pattern, a second gate metal pattern, a source metal pattern and an organic light emitting diode in sequence from the base substrate; an inorganic isolation layer between the base substrate and the active pattern; a first inorganic insulating layer between the active pattern and the first gate metal pattern; a second inorganic insulating layer between the first gate metal pattern and the second gate metal pattern; a third inorganic insulating layer between the second gate metal pattern and the source metal pattern; and a through-hole insulating layer between the source metal pattern and the organic light emitting diode, in: Each of the inorganic isolation layer, the first inorganic insulating layer, the second inorganic insulating layer, and the third inorganic insulating layer extends from the pixel region to define an inorganic layer in the peripheral region, A portion of the inorganic layer in the peripheral region is excluded in the bending region to define a remaining portion of the inorganic layer in the peripheral region, and The remaining portion of the inorganic layer in the peripheral region defines side surfaces of the inorganic layer, and the side surfaces of the inorganic layer are coplanar with each other and connected at the boundary of the curved region formed with the remaining portion of the peripheral region.

11. The display device according to claim 10, wherein: The side surface of the inorganic layer forms a taper angle with the base substrate, and The cone angle is 70° to 90°.

12. The display device according to claim 10, further comprising: an inorganic buffer layer between the inorganic isolation layer and the active pattern. 13 . The display device of claim 12 , wherein the inorganic isolation layer, the inorganic buffer layer, the first inorganic insulating layer, the second inorganic insulating layer, and the third inorganic insulating layer each include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

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