Silicon through hole structure and manufacturing method thereof

Abstract

The invention relates to a silicon through hole structure and a manufacturing method thereof. The structure comprises a bonding layer; the bonding pad is arranged on the bonding layer; the first insulating layer is arranged on the bonding layer and the bonding pad, and a first opening is formed in the first insulating layer; the wafer is arranged on the first insulating layer, a through hole is formed in the wafer, and the size of an opening of the through hole is larger than that of the first opening; the second insulating layer is arranged on the upper surface and the side surface of the wafer; and the interconnection structure is arranged on the second insulating layer and the bonding pad, and the interconnection structure is electrically connected with the bonding pad. According to the silicon through hole structure provided by the invention, the dry film is used as a mask during windowing of the insulating layer, and the size of the opening of the dry film is controlled, so that the size of the opening of the insulating layer is smaller than that of the opening of the through hole, notch generation during windowing of the insulating layer can be avoided, the windowing process difficulty is reduced, and the product yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a through silicon via structure and a manufacturing method thereof. Background Art

[0002] The demand of mobile device manufacturers for miniaturization, low cost and high integration of products has led to requirements for the cost, performance, integration and functionality of wafer-level packaging of related chips, as well as system-level packaging solutions. In system-level packaging, in order to realize the functions of the packaging structure, several types of heterogeneous chips or passive devices are often involved in a packaging structure. Through Silicon Via (TSV) adapter boards based on vertical through-hole interconnection and other processes are a better direction for system-level packaging because of their advantages such as short global interconnection, low delay, low power consumption, high bandwidth and high integration.

[0003] For three-dimensional integrated circuits, TSV processes are divided into Via-First, Via-Middle, and Via-Last. The Via-First process generally refers to processing TSV on a silicon wafer first, and then processing other devices including circuits; the Via-Middle process generally refers to the formation of TSV between device processing and back-end interconnection processing; the Via-Last process refers to TSV after all IC factory processes are completed, and can be completed independently by a wafer-level packaging factory.

[0004] Compared with the Via-first process and the Via-Middle process, the Via-Last process has the advantages of low cost and high modularity, and has significant advantages in three-dimensional integrated interconnection. However, the existing Via-Last process also has certain limitations, such as high process difficulty and large through-hole size. In terms of process difficulty, due to the uniformity of the thickness of the Si wafer before the incoming material, it is easy to produce a notch at the bottom of the TSV during TSV etching. When opening the window in the insulating layer, in order to ensure that the insulating layer is fully opened, a large over-etching amount needs to be increased, and notch is also easy to produce at this time. The generation of Notch will cause TSV insulation problems and affect product yield. At the same time, when the Via-Las process is used to make through holes in small-sized pads, the structure of large TSV switching to small TSV can only be used on the same layer of Si wafer, so that the interconnection metal of the through hole will not be abnormal due to the growth of metal grains in the subsequent process of the wafer. However, when using the large TSV switching to small TSV solution in the Si substrate, there are problems such as high technical difficulty, complex process flow, and high cost. Summary of the invention

[0005] In view of some or all of the problems in the prior art, the present invention provides a through silicon via structure, which includes:

[0006] Bonding layer;

[0007] A pad, the pad being arranged on the bonding layer;

[0008] A first insulating layer, wherein the first insulating layer is arranged on the bonding layer and the pad, and a first opening is arranged in the first insulating layer;

[0009] A wafer, wherein the wafer is arranged on the first insulating layer, a through hole is arranged in the wafer, and an opening size of the through hole is larger than a size of the first opening;

[0010] a second insulating layer, the second insulating layer being arranged on the upper surface and side surfaces of the wafer;

[0011] An interconnection structure is arranged on the second insulating layer and the pad, and the interconnection structure is electrically connected to the pad.

[0012] Furthermore, the through silicon via structure further comprises a carrier wafer;

[0013] The carrier is arranged under the bonding layer, and the carrier is a glass sheet, a silicon sheet, a sapphire sheet, or a metal sheet.

[0014] Furthermore, the material of the bonding layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or organic bonding adhesive.

[0015] Furthermore, the material of the pad includes one or more of copper, nickel, tin, silver, aluminum, or titanium.

[0016] Further, the wafer includes a chip module;

[0017] The chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

[0018] Further, the opening size of the through hole is 5 μm-300 μm; and / or

[0019] The size of the first opening is 3 μm-270 μm.

[0020] Further, the material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride; and / or

[0021] The material of the second insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum nitride.

[0022] Furthermore, the material of the interconnect structure includes one or more of copper, tungsten, aluminum, silver or titanium.

[0023] The present invention also provides a method for manufacturing a through silicon via structure, the method comprising the following steps:

[0024] Bonding the wafer to a carrier, arranging a bonding layer on the carrier, arranging a pad on the bonding layer, and arranging a first insulating layer on the bonding layer and the pad;

[0025] coating a photoresist on the wafer;

[0026] exposing and developing the photoresist;

[0027] Etching the wafer to the first insulating layer to form a through hole;

[0028] removing the photoresist;

[0029] depositing a second insulating layer, pressing a dry film onto the wafer;

[0030] exposing and developing the dry film, wherein the opening size of the dry film is smaller than the opening size of the through hole;

[0031] Etching the first insulating layer and the second insulating layer to remove the dry film;

[0032] An interconnection structure is fabricated on the second insulating layer and the pad to form a through silicon via structure.

[0033] Furthermore, the wafer is etched using a Bosch process.

[0034] The technical solution provided by the present invention has the following beneficial effects:

[0035] 1. The silicon through via structure provided by the present invention, based on the existing via-last through hole preparation, adopts a dry film as a window opening mask when opening a window in the insulating layer, controls the size of the dry film opening so that the size of the dry film opening is smaller than the size of the through hole opening, thereby obtaining an opening size of the opened insulating layer smaller than the size of the through hole opening, which can avoid the generation of notches when opening a window in the insulating layer, reduce the difficulty of the window opening process, and improve the product yield.

[0036] 2. The through silicon via structure provided by the present invention can accurately open a window on the top of a small-sized pad by controlling the size of the dry film opening, thereby meeting the production requirements of the via-last process for a small-sized pad. Compared with the large TSV to small TSV structure on the same Si substrate, the cost is lower and the process is simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0038] Figure 1 A schematic cross-sectional view of a through silicon via structure according to an embodiment of the present invention is shown;

[0039] Figure 2 A cross-sectional schematic diagram of a through silicon via structure according to another embodiment of the present invention is shown;

[0040] Figure 3 A schematic diagram showing a process of a method for manufacturing a through silicon via structure according to an embodiment of the present invention; and

[0041] Figure 4a-4i A schematic cross-sectional view of a process for forming a through silicon via structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0043] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0044] In this specification, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." only indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0045] In this specification, unless otherwise specified, "upper surface" and "side surface" are only used to describe the surfaces of the same component. In addition, "first", "second" and "third" are only used to distinguish and do not include differences in size.

[0046] In this specification, unless otherwise specified, the quantifiers "a", "an" do not exclude the presence of a plurality of elements, and the quantifiers "plurality" and "multiple" refer to one or more than one elements.

[0047] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0048] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0049] Figure 1 A cross-sectional schematic diagram of a through silicon via structure according to an embodiment of the present invention is shown. Figure 2 A cross-sectional schematic diagram of a through silicon via structure according to another embodiment of the present invention is shown. Figure 1 This corresponds to the case where the pad 104 is larger in size. Figure 2 This corresponds to the case where the pad 104 is smaller in size. Figure 1 and 2 As shown, the silicon through hole structure includes a wafer 101, a first insulating layer 102, a bonding layer 103, a pad 104, a carrier 105, a second insulating layer 108, and an interconnection structure 110. The carrier 105 is arranged under the bonding layer 103. In one embodiment of the present invention, the carrier 105 can be a glass sheet or a silicon sheet or a sapphire sheet or a metal sheet. The pad 104 is arranged in or on the bonding layer 103. The first insulating layer 102 is arranged on the bonding layer 103 and the pad 104, and a first opening is arranged in the first insulating layer 102, that is, the position where the first insulating layer 102 is disconnected in the through hole 107 in the figure. The wafer 101 is arranged on the first insulating layer 102, and the through hole 107 is arranged in the wafer 101, and the opening size of the through hole 1107 is larger than the size of the first opening. The second insulating layer 108 covers the upper surface and side surfaces of the wafer 101 and is also arranged in the area of ​​the first insulating layer 102 not covered by the wafer 101. The interconnection structure 110 is arranged on the second insulating layer 108 and the pad 104 and is electrically connected to the pad 104.

[0050] In one embodiment of the present invention, the wafer 101 may be a silicon wafer, a sapphire wafer, a silicon carbide wafer, a gallium nitride wafer, or a gallium arsenide wafer.

[0051] In one embodiment of the present invention, the material of the bonding layer 103 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or an organic bonding adhesive.

[0052] In one embodiment of the present invention, the material of the pad 104 may include one or more of copper, nickel, tin, silver, aluminum, or titanium.

[0053] In one embodiment of the present invention, the wafer 101 includes a chip module in the area without the through hole 107, and the chip module may include a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types. In one embodiment of the present invention, the chip may be a logic chip such as a CPU, a DSP, a GPU, or an FPGA, or a storage chip such as a DRAM, a Flash, or an HBM, or other types of chips such as SoC or sensors (such as MEMS sensors, etc.).

[0054] In one embodiment of the present invention, the opening size of the through hole 107 is 5 μm-300 μm; and / or the size of the first opening is 3 μm-270 μm.

[0055] In one embodiment of the present invention, the material of the first insulating layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride or aluminum nitride; and / or the material of the second insulating layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride or aluminum nitride.

[0056] In one embodiment of the present invention, the material of the interconnect structure 110 includes one or more of copper, tungsten, aluminum, silver, or titanium.

[0057] Figure 3 A schematic flow chart of a method for manufacturing a through silicon via structure according to an embodiment of the present invention is shown. Figure 4a-4i A schematic cross-sectional diagram of a process for forming a through silicon via structure according to an embodiment of the present invention is shown. Figure 3 and Figure 4a-4i A method for manufacturing a through silicon via structure of the present invention is described.

[0058] First, the wafer 101 is bonded to the carrier 105, as shown in FIG. Figure 4aAs shown. The bonding layer 103 is arranged on the carrier 105, the pad 104 is arranged in or on the bonding layer 103, and the first insulating layer 102 is arranged on the bonding layer 103 and the pad 104. In one embodiment of the present invention, the wafer 101 can be a silicon wafer or a sapphire wafer or a silicon carbide wafer or a gallium nitride wafer or a gallium arsenide wafer. In one embodiment of the present invention, the material of the first insulating layer 102 includes one or more of silicon oxide or silicon nitride or silicon oxynitride or aluminum nitride. In one embodiment of the present invention, the material of the bonding layer 103 can include one or more of silicon oxide or silicon nitride or silicon oxynitride or organic bonding glue. In one embodiment of the present invention, the material of the pad 104 can include one or more of copper or nickel or tin or silver or aluminum or titanium. In one embodiment of the present invention, the carrier 105 can be a glass sheet or a silicon sheet or a sapphire sheet or a metal sheet.

[0059] Next, a photoresist 106 is coated on the wafer 101. Figure 4b In one embodiment of the present invention, the photoresist 106 may be a positive photoresist or a negative photoresist, and the photoresist 106 may be applied by spin coating or spray coating.

[0060] Next, the photoresist 106 is exposed and developed to reveal the through hole pattern. Figure 4c shown.

[0061] Next, the wafer 101 is etched to the first insulating layer 102 to form a through hole 107, such as Figure 4d As shown. In one embodiment of the present invention, the Bosch process is used to etch the wafer 101 to form the through hole 107, the etching process gas is SF6, and the passivation process gas is C4F8. In one embodiment of the present invention, the opening size of the through hole 107 is 5μm-300μm. In one embodiment of the present invention, the wafer 101 includes a chip module in an area without the through hole 107, and the chip module may include a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types. In one embodiment of the present invention, the chip may be a logic chip such as a CPU, DSP, GPU, FPGA, or a storage chip such as a DRAM, Flash, HBM, or other types of chips such as SoC or sensors (such as MEMS sensors, etc.).

[0062] Next, the photoresist 106 is removed, as shown in FIG. Figure 4e In one embodiment of the present invention, the photoresist 106 on the surface of the wafer 101 is removed by dry stripping or wet stripping, the gas used in the dry stripping is O2 or O2+CF4, and the liquid used in the wet stripping is dimethyl sulfoxide.

[0063] Next, a second insulating layer 108 is deposited, and a dry film 109 is pressed onto the wafer 101. Figure 4f As shown. The second insulating layer 108 is mainly used for insulating protection of the upper surface of the wafer and the sidewalls of the through-hole. In one embodiment of the present invention, the second insulating layer 108 is deposited using a plasma enhanced chemical vapor deposition (PECVD) process. In one embodiment of the present invention, the material of the second insulating layer 108 includes one or more of silicon oxide or silicon nitride or silicon oxynitride or aluminum nitride. The dry film here is a solid photoresist, and pressing the dry film specifically involves softening the dry film at a certain temperature and pressure and then bonding it to the wafer surface, such as a temperature of 70-100°C and a pressure of 1-4kg.

[0064] Next, the dry film 109 is exposed and developed, and the opening size of the dry film 109 is smaller than the opening size of the through hole 107, such as Figure 4g shown.

[0065] Next, the first insulating layer 102 and the second insulating layer 108 are etched to remove the dry film 109. Figure 4h After etching the first insulating layer 102 and the second insulating layer 108, a first opening of the first insulating layer 102 is formed. In one embodiment of the present invention, the first opening of the first insulating layer 102 is smaller than the opening of the through hole 107, and the size of the first opening of the first insulating layer 102 is 3 μm-270 μm.

[0066] Finally, an interconnection structure 110 is fabricated on the second insulating layer 108 and the pad 104 to form a through silicon via structure, such as Figure 4i The interconnection structure 110 is electrically connected to the pad 104, and can lead the electrical signal on the pad 104 to the upper surface of the wafer 101. In one embodiment of the present invention, the material of the interconnection structure includes one or more of copper, tungsten, aluminum, silver, or titanium.

[0067] The silicon through via structure provided by the present invention, based on the existing via-last through hole preparation, adopts a dry film as a window opening mask when opening a window in the insulating layer, controls the size of the dry film opening so that the size of the dry film opening is smaller than the size of the through hole opening, thereby obtaining an opening size of the opened insulating layer smaller than the size of the through hole opening, which can avoid the generation of notches when opening a window in the insulating layer, reduce the difficulty of the window opening process, and improve the product yield; by controlling the size of the dry film opening, the top of the small-sized pad can be accurately opened to meet the production requirements of the via-last process of the small-sized pad, and compared with the large TSV to small TSV structure on the same Si substrate, the cost is lower and the process is simpler.

[0068] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A through silicon via structure, characterized in that: include: Bonding layer; A pad, the pad being arranged on the bonding layer; A first insulating layer, wherein the first insulating layer is arranged on the bonding layer and the pad, and a first opening is arranged in the first insulating layer; A wafer, wherein the wafer is arranged on the first insulating layer, a through hole is arranged in the wafer, and an opening size of the through hole is larger than a size of the first opening; a second insulating layer, the second insulating layer being arranged on the upper surface and side surfaces of the wafer; An interconnection structure is arranged on the second insulating layer and the pad, and the interconnection structure is electrically connected to the pad.

2. The through silicon via structure according to claim 1, characterized in that: Also included are slides; The carrier is arranged under the bonding layer, and the carrier is a glass sheet, a silicon sheet, a sapphire sheet, or a metal sheet.

3. The through silicon via structure according to claim 1, characterized in that: The material of the bonding layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride or organic bonding glue.

4. The through silicon via structure according to claim 1, characterized in that: The material of the pad includes one or more of copper, nickel, tin, silver, aluminum, and titanium.

5. The through silicon via structure according to claim 1, characterized in that: The wafer includes a chip module; The chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

6. The through silicon via structure according to claim 1, characterized in that: The opening size of the through hole is 5 μm-300 μm; and / or The size of the first opening is 3 μm-270 μm.

7. The through silicon via structure according to claim 1, characterized in that: The material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride; and / or The material of the second insulating layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum nitride.

8. The through silicon via structure according to claim 1, characterized in that: The material of the interconnect structure includes one or more of copper, tungsten, aluminum, silver, or titanium.

9. A method for manufacturing a through silicon via structure according to any one of claims 1 to 8, characterized in that: The steps include: Bonding the wafer to a carrier, arranging a bonding layer on the carrier, arranging a pad on the bonding layer, and arranging a first insulating layer on the bonding layer and the pad; coating a photoresist on the wafer; exposing and developing the photoresist; Etching the wafer to the first insulating layer to form a through hole; removing the photoresist; depositing a second insulating layer, pressing a dry film onto the wafer; exposing and developing the dry film, wherein the opening size of the dry film is smaller than the opening size of the through hole; Etching the first insulating layer and the second insulating layer to remove the dry film; An interconnection structure is fabricated on the second insulating layer and the pad to form a through silicon via structure.

10. The method for manufacturing a through silicon via structure according to claim 9, characterized in that: The wafer was etched using the Bosch process.

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