Silicon through hole structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor structures, and discloses a through silicon via structure and a preparation method thereof.The through silicon via structure comprises a silicon wafer, and a plurality of grooves are formed in the surface of one side of the silicon wafer; the plurality of dielectric layers are sequentially stacked and are positioned on the bottom surfaces and the side surfaces of the grooves and the surface of the silicon wafer between the adjacent grooves; the dielectric layer is made of an electrical insulating material; the metal layer is located in the groove and fills the groove; the thermal expansion coefficient of the dielectric layer is smaller than that of the metal layer; the thermal expansion coefficients of the dielectric layers are increased layer by layer in the direction from the silicon wafer to the metal layer. Compared with the prior art, the stress between the metal layer and the dielectric layer and between the dielectric layer and the silicon wafer can be reduced, the risks of cracks and layering are reduced, and the reliability and the electrical performance of the device are improved; and a stronger and wider-band insulation barrier can be provided between the metal layer and the silicon wafer, and the long-term reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a through silicon via structure and a preparation method thereof. Background Art

[0002] Through Silicon Via (TSV) technology is a feasible method to achieve three-dimensional WLP (wafer level packaging) and 3D integration. In 3D chip stacking technology, through silicon via technology has attracted much attention. It provides a method to produce overall high-performance interconnection integration. At present, the mainstream filling method for through silicon vias or blind vias is copper electroplating filling. Copper electroplating filling not only requires a short electroplating time, but also requires thin copper surface to achieve pore-free TSV filling. In the electroplating process, Cu can achieve gapless filling through bottom up filling or super filling. Due to the large mismatch in the coefficient of thermal expansion (CTE) between Cu material and dielectric-based low silicon material. The large stress between Cu / dielectric layer (such as SiO2) and dielectric layer / Si substrate will affect the occurrence of cracks and delamination, affecting the reliability and electrical performance of the device.

[0003] Therefore, a solution is needed to reduce the stress between Cu and the dielectric layer, and between the dielectric layer and the Si substrate, and reduce the risk of cracks and delamination. Summary of the invention

[0004] In view of this, the present invention provides a through silicon via structure and a preparation method thereof to solve the problem in the related art that large stress exists between the Cu / dielectric layer (such as SiO2) and the dielectric layer / Si substrate of the through silicon via, which may affect the occurrence of cracks and delamination, thereby affecting the reliability and electrical performance of the device.

[0005] In a first aspect, the present invention provides a through silicon via structure, the through silicon via structure comprising:

[0006] A silicon wafer, wherein a plurality of grooves are present on one surface of the silicon wafer;

[0007] A plurality of dielectric layers stacked in sequence are located on the bottom and side surfaces of the grooves, and on the surface of the silicon wafer between adjacent grooves; the material of the dielectric layers is an electrical insulating material;

[0008] The metal layer is located inside the groove and fills the groove; the thermal expansion coefficient of the dielectric layer is smaller than the thermal expansion coefficient of the metal layer; and the thermal expansion coefficient of the dielectric layer increases layer by layer from the silicon wafer to the metal layer.

[0009] The silicon through hole structure provided by the present invention, on the one hand, by setting multiple dielectric layers between the metal layer and the silicon wafer, the thermal expansion coefficient of the dielectric layer is less than the thermal expansion coefficient of the metal layer; from the silicon wafer to the metal layer, the thermal expansion coefficient of the dielectric layer increases layer by layer, and the thermal expansion coefficient gradient arrangement of the dielectric layer can alleviate the stress caused by thermal expansion mismatch, provide better thermal stress buffer between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, thereby improving the reliability and electrical performance of the device; on the other hand, the materials of the multiple dielectric layers are all electrical insulating materials, which can effectively isolate copper and silicon, and multiple insulating dielectric layers are superimposed to form an annular isolation cavity, which will produce a more powerful insulation barrier. This multi-layer annular isolation cavity can effectively prevent the migration of metal ions, reduce the risk of current leakage, increase the breakdown voltage, increase the overall insulation strength of the dielectric layer, and can also effectively block hot carriers, reduce hot carrier effects, and improve the long-term reliability of the device. In addition, since the insulation properties of different materials at different frequencies may be different, the multi-layer insulating dielectric layer structure can provide a wider band insulation performance. Therefore, the silicon through via structure provided by the present invention can provide better thermal stress buffering between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, and improve the reliability and electrical performance of the device; it can also provide a stronger and wider-bandwidth insulation barrier between the metal layer and the silicon wafer, reduce the risk of current leakage, reduce the hot carrier effect, and improve the long-term reliability of the device.

[0010] In an optional embodiment, the plurality of dielectric layers include a first dielectric layer, a second dielectric layer and a third dielectric layer;

[0011] The first dielectric layer is close to the silicon wafer side, and the third dielectric layer is close to the metal layer side;

[0012] The thermal expansion coefficients of the first dielectric layer, the second dielectric layer, the third dielectric layer and the metal layer gradually increase.

[0013] The silicon through hole structure provided by the present invention selects three dielectric layers, which can better control the thickness of the dielectric layer while providing a gradient arrangement of the thermal expansion coefficient, so that the thickness of the dielectric layer is not too thick, and can provide better thermal stress buffering between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, and improve the reliability and electrical performance of the device; in addition, the interface between the three dielectric layers can be used as a charge trap to further enhance the insulation effect, even if there are tiny defects or pinholes in one layer of material, the other two layers can compensate for these defects, and provide more reliable insulation performance, thereby further providing a stronger and wider-band insulation barrier between the metal layer and the silicon wafer, reducing the risk of current leakage, reducing the hot carrier effect, and improving the long-term reliability of the device.

[0014] In an optional embodiment, the material of the first dielectric layer is SiO2;

[0015] The material of the second dielectric layer is Si3N4;

[0016] The material of the third dielectric layer is Al2O3;

[0017] The metal layer is a copper layer.

[0018] The silicon through via structure provided by the present invention, on the one hand, can alleviate the stress caused by thermal expansion mismatch through the gradient arrangement of the thermal expansion coefficient of the dielectric layer, provide better thermal stress buffering between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, thereby improving the reliability and electrical performance of the device; on the other hand, the combination of three insulating materials with different insulation mechanisms, SiO2, Si3N4, and Al2O3, makes the device have high dielectric strength and good interface characteristics, improves the insulation performance, moisture resistance, high temperature resistance, thermal stability, and chemical stability of the device, thereby improving the long-term reliability of the device.

[0019] In an optional embodiment, the thermal expansion coefficient of the first dielectric layer is 8.1×10 -6 / K;

[0020] The thermal expansion coefficient of the second dielectric layer is 3.3×10 -6 / K;

[0021] The thermal expansion coefficient of the third dielectric layer is 0.5×10 -6 / K;

[0022] The thermal expansion coefficient of the metal layer is 16.6×10 -6 / K.

[0023] In an optional embodiment, the thickness of the first dielectric layer is 0.5 μm to 0.8 μm;

[0024] The thickness of the second dielectric layer is 1 μm to 1.6 μm;

[0025] The thickness of the third dielectric layer is 1 μm to 1.6 μm;

[0026] The total thickness of the multiple dielectric layers is 2.5 μm to 4 μm.

[0027] In the silicon through hole structure provided by the present invention, the thickness of the first dielectric layer is 0.5μm-0.8μm, the thickness of the second dielectric layer is 1μm-1.6μm, and the thickness of the third dielectric layer is 1μm-1.6μm, which can ensure that the total thickness of the multiple dielectric layers is 2.5μm-4μm, so that the thickness of the dielectric layer is not too thick, and can provide better thermal stress buffering between the metal layer and the silicon wafer while ensuring the performance of the silicon through hole, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, and improve the reliability and electrical performance of the device; in addition, the annular isolation cavity formed by the combination of the three dielectric layers can provide more reliable insulation performance, thereby further providing a stronger and wider-band insulation barrier between the metal layer and the silicon wafer, reducing the risk of current leakage, reducing the hot carrier effect, and improving the long-term reliability of the device; at the same time, by adjusting the thickness ratio of different material layers, the equivalent dielectric constant of the overall structure can be adjusted to a certain extent to meet specific electrical requirements.

[0028] In an optional embodiment, the thickness of the first dielectric layer is 0.5 μm;

[0029] The thickness of the second dielectric layer is 1 μm;

[0030] The thickness of the third dielectric layer is 1 μm;

[0031] The total thickness of multiple dielectric layers is 2.5 μm;

[0032] The copper layer has a height of 200 μm and a width of 30 μm.

[0033] In an optional implementation, the surface of the metal layer on the side facing away from the silicon wafer and the surface of the dielectric layer farthest from the side facing away from the silicon wafer are located in the same plane.

[0034] In a second aspect, the present invention provides a method for preparing a through silicon via structure, which is used to prepare the through silicon via structure of the first aspect, and the preparation method comprises:

[0035] Provide silicon wafers;

[0036] Forming a plurality of grooves on a surface of one side of the silicon wafer;

[0037] A plurality of dielectric layers stacked in sequence are formed on the bottom and side surfaces of the grooves and on the surface of the silicon wafer between adjacent grooves; the material of the dielectric layer is an electrical insulating material;

[0038] Filling the groove with metal material to form a metal layer;

[0039] The thermal expansion coefficient of the dielectric layer is smaller than that of the metal layer; from the silicon wafer to the metal layer, the thermal expansion coefficient of the dielectric layer increases layer by layer.

[0040] In an optional embodiment, a plurality of dielectric layers stacked in sequence are formed on the bottom and side surfaces of the grooves, and on the surface of the silicon wafer between adjacent grooves, including:

[0041] A first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on the bottom surface and the side surface of the grooves, and on the surface of the silicon wafer between adjacent grooves.

[0042] In an optional embodiment, filling a metal material in the groove to form a metal layer includes:

[0043] Electroplating to form a metal layer inside the groove; the metal layer is a copper layer;

[0044] The metal layer is polished by a chemical mechanical polishing process so that the surface of the metal layer facing away from the silicon wafer and the surface of the dielectric layer farthest from the side facing away from the silicon wafer are located in the same plane.

[0045] The preparation method of the silicon through hole structure provided by the present invention, on the one hand, by forming a plurality of dielectric layers stacked in sequence on the bottom and side surfaces of the grooves and the surface of the silicon wafer between adjacent grooves, the thermal expansion coefficient of the dielectric layer is less than the thermal expansion coefficient of the metal layer; from the silicon wafer to the metal layer, the thermal expansion coefficient of the dielectric layer increases layer by layer, and the thermal expansion coefficient gradient arrangement of the dielectric layer can alleviate the stress caused by thermal expansion mismatch, provide a better thermal stress buffer between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, thereby improving the reliability and electrical performance of the device; on the other hand, the materials of the plurality of dielectric layers are all electrical insulating materials, which can effectively isolate copper and silicon, and the plurality of insulating dielectric layers are superimposed to form an annular isolation cavity, which will produce a more powerful insulation barrier, and this multi-layer annular isolation cavity can effectively prevent the migration of metal ions, reduce the risk of current leakage, increase the breakdown voltage, increase the overall insulation strength of the dielectric layer, and can also effectively block hot carriers, reduce hot carrier effects, and improve the long-term reliability of the device. In addition, since the insulation properties of different materials at different frequencies may be different, the multi-layer insulating dielectric layer structure can provide a wider band insulation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 4 is a schematic structural diagram of a through silicon via structure according to an embodiment of the present invention.

[0048] Figure 2 This is a schematic diagram of the structure of Comparative Example 1.

[0049] Figure 3 It is a schematic diagram of the stress simulation results of comparative example 1 and example 1.

[0050] Figure 4 This is a comparison chart of the maximum tolerable thermal stress of Si and SiO2 at 25°C and 125°C between Comparative Example 1 and Example 1.

[0051] Figure 5 It is a schematic flow chart of a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0052] Figure 6 It is a structural schematic diagram of forming a groove in a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0053] Figure 7 It is a structural schematic diagram of forming a first dielectric layer in a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0054] Figure 8 It is a structural schematic diagram of forming a second dielectric layer in a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0055] Fig. 9 It is a structural schematic diagram of forming a third dielectric layer in a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0056] Fig.10 It is a structural schematic diagram of forming a metal layer in a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0057] Fig.11 It is a structural schematic diagram of grinding a metal layer by a chemical mechanical polishing process in a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0058] Fig.12 It is a schematic diagram of a specific process of a method for preparing a through silicon via structure according to an embodiment of the present invention.

[0059] Reference numerals:

[0060] 11. Silicon wafer; 12. Dielectric layer; 121. First dielectric layer; 122. Second dielectric layer; 123. Third dielectric layer; 13. Metal layer; 14. Groove. DETAILED DESCRIPTION

[0061] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0062] In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0063] Through Silicon Via (TSV) technology is a feasible method to achieve three-dimensional WLP (wafer level packaging) and 3D integration. In 3D chip stacking technology, through silicon via technology has attracted much attention. It provides a method to produce overall high-performance interconnection integration. At present, the mainstream filling method for through silicon vias or blind vias is copper electroplating filling. Copper electroplating filling not only requires a short electroplating time, but also requires thin copper surface to achieve pore-free TSV filling. In the electroplating process, Cu can achieve gapless filling through bottom up filling or super filling. Due to the large mismatch in the coefficient of thermal expansion (CTE) between Cu material and dielectric-based low silicon material. The large stress between Cu / dielectric layer (such as SiO2) and dielectric layer / Si substrate will affect the occurrence of cracks and delamination, affecting the reliability and electrical performance of the device.

[0064] like Figure 1 As shown, this embodiment provides a through silicon via structure, and the through silicon via structure includes:

[0065] A silicon wafer 11, wherein a plurality of grooves 14 are formed on one side of the silicon wafer 11;

[0066] A plurality of dielectric layers 12 stacked in sequence are located on the bottom and side surfaces of the grooves 14 and on the surface of the silicon wafer 11 between adjacent grooves 14; the material of the dielectric layers 12 is an electrical insulating material;

[0067] The metal layer 13 is located inside the groove 14 and fills the groove 14 ; the thermal expansion coefficient of the dielectric layer 12 is smaller than the thermal expansion coefficient of the metal layer 13 ; and the thermal expansion coefficient of the dielectric layer 12 increases layer by layer from the silicon wafer 11 to the metal layer 13 .

[0068] The silicon through hole structure provided in this embodiment, on the one hand, by setting multiple dielectric layers between the metal layer and the silicon wafer, the thermal expansion coefficient of the dielectric layer is smaller than the thermal expansion coefficient of the metal layer; from the silicon wafer to the metal layer, the thermal expansion coefficient of the dielectric layer increases layer by layer, and the gradient arrangement of the thermal expansion coefficient of the dielectric layer can alleviate the stress caused by thermal expansion mismatch, provide better thermal stress buffer between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, thereby improving the reliability and electrical performance of the device; on the other hand, the materials of the multiple dielectric layers are all electrical insulating materials, which can effectively isolate copper and silicon, and multiple insulating dielectric layers are superimposed to form an annular isolation cavity, which will produce a stronger insulation barrier. This multi-layer annular isolation cavity can effectively prevent the migration of metal ions, reduce the risk of current leakage, increase the breakdown voltage, increase the overall insulation strength of the dielectric layer, and can also effectively block hot carriers, reduce hot carrier effects, and improve the long-term reliability of the device. In addition, since the insulation properties of different materials at different frequencies may be different, the multi-layer insulating dielectric layer structure can provide a wider bandwidth insulation performance. Therefore, the silicon through via structure provided in this embodiment can provide better thermal stress buffering between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, and improve the reliability and electrical performance of the device; it can also provide a stronger and wider-bandwidth insulation barrier between the metal layer and the silicon wafer, reduce the risk of current leakage, reduce hot carrier effects, and improve the long-term reliability of the device.

[0069] In some optional embodiments, such as Figure 1 As shown, the plurality of dielectric layers 45 include a first dielectric layer 121, a second dielectric layer 122 and a third dielectric layer 123;

[0070] The first dielectric layer 121 is close to the side of the silicon wafer 11, and the third dielectric layer 123 is close to the side of the metal layer 13;

[0071] The thermal expansion coefficients of the first dielectric layer 121 , the second dielectric layer 122 , the third dielectric layer 123 and the metal layer 13 gradually increase.

[0072] The silicon through via structure provided in this embodiment selects three dielectric layers, which can better control the thickness of the dielectric layer while providing a gradient arrangement of the thermal expansion coefficient, so that the thickness of the dielectric layer will not be too thick, and can provide better thermal stress buffering between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, and improve the reliability and electrical performance of the device; in addition, the interface between the three dielectric layers can be used as a charge trap to further enhance the insulation effect. Even if there are tiny defects or pinholes in one layer of material, the other two layers can compensate for these defects and provide more reliable insulation performance, thereby further providing a stronger and wider-band insulation barrier between the metal layer and the silicon wafer, reducing the risk of current leakage, reducing hot carrier effects, and improving the long-term reliability of the device.

[0073] In some optional embodiments, the material of the first dielectric layer 121 is SiO2;

[0074] The material of the second dielectric layer 122 is Si3N4;

[0075] The material of the third dielectric layer 123 is Al2O3;

[0076] The metal layer 13 is a copper layer.

[0077] In some optional embodiments, the thermal expansion coefficient of the first dielectric layer is 8.1×10 -6 / K;

[0078] The thermal expansion coefficient of the second dielectric layer is 3.3×10 -6 / K;

[0079] The thermal expansion coefficient of the third dielectric layer is 0.5×10 -6 / K;

[0080] The thermal expansion coefficient of the metal layer is 16.6×10 -6 / K.

[0081] In specific implementation, since the thermal expansion coefficient of silicon wafer is 2.6×10 -6 / K, the thermal expansion coefficient of copper is 16.6×10 -6 / K, the thermal expansion coefficient of SiO2 is 8.1×10 -6 / K, the thermal expansion coefficient of Si3N4 is 3.3×10 -6 / K, the thermal expansion coefficient of Al2O3 is 0.5×10 -6 / K, so that an arrangement of copper, SiO2, Si3N4, Al2O3 and silicon can be formed, and the thermal expansion coefficients of copper, SiO2, Si3N4 and Al2O3 gradually decrease, forming a thermal expansion coefficient gradient.

[0082] In addition, SiO2, Si3N4, and Al2O3 are all insulating materials, and they are three different types of insulation mechanisms, which can complement each other. SiO2 has high dielectric strength and good interface properties; Si3N4 has a high dielectric constant and can block ion migration; Al2O3 has excellent thermal stability and chemical stability. At the same time, Si3N4 also has better moisture resistance, which can prevent the degradation of insulation performance caused by moisture penetration; Al2O3 is suitable for high-temperature applications, and combined with other materials, it can maintain good insulation in a wider temperature range. Therefore, the combination of these three insulating materials can make the multi-layer dielectric layer have a variety of insulation properties and other properties.

[0083] The silicon through via structure provided in this embodiment, on the one hand, can alleviate the stress caused by thermal expansion mismatch through the gradient arrangement of the thermal expansion coefficient of the dielectric layer, provide better thermal stress buffering between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, thereby improving the reliability and electrical performance of the device; on the other hand, the combination of three insulating materials with different insulation mechanisms, SiO2, Si3N4, and Al2O3, makes the device have high dielectric strength and good interface characteristics, improves the insulation performance, moisture resistance, high temperature resistance, thermal stability, and chemical stability of the device, thereby improving the long-term reliability of the device.

[0084] In some optional embodiments, the thickness of the first dielectric layer 121 is 0.5 μm to 0.8 μm, for example, 10 μm, 20 μm, 30 μm or 40 μm;

[0085] The thickness of the second dielectric layer 122 is 1 μm to 1.6 μm, for example, 10 μm, 20 μm, 30 μm or 40 μm;

[0086] The thickness of the third dielectric layer 123 is 1 μm to 1.6 μm, for example, 10 μm, 20 μm, 30 μm or 40 μm;

[0087] The total thickness of the plurality of dielectric layers 12 is 2.5 μm to 4 μm, for example, 10 μm, 20 μm, 30 μm or 40 μm.

[0088] In specific implementation, by adjusting the thickness ratio of different material layers, the equivalent dielectric constant of the overall structure can be adjusted to a certain extent to meet specific electrical requirements.

[0089] In the through silicon via structure provided in this embodiment, the thickness of the first dielectric layer is 0.5μm to 0.8μm, the thickness of the second dielectric layer is 1μm to 1.6μm, and the thickness of the third dielectric layer is 1μm to 1.6μm, which can ensure that the total thickness of the multiple dielectric layers is 2.5μm to 4μm, so that the thickness of the dielectric layer is not too thick, and while ensuring the performance of the through silicon via, better thermal stress buffering can be provided between the metal layer and the silicon wafer, reducing the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reducing the risk of cracks and delamination, and improving the reliability and electrical performance of the device; in addition, the annular isolation cavity formed by the combination of the three dielectric layers can provide more reliable insulation performance, thereby further providing a stronger and wider-band insulation barrier between the metal layer and the silicon wafer, reducing the risk of current leakage, reducing the hot carrier effect, and improving the long-term reliability of the device; at the same time, by adjusting the thickness ratio of different material layers, the equivalent dielectric constant of the overall structure can be adjusted to a certain extent to meet specific electrical requirements.

[0090] In some optional embodiments, the thickness of the first dielectric layer 121 is 0.5 μm;

[0091] The thickness of the second dielectric layer 122 is 1 μm;

[0092] The thickness of the third dielectric layer 123 is 1 μm;

[0093] The total thickness of the plurality of dielectric layers 12 is 2.5 μm;

[0094] The copper layer has a height of 200 μm and a width of 30 μm.

[0095] In a specific embodiment, Example 1 and Comparative Example 1 are provided for simulation.

[0096] In Example 1, Figure 1 As shown, the material of the first dielectric layer is SiO2, with a thickness of 0.5μm; the material of the second dielectric layer is Si3N4, with a thickness of 1μm; the material of the third dielectric layer is Al2O3, with a thickness of 1μm; the height of the copper layer is 200μm, and the width is 30μm. The specific data is shown in the following table.

[0097] Location Material Young's modulus(GPa) <![CDATA[Coefficient of thermal expansion (10 -6 / K)]]> thickness Annealing temperature Metal layer Cu 110-130 16.6 30μm 350℃ Close to the copper layer <![CDATA[Al2O3]]> 300-400 8.1 1μm 350℃ Middle side <![CDATA[Si3N4]]> 250-320 3.3 1μm 350℃ Close to the silicon wafer <![CDATA[SiO2]]> 70-75 0.5 0.5μm 350℃ Silicon Wafer Si 130-170 2.6 - 350℃

[0098] Comparative Example 1 is a conventional TSV structure, such as Figure 2 As shown in the figure, there is only one dielectric layer SiO2 between the silicon wafer and the copper layer, with a thickness of 2.5μm. The specific data is shown in the following table.

[0099] Location Material Young's modulus(GPa) <![CDATA[Coefficient of thermal expansion (10 -6 / K)]]> thickness Annealing temperature Metal layer Cu 110-130 16.6 30μm 350℃ Close to the silicon wafer side <![CDATA[SiO2]]> 70-75 0.5 2.5μm 350℃ Silicon Wafer Si 130-170 2.6 - 350℃

[0100] like Figure 3As shown, by simulating and verifying Example 1 and Comparative Example 1, the maximum tolerable thermal stress (Stress) of silicon and SiO2 of the two structures at 25°C and 125°C is obtained, and the specific data statistics are as follows:

[0101]

[0102] Figure 4 The maximum tolerable thermal stress comparison diagram of Si and SiO2 of two structures at 25°C and 125°C shows that compared with the conventional TSV structure of Comparative Example 1, the thermal stress that SiO2 of Example 1 provided in this embodiment can withstand is lower than that of Comparative Example 1 at both 125°C and 25°C, and the thermal stress that the silicon wafer can withstand is lower than that of Comparative Example 1 at both 125°C and 25°C. Therefore, this embodiment can significantly reduce the thermal stress on SiO2 and silicon wafer.

[0103] In an optional implementation, the surface of the metal layer 13 facing away from the silicon wafer 11 and the surface of the dielectric layer 12 farthest from the side facing away from the silicon wafer 11 are located in the same plane.

[0104] like Figure 5 As shown, this embodiment provides a method for preparing a through silicon via structure, and the preparation method includes but is not limited to steps S101 to S104.

[0105] Step S101, providing a silicon wafer 11;

[0106] Step S102, forming a plurality of grooves 14 on one side surface of the silicon wafer 11;

[0107] Step S103, forming a plurality of dielectric layers 12 stacked in sequence on the bottom and side surfaces of the grooves 14 and on the surface of the silicon wafer between adjacent grooves 14; the material of the dielectric layers 12 is an electrical insulating material;

[0108] Step S104 , filling the groove 14 with metal material to form a metal layer 13 ; the thermal expansion coefficient of the dielectric layer 12 is smaller than that of the metal layer 13 ; and the thermal expansion coefficient of the dielectric layer 12 increases layer by layer from the silicon wafer 11 to the metal layer 13 .

[0109] In a specific implementation, a plurality of grooves 14 may be formed on the surface of one side of the silicon wafer 11 by etching, punching, cutting or other grooving processes; a plurality of dielectric layers 12 stacked in sequence may be formed on the bottom and side surfaces of the grooves 14, and on the surface of the silicon wafer 11 between adjacent grooves 14 by deposition, film pasting or other processes; the specific method may be selected according to actual conditions, and this embodiment does not limit this.

[0110] The preparation method of the silicon through hole structure provided in this embodiment, on the one hand, by forming a plurality of dielectric layers stacked in sequence on the bottom and side surfaces of the grooves and the surface of the silicon wafer between adjacent grooves, the thermal expansion coefficient of the dielectric layer is less than the thermal expansion coefficient of the metal layer; from the silicon wafer to the metal layer, the thermal expansion coefficient of the dielectric layer increases layer by layer, and the gradient arrangement of the thermal expansion coefficient of the dielectric layer can alleviate the stress caused by thermal expansion mismatch, provide a better thermal stress buffer between the metal layer and the silicon wafer, reduce the stress between the metal layer and the dielectric layer, and between the dielectric layer and the silicon wafer, reduce the risk of cracks and delamination, thereby improving the reliability and electrical performance of the device; on the other hand, the materials of the plurality of dielectric layers are all electrical insulating materials, which can effectively isolate copper and silicon, and the plurality of insulating dielectric layers are superimposed to form an annular isolation cavity, which will produce a more powerful insulation barrier, and this multi-layer annular isolation cavity can effectively prevent the migration of metal ions, reduce the risk of current leakage, increase the breakdown voltage, increase the overall insulation strength of the dielectric layer, and can also effectively block hot carriers, reduce hot carrier effects, and improve the long-term reliability of the device. In addition, since the insulation properties of different materials at different frequencies may be different, the multi-layer insulating dielectric layer structure can provide a wider band insulation performance.

[0111] In an optional embodiment, if Figure 7 to Figure 9 As shown, a plurality of dielectric layers 12 stacked in sequence are formed on the bottom and side surfaces of the grooves 14 and on the surface of the silicon wafer 11 between adjacent grooves 14, including:

[0112] A first dielectric layer 121 , a second dielectric layer 122 and a third dielectric layer 123 are sequentially formed on the bottom surface and the side surface of the groove 14 and on the surface of the silicon wafer 11 between adjacent grooves 14 .

[0113] In an optional embodiment, if Fig.11 As shown, a metal material is filled inside the groove 14 to form a metal layer 13, including:

[0114] A metal layer 13 is formed by electroplating inside the groove; the metal layer 13 is a copper layer;

[0115] The metal layer 13 is polished by a chemical mechanical polishing process so that the surface of the metal layer 13 facing away from the silicon wafer 11 and the surface of the dielectric layer farthest from the side facing away from the silicon wafer 11 are located in the same plane.

[0116] like Fig.12 The present invention also provides a specific process diagram of a method for preparing a through silicon via structure, comprising the following steps:

[0117] Step S201, providing a silicon wafer 11;

[0118] Step S202, forming a plurality of grooves 14 on one side of the silicon wafer 11, such as Figure 6 As shown;

[0119] Step S203, forming a first dielectric layer 121 on the bottom and side surfaces of the grooves 14 and on the surface of the silicon wafer 11 between adjacent grooves, such as Figure 7 As shown;

[0120] Step S204, forming a second dielectric layer 122 on a surface of the first dielectric layer 121 facing away from the silicon wafer 11, such as Figure 8 As shown;

[0121] Step S205, forming a third dielectric layer 123 on a surface of the second dielectric layer 122 facing away from the silicon wafer 11, such as Fig. 9 As shown;

[0122] Step S206, electroplating to form a metal layer 13 inside the groove 14, such as Fig.10 As shown; the metal layer is a copper layer; the thermal expansion coefficient of the dielectric layer 12 is less than the thermal expansion coefficient of the metal layer 13; from the silicon wafer 11 to the metal layer 13, the thermal expansion coefficient of the dielectric layer 12 increases layer by layer;

[0123] Step S207, grinding the metal layer 13 by chemical mechanical polishing process, so that the surface of the metal layer 13 facing away from the silicon wafer 11 and the surface of the third dielectric layer 123 facing away from the silicon wafer 11 are located in the same plane, such as Fig.11 shown.

[0124] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless otherwise clearly and specifically defined. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0125] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0126] The above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention. The scope of protection of the present invention is determined by the scope of the attached claims.

Claims

1. A through silicon via structure, characterized in that: The through silicon via structure comprises: A silicon wafer, wherein a plurality of grooves are formed on one surface of the silicon wafer; A plurality of dielectric layers stacked in sequence are located on the bottom and side surfaces of the grooves, and on the surface of the silicon wafer between adjacent grooves; the dielectric layers are made of electrically insulating material; The metal layer is located inside the groove and fills the groove; the thermal expansion coefficient of the dielectric layer is smaller than the thermal expansion coefficient of the metal layer; and the thermal expansion coefficient of the dielectric layer increases layer by layer from the silicon wafer to the metal layer.

2. The through silicon via structure according to claim 1, characterized in that: The plurality of dielectric layers include a first dielectric layer, a second dielectric layer and a third dielectric layer; The first dielectric layer is close to a side of the silicon wafer, and the third dielectric layer is close to a side of the metal layer; The thermal expansion coefficients of the first dielectric layer, the second dielectric layer, the third dielectric layer and the metal layer gradually increase.

3. The through silicon via structure according to claim 2, characterized in that: The material of the first dielectric layer is SiO2; The material of the second dielectric layer is Si3N4; The material of the third dielectric layer is Al2O3; The metal layer is a copper layer.

4. The through silicon via structure according to claim 3, characterized in that: The thermal expansion coefficient of the first dielectric layer is 8.1×10 -6 / K; The thermal expansion coefficient of the second dielectric layer is 3.3×10 -6 / K; The thermal expansion coefficient of the third dielectric layer is 0.5×10 -6 / K; The thermal expansion coefficient of the metal layer is 16.6×10 -6 / K.

5. The through silicon via structure according to claim 3, characterized in that: The thickness of the first dielectric layer is 0.5 μm to 0.8 μm; The thickness of the second dielectric layer is 1 μm to 1.6 μm; The thickness of the third dielectric layer is 1 μm to 1.6 μm; The total thickness of the plurality of dielectric layers is 2.5 μm to 4 μm.

6. The through silicon via structure according to claim 5, characterized in that: The thickness of the first dielectric layer is 0.5 μm; The thickness of the second dielectric layer is 1 μm; The thickness of the third dielectric layer is 1 μm; The total thickness of the plurality of dielectric layers is 2.5 μm; The copper layer has a height of 200 μm and a width of 30 μm.

7. The through silicon via structure according to claim 1, characterized in that: The surface of the metal layer facing away from the silicon wafer and the surface of the dielectric layer farthest from the side facing away from the silicon wafer are located in the same plane.

8. A method for preparing a through silicon via structure, for preparing the through silicon via structure as claimed in claim 1, characterized in that: include: Provide silicon wafers; Forming a plurality of grooves on a surface of one side of the silicon wafer; Forming a plurality of dielectric layers stacked in sequence on the bottom surface and the side surface of the groove, and on the surface of the silicon wafer between adjacent grooves; The material of the dielectric layer is an electrical insulating material; Filling the groove with metal material to form a metal layer; The thermal expansion coefficient of the dielectric layer is smaller than the thermal expansion coefficient of the metal layer; and the thermal expansion coefficient of the dielectric layer increases layer by layer from the silicon wafer to the metal layer.

9. The method for preparing a through silicon via structure according to claim 8, characterized in that: The multiple dielectric layers stacked in sequence are formed on the bottom and side surfaces of the grooves and on the surface of the silicon wafer between adjacent grooves, including: A first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on the bottom surface and the side surface of the grooves, and on the surface of the silicon wafer between adjacent grooves.

10. The method for preparing a through silicon via structure according to claim 8, characterized in that: The step of filling the groove with a metal material to form a metal layer comprises: Electroplating to form a metal layer inside the groove; the metal layer is a copper layer; The metal layer is polished by a chemical mechanical polishing process so that the surface of the metal layer facing away from the silicon wafer and the surface of the dielectric layer farthest from the side facing away from the silicon wafer are located in the same plane.

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