Method for improving power supply performance of multi-phase interleaving circuit

Abstract

The invention belongs to the technical field of resonant converters, and discloses a method for improving the performance of a power supply by a multi-phase interleaving circuit, which comprises the following steps of: in an interleaving LLC asymmetric wave sending mode, enabling different phases (phase dislocation) SRB or SRC upper tubes / lower tubes of a secondary side to be simultaneously, transiently and periodically conducted in an A-phase primary side energy transmission region by secondary side drive through detecting a commutation region of a primary side resonant network; the energy is stored in the resonance network, before shutdown, SR driving energy inserted into the commutation area is stored in the resonance network, and the energy is released after the SRB or the SRC is transiently conducted, so that the output retention time of the whole machine is prolonged. The beneficial effects of the invention are that the gain of the resonant converter is improved, the input power-down retention time is prolonged, and the dynamic performance of the power supply can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of resonant converters, and in particular to a method for improving power supply performance through a multi-phase interleaved circuit. Background Art

[0002] LLC has become a popular DC / DC topology in power supply applications due to its high efficiency and excellent EMI performance. As the power requirements of a single PSU increase, interleaving technology has become an effective way to increase power levels without significantly upgrading power devices. In recent years, three-phase interleaved LLC, as a typical interleaved topology, has been widely used in telecommunications and server PSUs. Compared with the parallel topology, the three-phase interleaved LLC can significantly reduce current ripple and make it easier to achieve current balance. Combined with special magnetic component design, the size of the inductor and transformer can also be reduced. Coupled with the intelligent control strategy of the drive, the hold-up time can be extended. Under the same output power conditions, the LLC hold-up time is limited by the volume of the input large capacitor. It is very difficult to increase the output hold-up time without replacing the large-capacity capacitor or adding special circuits, such as the Baby-boost circuit. However, for multi-channel interleaved LLC converters, the conduction angle of the secondary-side SR rectifier tube can be adjusted to store part of the energy in the transformer, and then release the energy when the input is shut down, so as to achieve the purpose of extending the hold-up time.

[0003] Therefore, it is necessary to provide a method for improving power supply performance by using a multi-phase interleaved circuit, thereby increasing the gain of the resonant converter, extending the input power-off holding time, and improving the dynamic performance of the power supply. Summary of the invention

[0004] The present invention discloses a method for improving power supply performance by using a multi-phase interleaved circuit, and relates to a three-phase LLC resonant converter, and in particular to a three-phase interleaved LLC resonant full-wave rectifier converter, which is suitable for three-phase interleaved LLC full-wave rectification and can effectively solve the technical problems involved in the background technology.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] A method for improving power supply performance by a multi-phase interleaved circuit comprises the following steps:

[0007] S1. Determine the circuit structure. The circuit is divided into a primary side and a secondary side. The primary side is provided with multiple primary phases, and the secondary side is provided with multiple secondary phases. The primary phases and the secondary phases correspond to each other one by one. The dead zone interval of each phase has a fixed phase difference, and the dead zone time of each primary phase is confirmed;

[0008] S2, monitor the input voltage or output voltage to determine whether the power is off;

[0009] S3. When power is off, the dead time of a certain primary phase causes a certain secondary phase that does not correspond to it to be turned on.

[0010] Specifically, a three-phase staggered LLC circuit is disclosed, which is applied in high power density conditions, with limited volume and space, without adding large input capacitors, and extending the output voltage holding time by staggered short circuit. The primary side of the circuit has three LLC half-bridges, 6 MOS, and 3 groups of drivers, and the secondary side has three groups of full-bridge rectifiers, 12 MOS, and 6 groups of drivers. The three groups of resonant networks include main transformers, resonant inductors, and resonant capacitors. The output end is an output electrolytic filter, and the switch tubes of the secondary full-wave rectifier circuit are intelligently controlled. The present invention uses the switch tubes of the secondary rectifier circuit to perform intelligent control, improve the gain of the resonant converter, extend the input power-off holding time, and also improve the dynamic performance of the power supply.

[0011] As a preferred improvement of the present invention: the primary phase is an LLC half-bridge, and the secondary phase is a full-bridge rectifier.

[0012] As a preferred improvement of the present invention: the number of primary phases is 3-6. Specifically, through the three-phase staggered LLC asymmetric wave generation mode, the secondary side driver detects the commutation area of ​​the primary side resonant network, and in the dead zone of the primary side of the A phase, the secondary side staggered phase SRB or SRC upper tube / lower tube is turned on briefly and periodically at the same time to store energy in the resonant network. Before shutdown, the SR drive energy inserted in the commutation area is stored in the resonant network, and the energy is released after shutdown, so that the output holding time of the whole machine will be extended. The implementation of this technology is not limited to the three-phase architecture, and can be expanded to the six-phase architecture to implement this technology. This wave generation method uses the existing switching time node for asymmetric wave generation technology, and the known technology must be complicated to calculate the SR front edge. The difference between this wave generation method and the known one is that the behavior of the primary side resonant current (ILr) and the excitation current (ILm) is inconsistent. The known technology is implemented when the two currents are equal, and this patent is implemented when the two currents are different.

[0013] As a preferred improvement of the present invention: the number of primary phases is 3, which are defined as phase A, phase B and phase C according to the phase sequence. When power is off, the secondary phase corresponding to phase B is turned on during the dead time of phase A, or the secondary phase corresponding to phase C is turned on during the dead time of phase B.

[0014] As a preferred improvement of the present invention: when the circuit is powered off, the conduction time is T phaseshift , T setting.max is the maximum pulse width, T seting.min is the minimum pulse width, V error is the output voltage feedback error, V error.max is the maximum value of the output voltage feedback error, V error =(V fb -V ref)*K p *K i , V fb is the output voltage, V ref is the output voltage reference value, K p , K i is the loop operation coefficient.

[0015] As a preferred improvement of the present invention: seting.min 50ns, T setting.max is the corresponding dead time of the primary, V error.max is 5%, and the circuit performs voltage loop control.

[0016] As a preferred improvement of the present invention: in the step S2, when the input voltage is less than the set value Vac_out, the circuit is judged to be powered off; when the output voltage drops by more than 5%, the circuit is judged to be powered off.

[0017] As a preferred improvement of the present invention: in the step S3, when the power is off, the circuit switching frequency is first reduced, and when the switching frequency drops to Tfp, the secondary phase is turned on.

[0018] As a preferred improvement of the present invention: Tfp=Fswmin=Frmin+10kHz, where Frmin is the lowest resonance frequency of the primary phase.

[0019] The beneficial effects of the present invention are as follows:

[0020] During the discharge process of the HVDC bus voltage, the output voltage will eventually drop due to the fixed gain of the transformer turns ratio and the fixed maximum LLC resonant network gain. After the countermeasure is cut in (by turning on the SR drive in the primary side dead zone), the gain can be increased, and the output voltage can be temporarily pulled back, thereby extending the output holding time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0022] Figure 1 is a schematic diagram of an interleaved circuit;

[0023] Figure 2 A flow chart of a method for improving power supply performance of a multi-phase interleaved circuit according to the present invention;

[0024] Figure 3 It is a schematic diagram of three-phase interleaved LLC drive;

[0025] Figure 4 It is a schematic diagram of the dead zone control of three-phase LLC and SR drive;

[0026] Figure 5 is a schematic diagram of the phase shift curve;

[0027] Figure 6 It is a schematic diagram of driving dead zone phase shift pulse width control;

[0028] Figure 7 It is a three-phase interleaved LLC drive and resonant current;

[0029] Figure 8 It is the phase-out short circuit of the three-phase interleaved LLC drive and the resonant current;

[0030] Fig. 9 It is the three-phase resonant current and output voltage with phase mismatch and short circuit. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0033] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0034] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0036] The technical problem to be solved by the present invention is to extend the holding time of the three-phase LLC interleaved topology and improve the power supply performance, such as Figure 1 As shown, the primary side is a three-phase staggered LLC "Y" type topology, and the secondary side is synchronous rectifier SR full-wave rectification. The drivers of the three-phase LLC on the primary side are A phase DRV_A, defined as a group of complementary drivers QA1, QA2; B phase DRV_B, defined as a group of complementary drivers QB1, QB2; C phase DRV_C is defined as a group of complementary drivers QC1, QC2; the wave interval of each group of drivers is 1 / 3π, and there is a working dead zone, such as Figure 3 As shown. In the DRV_A diagram, the solid line is the driving waveform of QA1, and the dotted line is the driving waveform of QA2. In the DRV_B diagram, the solid line is the driving waveform of QB1, and the dotted line is the driving waveform of QB2. In the DRV_C diagram, the solid line is the driving waveform of QC1, and the dotted line is the driving waveform of QC2. The circuit control flow chart is shown in Figure 2 shown.

[0037] The present invention is implemented as follows:

[0038] The input voltage is sampled from the input end to the AC monitoring, and compared with the set value Vac_out to determine whether the power is off (CASE1). The basis for power off is that there is an AC sampling signal on the primary side, which is less than the set value of Vac_out to trigger the condition; the output voltage Vfb gain drops by 5% (CASE2), which can also trigger SR to conduct in the primary side dead zone.

[0039] When the three-phase interleaved circuit is working in steady state, the secondary side drive of the three-phase interleaved LLC is bound to the primary side drive, and the binding relationship is as follows:

[0040] The primary side QA1, QA2 is divided into two groups corresponding to the secondary side. In the positive half cycle of the resonant current, QA3 and QA6 form a group and switch at the same time. In the negative half cycle of the resonant current, QA4 and QA5 form a group and switch at the same time.

[0041] The primary side QB1, QB2 is divided into two groups corresponding to the secondary side. In the positive half cycle of the resonant current, QB3 and QB6 form a group and switch at the same time. In the negative half cycle of the resonant current, QB4 and QB5 form a group and switch at the same time.

[0042] The primary side QA1, QA2 is divided into two groups corresponding to the secondary side. In the positive half cycle of the resonant current, QC3, QC6 are a group and switch at the same time. In the negative half cycle of the resonant current, QC4, QC5 are a group and switch at the same time.

[0043] LLC and SR dead zone Figure 4 As shown, there are 4 comparators inside the MCU and two groups of PWM controllers, namely PWM_H / PWM_L, which control the upper / lower tube drive and reserve the leading / trailing edge adjustment area, such as the shaded area of ​​LLC_HG / LLC_LG drive, which is the fixed dead zone inserted by the primary side according to the resonant frequency.

[0044] After the transformer topology is confirmed, the LLC resonant network parameters Lm, Lr, Cr for each phase are known conditions, and the highest resonant frequency is The lowest resonant frequency is

[0045] In the above circuit, when the input power is off or the output drops out of specification, the primary side resonant network frequency will first reduce the frequency to increase the gain until the switching frequency reaches Tfp (which can be set at Fswmin = Frmin + 10kHz). Figure 5 As shown in the phase shift curve, after the switching frequency drops to the Tfp point, the frequency will not be further reduced to increase the gain and maintain the output holding time; the secondary side SRMOS will be driven to briefly turn on the SR MOS in the primary side dead zone of the other two phases. The Tphaseshift on time is limited by the MCU to the maximum / minimum pulse width. The minimum pulse width can be set to a fixed value Tsetting.min. For example, if the STM32G4 series is used, the typical value can be set to 50ns. The maximum pulse width Tsetting.max is Tdead_llc, which is updated in real time according to the resonant frequency. Tphaseshift needs to be calculated by the error Verror between Vfb and the feedback. Verror.max is the maximum value of the output voltage Vfb error range, which is generally +5%. The reference value Vref loop proportional (Kp) integral (Ki) is calculated as follows: V error =(V fb -V ref )*K p *K i , The energy after triggering the out-of-phase conduction is stored in the LLC resonant cavity and released cycle by cycle to improve the output gain of the power supply.

[0046] The three-phase interleaved LLC symmetrical wave working waveform is as follows: Figure 7 The three-phase interleaved LLC asymmetric wave generation working waveform is mainly aimed at the SR drive on the secondary side, such as Figure 7-8As shown, after the condition is triggered, the phase difference of the resonant current of the three-phase interleaved LLC on the primary side is 60°. It can be seen that there are two dead zones Td1 / Td2 at the beginning and end of each phase complete cycle; the figure shows the LLC resonant current of phase A on the primary side and the SR drive of phase B, and Td1_B and Td2_B are the dead zones of phase B on the primary side.

[0047] IL1 is the primary side A phase resonant current, IL2 is the primary side B phase resonant current, IL3 is the primary side C phase primary current; Short1 is the secondary side B phase pre-conduction SR drive 3 groups (driving QB3 and QB5 at the same time), Short2 is the secondary side B phase pre-conduction SR drive 4 groups (driving QB4 and QB6 at the same time).

[0048] The converter gain or output voltage abnormal conditions (Case1 or Case2) trigger the resonant frequency to adjust to the phase shift region. The short3 conduction drive is turned on at Td1_B in front of the primary side phase A, that is, the positive half cycle of the phase A resonant current, and the short4 conduction drive is turned on at Td2_B behind the primary side phase A, that is, the negative half cycle of the phase A resonant current. The pulse width of the Short3 and Short4 drives can be adjusted, and the calculation formula can refer to Tphaseshift.

[0049] The SR drive conduction in the phase shift region has the following principles:

[0050] (1) Phase staggered conduction: SRB short-circuit trigger conduction is in the dead zone of DRV_A phase, and SRC short-circuit trigger conduction is in the dead zone of DRV_B phase;

[0051] (2) Conditional triggering moment, for easier control, PWM implements full-cycle triggering, that is, the secondary side SR opening point is at SRB, SRC. After power failure, the trigger mechanism starts after the end of the cycle, and the secondary side is turned on during the dead time of phase A in the next cycle.

[0052] During the discharge process of the HVDC bus voltage, the output voltage will eventually drop due to the fixed gain of the transformer turns ratio and the fixed maximum LLC resonant network gain. After the countermeasure is cut in (by turning on the SR drive in the primary side dead zone), the gain can be increased, and the output voltage can be temporarily pulled back, thereby extending the output holding time.

[0053] The circuit diagram of the three-phase LLC "Y" type interleaved full-wave rectifier resonant converter is as follows Figure 1 , in normal operation, the three groups of drivers are 60° apart in phase, and the SR drive of QB3, QB6 (or QB4, QB5) on the secondary side is turned on to one of the LLC resonant networks on the primary side, such as DRV_B, DRV_C, through asymmetric wave generation; when extended to multi-interleaved circuits (six interleaved), referring to the above working logic, the derivation relationship is as shown in Table 1.1:

[0054] Table 1.1 Six-phase LLC interleaved drive and SR drive phase relationship table

[0055]

[0056] from Fig. 9 It can be seen that after using the three-phase LLC staggered phase control strategy, the three output voltages can be temporarily raised by 2.0V, which is converted to about 30Vdc on the primary side through the transformer turns ratio of 15:1. That is, the gain of the three-phase LLC converter is increased by 30V during this period, and the output voltage holding time is extended.

[0057] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the embodiments. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A method for improving power supply performance by using a multi-phase interleaved circuit, characterized in that: The following steps are involved: S1. Determine the circuit structure. The circuit is divided into a primary side and a secondary side. The primary side is provided with multiple primary phases, and the secondary side is provided with multiple secondary phases. The primary phases and the secondary phases correspond to each other one by one. The dead zone interval of each phase has a fixed phase difference, and the dead zone time of each primary phase is confirmed; S2, monitor the input voltage or output voltage to determine whether the power is off; S3. When power is off, the dead time of a primary phase causes a secondary phase that does not correspond to it to be turned on.

2. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 1, characterized in that: The primary phase is LLC half-bridge, and the secondary phase is full-bridge rectifier.

3. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 1, characterized in that: The number of the primary phases is 3-6.

4. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 1, characterized in that: The number of primary phases is 3, which are defined as phase A, phase B and phase C according to the phase sequence. When power is off, the secondary phase corresponding to phase B is turned on during the dead time of phase A, or the secondary phase corresponding to phase C is turned on during the dead time of phase B.

5. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 1, characterized in that: When the circuit is powered off, the conduction time is T phaseshift , T setting.max is the maximum pulse width, T seting.min is the minimum pulse width, V error is the output voltage feedback error, V error.max is the maximum value of the output voltage feedback error, V error =(V fb -V ref )*K p *K i , V fb is the output voltage, V ref is the output voltage reference value, K p , K i is the loop operation coefficient.

6. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 5, characterized in that: The T seting.min 50ns, T setting.max is the corresponding dead time of the primary, V error.max is 5%, and the circuit performs voltage loop control.

7. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 1, characterized in that: In the step S2, when the input voltage is less than the set value Vac_out, the circuit is determined to be powered off; when the output voltage drops by more than 5%, the circuit is determined to be powered off.

8. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 1, characterized in that: In step S3, when power is off, the circuit switching frequency is first reduced, and when the switching frequency drops to Tfp, the secondary phase is turned on.

9. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 8, characterized in that: The Tfp=Fswmin=Frmin+10kHz, where Frmin is the lowest resonance frequency of the primary phase.

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