Ring oscillator

Abstract

The invention discloses a ring oscillator which comprises a bias module and an oscillation module. The bias module comprises a current unit and a conversion unit which are connected, the current unit is used for generating a first current and a second current based on the reference current, and the conversion unit is used for generating a bias voltage based on the second current or generating the bias voltage based on a current difference between the first current and the second current; and a driving current is generated based on the current difference between the first current and the second current, the oscillation module is connected with the bias module to receive the bias voltage and the driving current, and an oscillation signal is generated based on the bias voltage and the driving current. The ring oscillator obtains a stable bias voltage as a working voltage of the oscillation module through two currents generated by the bias module based on a reference current, and obtains a driving current of the oscillation module based on a difference current of the two currents. The current has good temperature stability, so that the oscillation precision can be ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a ring oscillator. Background Art

[0002] As an important component of integrated circuit systems, oscillators provide stable clock signals for the system to ensure the normal operation of the chip. Among them, ring oscillators are widely used due to their advantages such as low cost, simple structure and small area.

[0003] The traditional ring oscillator structure is as follows: Figure 1 As shown, it is an odd number (greater than or equal to 3) of inverters cascaded head to tail. When the "Barkhausen criterion" is met (loop gain greater than or equal to 1, phase shift 180 degrees), it will start to oscillate and output a clock signal with a frequency of f:

[0004] in, is the number of inverter cascades, is the delay of a single-stage inverter, for a long channel circuit:

[0005] in, are the rising delay and falling delay of the inverter respectively, is the equivalent capacitance of the inverter input and output nodes, , Parameters associated with process materials, are the width-to-length ratios of PMOS and NMOS respectively. is the threshold voltage of PMOS and NMOS. It is the gate-source voltage of the MOS tube.

[0006] Assumptions , we can get:

[0007] According to the above formula, the frequency output by the ring oscillator is sensitive to the power supply voltage, temperature and process parameters. In the actual operation of the chip, these parameters will inevitably change due to the influence of signal coupling, noise, chip self-heating, etc., which will cause the output clock frequency to shift and make the chip unable to work stably. Therefore, the application scope of traditional ring oscillators is very limited and can only be used in occasions that are not sensitive to frequency stability.

[0008] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0009] The object of the present invention is to provide a ring oscillator which can ensure the stability of the generated signal frequency.

[0010] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows: A ring oscillator comprises: a bias module and an oscillation module; the bias module comprises a current unit and a conversion unit connected to each other, the current unit is used to generate a first current and a second current based on a reference current, the conversion unit is used to generate a bias voltage based on the second current or to generate a bias voltage based on a current difference between the first current and the second current, and to generate a driving current based on the current difference between the first current and the second current, the oscillation module is connected to the bias module to receive the bias voltage and the driving current, and generates an oscillation signal based on the bias voltage and the driving current.

[0011] In one or more embodiments of the present invention, the conversion unit includes a first load unit, both ends of the first load unit are connected to a current unit, the current unit is used to inject a first current into the first load unit and extract a second current from the first load unit to generate a bias voltage and a driving current at one end of the first load unit; or the conversion unit includes a current generating unit and a second load unit, the current generating unit is connected to the current unit to generate a third current based on a current difference between the first current and the second current, the first end of the second load unit is connected to the current generating unit to generate a bias voltage and a driving current based on the third current, and the second end of the second load unit is connected to a ground voltage; or the conversion unit includes a current generating unit, a second load unit and a buffer, the current generating unit is connected to the current unit to generate a third current based on a current difference between the first current and the second current, the first end of the second load unit is connected to the current generating unit to generate a conversion voltage based on the third current, the second end of the second load unit is connected to the ground voltage, the input end of the buffer is connected to the first end of the second load unit to receive the conversion voltage, and the output end of the buffer is used to output a bias voltage and a driving current.

[0012] In one or more embodiments of the present invention, the ring oscillator further includes a control module connected to the oscillation module and a signal processing module connected to the control module, the signal processing module is used to perform signal processing on the enable signal to generate a control signal, and the control module is used to control the working state of the oscillation module based on the control signal.

[0013] In one or more embodiments of the present invention, the control module includes an OR gate, a first input end of the OR gate is connected to the signal processing module to receive a control signal, a second input end of the OR gate is connected to the input end of the oscillation module, and an output end of the OR gate is connected to the output end of the oscillation module.

[0014] In one or more embodiments of the present invention, the signal processing module includes a capacitor and a delay inverter, the first end of the capacitor is connected to the input end of the delay inverter and is used to receive the first enable signal, and the output end of the delay inverter is used to generate a control signal; or the signal processing module includes a capacitor, a delay inverter and a first switch tube, the first end of the capacitor is connected to the input end of the delay inverter and is used to receive the first enable signal, the output end of the delay inverter is used to generate a control signal, the first end and the second end of the first switch tube are respectively connected to the two ends of the capacitor, and the control end of the first switch tube is used to receive the second enable signal; or the signal processing module includes a capacitor, a delay inverter and a second switch tube, the first end of the capacitor is connected to the input end of the delay inverter and is used to receive the first enable signal, the output end of the delay inverter is used to generate a control signal, and the second switch The first end of the tube is connected to the reference voltage, the second end of the second switch tube is connected to the input end of the delay inverter, and the control end of the second switch tube is connected to the output end of the delay inverter; or the signal processing module includes a capacitor, a delay inverter, a first switch tube and a second switch tube, the first end of the capacitor is connected to the input end of the delay inverter and is used to receive the first enable signal, the output end of the delay inverter is used to generate a control signal, the first end and the second end of the first switch tube are respectively connected to the two ends of the capacitor, the control end of the first switch tube is used to receive the second enable signal, the first end of the second switch tube is connected to the reference voltage, the second end of the second switch tube is connected to the input end of the delay inverter, and the control end of the second switch tube is connected to the output end of the delay inverter; or the signal processing module includes a first inverting unit for inverting the initial enable signal to generate a control signal.

[0015] In one or more embodiments of the present invention, the ring oscillator further includes a first level converter and a second inverting unit, the second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal, the first level converter is connected to the second inverting unit to receive the first inverted signal, and the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the first inverted signal; or the ring oscillator further includes a first level converter, a second inverting unit and a Schmitt trigger, the second inverting unit is connected to the signal processing module to invert the control signal to generate the first inverted signal, the first level converter is connected to the second inverting unit to receive the first inverted signal, the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the first inverted signal, the input end of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output end of the Schmitt trigger is used to generate a clock signal; or the ring oscillator further includes a first level converter, a second level converter and a second inverting unit, the first level converter is connected to the second inverting unit to receive the first inverted signal, the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the first inverted signal, the input end of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output end of the Schmitt trigger is used to generate a clock signal; The second inversion unit is connected to the signal processing module to invert the control signal to generate a first inversion signal, the second level converter is connected to the second inversion unit to convert the first inversion signal into a second inversion signal, the first level converter is connected to the second level converter to receive the second inversion signal, and the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the second inversion signal; or the ring oscillator also includes a first level converter, a second level converter, a second inversion unit and a Schmitt trigger, the second inversion unit is connected to the signal processing module to invert the control signal to generate a first inversion signal, the second level converter is connected to the second inversion unit to convert the first inversion signal into a second inversion signal, the first level converter is connected to the second level converter to receive the second inversion signal, the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the second inversion signal, the input end of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output end of the Schmitt trigger is used to generate a clock signal.

[0016] In one or more embodiments of the present invention, the oscillation module includes multiple first inverters and a loop control unit, the loop control unit includes multiple loop control sub-units, each of the loop control sub-units and each of the first inverters constitutes a plurality of oscillation loops, and the loop control unit controls each of the loop control sub-units based on an adjustment signal to select one of the oscillation loops to generate an oscillation signal.

[0017] In one or more embodiments of the present invention, the loop control subunit includes a second inverter, and each of the second inverters forms an oscillation loop with at least two first inverters.

[0018] In one or more embodiments of the present invention, an even number of the first inverters corresponding to two branches constitute an inverter group, the inverter groups are connected in sequence to form two branches, and each of the second inverters is respectively connected between the first inverters of each inverter group and forms an oscillation loop with one or more inverter groups.

[0019] In one or more embodiments of the present invention, the ring oscillator further includes a decoder connected to each loop control subunit, the decoder is used to decode the adjustment value to generate an adjustment signal to control each loop control subunit to select one of the oscillation loops to generate an oscillation signal; or the ring oscillator further includes a decoder and a logic unit, the decoder is connected to each loop control subunit, the logic unit is connected to the decoder and each first inverter, the decoder is used to decode the adjustment value to generate an adjustment signal to control each loop control subunit, the logic unit is used to perform logic operations on the adjustment signal, or perform logic operations on the adjustment signal and the bias voltage respectively to generate corresponding logic signals to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logic signal.

[0020] Compared with the prior art, the ring oscillator of the present invention obtains a stable bias voltage as the working voltage of the oscillation module through two currents generated by the bias module based on a reference current, and obtains the driving current of the oscillation module based on the difference current of the two currents. This current has good temperature stability, so that the oscillation accuracy can be guaranteed. At the same time, this current can also be maintained at a relatively low level, which is suitable for generating an oscillation signal with a lower frequency, and finally enables the ring oscillator to output a stable and low-frequency clock signal.

[0021] At the same time, by adding a signal processing module and a control module, the enable signal can be delayed to stabilize it and then the oscillation module can be controlled to oscillate, thereby filtering out the frequency instability at the initial stage of the circuit operation.

[0022] Furthermore, a plurality of oscillation loops are formed in the oscillation module, and a corresponding oscillation loop can be selected according to actual needs to oscillate and generate an oscillation signal of a target frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 The figure is a circuit diagram of a ring oscillator in the prior art.

[0025] Figure 2 FIG. 4 is a schematic diagram of the structure of a ring oscillator in one embodiment of the present invention.

[0026] Figure 3 FIG. 4 is a circuit diagram of a current unit according to an embodiment of the present invention.

[0027] Figure 4 FIG. 4 is a circuit diagram of a conversion unit in one embodiment of the present invention.

[0028] Figure 5 The figure is a circuit schematic diagram of a control module, a signal processing module and an oscillation module in one embodiment of the present invention.

[0029] Figure 6 FIG. 4 is a circuit diagram of a decoder in one embodiment of the present invention.

[0030] Figure 7 FIG. 4 is a circuit schematic diagram of a logic unit in an embodiment of the present invention.

[0031] Figure 8 FIG. 4 is a diagram of calibration steps of a ring oscillator at different process angles according to an embodiment of the present invention.

[0032] Fig. 9 FIG. 4 is a temperature characteristic diagram of a ring oscillator in one embodiment of the present invention.

[0033] Fig.10 FIG. 4 is a circuit diagram of a conversion unit in another embodiment of the present invention.

[0034] Fig.11 FIG. 4 is a circuit schematic diagram of a signal processing module in another embodiment of the present invention.

[0035] Fig.12 FIG. 4 is a circuit schematic diagram of an oscillation module in another embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0038] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be considered in a limiting sense.

[0039] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0040] For purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0041] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element mentioned in the singular form may include multiple such elements according to the teachings of this document.

[0042] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present application are synonymous.

[0043] Embodiment 1 like Figure 2As shown, the ring oscillator in the first embodiment of the present invention includes a bias module 10 , an oscillation module 20 , a control module 30 and a signal processing module 40 .

[0044] Combination Figure 3 and Figure 4 As shown, the bias module 10 includes a connected current unit 11 and a conversion unit 12, the current unit 11 is used to generate a first current Ib1 and a second current Ib2 based on a reference current Isink, the conversion unit 12 is used to generate a bias voltage VH based on the second current Ib2, and generate a drive current Ic based on a current difference between the first current Ib1 and the second current Ib2.

[0045] The oscillation module 20 is connected to the bias module 10 to receive the bias voltage VH and the driving current Ic, and generates an oscillation signal based on the bias voltage VH and the driving current Ic.

[0046] The control module 30 is connected to the oscillation module 20 and the signal processing module 40 . The signal processing module 40 is used to process the enable signal to generate a control signal OSC_CON. The control module 30 is used to control the working state of the oscillation module 20 based on the control signal OSC_CON.

[0047] like Figure 3 As shown, the current unit 11 is used to mirror the reference current Isink to generate a first current Ib1 and a second current Ib2.

[0048] Specifically, the current unit 11 includes an input unit, a first mirror output unit, and a second mirror output unit. The input unit is used to receive a reference current Isink, the first mirror output unit is connected to the input unit to generate a first current Ib1 by mirroring the reference current Isink, and the second mirror output unit is connected to the input unit to generate a second current Ib2 by mirroring the reference current Isink.

[0049] In one embodiment, the reference current Isink is generated by a bandgap reference circuit, and the reference current Isink has a positive temperature coefficient.

[0050] Further, the input unit includes a resistor R, a transistor Mn3 and a transistor Mn4. The first end of the resistor R is connected to the bandgap reference circuit to receive the reference current Isink, the second end of the resistor R is connected to the second end of the transistor Mn3, the first end of the transistor Mn3 is connected to the second end of the transistor Mn4, and the first end of the transistor Mn4 is connected to the ground voltage GND. The control end of the transistor Mn3 is connected to the first end of the resistor R, and the control end of the transistor Mn4 is connected to the second end of the resistor R.

[0051] The first mirror output unit includes a transistor Mn5, a transistor Mn6, a transistor Mn7, a transistor Mn8, a transistor Mp3, a transistor Mp4, a transistor Mp5, a transistor Mp6, and a transistor Mp7.

[0052] The control end of transistor Mn5 and the control end of transistor Mn7 are connected to the first end of resistor R, and the control end of transistor Mn6 and the control end of transistor Mn8 are connected to the second end of resistor R. The first end of transistor Mn6 and the first end of transistor Mn8 are connected to the ground voltage GND, the second end of transistor Mn6 is connected to the first end of transistor Mn5, the second end of transistor Mn8 is connected to the first end of transistor Mn7, the second end of transistor Mn5 is connected to the second end of transistor Mp3, the control end of transistor Mp3, the control end of transistor Mp4 and the control end of transistor Mp7, the second end of transistor Mn7 is connected to the second end of transistor Mp4, the control end of transistor Mp5 and the control end of transistor Mp6, the first end of transistor Mp3, the first end of transistor Mp5 and the first end of transistor Mp6 are connected to the power supply voltage, the first end of transistor Mp4 is connected to the second end of transistor Mp5, the second end of transistor Mp6 is connected to the first end of transistor Mp7, and the second end of transistor Mp7 is used to generate the first current Ib1.

[0053] The second mirror output unit includes a transistor Mn9 and a transistor Mn10, wherein the control end of the transistor Mn9 is connected to the first end of the resistor R, the control end of the transistor Mn10 is connected to the second end of the resistor R, the first end of the transistor Mn10 is connected to the ground voltage GND, the second end of the transistor Mn10 is connected to the first end of the transistor Mn9, and the second end of the transistor Mn9 is used to generate a second current Ib2.

[0054] Since the reference current Isink has a positive temperature coefficient, and the first current Ib1 and the second current Ib2 are both generated by mirroring the reference current Isink, the first current Ib1 and the second current Ib2 also have positive temperature coefficients. By changing the size of each transistor in the input unit, the first mirror output unit and the second mirror output unit, the size of the first current Ib1 and the second current Ib2 can be changed. In one embodiment, the first current Ib1 is greater than the second current Ib2.

[0055] In other embodiments, the current unit 11 may also sample other forms of current mirror circuits to mirror the reference current Isink to generate the first current Ib1 and the second current Ib2 .

[0056] like Figure 4As shown, the conversion unit 12 includes a first load unit. Both ends of the first load unit are connected to the current unit 11, and the current unit 11 is used to inject a first current Ib1 into the first load unit and extract a second current Ib2 from the first load unit to generate a bias voltage VH and a driving current Ic at one end of the first load unit.

[0057] Specifically, the first load unit may include a transistor Mp1 and a transistor Mn1. The first end of the transistor Mp1 is connected to the second end of the transistor Mp7 and forms the first end of the first load unit, receiving the injected first current Ib1. The control end of the transistor Mp1, the second end of the transistor Mp1, and the second end of the transistor Mn1 are connected to the control end of the transistor Mn1, and the first end of the transistor Mn1 is connected to the second end of the transistor Mn9 and forms the second end of the first load unit, from which the second current Ib2 is extracted. The first end of the first load unit is connected to the oscillation module 20 to output the bias voltage VH and the drive current Ic.

[0058] By injecting the first current Ib1 into the first end of the transistor Mp1 and extracting the second current Ib2 from the first end of the transistor Mn1, the magnitude of the driving current Ic flowing out from the first end of the transistor Mp1 is Ib1-Ib2. Since the first current Ib1 and the second current Ib2 are both positive temperature coefficient currents, their current difference can offset each other's temperature coefficients, so that the driving current Ic is less affected by temperature and has good stability.

[0059] This driving current Ic finally provides the current required for the oscillation module 20 to work, thereby ensuring that the oscillation module 20 has a stable bias voltage VH and the current consumed is also at a stable level, making the output frequency more stable. At the same time, the driving current Ic can be controlled at a smaller current value, which is conducive to the oscillation module 20 to generate a low-frequency oscillation signal.

[0060] In other embodiments, the first load unit may also include one or more resistors or other devices connected between the second end of the transistor Mp7 and the second end of the transistor Mn9, and a plurality of such devices may be connected in series, in parallel or in other ways.

[0061] like Figure 5 As shown, the control module 30 may include an OR gate OR, a first input end of the OR gate OR is connected to the signal processing module 40 to receive the control signal OSC_CON, a second input end of the OR gate OR is connected to the input end of the oscillation module 20, and an output end of the OR gate OR is connected to the output end of the oscillation module 20.

[0062] In a specific embodiment, for a ring oscillator, the oscillation module 20 generally includes an inverter oscillation loop formed by an odd number of inverters connected in series, and the input and output of the oscillation module 20 can be connection nodes of any two inverters in the oscillation loop. Among them, the output of the first inverter can be connected to the second input of the OR gate OR as the input of the oscillation module 20, and the input of the second inverter can be connected to the output of the OR gate OR as the output of the oscillation module 20. At this time, when the first input of the OR gate OR receives a high level, the output of the OR gate OR is also controlled at a high level, then the oscillation module 20 does not oscillate and maintains a high level output; when the first input of the OR gate OR receives a low level, the output of the OR gate OR will follow the level on the second input of the OR gate OR, then the oscillation module 20 can normally perform oscillation and output an oscillation signal.

[0063] In other embodiments, the OR gate OR may be connected to the oscillation module 20 according to the specific form of the oscillation module 20, so that the OR gate OR can control the oscillation module 20 to oscillate. The control module 30 may also include a switch or other devices connected between the input end and the output end of the oscillation module 20, and these devices may control their own on and off based on the control signal OSC_CON, and control the oscillation module 20 to oscillate based on their own on and off.

[0064] like Figure 5 As shown, the signal processing module 40 includes a capacitor C1, a delay inverter Nlc, a first switch tube Mn2 and a second switch tube Mp2.

[0065] Among them, the first end of the capacitor C1 is connected to the input end of the delay inverter Nlc and is used to receive the first enable signal EN, the output end of the delay inverter Nlc is used to generate the control signal OSC_CON, the first end and the second end of the first switch tube Mn2 are respectively connected to the two ends of the capacitor C1, the control end of the first switch tube Mn2 is used to receive the second enable signal ENB, the first end of the second switch tube Mp2 is connected to the reference voltage, the second end of the second switch tube Mp2 is connected to the input end of the delay inverter Nlc, and the control end of the second switch tube Mp2 is connected to the output end of the delay inverter Nlc.

[0066] In one embodiment, the initial enable signal OSC_EN is inverted by the inverter N1 to obtain the second enable signal ENB, and the second enable signal ENB is inverted by the inverter N2 to obtain the first enable signal EN. In other embodiments, the first enable signal EN and the second enable signal ENB can also be set to other signals as needed.

[0067] In one embodiment, the reference voltage is a bias voltage VH. In other embodiments, the reference voltage may also be set to other voltages as required.

[0068] When the initial enable signal OSC_EN is low, the second enable signal ENB is high, and the first enable signal EN is low. The first switch tube Mn2 is turned on, both ends of the capacitor C1 are low, the control signal OSC_CON generated by the delay inverter Nlc is high, and the second switch tube Mp2 is turned off.

[0069] At this time, the OR gate OR always receives a high level signal, and the output is also high level, and the oscillation module 20 continuously outputs a high level without oscillating.

[0070] When the initial enable signal OSC_EN becomes high, the second enable signal ENB is low, and the first enable signal EN is high. The first switch tube Mn2 is turned off, the capacitor C1 starts to charge, and the voltage on the first end of the capacitor C1 gradually rises to a high level. After the delay inverter Nlc delays for a period of time, the control signal OSC_CON turns low. The second switch tube Mp2 is turned on, and the voltage at the input end of the delay inverter Nlc is pulled up, so that the control signal OSC_CON is locked at a low level.

[0071] At this time, the first input terminal of the OR gate OR is at a low level, the output terminal level of the OR gate OR is consistent with the level of the second input terminal of the OR gate OR, and the oscillation module 20 starts to oscillate.

[0072] The signal processing module 40 generates a control signal OSC_CON after delay processing of the initial enable signal OSC_EN. When the oscillation module 20 is controlled to oscillate based on the control signal OSC_CON, a period of unstable frequency when the initial enable signal OSC_EN just turns high can be filtered out.

[0073] In other embodiments, the first switch tube Mn2 and / or the second switch tube Mp2 may not be provided in the signal processing module 40. When the first switch tube Mn2 is not provided, the second end of the capacitor C1 may be connected to the ground voltage GND or other voltages as required.

[0074] like Figure 5 As shown, in one embodiment, the ring oscillator may further include a first level converter LS1, a second level converter LS2, a second inverting unit N3 and a Schmitt trigger SMT.

[0075] The input end of the second inverting unit N3 is connected to the output end of the delay inverter N1c to receive the control signal OSC_CON, and the second inverting unit N3 is used to invert the control signal OSC_CON to generate a first inverted signal. The input end of the second level converter LS2 is connected to the output end of the second inverting unit N3 to receive the first inverted signal, and the second level converter LS2 is used to convert the first inverted signal into a second inverted signal EN_Delay. The enable end of the first level converter LS1 is connected to the output end of the second level converter LS2 to receive the second inverted signal EN_Delay, the input end of the first level converter LS1 is connected to the output end of the oscillation module 20 to receive the oscillation signal, and the first level converter LS1 is used to convert the oscillation signal into an output signal based on the control of the second inverted signal EN_Delay, the input end of the Schmitt trigger SMT is connected to the output end of the first level converter LS1 to receive the output signal, and the output end of the Schmitt trigger SMT is used to generate a clock signal OSC_OUT.

[0076] Before the control signal OSC_CON turns from high level to low level, the first inverted signal generated by the second inverting unit continues to be at a low level. The enable end of the second level converter LS2 can receive the initial enable signal OSC_EN or the power supply voltage. At this time, regardless of whether the second level converter LS2 works normally, the second inverted signal EN_Delay is always at a low level, the first level converter LS1 does not work, and the clock signal OSC_OUT output by the Schmitt trigger SMT is a constant 0 or 1.

[0077] When the control signal OSC_CON turns to a low level, the oscillation module 20 starts to oscillate, and the first inverted signal is at a high level. At this time, the second level converter LS2 has been working normally. The second level converter LS2 converts the first inverted signal into a second inverted signal EN_Delay with a suitable voltage. The first level converter LS1 starts to work normally based on the second inverted signal EN_Delay, and performs level conversion on the oscillation signal to output an output signal in a specified voltage domain. Finally, the Schmitt trigger SMT shapes the output signal to obtain a clock signal OSC_OUT with a stable frequency.

[0078] In other embodiments, the second level converter LS2 and / or the Schmitt trigger SMT may not be provided. When the second level converter LS2 is not provided, the enable end of the first level converter LS1 may be directly connected to the output end of the second inverting unit to receive the first inverting signal, and the oscillation signal may be converted into an output signal based on the control of the first inverting signal. When the Schmitt trigger SMT is not provided, the output signal generated by the first level converter LS1 is directly used as the output signal of the entire ring oscillator.

[0079] like Figure 5 As shown, the oscillation module 20 includes a plurality of first inverters and a loop control unit. The loop control unit includes a plurality of loop control subunits, each loop control subunit and each first inverter form a plurality of oscillation loops, and the loop control unit controls each loop control subunit based on the adjustment signal to select one of the oscillation loops to generate an oscillation signal.

[0080] In one embodiment, 2N first inverters are provided, namely, first inverter Na1 to first inverter NaN, first inverter Nb1 to first inverter NbN, wherein N≥ 2. In other embodiments, the number of first inverters may also be other.

[0081] Specifically, the loop control subunit may include second inverters, and each second inverter and at least two first inverters form an oscillation loop.

[0082] In one embodiment, there are N second inverters, namely, second inverter Nc1 to second inverter NcN. In other embodiments, the number of second inverters may also be other.

[0083] The adjustment signal can be used as an enable signal for the second inverter, and each second inverter can be turned on or off based on the adjustment signal. When the second inverter is turned on, the oscillation loop formed by the second inverter is turned on and starts to oscillate, and when the second inverter is turned off, the oscillation loop formed by the second inverter is disconnected and does not oscillate.

[0084] In one embodiment, an even number of first inverters corresponding to two branches constitute an inverter group, the inverter groups are connected in sequence to form two branches, and each second inverter is respectively connected between the first inverters of each inverter group and forms an oscillation loop with one or more inverter groups.

[0085] like Figure 5 As shown, in a specific embodiment, a first inverter Nai and a first inverter Nbi may form an inverter group, where 1≤i≤N. These inverter groups are sequentially connected to form two branches, namely, a first branch formed by the first inverter Na1 to the first inverter NaN, and a second branch formed by the first inverter Nb1 to the first inverter NbN.

[0086] The input end of the first inverter Na1 is the output end of the oscillation module 20 and is connected to the output end of the OR gate OR. The output end of the first inverter Nb1 is the input end of the oscillation module 20 and is connected to the second input end of the OR gate OR.

[0087] The input end of the second inverter Nci can be connected to the output end of the first inverter Nai, and the output end of the second inverter Nci can be connected to the input end of the first inverter Nbi. At this time, the second inverter Nci and the first inverter Na1~first inverter Nai, the first inverter Nb1~first inverter Nbi form an oscillation loop, and this loop is connected with 2i+1 inverters in total. Only when the second inverter Nci is turned on, this oscillation loop can be turned on and oscillate, and when the second inverter Nci is turned off, this oscillation loop is turned off.

[0088] In other embodiments, other first inverters may be used to form an inverter group, and the number of second inverters connected between the inverter groups may be another odd number.

[0089] like Figure 6 and Figure 7 As shown, the ring oscillator in this embodiment may further include a decoder 50 and a logic unit 60 .

[0090] The decoder 50 is connected to each loop control subunit, and the logic unit 60 is connected to the decoder 50 and each first inverter. The decoder 50 is used to decode the adjustment value to generate an adjustment signal to control each loop control subunit. The logic unit 60 is used to perform logical operations on the adjustment signal and the bias voltage VH respectively to generate a corresponding logic signal to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logic signal.

[0091] Specific, combined Figure 5 , Figure 6 and Figure 7 As shown, the decoder 50 is connected to the enable terminal of each second inverter, and the decoder 50 generates the adjustment signal SW1~adjustment signal SWN by decoding the adjustment value, and transmits the adjustment signal SW1~adjustment signal SWN to the corresponding second inverter Nc1~second inverter NcN to control the second inverter to be turned on or off. In this embodiment, the adjustment signal only turns on one second inverter at the same time, that is, only one adjustment signal is at a high level at the same time, and the others are all at a low level.

[0092] The logic unit 60 is connected to the enable end of each first inverter. The logic unit 60 performs logic operations on the adjustment signal SW1~adjustment signal SWN and the bias voltage VH to generate corresponding logic signals: logic signal SW1a~logic signal SWNa, and transmits the logic signal to the enable end of the corresponding first inverter, that is, transmits the logic signal SWia to the enable end of the first inverter Nai and the enable end of the first inverter Nbi to control each first inverter.

[0093] In this embodiment, when the second inverter Nci is turned on, the logic unit 60 controls the first inverter Na1~first inverter Nai, the first inverter Nb1~first inverter Nbi to be turned on, and the other first inverters are turned off, so that the oscillation loops formed by the second inverter Nci and the first inverter Na1 to the first inverter Nai, the first inverter Nb1 to the first inverter Nbi are all turned on and start to oscillate, and the other oscillation loops do not work.

[0094] In a specific embodiment, N is 16, and the decoder 50 can be a 4-16 decoder, that is, it can decode the 4-bit binary adjustment values ​​DEC0, DEC1, DEC2, and DEC3, and output 16 independent adjustment signals: adjustment signal SW1~adjustment signal SW16. 4-16 decoding can be implemented using existing technology, and will not be described in detail here. In other embodiments, other decoders can also be selected according to the form of the adjustment value and the actual needs of the adjustment signal.

[0095] The logic unit 60 includes 16 logic sub-units, namely a first logic sub-unit 61 to a sixteenth logic sub-unit 616 .

[0096] The first logic subunit 61 includes two inverters connected in series, and is used to generate a logic signal SW1a after inverting the bias voltage VH twice. The logic signal SW1a is always at a high level, and controls the first inverter Na1 and the first inverter Nb1 to be always turned on.

[0097] The second logic subunit 62 includes three inverters connected in series, and is used to invert the adjustment signal SW1 to generate a logic signal SW2a. The logic signal SW2a is low level only when the adjustment signal SW1 is high level, that is, when the second inverter Nc1 is turned on, otherwise it is high level, and controls the first inverter Na2 and the first inverter Nb2 to be turned off when the second inverter Nc1 is turned on, and to be turned on at other times.

[0098] The third logic subunit 63 includes three inverters and a NOR gate. The input end of the first inverter is connected to the output end of the first inverter in the second logic subunit 62, and the output end is connected to the first input end of the NOR gate. The second input end of the NOR gate is used to receive the adjustment signal SW2. The output end of the NOR gate is connected to the second inverter and the third inverter connected in series, and finally generates a logic signal SW3a in phase with the output signal of the NOR gate.

[0099] Specifically, the two input ends of the NOR gate receive the adjustment signal SW2 and the signal in phase with the adjustment signal SW1, respectively, that is, only when the adjustment signal SW2 and the adjustment signal SW1 are both at a low level, the output of the XOR gate OR is at a high level, otherwise it is at a low level. Therefore, it can be regarded that only when the second inverter Nc1 is turned on and the second inverter Nc2 is turned off, the logic signal SW3a is at a high level and controls the first inverter Na3 and the first inverter Nb3 to turn on.

[0100] The structures and working principles of the fourth logic sub-unit 64 to the sixteenth logic sub-unit 616 are similar to those of the third logic sub-unit 63 , and are not elaborated herein.

[0101] In other embodiments, the first logic subunit 61 may also generate a high-level logic signal SW1a based on other voltages to put the first inverter Na1 and the first inverter Nb1 in a normally open state. The first logic subunit 61 may also not be provided, and the first inverter Na1 and the first inverter Nb1 may be directly placed in a normally open state. In this case, the logic unit 60 is used to perform logic operations on the adjustment signal only to generate corresponding logic signals to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logic signal.

[0102] In other embodiments, the specific structure and working principle of the logic unit 60 can be adjusted according to the specific form of the adjustment signal and the oscillation module 20 .

[0103] In one embodiment, the power supply terminals of all the first inverters and the second inverters in the oscillation module 20 are connected to the first terminal of the transistor Mp1 in the bias module 10 to obtain the bias voltage VH as the working voltage and the drive current Ic as the working current. Thanks to the good stability of the drive current Ic and the bias voltage VH, the output frequency of the oscillation loop composed of the first inverter and the second inverter is less affected by temperature, process angle, etc., and the stability is significantly improved.

[0104] The signal processing module 40, control module 30, decoder 50, logic unit 60 and other parts in the ring oscillator can also use the bias voltage VH as the operating voltage, and provide the operating current through the driving current Ic, or other power supply voltages can be used. The voltage division of these circuit parts will not affect the working characteristics of the oscillation loop.

[0105] In one embodiment, the transistors and switch tubes mentioned in the present application are all MOS tubes, the first end of each transistor and switch tube is a source, the second end of each transistor and switch tube is a drain, and the control end of each transistor and switch tube is a gate. In other embodiments, each transistor and switch tube can also use other devices, each P-type tube can be replaced by an N-type tube, and the N-type tube can be replaced by a P-type tube, and their connection methods and control methods can be adaptively adjusted.

[0106] In the actual working process, the bias module 10 first generates a first current Ib1 and a second current Ib2 based on the reference current Isink, and then generates a bias voltage VH and a drive current Ic provided to the oscillation module 20 based on the first current Ib1 and the second current Ib2. Since the bias voltage VH and the drive current Ic have good stability, the output frequency of the oscillation module 20 is more stable. At the same time, since the drive current Ic can be controlled at a smaller current value, it can also help control the oscillation module 20 to generate a low-frequency oscillation signal.

[0107] Next, after the initial enable signal OSC_EN turns high, the signal processing module 40 delays it to generate the control signal OSC_CON, and then controls the oscillation module 20 to oscillate based on the control signal OSC_CON, so that the oscillation module 20 starts to oscillate later than the initial enable signal OSC_EN turns high, thereby filtering out a period of unstable frequency when the ring oscillator just starts to work, ensuring that the frequency of the oscillation signal is always stable.

[0108] Finally, the oscillation signal generated by the oscillation module 20 can be sorted by the first level converter LS1 and the Schmitt trigger SMT, and finally a clock signal within a target range can be generated.

[0109] When the oscillation module 20 oscillates to generate an oscillation signal, the specified oscillation loop can be selected for oscillation by setting an adjustment value, and generating a corresponding adjustment signal and logic signal based on the adjustment value, thereby changing the number of inverters connected to the oscillation loop. The frequency can be calibrated by increasing / decreasing the inverters in the oscillation loop, and then the frequency deviation under different process angles can be calibrated, so that the target frequency can be reached more accurately without introducing other errors when adjusting the frequency.

[0110] Figure 8 The figure shows the calibration step size under different process angles. It can be seen that the maximum calibration step size is 3.4%, which means that after calibration, the output frequency accuracy of the system can be within ±1.7%.

[0111] Fig. 9The figure shows the change in the output frequency of the ring oscillator when the temperature changes from -40°C to 125°C after calibration. It can be seen that the output frequency deviation is between -7% and 5%. Compared with existing ring oscillator products, the stability has been effectively improved.

[0112] Embodiment 2

[0113] like Fig.10 As shown, the ring oscillator in this embodiment is different from that in the first embodiment only in the conversion unit 12, and the structures and working principles of other modules are the same as those in the first embodiment. Only the conversion unit 12 is described below, and other aspects are not elaborated in detail.

[0114] In this embodiment, the conversion unit 12 of the ring oscillator includes a current generating unit, a second load unit and a buffer.

[0115] Among them, the current generating unit is connected to the current unit 11 to generate a third current I3 based on the current difference between the first current Ib1 and the second current Ib2, the first end of the second load unit is connected to the current generating unit to generate a conversion voltage VHa based on the third current I3, the second end of the second load unit is connected to the ground voltage GND, the input end of the buffer B1 is connected to the first end of the second load unit to receive the conversion voltage VHa, and the output end of the buffer B1 is used to output a bias voltage VH and a drive current Ic.

[0116] Specifically, the current generating unit may include a current mirror connected to the second end of the transistor Mp7 and the second end of the transistor Mn9, and the current mirror is used to generate a third current by mirroring the current difference between the first current Ib1 and the second current Ib2.

[0117] In one embodiment, the current mirror may include a transistor Mn21, a transistor Mn22, a transistor Mp21, and a transistor Mp22.

[0118] The control end of transistor Mn21, the second end of transistor Mn21 and the control end of transistor Mn22 are connected to the second end of transistor Mp7 and the second end of transistor Mn9, the first end of transistor Mn21 and the first end of transistor Mn22 are connected to the ground voltage GND. The second end of transistor Mn22 is connected to the control end of transistor Mp21, the second end of transistor Mp21 and the control end of transistor Mp22, the first end of transistor Mp21 and the first end of transistor Mp22 are connected to the power supply voltage, and the second end of transistor Mp22 is connected to the first end of the second load unit to generate the third current I3.

[0119] In one embodiment, the second load unit may include a transistor Mn23. The second terminal of the transistor Mn23 and the control terminal of the transistor Mn23 are connected to the second terminal of the transistor Mp22 in the current mirror to generate the conversion voltage VHa, and the first terminal of the transistor Mn21 is connected to the ground voltage GND.

[0120] In other embodiments, the second load unit may include one or more resistors or other devices connected between the second end of the transistor Mp22 and the ground voltage, and a plurality of such devices may be connected in series, in parallel or in other connection modes.

[0121] In other embodiments, the buffer B1 may not be provided, and the first end of the second load unit is connected to the current generating unit to directly generate the bias voltage VH and the driving current Ic based on the third current I3.

[0122] In this embodiment, the power supply terminals of the first inverter and the second inverter may be connected to the output terminal of the buffer B1 to obtain the bias voltage VH as the operating voltage and the drive current Ic as the operating current.

[0123] In this embodiment, the third current I3 is obtained by mirroring the difference current between the first current Ib1 and the second current Ib2, and then the third current I3 is converted by the second load unit to obtain the conversion voltage VH, so that the conversion voltage VH also has the characteristics of stability and easy control.

[0124] Then, the conversion voltage VH is buffered by the buffer B1, so that the bias voltage VH and the driving current Ic outputted by the buffer B1 inherit the above characteristics, thereby making the output frequency of the oscillation module 20 more stable and facilitating the control of the oscillation module 20 to generate a low-frequency oscillation signal.

[0125] Embodiment 3 like Fig.11 As shown, the ring oscillator in this embodiment is different from that in the first embodiment only in the signal processing module 40, and the structures and working principles of other modules are the same as those in the first embodiment. Only the signal processing module 40 is described below, and other aspects are not elaborated in detail.

[0126] In this embodiment, the signal processing module 40 of the ring oscillator includes a first inverting unit for inverting the initial enable signal OSC_EN to generate the control signal OSC_CON. Specifically, the first inverting unit may include one or more inverters connected in series, and the number of the inverters is an odd number.

[0127] Different from the first embodiment, the signal processing module 40 in this embodiment does not have a delay function, but other control functions are the same as those in the first embodiment.

[0128] Embodiment 4

[0129] like Fig.12 As shown, the ring oscillator in this embodiment is different from that in the first embodiment only in the oscillation module 20, and the structures and working principles of other modules are the same as those in the first embodiment. Only the oscillation module 20 is described below, and other aspects are not elaborated in detail.

[0130] In this embodiment, the oscillation module 20 includes multiple first inverters and a loop control unit. The loop control unit includes multiple loop control sub-units. Each loop control sub-unit and each first inverter constitute multiple oscillation loops. The loop control unit controls each loop control sub-unit based on the adjustment signal to select one of the oscillation loops to generate an oscillation signal.

[0131] Among them, multiple first inverters are connected in series to form a group of inverter groups, the output end of each inverter group is connected to form the input end of the oscillation module 20, and is connected to the second input end of the OR gate OR, and the input end of each inverter group is connected to form the output end of the oscillation module 20, and is connected to the output end of the OR gate OR.

[0132] In one embodiment, the first inverters are divided into N groups, and the i-th group of first inverters is recorded as first inverter Nai, where 1≤i≤N. Each group of first inverters is sequentially connected in series to form an inverter group. The number of first inverters in each group is an even number.

[0133] In one embodiment, the loop control subunit includes second inverters, and each second inverter forms an oscillation loop with at least two first inverters.

[0134] Specifically, there are N second inverters, namely, second inverters Nc1 to second inverters NcN. The second inverter Nci is connected to the i-th inverter group and forms an oscillation loop with the i-th inverter group. At this time, each oscillation loop includes at least two first inverters and one second inverter, and the total number of first inverters and second inverters is an odd number.

[0135] In other embodiments, other numbers of first inverters and second inverters may be provided, and the number of first inverters and second inverters in each inverter group may also be changed, as long as the total number of first inverters and second inverters in each oscillation loop is an odd number.

[0136] The adjustment signal can be used as an enable signal for the second inverter, and each second inverter can be turned on or off based on the adjustment signal, and the second inverters located in the same oscillation loop receive the same adjustment signal. When the second inverter is turned on, the oscillation loop formed by the second inverter is turned on and starts to oscillate, and when the second inverter is turned off, the oscillation loop formed by the second inverter is disconnected and does not oscillate.

[0137] The decoder 50 in this embodiment may be the same as the decoder 50 in the first embodiment, and the adjustment signal generated by the decoder 50 may be transmitted to the second inverter in the corresponding oscillation loop.

[0138] In this embodiment, the logic unit 60 may not be provided, and the oscillation loop can be selected by simply selecting the second inverter.

[0139] In other specific embodiments, the second inverter in the loop control subunit may also be replaced by a switch or other device. Specifically, the switch or other device may be connected to the inverter group and form an oscillation loop with the inverter group. The switch or other device may control its own on and off based on the adjustment signal to control the oscillation loop to oscillate. In this case, the number of first inverters in each oscillation loop is an odd number.

[0140] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0141] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A ring oscillator, characterized in that: include: Bias module and oscillation module; The bias module includes a current unit and a conversion unit connected to each other, the current unit is used to generate a first current and a second current based on a reference current, the conversion unit is used to generate a bias voltage based on the second current or generate a bias voltage based on a current difference between the first current and the second current, and generate a drive current based on the current difference between the first current and the second current, the oscillation module is connected to the bias module to receive the bias voltage and the drive current, and generates an oscillation signal based on the bias voltage and the drive current.

2. The ring oscillator according to claim 1, characterized in that The conversion unit includes a first load unit, two ends of the first load unit are connected to a current unit, and the current unit is used to inject a first current into the first load unit and extract a second current from the first load unit to generate a bias voltage and a driving current at one end of the first load unit; or The conversion unit includes a current generating unit and a second load unit, the current generating unit is connected to the current unit to generate a third current based on a current difference between the first current and the second current, a first end of the second load unit is connected to the current generating unit to generate a bias voltage and a driving current based on the third current, and a second end of the second load unit is connected to a ground voltage; or The conversion unit includes a current generating unit, a second load unit and a buffer, wherein the current generating unit is connected to the current unit to generate a third current based on a current difference between a first current and a second current, a first end of the second load unit is connected to the current generating unit to generate a conversion voltage based on the third current, a second end of the second load unit is connected to a ground voltage, an input end of the buffer is connected to the first end of the second load unit to receive the conversion voltage, and an output end of the buffer is used to output a bias voltage and a driving current.

3. The ring oscillator according to claim 1, characterized in that: The ring oscillator further comprises a control module connected to the oscillation module and a signal processing module connected to the control module, wherein the signal processing module is used to process the enable signal to generate a control signal, and the control module is used to control the working state of the oscillation module based on the control signal.

4. The ring oscillator according to claim 3, characterized in that: The control module comprises an OR gate, a first input end of the OR gate is connected to the signal processing module to receive a control signal, a second input end of the OR gate is connected to the input end of the oscillation module, and an output end of the OR gate is connected to the output end of the oscillation module.

5. The ring oscillator according to claim 3, characterized in that: The signal processing module includes a capacitor and a delay inverter, wherein a first end of the capacitor is connected to an input end of the delay inverter and is used to receive a first enable signal, and an output end of the delay inverter is used to generate a control signal; or The signal processing module includes a capacitor, a delay inverter and a first switch tube, wherein the first end of the capacitor is connected to the input end of the delay inverter and is used to receive a first enable signal, the output end of the delay inverter is used to generate a control signal, the first end and the second end of the first switch tube are respectively connected to the two ends of the capacitor, and the control end of the first switch tube is used to receive a second enable signal; or The signal processing module includes a capacitor, a delay inverter and a second switch tube, wherein the first end of the capacitor is connected to the input end of the delay inverter and is used to receive a first enable signal, the output end of the delay inverter is used to generate a control signal, the first end of the second switch tube is connected to a reference voltage, the second end of the second switch tube is connected to the input end of the delay inverter, and the control end of the second switch tube is connected to the output end of the delay inverter; or The signal processing module includes a capacitor, a delay inverter, a first switch tube and a second switch tube, the first end of the capacitor is connected to the input end of the delay inverter and is used to receive a first enable signal, the output end of the delay inverter is used to generate a control signal, the first end and the second end of the first switch tube are respectively connected to the two ends of the capacitor, the control end of the first switch tube is used to receive a second enable signal, the first end of the second switch tube is connected to a reference voltage, the second end of the second switch tube is connected to the input end of the delay inverter, and the control end of the second switch tube is connected to the output end of the delay inverter; or The signal processing module comprises a first inverting unit for inverting an initial enable signal to generate a control signal.

6. The ring oscillator according to claim 3, characterized in that: The ring oscillator further includes a first level converter and a second inverting unit, the second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal, the first level converter is connected to the second inverting unit to receive the first inverted signal, and the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the first inverted signal; or The ring oscillator further includes a first level converter, a second inverting unit and a Schmitt trigger, wherein the second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal, the first level converter is connected to the second inverting unit to receive the first inverted signal, the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the first inverted signal, the input end of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output end of the Schmitt trigger is used to generate a clock signal; or The ring oscillator further comprises a first level converter, a second level converter and a second inverting unit, wherein the second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal, the second level converter is connected to the second inverting unit to convert the first inverted signal into a second inverted signal, the first level converter is connected to the second level converter to receive the second inverted signal, and the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the second inverted signal; or The ring oscillator further includes a first level converter, a second level converter, a second inverting unit and a Schmitt trigger, wherein the second inverting unit is connected to the signal processing module to invert the control signal to generate a first inverted signal, the second level converter is connected to the second inverting unit to convert the first inverted signal into a second inverted signal, the first level converter is connected to the second level converter to receive the second inverted signal, the first level converter is connected to the oscillation module to convert the oscillation signal into an output signal based on the control of the second inverted signal, the input end of the Schmitt trigger is connected to the first level converter to receive the output signal, and the output end of the Schmitt trigger is used to generate a clock signal.

7. The ring oscillator according to claim 1, characterized in that: The oscillation module includes a plurality of first inverters and a loop control unit. The loop control unit includes a plurality of loop control sub-units. Each of the loop control sub-units and each of the first inverters form a plurality of oscillation loops. The loop control unit controls each of the loop control sub-units based on an adjustment signal to select one of the oscillation loops to generate an oscillation signal.

8. The ring oscillator according to claim 7, characterized in that: The loop control subunit includes second inverters, and each of the second inverters forms an oscillation loop with at least two first inverters.

9. The ring oscillator according to claim 8, characterized in that: An even number of the first inverters corresponding to two branches constitute an inverter group, the inverter groups are connected in sequence to form two branches, and each of the second inverters is respectively connected between the first inverters of each inverter group and forms an oscillation loop with one or more inverter groups.

10. The ring oscillator according to any one of claims 7, 8 and 9, characterized in that: The ring oscillator further comprises a decoder connected to each loop control subunit, the decoder being used to decode the adjustment value to generate an adjustment signal to control each loop control subunit to select one of the oscillation loops to generate an oscillation signal; or The ring oscillator also includes a decoder and a logic unit. The decoder is connected to each loop control subunit, and the logic unit is connected to the decoder and each first inverter. The decoder is used to decode the adjustment value to generate an adjustment signal to control each loop control subunit. The logic unit is used to perform a logic operation on the adjustment signal, or perform a logic operation on the adjustment signal and the bias voltage respectively to generate a corresponding logic signal to control each first inverter, and select one of the oscillation loops to generate an oscillation signal in combination with the adjustment signal and the logic signal.

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