LDPC code coding circuit for improving coding efficiency based on 5G communication system

Abstract

The invention relates to the technical field of LDPC code coding, in particular to an LDPC code coding circuit for improving coding efficiency based on a 5G communication system, and the circuit comprises a processing unit which is used for obtaining a check matrix of a cyclic LDPC code, obtaining a generation matrix according to the check matrix, and splitting the generation matrix; the calculation unit is used for receiving information input needing to be verified and calculated to generate currents of different magnitudes and collecting the currents of all columns of units; the comparison unit is used for comparing the collected current with a reference current and generating 0 / 1 output; and the accumulation unit is used for performing XOR accumulation on calculation results of the parallel calculation array. According to the method, the memristor array can be dynamically adjusted according to requirements, higher calculation efficiency and area advantages are achieved, calculation efficiency is improved through calculation concurrency, a grouping mode is adopted, and interference of potential channel currents in a large calculation array is avoided.

Description

Technical Field

[0001] The present invention relates to the field of LDPC code encoding technology, and in particular to an LDPC code encoding circuit for improving encoding efficiency based on a 5G communication system. Background Art

[0002] LDPC code, as an efficient error correction code, has a wide range of uses and remarkable characteristics. In the field of communications, LDPC code is widely used in wireless communication standards such as 5G, Wi-Fi and satellite communications. Due to its performance close to the Shannon limit, it can significantly improve the reliability of data transmission. In addition, LDPC code also plays an important role in fiber-optic communication and digital video broadcasting, enhancing the anti-interference ability of communication systems by improving signal transmission quality. In storage systems, LDPC codes reduce data transmission errors by improving the reliability and density of data storage, thereby optimizing the performance of storage devices. Its characteristics include sparse parity check matrices, which make LDPC codes easy to implement in hardware and have low computational complexity.

[0003] For the calculation of sparse check matrices in traditional circuits, the hardware implementation of LDPC coding circuits needs to consider how to efficiently implement the encoding and decoding algorithms. However, as the code length of LDPC coding continues to increase, the cost of hardware resources is also increasing. Summary of the invention

[0004] The purpose of the present invention is to provide an LDPC code encoding circuit for improving coding efficiency based on a 5G communication system to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the object of the present invention is to provide an LDPC code encoding circuit for improving coding efficiency based on a 5G communication system, comprising:

[0006] Processing unit: used to obtain the check matrix of the cyclic LDPC code, obtain the generator matrix according to the check matrix, and split the generator matrix;

[0007] Calculation unit: used to receive the information input that needs to be verified and calculated to generate currents of different magnitudes, and to collect the currents of each column unit;

[0008] Comparison unit: used to compare the collected current with the reference current and generate 0 / 1 output;

[0009] Accumulation unit: used to perform XOR accumulation on the calculation results of the parallel calculation array.

[0010] As a further improvement of the technical solution, the processing unit is based on the check basis matrix S and the unit matrix I 0 Get the check matrix H.

[0011] As a further improvement of the technical solution, the specific steps of the processing unit obtaining the generator matrix according to the check matrix are:

[0012] Divide the codeword and check matrix into two parts, c 1×n =c=[s 1×k |p 1×m ]=[s|p],c 1×n and c both represent n-bit codewords, s 1×k and s both represent k bits of information, p 1×m and p both represent the m-bit check digit, H m×n and H both represent the check matrix with m rows and n columns. and H s Both represent the systematic bits in the check matrix. and H p All represent the check bit part in the check matrix, which are:

[0013]

[0014] H s s T +H p p T =0 m×1

[0015] All of the above are calculated on the modulo 2 operation, then:

[0016] H s s T =H p p T

[0017]

[0018] Divide the generator matrix into two parts, G k×n =G=[I k×k |P k×(n-k) ]=[I|P],G k×n and G both represent k-row n-column generator matrices, I k×k and I both represent the identity matrix with k rows and k columns, P k×(n-k) and P both represent circulant permutation matrices with k rows (nk) and columns,

[0019] c=sG=s[I|P]=[s|sP]=[s|p]

[0020]

[0021] Where T represents transpose, c 1×n The transposed matrix, sT is the transposed matrix of s, p T is the transposed matrix of p, 0 m×1 is an all-zero matrix with m rows and 1 column, H p The inverse matrix of

[0022]

[0023] Among them, I 0 is the b×b identity matrix, 0 is the b×b all-zero matrix, G i,j is a circulant submatrix, 1≤i≤k, 1≤j≤nk, i and j represent the position of the circulant submatrix in the circulant permutation matrix, and ∣ only represents the partition for easy distinction and does not need to be written in actual input and calculation.

[0024] As a further improvement of the technical solution, the calculation unit takes the information that needs to be verified as input, converts the input information bit data into column information, and the 1 and 0 in the input information bit data correspond to high level and low level respectively.

[0025] As a further improvement of the present technical solution, the computing unit includes a plurality of parallel memristor arrays, the memristor array includes a plurality of memristors distributed in an array, the first ends of the memristors on the same row are connected to each other, the first ends of the memristors are connected to column information corresponding to information bit data conversion, and the second ends of the memristors on the same column are connected to each other.

[0026] As a further improvement of the present technical solution, the memristor array corresponds one-to-one to the circulant sub-matrix. When the cell data in the circulant sub-matrix is ​​0, the corresponding memristor in the memristor array is written with high resistance. When the cell data in the circulant sub-matrix is ​​1, the corresponding memristor in the memristor array is written with low resistance.

[0027] As a further improvement of the present technical solution, the rule for the memristors in the memristor array to generate currents of different sizes is: when the column information converted by the input information bit data is at a high level and the memristor is of low resistance, a larger current is generated on the memristor; otherwise, a smaller current or no current is generated on the memristor.

[0028] As a further improvement of the present technical solution, the comparison unit includes a plurality of comparison circuits, the comparison circuit includes an operational amplifier and a sampling resistor, the first end of the sampling resistor is connected to the current collected by each column of memristors, the first end of the sampling resistor is also connected to the non-inverting input end of the operational amplifier, the second end of the sampling resistor is grounded, the inverting input end of the operational amplifier is connected to a reference voltage, the output end of the operational amplifier generates a 0 / 1 output, and the 0 / 1 output generated by the output end of the operational amplifier represents the data of the codeword.

[0029] As a further improvement of the technical solution, the accumulating unit performs an XOR operation on the output results of the comparison circuit on each column.

[0030] Compared with the prior art, the present invention has the following beneficial effects: in the LDPC code encoding circuit for improving coding efficiency based on the 5G communication system, because the memristor is configurable, the memristor array can be dynamically adjusted according to demand, avoiding the sharp increase in circuit scale caused by flexible configuration when traditional CMOS is used for implementation, and having higher computing performance and area advantages. The computing efficiency is improved by concurrent computing, and a grouping method is used to avoid interference from potential channel currents in large computing arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is the overall structure diagram of the present invention;

[0032] Figure 2 It is a schematic diagram of the structure of the calculation unit and the comparison unit in the present invention;

[0033] Figure 3 is a circuit diagram of a comparison circuit in the present invention;

[0034] Figure 4 It is a partial schematic diagram of Example 1 of the present invention;

[0035] Figure 5 It is a partial schematic diagram of Example 2 of the present invention;

[0036] The meaning of each mark in the figure is:

[0037] 10. Processing unit;

[0038] 20. computing unit; 200. memristor array;

[0039] 30. comparison unit; 300. comparison circuit;

[0040] 40. Accumulation unit. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Example 1

[0043] like Figure 1-Figure 4 As shown, this embodiment provides an LDPC code encoding circuit for improving coding efficiency based on a 5G communication system, including:

[0044] Processing unit 10: used to obtain a check matrix of a cyclic LDPC code, obtain a generator matrix according to the check matrix, and split the generator matrix;

[0045] Calculation unit 20: used to receive information input that needs to be verified and calculated, generate currents of different magnitudes, and collect the currents of each column unit;

[0046] Comparison unit 30: used to compare the collected current with the reference current and generate a 0 / 1 output;

[0047] Accumulation unit 40: used for performing XOR accumulation on the calculation results of the parallel calculation array.

[0048] 5G communication systems require high-speed, low-latency and high-reliability data transmission. The low-complexity encoding and decoding characteristics of quasi-cyclic LDPC codes enable them to effectively reduce processing delays while meeting error correction performance requirements, adapting to the needs of high-speed data processing in 5G communications. The check matrix H of the quasi-cyclic LDPC code has a quasi-cyclic characteristic. This special structure makes the check matrix H have a certain regularity and sparsity. The sparsity helps to reduce the computational complexity in the encoding and decoding process, while the regularity facilitates hardware implementation.

[0049] In this embodiment, the processing unit 10 calculates the value of the check basis matrix S and the identity matrix I according to the 0 Get the check matrix H, assume that the check matrix S is a two-row and three-column matrix, and the unit matrix I 0 The order of is three, we have:

[0050]

[0051] but:

[0052]

[0053] The -1 in the check matrix S is represented by a third-order all-zero matrix, the 0 in the check matrix S is represented by a third-order all-zero matrix, and the 1 in the check matrix S is represented by the third-order identity matrix I 0 The matrix obtained by looping one position to the right, the 2 in the check basis matrix S is represented by the third-order identity matrix I 0 Rotate right two bits to get the resulting matrix.

[0054] Furthermore, the specific steps of the processing unit 10 obtaining the generator matrix according to the check matrix are:

[0055] Divide the codeword and check matrix into two parts, c 1×n =c=[s 1×k |p 1×m ]=[s|p],c 1×nand c both represent n-bit codewords, s 1×k and s both represent k bits of information, p 1×m and p both represent the m-bit check digit, H m×n and H both represent the check matrix with m rows and n columns. and H s Both represent the systematic bits in the check matrix. and H p All represent the check bit part in the check matrix, which are:

[0056]

[0057] H s s T +H p p T =0 m×1

[0058] All of the above operations are performed on modulo 2 operations. GF(2) is a binary Galois field, which contains only two elements, namely 0 and 1. The addition operation is modulo 2 addition, and the rules are: 0+0=0, 0+1=1, 1+0=1, 1+1=0. The multiplication operation is a regular multiplication operation. The subtraction operation is similar to the previous addition operation, and the rules are: 1-1=0, 0-0=0, 1-0=1, 0-1=1, then:

[0059] H s s T =H p p T

[0060]

[0061] Divide the generator matrix into two parts, G k×n =G=[I k×k |P k×(n-k) ]=[I|P],G k×n and G both represent k-row n-column generator matrices, I k×k and I both represent the identity matrix with k rows and k columns, P k×(n-k) and P both represent circulant permutation matrices with k rows (nk) and columns;

[0062] Assume that the information to be transmitted is the number 6, then s = [1 1 0],

[0063]

[0064] c=sG=s[I|P]=[s|sP]=[s|p]

[0065]

[0066]

[0067] All of the above are performed modulo 2 operations, so -1 in the matrix can be replaced with 1.

[0068]

[0069] Where T represents transpose, c 1×n The transposed matrix, s T is the transposed matrix of s, p T is the transposed matrix of p, 0 m×1 is an all-zero matrix with m rows and 1 column, H p The inverse matrix of

[0070]

[0071] Among them, I 0 is the b×b identity matrix, 0 is the b×b all-zero matrix, G i,j is a circulant submatrix, 1≤i≤k, 1≤j≤nk, i and j represent the position of the circulant submatrix in the circulant permutation matrix, ∣ only represents the partition, which is convenient for distinction and does not need to be written in actual input and calculation;

[0072] Calculate the codeword c and check bit p for subsequent verification:

[0073]

[0074] We can obtain the check bit p = [0 1 1 1 0 1] and the code word c = [1 1 0 0 1 1 1 0 1].

[0075] In this embodiment, the calculation unit 20 takes the information to be verified as input, converts the input information bit data into column information, and the 1 and 0 in the input information bit data correspond to the high level and the low level respectively, s = [1 1 0], which can be converted into

[0076] Furthermore, the computing unit 20 includes a plurality of parallel memristor arrays 200, and the memristor array 200 includes a plurality of memristors distributed in an array. A memristor is a special type of electronic component having memory and variable resistance properties. A memristor can change its resistance value under the action of an external voltage or current, and can maintain this resistance value after power failure, that is, it has non-volatility. The first ends of the memristors on the same row are connected to each other, and the first ends of the memristors are connected to the column information of the corresponding information bit data conversion, that is, the memristors on each row receive the column information of the same information bit data conversion, and the second ends of the memristors on the same column are connected to each other, that is, the current generated by the memristors on each column can be collected.

[0077] Furthermore, the memristor array 200 corresponds to the circulant sub-matrix one-to-one. When the cell data in the circulant sub-matrix is ​​0, the corresponding memristor in the memristor array 200 is written with high resistance. When the cell data in the circulant sub-matrix is ​​1, the corresponding memristor in the memristor array is written with low resistance. Then:

[0078]

[0079] The computing unit 20 corresponds to three memristor arrays 200, which correspond to three circulant sub-matrices from front to back. The first circulant sub-matrix is ​​a 3×3 unit matrix, and the following two circulant sub-matrices are obtained by cyclic shift of the first circulant sub-matrix. There is only one 1 in each row or column of the matrix. The current result in this circuit does not need to be processed by multi-bit quantization, but only needs to be binarized.

[0080] Furthermore, the rule for the memristors in the memristor array 200 to generate currents of different magnitudes is: when the column information converted by the input information bit data is at a high level and the memristor is at a low resistance, a larger current is generated on the memristor; otherwise, a smaller current or no current is generated on the memristor. Putting the column information and the memristor array 200 together, we can obtain:

[0081]

[0082] Then we can get the current on the memristor:

[0083]

[0084] In this embodiment, the comparison unit 30 includes a plurality of comparison circuits 300. The comparison circuit 300 includes an operational amplifier and a sampling resistor. The first end of the sampling resistor is connected to the current collected by each column of memristors. The first end of the sampling resistor is also connected to the non-inverting input end of the operational amplifier. The second end of the sampling resistor is grounded. The inverting input end of the operational amplifier is connected to a reference voltage. The current is converted into a voltage through the sampling resistor, and then compared with the reference voltage. After that, a 0 / 1 output is generated at the output end of the operational amplifier. The 0 / 1 output generated at the output end of the operational amplifier represents the data of the codeword. The three memristor arrays 200 correspond to nine comparison circuits 300. After the current on each column is collected, the following can be obtained:

[0085] [Big, small, big, big, big, big]

[0086] Thus, we get c = [1 1 0 0 1 1 1 0 1], which is the same as the result of the previous calculation. Since the memristor is configurable, the calculation matrix can be dynamically adjusted according to demand, avoiding the sharp increase in circuit scale caused by flexible configuration in traditional CMOS implementation, and has higher computing efficiency and area advantages.

[0087] Example 2

[0088] like Figure 5 As shown, let the check matrix S be a matrix with one row and three columns, and the unit matrix I 0 The order of is three, s = [1 1 11 1 1], we have:

[0089] S = [1 1 2]

[0090]

[0091] but:

[0092]

[0093] All of the above operations are performed on modulo 2 operations, so the 2 in the p matrix can be replaced by 0, and we can get p = [0 0 0];

[0094]

[0095] We can get the check bit p = [0 0 0] and the code word c = [1 1 1 1 1 1 0 0 0];

[0096] The input information bit data is converted into column information, s = [1 1 1 1 1 1], which can be converted into The writing relationship of the memristor array 200 is:

[0097]

[0098] The computing unit 20 corresponds to six memristor arrays 200, which correspond to six 3×3 circulant sub-matrices respectively; thus, the current on the memristor can be obtained:

[0099]

[0100] The eighteen comparison circuits 300 corresponding to the six memristor arrays 200 generate the following results:

[0101]

[0102] In this embodiment, the accumulator unit 40 performs an XOR operation on the output results of the comparison circuit 300 on each column, and improves the calculation efficiency through concurrent calculation. At the same time, a grouping method is adopted to avoid the interference of the latent channel current in a large calculation array, and the final result can be obtained:

[0103] [Big big big big small small]

[0104] So we get c = [1 1 1 1 1 1 0 0 0], which is the same as the result calculated before.

[0105] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An LDPC code encoding circuit for improving coding efficiency based on a 5G communication system, characterized in that: include: Processing unit (10): used for obtaining a check matrix of a cyclic LDPC code, obtaining a generator matrix according to the check matrix, and splitting the generator matrix; A calculation unit (20): used to receive information input that needs to be verified and calculated, generate currents of different magnitudes, and collect the currents of each column unit; Comparison unit (30): used for comparing the collected current with the reference current to generate a 0 / 1 output; Accumulation unit (40): used for performing XOR accumulation on the calculation results of the parallel calculation array.

2. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 1, characterized in that: The processing unit (10) obtains a check matrix H according to a check basis matrix S and an identity matrix I0.

3. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 2, characterized in that: The specific steps of the processing unit (10) obtaining the generator matrix according to the check matrix are: Divide the codeword and check matrix into two parts, c 1×n =c=[s 1×k |p 1×m ]=[s|p],c 1×n and c both represent n-bit codewords, s 1×k and s both represent k bits of information, p 1×m and p both represent the m-bit check digit, H m×n and H both represent the check matrix with m rows and n columns. and H s Both represent the systematic bits in the check matrix. and H p All represent the check bit part in the check matrix, which are: H s s T +H p p T =0 m×1 All of the above are calculated on the modulo 2 operation, then: H s s T =H p p T Divide the generator matrix into two parts, G k×n =G=[I k×k |P k×(n-k) ]=[I|P],G k×n and G both represent k-row n-column generator matrices, I k×k and I both represent the identity matrix with k rows and k columns, P k×(n-k) and P both represent circulant permutation matrices with k rows (nk) and columns, c=sG=s[I|P]=[s|sP]=[s|p] Where T represents transpose, c 1×n The transposed matrix, s T is the transposed matrix of s, p T is the transposed matrix of p, 0 m×1 is an all-zero matrix with m rows and 1 column, H p The inverse matrix of Among them, I0 is the b×b identity matrix, 0 is the b×b all-zero matrix, G i,j is a circulant submatrix, 1≤i≤k, 1≤j≤nk, i and j represent the position of the circulant submatrix in the circulant permutation matrix, and ∣ only represents the partition for easy distinction and does not need to be written in actual input and calculation.

4. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 3, characterized in that: The calculation unit (20) takes information that needs to be verified as input, converts the input information bit data into column information, and 1 and 0 in the input information bit data correspond to a high level and a low level respectively.

5. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 4, characterized in that: The computing unit (20) comprises a plurality of parallel memristor arrays (200), wherein the memristor array (200) comprises a plurality of memristors distributed in an array, wherein the first ends of the memristors in the same row are connected to each other, the first ends of the memristors are connected to column information corresponding to information bit data conversion, and the second ends of the memristors in the same column are connected to each other.

6. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 5, characterized in that: The memristor array (200) corresponds to the circulant sub-matrix one-to-one; when the cell data in the circulant sub-matrix is ​​0, the corresponding memristor in the memristor array (200) is written with high resistance; when the cell data in the circulant sub-matrix is ​​1, the corresponding memristor in the memristor array is written with low resistance.

7. The LDPC code encoding circuit for improving coding efficiency based on a 5G communication system according to claim 6, characterized in that: The rule for the memristors in the memristor array (200) to generate currents of different magnitudes is that when the column information converted from the input information bit data is at a high level and the memristor is at a low resistance, a relatively large current is generated on the memristor; otherwise, a relatively small current or no current is generated on the memristor.

8. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 7, characterized in that: The comparison unit (30) comprises a plurality of comparison circuits (300), wherein the comparison circuit (300) comprises an operational amplifier and a sampling resistor, wherein the first end of the sampling resistor is connected to the current collected by each column of memristors, the first end of the sampling resistor is also connected to the in-phase input end of the operational amplifier, the second end of the sampling resistor is grounded, the inverting input end of the operational amplifier is connected to a reference voltage, the output end of the operational amplifier generates a 0 / 1 output, and the 0 / 1 output generated by the output end of the operational amplifier represents the data of the codeword.

9. The LDPC code encoding circuit for improving coding efficiency based on the 5G communication system according to claim 8, characterized in that: The accumulating unit (40) performs an exclusive OR operation on the output results of the comparison circuit (300) on each column.

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