Low-density parity check code generation method and device, equipment and medium

Abstract

The invention relates to the technical field of communication, in particular to a low-density parity check code generation method and device, computer equipment and a storage medium. The low-density parity check code generation method comprises the following steps: dividing a to-be-processed check matrix of a low-density parity check code into an information bit matrix and a check bit matrix; performing row transformation and rearrangement on the information bit matrix and the check bit matrix based on a preset row index, and performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solving the matrix equation to obtain each target check bit value in the second check bit matrix; and generating a target codeword of the low-density parity check code based on each information bit in the first information bit matrix and the target check bit value. The invention provides a low-density parity check code generation method which is higher in efficiency, wider in application range and lower in cost.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, device, computer equipment and storage medium for generating a low-density parity-check code. Background Art

[0002] LDPC code (Low Density Parity Check Code) is the most studied and most promising coding technology in the field of error correction coding. Various satellite communication systems have adopted LDPC codes, such as the CCSDS standard and the European second-generation digital satellite television broadcasting DVB-S2 (a digital satellite broadcasting standard) standard, as well as its evolved LDVB-S2X (another digital satellite broadcasting standard) standard, which further established the importance of LDPC codes. In the existing DVB-S2 literature, more attention is paid to the architecture and implementation of the LDPC decoder, because the decoder is the most complex module in the digital baseband part of the receiver, while the research on the architecture and implementation technology of the encoder is relatively lacking. The existing encoder structure design is also based on FPGA (Field-Programmable Gate Array) / ASIC (Application-Specific Integrated Circuit) implementation, and the coding efficiency and flexibility are not enough. Therefore, how to improve the coding efficiency of LDPC in the existing DVB-S2X system will be an urgent problem to be solved. Summary of the invention

[0003] Embodiments of the present application provide a method, apparatus, computer device, and storage medium for generating a low-density parity-check code.

[0004] A first aspect of an embodiment of the present application provides a method for generating a low-density parity-check code, comprising:

[0005] Dividing a check matrix to be processed of a low-density parity-check code into an information bit matrix and a check bit matrix; wherein the check bit matrix is ​​a dual diagonal matrix;

[0006] Performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit circulant matrices;

[0007] Performing a column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein, except for a sub-diagonal all-1 matrix in the second check bit matrix, all other matrix units are 0 matrices or unit matrices;

[0008] Constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solving the matrix equation to obtain each target check bit value in the second check bit matrix;

[0009] A target codeword of a low-density parity-check code is generated based on each information bit in the first information bit matrix and the target check bit value.

[0010] In an optional embodiment of the present application, the performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix includes:

[0011] According to the preset row index

[0012] The information bit matrix and the check bit matrix are row transformed in the manner of [0,q,2q,…(L-1)q,1,q+1,2q+1,…,(L-1)q+1,…,q-1,2q-1,3q-1,…,Lq-1] to form the rearranged first information bit matrix and the first check bit matrix; wherein L represents the number of units of the unit matrix, and q represents a matrix parameter related to the code rate and code length of the check code encoding.

[0013] In an optional embodiment of the present application, the performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix includes:

[0014] According to the preset column index according to the column index

[0015] [0,q,2q,…(L-1)q,1,q+1,2q+1,…,(L-1)q+1,…,q-1,2q-1,3q-1,…,Lq-1] performs column transformation on the first check bit matrix to form a rearranged second check bit matrix; wherein q represents a matrix parameter related to the code rate and code length of the check code encoding.

[0016] In an optional embodiment of the present application, constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix includes:

[0017]

[0018] Wherein, s represents each information bit in the first information bit matrix, p represents each check bit in the second check bit matrix, j represents the information bit index, n represents the number of rows of the check matrix to be processed, q represents a matrix parameter related to the code rate and code length, and different code rates in the coding protocol correspond to specific q values; Qh(n,j) (0≤n≤q-1) means that the unit matrix is ​​cyclically shifted right by h(n,j) positions. If h(n,j)=-1, then h(n,j) represents an all-0 matrix.

[0019] In an optional embodiment of the present application, if the current unit matrix includes multiple cyclic shifts, the current unit matrix is ​​cyclically processed multiple times and then superimposed.

[0020] In an optional embodiment of the present application, solving the matrix equation to obtain each target check bit value in the second check bit matrix includes:

[0021] Calculate a final check bit value of a final matrix cell in the second check bit matrix based on the matrix equation;

[0022] Calculate the first check bit value of the first matrix unit in the second check bit matrix based on the last check bit value;

[0023] Based on the bidirectional recursive method and the last check bit value and the first check bit value, other bit values ​​in the second check bit matrix are calculated to obtain the target check bit value including the first check bit value, the last check bit value and each of the other bit values.

[0024] In an optional embodiment of the present application, generating a target codeword of a low-density parity-check code based on each information bit in the first information bit matrix and the target check bit value includes:

[0025] Transforming each of the target check bit values ​​based on the preset column index to obtain a third check bit after column restoration;

[0026] Each information bit in the first information bit matrix and the third check bit are concatenated to obtain encoded bits of a low-density parity check code, thereby obtaining the target codeword.

[0027] A second aspect of an embodiment of the present application provides a low-density parity-check code generation device, comprising:

[0028] A division module, used for dividing the to-be-processed check matrix of the low-density parity-check code into an information bit matrix and a check bit matrix; wherein the check bit matrix is ​​a dual diagonal matrix;

[0029] A row transformation module, used for performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit circulant matrices;

[0030] A column transformation module, used for performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein, except for a sub-diagonal all-1 matrix in the second check bit matrix, all other matrix units are 0 matrices or unit matrices;

[0031] An equation module, used for constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solving the matrix equation to obtain each target check bit value in the second check bit matrix;

[0032] A target module is used to generate a target codeword of a low-density parity-check code based on each information bit in the first information bit matrix and each target check bit value.

[0033] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0034] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0035] In the first aspect, the low-density parity-check code generation method provided in the embodiment of the present application first divides the to-be-processed check matrix of the low-density parity-check code into an information bit matrix and a check bit matrix, performs row transformation on the information bit matrix and the check bit matrix based on a preset row index, and then performs column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit cyclic matrices, and each matrix unit in the second check bit matrix except for a sub-diagonal all-1 matrix is ​​a 0 matrix or a unit matrix; after constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, the solution of the equation is faster and more efficient, which can greatly improve the generation efficiency of the low-density parity-check code;

[0036] Secondly, when performing row-column transformation by using preset row indexes and preset column indexes, it is only necessary to record the right circular shift factor of the row-column transformation each time to fully reproduce it, thereby simplifying matrix multiplication to circular shifting of vectors, which has low complexity and can be adapted to the storage method of DSP. It can utilize the rich vector multiplication and addition units of DSP for calculation, and can be applied to DSP, thereby improving the scope of application of the low-density parity-check code generation method of the embodiment of the present application; at the same time, DSP has powerful computing power, and compared with FPGA / ASIC, it has low power consumption, low cost, and short development cycle, which further improves the efficiency of the low-density parity-check code generation method provided in the embodiment of the present application and reduces cost and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0038] Figure 1 A flowchart of a method for generating a low-density parity-check code provided by one embodiment of the present application;

[0039] Figure 2 A schematic diagram of the structure of a check matrix to be processed provided in one embodiment of the present application;

[0040] Figure 3 A schematic diagram of a structure for performing row transformation on a check matrix to be processed provided by one embodiment of the present application;

[0041] Figure 4 A structural schematic diagram of performing column transformation on a second check bit matrix in a check matrix to be processed provided by one embodiment of the present application;

[0042] Figure 5 A flowchart of a method for generating a low-density parity-check code provided by one embodiment of the present application;

[0043] Figure 6 A flowchart for solving a matrix equation in a method for generating a low-density parity-check code provided in one embodiment of the present application;

[0044] Figure 7 A flowchart of a method for generating a low-density parity-check code provided by one embodiment of the present application;

[0045] Figure 8 A schematic diagram of the structure of a low-density parity-check code generating device provided in one embodiment of the present application;

[0046] Fig. 9 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0047] In the process of implementing the present application, the inventors found that how to improve the coding efficiency of LDPC in the existing DVB-S2X system will be a problem to be solved urgently.

[0048] In response to the above problems, embodiments of the present application provide a method, apparatus, computer device and storage medium for generating a low-density parity-check code.

[0049] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0050] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0051] The low-density parity-check code generation method provided in the embodiment of the present application includes the following steps 101 to 105:

[0052] Step 101, dividing a check matrix to be processed of a low-density parity-check code into an information bit matrix and a check bit matrix;

[0053] Wherein, the check bit matrix is ​​a dual diagonal matrix; see Figure 2 , is an exemplary check matrix H to be processed. For the LDPC code of the DVB-S2 standard, the check matrix H is divided into two parts, H1 and H2. H1 is the information bit matrix of the information bit part, and H2 is the check bit matrix of the check bit part. H2 is a dual diagonal matrix. H can be written as an array of q*45 dimensions, and each matrix unit is a square matrix of L*L (L=360). Among them, the dimension of H1 is q*(45-q), the dimension of H2 is q*q columns, q is a matrix parameter related to the code rate and code length, and different code rates in the protocol correspond to specific q values. For the convenience of explanation, the embodiments of the present application are for Figure 2 The check matrix H in the example is an example of the original check matrix after parameter simplification. Figure 2 The check matrix H in the original check matrix H is changed from 45 to 5, q is set to 3, and L is changed from the original 360 to 5.

[0054] Step 102: Performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix;

[0055] Each matrix unit in the first information bit matrix is ​​a zero matrix or an accumulation of 1 to 3 unit circulant matrices; after row transformation, the first information bit matrix forms a unit matrix cycle of a zero matrix or 1 to 3 unit circulant matrices, which is convenient for calculation. Figure 3 Yes Figure 2 The result of row transformation of the check matrix H (including the information bit matrix H1 and the check bit matrix H2) in the first information bit matrix H11 is that each matrix unit is a 0 matrix or the accumulation of 1 to 3 unit circulant matrices, which is convenient for calculation. At this time, the rearranged first check bit matrix H21 is still in an irregular state.

[0056] Step 103: performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix;

[0057] Among them, except for a sub-diagonal all-1 matrix in the second check bit matrix, all other matrix units are 0 matrices or unit matrices; for example Figure 4 In the first information bit matrix H11, each L*L unit matrix is ​​a 0 matrix or the accumulation of 1 to 3 unit circulant matrices. Each L*L unit matrix in the second check bit matrix H22 is a 0 matrix or a 1 unit matrix, and there is only the unit matrix p in the upper right corner. h(0,2) It is not the identity matrix cycle, but a matrix with all 1s on the sub-diagonal.

[0058] By performing row and column transformations on the check matrix, the check matrix H is transformed into a QC_LDPC structure (Quasi-Cyslic Low-Density Parity-Check Codes) including a first information bit matrix H11 and a second check bit matrix H22. Quasi-cyclic LDPC codes are an important subset of structured LDPC codes, and their parity check matrices can be divided into multiple square matrices of equal size, each of which is a cyclic shift matrix of the unit matrix or an all-0 matrix). Figure 4 As shown, the check matrix H after the row-column transformation is a matrix of q×L rows and 45×L columns, which is composed of the first information bit matrix H11 and the second check bit matrix H22. Each L×L square matrix in the first information bit matrix H11 is a 0 matrix or 1 to 3 unit matrices are obtained by accumulating the circulant matrix, and each L×L square matrix in the second check bit matrix H22 is a 0 matrix or a unit matrix, and only one matrix is ​​not a unit matrix, which is a matrix with all 1s on the sub-diagonal.

[0059] Step 104: construct a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solve the matrix equation to obtain each target check bit value in the second check bit matrix;

[0060] Assume that each information bit in the first information bit matrix H11 is represented by: s = [s(0), s(1), s(2), ..., s(j), ..., s(44-q)], where s(j) = [s j0 ,s j1 ,...s j(L-1) ], wherein s represents each information bit in the first information bit matrix H11, j represents the information bit index, and L represents the number of rows and columns of the unit matrix (where the number of rows and columns is the same);

[0061] Assume that each check bit in the second check bit matrix H22 is represented by: p = [p(0), p(1), p(2), ..., p(j), ..., p(q-1)], p(j) = [p j0 ,p j1 ,...p j(L-1) ], wherein p represents each check bit in the second check bit matrix H22, j represents the check bit index, and L represents the number of rows and columns of the unit matrix (where the number of rows and columns is the same).

[0062] The target encoded codeword c in the encoded second check bit matrix is ​​[s(0), s(1), s(2), ..., s(44-q), ..., p(0), p(1), p(2), ..., p(q-1)];

[0063] Correspondingly, for Figure 4 In the example in FIG. 1 , each information bit in the first information bit matrix H11 is represented by: s = [s(0)s(1)], s(j) = [s j0 ,s j1 ,s j2 ,s j3 ,s j4 ], each check bit in the second check bit matrix H22 is expressed as: p = [p(0), p(1), p(2)], p(j) = [p j0 ,p j1 ,p j2 ,p j3 ,p j4 ], the target check bit values ​​c in the encoded second check bit matrix are c = [s(0), s(1), p(0), p(1), p(2)].

[0064] Step 105: Generate a target codeword of a low-density parity-check code based on the information bit matrix and each of the target check bit values.

[0065] In the first aspect, the low-density parity-check code generation method provided in the embodiment of the present application first divides the to-be-processed check matrix of the low-density parity-check code into an information bit matrix and a check bit matrix, performs row transformation on the information bit matrix and the check bit matrix based on a preset row index, and then performs column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit cyclic matrices, and each matrix unit in the second check bit matrix except for a sub-diagonal all-1 matrix is ​​a 0 matrix or a unit matrix; after constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, the equation is solved faster and more efficiently, which can greatly improve the efficiency of low-density parity-check code generation;

[0066] Secondly, when performing row-column transformation by using preset row indexes and preset column indexes, it is only necessary to record the right circular shift factor of the row-column transformation each time to fully reproduce it, thereby simplifying matrix multiplication to circular shifting of vectors, which has low complexity and can be adapted to the storage method of DSP. It can utilize the rich vector multiplication and addition units of DSP for calculation, and can be applied to DSP, thereby improving the scope of application of the low-density parity-check code generation method of the embodiment of the present application; at the same time, DSP has powerful computing power, and compared with FPGA / ASIC, it has low power consumption, low cost, and short development cycle, which further improves the efficiency of the low-density parity-check code generation method provided in the embodiment of the present application and reduces cost and power consumption.

[0067] In an optional embodiment of the present application, the above step 102, performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix, includes the following steps:

[0068] For example Figure 3 In the method of the preset row index [0, q, 2q, ... (L-1) q, 1, q+1, 2q+1, ..., (L-1) q+1, ..., q-1, 2q-1, 3q-1, ..., Lq-1], Figure 1 The check matrix H to be processed, which includes the information bit matrix H1 and the check bit matrix H2, is subjected to row transformation to form the first information bit matrix and the first check bit matrix after rearrangement; wherein L represents the number of units of the unit matrix, and q represents a matrix parameter related to the code rate and code length of the check code encoding. Figure 2 and Figure 3In the example, q is set to 3, L is set to 5, and they are rearranged according to the preset row index [0,3,6,9,12,1,4,7,10,13,2,5,8,11,14]. The values ​​in the preset row index are all the initial row numbers in the check matrix H to be processed. For example, the first row in the current check matrix is ​​the initial matrix row 0 in the check matrix H to be processed, the second row in the current check matrix is ​​the initial matrix row 3 in the check matrix H to be processed, the third row in the current check matrix is ​​the initial matrix row 6 in the check matrix H to be processed, and so on. The examples are not enumerated here.

[0069] In an optional embodiment of the present application, the above step 103, performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix, includes:

[0070] For example Figure 4 In the example, according to the preset column index, according to the column index [0, q, 2q, ... (L-1) q, 1, q+1, 2q+1, ..., (L-1) q+1, ..., q-1, 2q-1, 3q-1, ..., Lq-1] Figure 3 The first check bit matrix H21 in the matrix to be checked in the column transformation is formed Figure 4 The second check bit matrix H22 after rearrangement in ; wherein q represents a matrix parameter related to the code rate and code length of the check code encoding.

[0071] When the embodiment of the present application performs row-column transformation through preset row indexes and preset column indexes, it is only necessary to record the right circular shift factor of the row-column transformation each time to fully reproduce it, simplifying the matrix multiplication to circular shift of the vector, which has low complexity and can be adapted to the storage method of DSP, thereby improving the scope of application of the low-density parity-check code generation method of the embodiment of the present application.

[0072] In an optional embodiment of the present application, the step 104, constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, includes:

[0073]

[0074] Wherein, s represents each information bit in the first information bit matrix, p represents each check bit in the second check bit matrix, j represents the information bit index, n represents the number of rows of the check matrix to be processed, q represents the matrix parameter related to the code rate and code length, and different code rates in the coding protocol correspond to specific q values; Qh(n,j) (0≤n≤q-1) represents the unit matrix of the all-0 matrix cyclically shifted to the right by h(n,j) bits, h(n,j)∈{-1,shift1,shift1+shift2,shift1+shift2+shift3}, if h(n,j)=-1, then Qh(n,j) represents an all-0 matrix. Wherein, shift1, shift2, shift3 represent the right cyclic shift factors of the unit matrix, the dimension of the check matrix is ​​q*(45-q), and the value range of the right cyclic shift factor of the unit matrix is ​​-1~359. Wherein, Figure 4 The expression of ph(0,q-1) in the example is as follows:

[0075]

[0076] for Figure 4 In the example, the matrix equation of each row in the above check matrix can be exemplified as follows:

[0077]

[0078] The examples for other rows are similar and will not be repeated here.

[0079] In the DVB-S2x system, the L*L unit matrix of the information bit matrix H1 may have 1 to 3 shift factors. In an optional embodiment of the present application, if the current unit matrix contains multiple cyclic shifts, the current unit matrix is ​​cyclically processed multiple times and then superimposed. That is, the current unit matrix can be regarded as h(n,j) with multiple values, which can be directly used for calculation after superposition. The operation is simple and convenient, which greatly reduces the complexity of low-density parity-check code generation, thereby improving the efficiency of the low-density parity-check code generation method of the embodiment of the present application.

[0080] See also Figure 5 and Figure 6 In an optional embodiment of the present application, the above step 104, the step of solving the matrix equation to obtain each target check bit value in the second check bit matrix, includes the following steps 501-503:

[0081] Step 501: Calculate the last check bit value of the last matrix unit in the second check bit matrix based on the matrix equation;

[0082]

[0083] Among them, p(q-1) represents the final check bit value, which generally refers to the check bit value represented by the last unit matrix of the matrix during calculation; ph(0,q-1) refers to a unit matrix, sumλ i represents the sum of the sub-equations corresponding to each row in the matrix equation, L represents the number of units in the unit matrix, and I represents that the unit matrix is ​​a unit matrix, which means that the diagonal is 1 and the rest are 0. i It can be calculated according to the following formula:

[0084]

[0085] in,

[0086] And because sumλ i =(P h(0A-1) +I)*p(q-1)

[0087] get

[0088] Among them, Q h(i,j) *s(j) represents the result of right shifting each information bit s(j) in the first information bit matrix, which can be completed through a shift instruction with higher efficiency.

[0089] Step 502: Calculate the first check bit value of the first matrix unit in the second check bit matrix based on the last check bit value:

[0090]

[0091] Among them, p(0) represents the first check bit value, which generally refers to the check bit value represented by the first unit matrix of the matrix; λ0 represents the value of the 0th row sub-equation in the above matrix equation, It means p(q-1) is circularly shifted 1 bit to the right, and let (Encoding rule output must be 0).

[0092] Step 503: Calculate other bit values ​​in the second check bit matrix based on the bidirectional recursive method and the last check bit value and the first check bit value to obtain the target check bit value including the first check bit value, the last check bit value and each of the other bit values.

[0093] Use bidirectional recursion to calculate p(q-2)...p(1):

[0094] Forward recursion: p(i) = λ i +p(i-1),

[0095] Backward recursion: p(i) = λ i+1 +p(i+1),

[0096] The embodiment of the present application utilizes the powerful multiplication and addition processing and table lookup processing of DSP, and adopts a bidirectional recursive structure, such as Figure 4 and Figure 6 As shown, the check bit p = [p(0), p(1), p(2), ..., p(q-1)], first calculate p(q-1), then calculate p(0) based on p(q-1), and then calculate the remaining check bits based on p(q-1) and p(0), respectively. A bidirectional recursive structure is adopted to output the final check bit value from both the forward and reverse directions, which can greatly improve the parallelism of the check bit output and greatly improve the efficiency of low-density parity-check code generation.

[0097] See also Figure 7 In an optional embodiment of the present application, the above step 105, generating a target codeword of a low-density parity check code based on each information bit in the first information bit matrix and the target check bit value, includes the following steps 701-702:

[0098] Step 701: transform each of the target check bit values ​​based on the preset column index to obtain a third check bit after column restoration;

[0099] The third check bit refers to a bit in a third check bit matrix, and the third check bit matrix refers to a matrix restored by performing the above-mentioned row-column transformation on the second check bit matrix.

[0100] Step 702: Concatenate each information bit in the first information bit matrix and the third check bit to obtain encoded bits of a low-density parity check code, thereby obtaining the target codeword.

[0101]

[0102] 0,L,2L,...,(q-1)L,

[0103] 1,L+1,2L+1,...,(q-1)L+1, ...

[0105] L-1,2L-1,3L-1,...,q(L-1)]

[0106] in, represents the target check bit value, L represents the number of units in the unit matrix, q represents the matrix parameter related to the code rate and code length, and different code rates in the coding protocol correspond to specific q values.

[0107] Rearrange the check bits p as follows to obtain the target check bit value Output the final encoded target codeword:

[0108]

[0109] The embodiment of the present application transforms each of the target check bit values ​​based on the preset column index to obtain a third check bit matrix after column restoration, and splices the information bit matrix and the third check bit matrix to obtain the encoded target codeword of the low-density parity check code. The efficiency and convenience of low-density parity check code generation can be greatly improved.

[0110] After obtaining the above-mentioned target codeword, in an optional embodiment of the present application, the data between the physical layer and the protocol stack in the terminal device (for example, the terminal device corresponding to the DVB-S2X system) can be interacted based on the above-mentioned target codeword (as an interface communication protocol), and the terminal device at least includes a physical layer and a protocol stack, and the terminal device is configured with a memory module for storing the forward physical layer frame data of the terminal; the data interaction process between the physical layer and the protocol stack includes at least the following steps:

[0111] The physical layer stores, within the current frame interruption period, a plurality of the forward physical layer frame data received within the current frame period into a corresponding preset memory address in the memory module, and updates a storage identifier of the preset memory address to a first occupation identifier;

[0112] After receiving the frame interrupt message, the protocol stack reads the corresponding forward physical layer frame data from the memory module based on each of the preset memory addresses, and changes the storage identifier of the preset memory address to a first vacant identifier;

[0113] The protocol stack integrates the plurality of forward physical layer frame data into a target forward data message based on the physical layer frame index of each forward physical layer frame data and then processes the message.

[0114] In an optional embodiment of the present application, before the physical layer stores the plurality of forward physical layer frame data received in the current frame period in the corresponding preset memory address in the memory module within the current frame interruption period, and updates the storage identifier of the preset memory address to the first occupied identifier, the method further includes:

[0115] During the current frame interruption period of the physical layer, the physical layer receives each of the forward physical layer frame data from multiple processing cores respectively; wherein the forward physical layer frame data includes a corresponding physical layer frame index; wherein the physical layer frame index is used to characterize the order of each of the forward physical layer frame data.

[0116] In an optional embodiment of the present application, the processing core corresponds one-to-one to the preset memory address; and / or at least the first 4 bytes of the memory module are occupied bytes of the storage identifier.

[0117] 4. The data interaction method according to claim 1, characterized in that after the protocol stack receives the frame interrupt message, based on each of the preset memory addresses, the corresponding forward physical layer frame data is read from the memory module, and before the storage identifier of the preset memory address is changed to the first vacant identifier, the method further comprises:

[0118] The preset memory address of each of the forward physical layer frame data filled in by each processing core of the physical layer to the memory module;

[0119] After the current frame interruption period ends, the physical layer sends the frame interruption message carrying the preset memory address to the protocol stack.

[0120] In an optional embodiment of the present application, the protocol stack is configured with a structure memory including multiple array pointers, and the structure memory is used to integrate the multiple forward data into the target forward data message according to the physical layer frame index.

[0121] In an optional embodiment of the present application, the identifier corresponding to the physical layer frame index is updated to a second occupancy identifier.

[0122] In an optional embodiment of the present application, the forward physical layer frame data is 1 to 56 groups, and correspondingly, the index range of the physical layer frame index is 0 to 55.

[0123] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0124] See also Figure 8 An embodiment of the present application provides a low-density parity-check code generating device 800, comprising:

[0125] A division module 810 is used to divide the to-be-processed check matrix of the low-density parity-check code into an information bit matrix and a check bit matrix; wherein the check bit matrix is ​​a dual diagonal matrix;

[0126] A row transformation module 820 is used to perform row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit circulant matrices;

[0127] A column transformation module 830 is used to perform a column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein, except for a sub-diagonal all-1 matrix in the second check bit matrix, all other matrix cells are 0 matrices or unit matrices;

[0128] An equation module 840 is used to construct a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solve the matrix equation to obtain each target check bit value in the second check bit matrix;

[0129] The target module 850 is used to generate a target codeword of a low-density parity-check code based on each information bit in the first information bit matrix and each target check bit value.

[0130] In an optional embodiment of the present application, the row transformation module 820 is specifically used to perform row transformation on the information bit matrix and the check bit matrix according to the preset row index [0, q, 2q, … (L-1)q, 1, q+1, 2q+1, …, (L-1)q+1, …, q-1, 2q-1, 3q-1, …, Lq-1] to form the rearranged first information bit matrix and the first check bit matrix; wherein L represents the number of units of the unit matrix, and q represents the matrix parameter related to the code rate and code length of the check code encoding.

[0131] In an optional embodiment of the present application, the column transformation module 830 is specifically used to perform column transformation on the first check bit matrix according to the preset column index [0, q, 2q, …(L-1)q, 1, q+1, 2q+1, …, (L-1)q+1, …, q-1, 2q-1, 3q-1, …, Lq-1] to form a rearranged second check bit matrix; wherein q represents a matrix parameter related to the code rate and code length of the check code encoding.

[0132] In an optional embodiment of the present application, the equation module 840 is specifically used to construct the following equation:

[0133]

[0134] Among them, s represents each information bit in the first information bit matrix, p represents each check bit in the second check bit matrix, j represents the information bit index, n represents the number of rows of the check matrix to be processed, q represents a matrix parameter related to the code rate and code length, and different code rates in the coding protocol correspond to specific q values; Qh(n,j)(0≤n≤q-1) represents a unit matrix cyclically shifted right by h(n,j) bits. If h(n,j)=-1, then h(n,j) represents an all-0 matrix.

[0135] In an optional embodiment of the present application, if the current unit matrix includes multiple cyclic shifts, the current unit matrix is ​​cyclically processed multiple times and then superimposed.

[0136] In an optional embodiment of the present application, the equation module 840 is specifically used to calculate the final check bit value of the last matrix unit in the second check bit matrix based on the matrix equation; calculate the first check bit value of the first matrix unit in the second check bit matrix based on the last check bit value; calculate other bit values ​​in the second check bit matrix based on the bidirectional recursive method and the last check bit value and the first check bit value, and obtain the target check bit value including the first check bit value, the last check bit value and each of the other bit values.

[0137] In an optional embodiment of the present application, the target module 850 is specifically used to transform each of the target check bit values ​​based on the preset column index to obtain a third check bit after column restoration; splice each information bit in the first information bit matrix and the third check bit to obtain the encoded bits of the low-density parity check code to obtain the target codeword.

[0138] For the specific definition of the low-density parity-check code generating device 800, please refer to the definition of the low-density parity-check code generating method in the above text, which will not be repeated here. Each module in the low-density parity-check code generating device 800 can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0139] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Fig. 9As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a low-density parity check code generation method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the low-density parity check code generation method as described above is implemented.

[0140] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above method for generating a low-density parity-check code can be implemented.

[0141] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0142] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0143] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0144] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0145] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0146] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for generating a low-density parity-check code, characterized in that: include: Dividing a check matrix to be processed of a low-density parity-check code into an information bit matrix and a check bit matrix; wherein the check bit matrix is ​​a dual diagonal matrix; Performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit circulant matrices; Performing a column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein, except for a sub-diagonal all-1 matrix in the second check bit matrix, all other matrix units are 0 matrices or unit matrices; Constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solving the matrix equation to obtain each target check bit value in the second check bit matrix; A target codeword of a low-density parity-check code is generated based on each information bit in the first information bit matrix and the target check bit value.

2. The method for generating a low-density parity-check code according to claim 1, wherein: The performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix includes: According to the preset row index The information bit matrix and the check bit matrix are row transformed in the manner of [0,q,2q,…(L-1)q,1,q+1,2q+1,…,(L-1)q+1,…,q-1,2q-1,3q-1,…,Lq-1] to form the rearranged first information bit matrix and the first check bit matrix; wherein L represents the number of units of the unit matrix, and q represents a matrix parameter related to the code rate and code length of the check code encoding.

3. The method for generating a low-density parity-check code according to claim 1, wherein: The performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix includes: According to the preset column index according to the column index [0,q,2q,…(L-1)q,1,q+1,2q+1,…,(L-1)q+1,…,q-1,2q-1,3q-1,…,Lq-1] performs column transformation on the first check bit matrix to form a rearranged second check bit matrix; wherein q represents a matrix parameter related to the code rate and code length of the check code encoding.

4. The method for generating a low-density parity-check code according to claim 3, wherein: The constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix includes: Wherein, s represents each information bit in the first information bit matrix, p represents each check bit in the second check bit matrix, j represents the information bit index, n represents the number of rows of the check matrix to be processed, q represents a matrix parameter related to the code rate and code length, and different code rates in the coding protocol correspond to specific q values; Q h(n,j) (0≤n≤q-1) means that the unit matrix is ​​cyclically shifted right by h(n,j) positions. If h(n,j)=-1, then Qh(n,j) represents an all-0 matrix.

5. The method for generating a low-density parity-check code according to claim 4, wherein: If the current identity matrix includes multiple cyclic shifts, the current identity matrix is ​​cyclically processed multiple times and then superimposed.

6. The method for generating a low-density parity-check code according to claim 4, wherein: The step of solving the matrix equation to obtain target check bit values ​​in the second check bit matrix includes: Calculate a final check bit value of a final matrix cell in the second check bit matrix based on the matrix equation; Calculate the first check bit value of the first matrix unit in the second check bit matrix based on the last check bit value; Based on the bidirectional recursive method and the last check bit value and the first check bit value, other bit values ​​in the second check bit matrix are calculated to obtain the target check bit value including the first check bit value, the last check bit value and each of the other bit values.

7. The method for generating a low-density parity-check code according to claim 4, wherein: The step of generating a target codeword of a low-density parity check code based on each information bit in the first information bit matrix and the target check bit value comprises: Transforming each of the target check bit values ​​based on the preset column index to obtain a third check bit after column restoration; Each information bit in the first information bit matrix and the third check bit are concatenated to obtain encoded bits of a low-density parity check code, thereby obtaining the target codeword.

8. A low-density parity-check code generating device, characterized in that: include: A division module, used for dividing the to-be-processed check matrix of the low-density parity-check code into an information bit matrix and a check bit matrix; wherein the check bit matrix is ​​a dual diagonal matrix; A row transformation module, used for performing row transformation on the information bit matrix and the check bit matrix based on a preset row index to form a rearranged first information bit matrix and a first check bit matrix; wherein each matrix unit in the first information bit matrix is ​​a 0 matrix or an accumulation of 1 to 3 unit circulant matrices; A column transformation module, used for performing column transformation on the first check bit matrix based on a preset column index to form a rearranged second check bit matrix; wherein, except for a sub-diagonal all-1 matrix in the second check bit matrix, all other matrix units are 0 matrices or unit matrices; An equation module, used for constructing a matrix equation for the check matrix based on the first information bit matrix and the second check bit matrix, and solving the matrix equation to obtain each target check bit value in the second check bit matrix; A target module is used to generate a target codeword of a low-density parity-check code based on each information bit in the first information bit matrix and each target check bit value.

9. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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