Coding method

Abstract

A method of a joint coding scheme with an interleaver and a tone mapper for multi-resource unit (RU) operation involves performing joint coding of a plurality of information bits to generate a plurality of coded bit sequences. The method involves processing the plurality of encoded bit sequences by interleaving and tone mapping the plurality of encoded bit sequences with respect to a plurality of RUs based on either or both of an aggregate-RU and a single-RU to produce a plurality of processed bit sequences. The method then further involves transmitting the plurality of processed bit sequences on a plurality of RUs.

Description

[0001] Related references

[0002] The present disclosure is part of a non-provisional patent application and claims priority to U.S. Provisional Patent Application No. 62 / 908,665 filed on October 1, 2019 and U.S. Non-provisional Patent Application No. 17 / 022,934 filed on September 16, 2020, the entire contents of which are incorporated by reference into the present disclosure. Technical Field

[0003] The present disclosure relates to wireless communications, and more particularly, to a joint coding scheme with an interleaver and a tone mapper for multi-resource unit (multi-RU) operation. Background Art

[0004] Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.

[0005] In order to achieve better efficiency in spectrum utilization and frequency diversity to improve link quality, in the next generation wireless local area network (WLAN) of the Institute of Electrical and Electronics Engineers (IEEE) 802.11be standard for extremely high throughput (EHT) wireless communications, multi-RU allocation for a single station (STA) is adopted. For multiple RUs, STAs are allowed to use more than one RU for reception and / or transmission. In order to achieve multi-RU operation, several technical problems need to be solved, such as how to encode information and how to interleave and tone map multiple RUs. For binary convolutional code (BCC) encoding for multi-RU operation, the encoded bits will need to pass through a BCC interleaver. On the other hand, for low-density parity-check (LDPC) encoding for multi-RU operation, the encoded bits will be modulated and then pass through an LDPC tone mapper. However, how to implement the BCC interleaver and LDPC tone mapper remains to be defined or designed by individual manufacturers. Summary of the invention

[0006] The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. Selected implementations are further described in the detailed description below. Therefore, the following summary is not intended to identify the essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0007] The purpose of the present disclosure is to provide schemes, concepts, designs, techniques, methods and devices related to a joint coding scheme with an interleaver and a tone mapper for multi-RU operation.

[0008] In one aspect, a method may include: performing joint encoding on a plurality of information bits to generate a plurality of coded bit sequences. The method may also include: interleaving and tone mapping the coded bit sequences relative to a plurality of RUs based on either or both of an aggregated-RU and a single-RU to process the plurality of coded bit sequences to generate a plurality of processed bit sequences. The method may further include sending the plurality of processed bit sequences on the plurality of RUs.

[0009] On the other hand, a method may involve performing joint encoding on multiple information bits by a processor of a device to generate multiple coded bit sequences. The method may also include the processor processing the multiple coded bit sequences by interleaving and tone mapping the coded bit sequences relative to multiple RUs allocated to the device based on an aggregate-RU to generate multiple processed bit sequences by: (a) interleaving the multiple coded bit sequences relative to a set of multiple RUs by an interleaver of the processor to provide multiple interleaved bit sequences; (b) tone mapping the multiple interleaved bit sequences relative to a set of multiple RUs by a tone mapper of the processor to provide multiple processed bit sequences; (c) parsing the multiple processed bit sequences by a parser of the processor.

[0010] On the other hand, a method may involve performing joint encoding on multiple information bits by a processor of a device to generate multiple coded bit sequences. The method may also include the processor processing the multiple coded bit sequences in the following manner: relative to multiple RUs allocated to the device based on a single-RU, the multiple coded bit sequences are interleaved and tone mapped to generate multiple processed bit sequences in the following manner: (a) parsing the multiple coded bit sequences to multiple interleavers of the processor by a parser of the processor, each interleaver corresponding to a corresponding one of the multiple RUs; (b) interleaving corresponding coded bit sequences in the multiple coded bit sequences by each of the multiple interleavers to provide the corresponding interleaved bit sequences to a corresponding one of the multiple tone mappers of the processor, each tone mapper corresponding to a corresponding one of the multiple RUs; (c) tone mapping the corresponding interleaved bit sequences by each of the multiple tone mappers to provide corresponding processed bit sequences in the multiple processed bit sequences.

[0011] It is worth noting that although the description provided herein may be in the context of a specific radio access technology, network and network topology (e.g., Wi-Fi), the proposed concepts, schemes and any (multiple) variants / derivatives may be implemented in and through other types of radio access technologies, networks and network topologies, such as but not limited to Bluetooth, ZigBee, 5th Generation (5G / New Radio, NR), Long-Term Evolution (LTE), Advanced LTE, Advanced LTE Pro, Internet-of-Things (IoT), Industrial Internet of Things (IIoT) and narrowband Internet of Things (NB-IoT). Therefore, the scope of the present disclosure is not limited to the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following illustrations are used to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present disclosure. These illustrations illustrate the embodiments of the present disclosure and are used together with the description to explain the principles of the present disclosure. In order to clearly illustrate the concepts of the present disclosure, some elements may be shown out of scale compared to the dimensions in the actual embodiments, and these illustrations do not need to be drawn to scale.

[0013] Figure 1 A diagram illustrating an example network environment in which various solutions and schemes according to the present disclosure may be implemented.

[0014] Figure 2Diagram showing an example design according to the present disclosure.

[0015] Figure 3 A diagram illustrating an example scenario according to the present disclosure.

[0016] Figure 4 Diagram showing an example design according to the present disclosure.

[0017] Figure 5 A diagram illustrating an example scenario according to the present disclosure.

[0018] Figure 6 A diagram illustrating an example scenario according to the present disclosure.

[0019] Figure 7 A diagram illustrating an example scenario according to the present disclosure.

[0020] Figure 8 A diagram illustrating an example scenario according to the present disclosure.

[0021] Fig. 9 A diagram illustrating an example scenario according to the present disclosure.

[0022] Fig.10 A diagram illustrating an example scenario according to the present disclosure.

[0023] Fig.11 A diagram illustrating an example scenario according to the present disclosure.

[0024] Fig.12 A diagram illustrating an example scenario according to the present disclosure.

[0025] Fig.13 A block diagram of an example communication system is shown in accordance with an embodiment of the present disclosure.

[0026] Fig.14 A flow chart illustrating an example process according to an implementation of the present disclosure.

[0027] Fig.15 A flow chart illustrating an example process according to an implementation of the present disclosure.

[0028] Fig.16 A flow chart illustrating an example process according to an implementation of the present disclosure. DETAILED DESCRIPTION

[0029] The following describes detailed embodiments and implementations of the subject matter claimed in the present disclosure. However, it should be understood that the disclosed embodiments and implementations are merely illustrations of the subject matter claimed, which can be embodied in various forms. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments and implementations set forth in the present disclosure. Rather, the provision of these exemplary embodiments and implementations makes the description of the present disclosure thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the following description, the details of well-known features and technologies may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

[0030] Overview

[0031] Embodiments according to the present disclosure relate to various technologies, methods, schemes and / or solutions related to a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communication. According to the present disclosure, a variety of possible solutions can be implemented individually or jointly. That is, although the possible solutions can be described separately below, two or more of the possible solutions can be implemented in one or another combination.

[0032] Figure 1 An example network environment 100 is shown in which various solutions and schemes according to the present disclosure may be implemented. Figure 2-Figure 12 An example of implementation of various proposed solutions in a network environment 100 according to the present disclosure is shown. Figure 1-Figure 12 ,A description of various proposed schemes is provided below.

[0033] Reference Figure 1 , the network environment 100 may include at least one STA 110, which is associated with an access point (AP) 120 in a basic service set (BSS) 130 and wirelessly communicates with it according to one or more IEEE 802.11 standards (e.g., IEEE 802.11ax, IEEE 802.11be, and standards to be developed in the future). STA 110 may be allocated multiple RUs by AP 120 for multi-RU operation, because STA 110 may use the allocated multiple RUs to receive and transmit. Under various proposed schemes according to the present disclosure, according to various proposed schemes described below, STA 110 and AP 120 may be configured to perform a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communication.

[0034] For multi-RU operation, any of a variety of methods may be used, including independent coding of each RU, joint coding across multiple RUs, and hybrid coding involving a combination of independent coding of each RU and joint coding across multiple RUs. For joint and / or hybrid coding methods, the new concept of "aggregate-RU" (interchangeably referred to as "virtual-RU" herein) can be used in the pre-forward error correction (pre-FEC) padding, post-FEC padding and encoding process for multi-RU operation under various proposed schemes according to the present disclosure. For example, for BCC coding of multiple RUs (assuming that the size of the virtual-RU is less than or equal to 242), the coded bits will be processed by the BCC interleaver, and the interleaving can be performed by the interleaver based on a single-RU (interchangeably referred to as "physical-RU" herein) or an aggregate-RU (interchangeably referred to as "virtual-RU" herein). Similarly, for LDPC coding of multiple RUs, the coded bits are modulated and processed by the LDPC tone mapper, and the tone mapping can be performed by the tone mapper based on a single-RU (or physical-RU) or an aggregate-RU (or virtual-RU). The term "aggregate-RU" (or "virtual-RU") herein refers to a collection or combination of two or more physical-RUs (e.g., a 26-tone RU and a 52-tone RU with a total of 78 tones), and the term "single-RU" (or "physical-RU") herein refers to a single-RU with one or more tones (e.g., as defined in IEEE802.11ax).

[0035] Figure 2 An example design 200 according to the present disclosure is shown. The design 200 may be a design or configuration of electronic circuits in the STA 110 for multi-RU operation, where bit sequences are processed based on a single-RU (or physical-RU). Figure 2, design 200 may include a joint encoding stage and a post-joint encoding stage. The post-joint encoding stage may process multiple RUs on the basis of a single-RU (or physical-RU). The joint encoding stage may involve a series of functional blocks, for example, including a cyclic redundancy check (CRC32) function, which converts a variable length string into a 32-bit binary sequence, followed by a scrambler, a pre-FEC padding block, a FEC encoding block, a post-FEC padding block, a stream parser, a segment parser, and an RU parser. The joint encoding stage may receive multiple or a string of information bits for transmission (TX), and perform joint encoding thereon to generate multiple or a string of coded bit sequences. The joint encoding stage may also include additional functional blocks, such as a multi-RU configuration block and an aggregate-RU parameter selection block. The multi-RU configuration block may provide configuration information to the aggregate-RU parameter selection block and the RU parser. Based on the configuration information, the aggregate-RU parameter selection block may select a corresponding parameter set from multiple possible parameter sets, and provide the selected parameter set to the pre-FEC padding block, the FEC encoding block, the post-FEC padding block and the RU parser.

[0036] The post-joint coding stage may include n single-RU processing sets, where n is a positive integer greater than 1 and represents a number of RUs allocated to the STA 110 (eg, ) in the RU. Each single-RU processing set may include Ru i Interleaver, followed by Ru i modulator, then Ru i Tone mapper, where 1≤i≤n. The n single-RU processing sets may process a plurality of coded bit sequences generated by the joint coding stage. Specifically, the n single-RU processing sets may process the plurality of coded bit sequences by interleaving and tone mapping the coded bit sequences with respect to the n RUs assigned to the STA 110 on a single-RU (physical-RU) basis to generate a plurality of processed bit sequences. Specifically, the RU parser may parse the plurality of coded bit sequences into Interleaver, Each of the interleavers can be sequentially passed through the A corresponding one of the modulators interleaves a corresponding coded bit sequence to provide a corresponding interleaved bit sequence to The corresponding one in the tone mapper. Each of the tone mappers may tone map a corresponding interleaved bit sequence to provide a corresponding processed bit sequence in a plurality of processed bit sequences. The processed bit sequences may then be mapped by the RU mapper and provided to an inverse fast Fourier transform (IFFT) function block that converts one or more signals represented by the processed bit sequences from a frequency domain to a time domain for transmission via one or more antennas such as radio frequency (RF) waves.

[0037] Under the scheme proposed according to the present disclosure, each The interleaver may be a BCC interleaver, and each The tone mapper can be an LDPC tone mapper. Under the proposed scheme, by For each of the interleavers, the interleaver parameters defined in the IEEE 802.11ax standard (e.g., Tables 27-34) may be used to interleave the corresponding coded bit sequence based on a single-RU (or physical-RU). For each of the tone mappers, tone mapper parameters defined in the IEEE 802.11ax standard (eg, Tables 27-35) may be used to tone map corresponding coded bit sequences based on a single-RU (or physical-RU).

[0038] Figure 3 An example scenario 300 according to the present disclosure is shown. Figure 3 , through the design of 200 For each of the interleavers, the interleaver parameters defined in Tables 27-34 of the IEEE 802.11ax standard may be used to interleave the corresponding coded bit sequence based on a single-RU (or physical-RU). For each of the tone mappers, the tone mapper parameters defined in Tables 27-35 of the IEEE 802.11ax standard are used to perform audio mapping on the corresponding coded bit sequence based on a single-RU (or physical-RU).

[0039] Figure 4 An example design 400 according to the present disclosure is shown. The design 400 may be a design or configuration of electronic circuits in the STA 110 for multi-RU operation with processing of bit sequences based on aggregate-RUs (or virtual-RUs).

[0040] Reference Figure 4, design 400 may include a joint encoding stage and a post-joint encoding stage. The post-joint encoding stage may process multiple RUs on the basis of an aggregate-RU (or virtual-RU). The joint encoding stage may involve a series of functional blocks, for example, including a CRC32 function that converts a variable length string into a 32-bit binary sequence, followed by a scrambler, followed by a pre-FEC padding block, followed by an FEC encoding block, a post-FEC padding block, a stream parser, and a segment parser. The joint encoding stage may receive multiple or a string of information bits for transmission (TX) and perform joint encoding thereon to generate multiple or a string of coded bit sequences. The joint encoding stage may also include additional functional blocks, such as a multi-RU configuration block and an aggregate-RU parameter selection block. The multi-RU configuration block may provide configuration information to the aggregate-RU parameter selection block and the RU parser. Based on the configuration information, the aggregate-RU parameter selection block may select a corresponding parameter set from multiple possible parameter sets, and provide the selected parameter set to various functional blocks of the pre-FEC padding block, the FEC encoding block, the post-FEC padding block, and the post-joint encoding stage.

[0041] The post-joint coding stage may include a virtual RU (vRU) interleaver, followed by a vRU modulator, a vRU tone mapper, and a RU parser. The post-joint coding stage may process multiple coded bit sequences by interleaving and tone mapping multiple coded bit sequences relative to multiple RUs (e.g., n RUs) assigned to STA 110 based on an aggregate-RU (virtual-RU) to generate multiple processed bit sequences. Specifically, the vRU interleaver may interleave multiple coded bit sequences relative to the aggregation of multiple RUs to provide multiple interleaved bit sequences, which are then provided to the vRU tone mapper via the vRU modulator. The vRU tone mapper may tone map multiple interleaved bit sequences relative to the aggregation of multiple RUs to provide multiple processed bit sequences to the RU parser. The RU parser may parse multiple processed bit sequences. Then, the processed bit sequences are mapped by the RU mapper and provided to an IFFT functional block, which converts one or more signals represented by the processed bit sequences from the frequency domain to the time domain for transmission through one or more antennas such as RF waves.

[0042] Under the scheme proposed according to the present disclosure, the vRU interleaver can be a BCC interleaver, and the vRU tone mapper can be an LDPC tone mapper. Under the proposed scheme, the vRU interleaver can be used by using Figure 5-9Any of the multiple interleaver parameter sets shown interleaves multiple coded bit sequences based on an aggregate-RU (or virtual-RU). For example, a vRU interleaver may use parameter sets corresponding to 26-tone RU and 106-tone RU for a total of 132 data subcarriers (e.g., Nsd=132), where the number of interleaver matrix columns is 21 (e.g., Ncol=21), and the number of interleaver matrix rows is a multiple of 6 (e.g., Nrow=6*coded bit count per single carrier per spatial stream (Nbpscs)). Similarly, a vRU tone mapper may be configured by using Figure 5 and Figure 10-12 Any of the plurality of tone mapper parameter sets shown may be used to tone map a plurality of interleaved bit sequences based on an aggregate-RU (or virtual-RU). For example, a vRU tone mapper may utilize a parameter set corresponding to a 106-tone RU and a 26-tone RU, with a distance between tones of 6 (e.g., DTM=6). Alternatively, as another example, a vRU tone mapper may utilize a parameter set corresponding to a 484-tone RU and a 242-tone RU, with a distance between tones of 18 (e.g., DTM=18).

[0043] Figure 5 An example scenario 500 according to the present disclosure is shown. Figure 5 , scheme 500 illustrates some possible sets of interleaver parameters and some possible sets of tone mapper parameters that may be used, respectively, by the vRU interleaver and vRU tone mapper of design 400. It is worth noting that for smaller sized RUs (e.g., less than 242 tones), the RUs may be contiguous to each other in the frequency domain, while larger sized RUs may not necessarily be contiguous in the frequency domain.

[0044] Figure 6 An example scenario 600 according to the present disclosure is shown. Figure 6 , scenario 600 shows some possible sets of interleaver parameters without dual carrier modulation (DCM) or DCM=0. Figure 7 An example scenario 700 according to the present disclosure is shown. Figure 7 , scenario 700 shows some possible sets of interleaver parameters with DCM or DCM=1. Figure 8 An example scenario 800 according to the present disclosure is shown. Figure 8 , scenario 800 shows some possible sets of interleaver parameters in the case of no DCM or DCM=0. Fig. 9 An example scenario 900 according to the present disclosure is shown. Fig. 9, scenario 900 shows some possible sets of interleaver parameters with DCM or DCM=1. Fig.10 An example scenario 1000 according to the present disclosure is shown. Fig.10 , scenario 1000 shows a possible set of some tone mapper parameters in the case of no DCM or DCM=0. Fig.11 An example scenario 1100 according to the present disclosure is shown. Fig.11 , scenario 1100 shows some possible sets of tone mapper parameters in the case of no DCM or DCM=0. Fig.12 An example scenario 1200 according to the present disclosure is shown. Fig.12 , scenario 1200 shows some possible sets of tone mapper parameters with DCM or DCM=1.

[0045] Illustrative Implementation

[0046] Fig.13 An example system 1 having at least an example device 1310 and an example device 1320 according to an embodiment of the present disclosure is shown. Each of the devices 1310 and 1320 can perform various functions to implement the schemes, techniques, processes and methods described herein for a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communication, including various schemes above for various proposed designs, concepts, schemes, systems and methods and the processes described below. For example, the device 1310 can be implemented in the STA 110, and the device 1320 can be implemented in the AP 120, and vice versa.

[0047] Each of the devices 1310 and 1320 may be part of an electronic device, which may be a STA or an AP, such as a portable or mobile device, a wearable device, a wireless communication device, or a computing device. When implemented in a STA, each of the devices 1310 and 1320 may be implemented in a smart phone, a smart watch, a personal digital assistant, a digital camera, or a computing device such as a tablet, a laptop, or a notebook computer. Each of the devices 1310 and 1320 may also be part of a machine-type device, which may be an IoT device such as a stationary or fixed device, a household device, a wired communication device, or a computing device. For example, each of the devices 1310 and 1320 may be implemented in a smart thermostat, a smart refrigerator, a smart door lock, a wireless speaker, or a home control center. When implemented in or as a network device, the devices 1310 and / or 1320 may be implemented in a network node such as an AP in a WLAN.

[0048] In some embodiments, each of the devices 1310 and 1320 may be implemented in the form of one or more integrated-circuit (IC) chips, such as, but not limited to, one or more single-core processors, one or more multi-core processors, one or more reduced-instruction set computing (RISC) processors, or one or more complex-instruction-set computing (CISC) processors. In the above various schemes, each of the devices 1310 and 1320 may be implemented as a STA or an AP or as a STA or an AP. Each of the devices 1310 and 1320 may include Fig.13 At least some of the components such as processor 1312 and processor 1322 shown in the figure. Each of device 1310 and device 1320 may further include one or more other components (e.g., internal power supply, display device and / or user interface device) that are not related to the proposed scheme of the present disclosure, and therefore, for the sake of simplicity and brevity, these components of device 1310 and device 1320 are not shown in the figure. Fig.13 It is not shown in the figure and is not described below.

[0049] On the one hand, each of the processors 1312 and 1322 can be implemented in the form of one or more single-core processors, one or more multi-core processors, one or more RISC processors, or one or more CISC processors. That is, even if the singular term "processor" is used herein to refer to the processors 1312 and 1322, according to the present disclosure, each of the processors 1312 and 1322 may include multiple processors in some embodiments, and may include a single processor in other embodiments. On the other hand, each of the processors 1312 and 1322 can be implemented in the form of hardware (and optionally, firmware) having electronic components, the electronic components including, for example, but not limited to, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and / or one or more varactor diodes, which are configured and arranged to achieve a specific purpose according to the present disclosure. In other words, in at least some embodiments, each of the processors 1312 and 1322 is a dedicated machine specially designed, arranged and configured to perform specific tasks, including tasks related to a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communications according to various embodiments of the present disclosure. For example, each of processor 1312 and processor 1322 may be configured with hardware, electronic components, and / or circuits arranged in design 200 and design 400 (e.g., one or more encoding / processing pipelines of circuits according to design 200 and one or more encoding / processing pipelines of circuits according to design 400).

[0050] In some embodiments, the device 1310 may further include a transceiver 1316 coupled to the processor 1312. The transceiver 1316 may include a transmitter capable of wireless transmission and a receiver capable of wirelessly receiving data. In some embodiments, the device 1320 may further include a transceiver 1326 coupled to the processor 1322. The transceiver 1326 may include a transmitter capable of wireless transmission and a receiver capable of wirelessly receiving data. It is worth noting that although the transceiver 1316 and the transceiver 1326 are respectively illustrated as being external to the processor 1312 and the processor 1322 and being separated from the processor 1312 and the processor 1322, in some embodiments, the transceiver 1316 may be a component of the processor 1312 as a system on chip (SoC). The transceiver 1326 and / or the transceiver 1326 may be a component of the processor 1322 as a SoC.

[0051] In some embodiments, the device 1310 may further include a memory 1314, which is coupled to the processor 1312 and can be accessed by the processor 1312 and store data therein. In some embodiments, the device 1320 may further include a memory 1324, which is coupled to the processor 1322 and can be accessed by the processor 1322 and store data therein. Each of the memory 1314 and the memory 1324 may include a random access memory (RAM), such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (T-RAM) and / or a zero-capacitor RAM (Z-RAM). Alternatively or additionally, each of the memory 1314 and the memory 1324 may include a type of read-only memory (ROM), such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and / or electrically erasable programmable ROM (EEPROM). Alternatively or additionally, each of the memory 1314 and the memory 1324 may include a type of non-volatile random-access memory (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM) and / or phase change memory.

[0052] Each of the devices 1310 and 1320 may be a communication entity capable of communicating with each other using various proposed schemes according to the present disclosure. For illustrative purposes and not limitation, a description of the capabilities of the device 1310 as the STA 110 and the device 1320 as the AP 120 is provided below. It is worth noting that although a detailed description of the functions, features and / or technical features of the device 1310 is provided below, it can be applied to the device 1320 in the same manner, although a detailed description thereof is not provided for the purpose of brevity. It is also worth noting that although the example implementation described below is provided in the context of a WLAN, it may also be implemented in other types of networks.

[0053] Under the proposed scheme involving a joint coding scheme with an interleaver and a tone mapper for multi-RU operation according to the present disclosure, the device 1310 is implemented in or as a STA 110, the device 1320 is implemented in or as an AP 120 in the STA 110, and the AP 120 is associated with a BSS (e.g., BSS 130) of a wireless network such as a WLAN in a network environment 100 according to one or more IEEE 802.11 standards, and the processor 1312 of the device 1310 may perform joint coding on a plurality of information bits to generate a plurality of coded bit sequences. In addition, the processor 1312 may process the plurality of coded bit sequences by interleaving and tone mapping the plurality of coded bit sequences with respect to a plurality of RUs (e.g., assigned to the device 1310 by the device 1320 as the AP 120) based on one or both of aggregated-RUs (virtual-RUs) and single-RUs (physical-RUs), to generate a plurality of processed bit sequences. In addition, the processor 1312 can send multiple processed bit sequences to the device 1320 on multiple RUs through the transceiver 1316.

[0054] In some implementations, in processing multiple coded bit sequences, processor 1312 may interleave and tone map multiple coded bit sequences based on an aggregate-RU (or virtual-RU) by performing specific operations. For example, processor 1312 may interleave multiple coded bit sequences for a set of multiple RUs through an interleaver of processor 1312 (e.g., a vRU interleaver in design 400) to provide multiple interleaved bit sequences. In addition, processor 1312 may tone map multiple interleaved bit sequences relative to a set of multiple RUs through a tone mapper of processor 1312 (e.g., a vRU tone mapper in design 400) to provide multiple processed bit sequences. In addition, processor 1312 may parse multiple processed bit sequences through a parser of processor 1312 (e.g., an RU parser in design 400).

[0055] In some embodiments, when interleaving multiple coded bit sequences, processor 1312 may interleave the multiple coded bit sequences via a BCC interleaver of processor 1312 (e.g., a vRU interleaver in design 400) relative to one or more RU sizes having corresponding one or more interleaver parameters.

[0056] In some embodiments, one or more RU sizes may include a 26-tone RU and a 106-tone RU for a total of 132 data subcarriers (e.g., Nsd=132). In this case, one or more interleaver parameters may include a number of interleaver matrix columns of 21 (e.g., Ncol=21) and a number of interleaver matrix rows of a multiple of 6 (e.g., Nrow=6*the number of coded bits per single carrier per spatial stream (Nbpscs)).

[0057] In some implementations, when tone mapping multiple interleaved bit sequences, processor 1312 may tone map the multiple interleaved bit sequences via an LDPC tone mapper of processor 1312 (e.g., the vRU tone mapper in design 400) relative to one or more RU sizes having corresponding one or more tone mapper parameters.

[0058] In some embodiments, one or more RU sizes may include a 106-tone RU and a 26-tone RU. In this case, one or more tone mapper parameters include a distance between tones of 6 (DTM=6).

[0059] In some implementations, one or more RU sizes may include a 484-tone RU and a 242-tone RU. In this case, one or more tone mapper parameters include a distance between tones of 18 (DTM=18).

[0060] In some embodiments, when processing multiple coded bit sequences, processor 1312 may interleave and tone map the multiple coded bit sequences based on a single-RU (or physical-RU) by performing specific operations. For example, processor 1312 may parse the multiple coded bit sequences into multiple interleavers (e.g., RU parsers in design 200) of processor 1312 through a parser of processor 1312 (e.g., RU parsers in design 200). In addition, processor 1312 may interleave a corresponding coded bit sequence from the plurality of coded bit sequences through each of the plurality of interleavers to provide a corresponding interleaved bit sequence (e.g., (in design 200)) to a corresponding one of the plurality of tone mappers of processor 1312. Tone mappers), each tone mapper corresponding to a corresponding one of the plurality of RUs. In addition, processor 1312 may tone map a corresponding interleaved bit sequence through each of the plurality of tone mappers to provide a corresponding processed bit sequence in a plurality of processed bit sequences.

[0061] In some implementations, when parsing the plurality of coded bit sequences, the processor 1312 may parse the plurality of coded bit sequences with respect to one or more RU sizes having corresponding interleaver parameters and tone mapper parameters.

[0062] In some embodiments, the plurality of interleavers may include a BCC interleaver. In addition, the plurality of tone mappers may include an LDPC tone mapper. In this case, the interleaver parameters and the tone mapper parameters may include interleaver parameters and tone mapper parameters specified in the IEEE 802.11ax standard for Wi-Fi (e.g., parameters specified in Tables 27-34 and 27-35 of the IEEE 802.11ax standard).

[0063] According to the present disclosure, under another proposed scheme regarding a joint coding scheme with an interleaver and a tone mapper for multi-RU operation, the device 1310 is implemented in or as a STA 110, the device 1320 is implemented in or as an AP 120, and the AP 120 is associated with a BSS (e.g., BSS 130) of a wireless network such as a WLAN in a network environment 100 according to one or more IEEE 802.11 standards, and the processor 1312 of the device 1310 may perform joint coding on a plurality of information bits to generate a plurality of coded bit sequences. In addition, the processor 1312 may process the plurality of coded bit sequences by interleaving and tone mapping with respect to a plurality of RUs allocated to the device 1310 (e.g., by the device 1320 as the AP 120) based on an aggregate-RU (or virtual-RU) to generate a plurality of processed bit sequences. For example, processor 1312 may interleave multiple coded bit sequences relative to an aggregation of multiple RUs by an interleaver of processor 1312 (e.g., a vRU interleaver in design 400) to provide multiple interleaved bit sequences. In addition, processor 1312 may tone map multiple interleaved bit sequences relative to an aggregation of multiple RUs by a tone mapper of processor 1312 (e.g., a vRU tone mapper in design 400) to provide multiple processed bit sequences. In addition, processor 1312 may parse the multiple processed bit sequences by a parser of processor 1312 (e.g., an RU parser in design 400). Thereafter, processor 1312 may send the multiple processed bit sequences to device 1320 on multiple RUs via transceiver 1316.

[0064] In some embodiments, when interleaving a plurality of coded bit sequences, the processor 1312 may interleave the plurality of coded bit sequences via a BCC interleaver of the processor 1312 with respect to one or more RU sizes having one or more interleaver parameters.

[0065] In some embodiments, one or more RU sizes may include 26-tone RU and 106-tone RU for a total of 132 data subcarriers (e.g., Nsd=132). In this case, one or more interleaver parameters may include the number of interleaver matrix columns being 21 (e.g., Ncol=21) and the number of interleaver matrix rows being a multiple of 6 (e.g., Nrow=6*Nbpscs).

[0066] In some embodiments, when tone mapping the multiple interleaved bit sequences, the processor 1312 may tone map the multiple interleaved bit sequences via an LDPC tone mapper of the processor 1312 relative to one or more RU sizes having one or more tone mapping parameters.

[0067] In some implementations, one or more RU sizes may include a 106-tone RU and a 26-tone RU. In this case, one or more tone mapper parameters may include a distance between tones of 6 (DTM=6).

[0068] In some embodiments, one or more RU sizes may include a 484-tone RU and a 242-tone RU. In this case, one or more tone mapper parameters may include a distance between tones of 18 (DTM=18).

[0069] Under another proposed scheme involving a joint coding scheme with an interleaver and a tone mapper for multi-RU operation according to the present disclosure, the device 1310 is implemented in or as a STA 110, the device 1320 is implemented in or as an AP 120, and the AP 120 is associated with a BSS (e.g., BSS 130) of a wireless network such as a WLAN in a network environment 100 according to one or more IEEE 802.11 standards, and the processor 1312 of the device 1310 may perform joint coding on a plurality of information bits to generate a plurality of coded bit sequences. In addition, the processor 1312 may interleave and tone map the coded bit sequences by a plurality of RUs allocated to the device 1310 (e.g., by the device 1320 as the AP 120) based on a single-RU (or physical-RU) to generate a plurality of processed bit sequences. For example, the processor 1312 may parse the plurality of coded bit sequences into the plurality of interleavers (e.g., the RU parser in the design 200) of the processor 1312 through a parser of the processor 1312 (e.g., the RU parser in the design 200). interleaver), where each interleaver corresponds to a corresponding one of the plurality of RUs. In addition, processor 1312 may interleave a corresponding coded bit sequence from the plurality of coded bit sequences via each of the plurality of interleavers to provide a corresponding interleaved bit sequence to a corresponding one of the plurality of tone mappers of processor 1312 (e.g., the one in design 200). The processor 1312 may perform tone mapping on a corresponding interleaved bit sequence through each of the plurality of tone mappers to provide a corresponding processed bit sequence in a plurality of processed bit sequences. The processor 1312 may then transmit the plurality of processed bit sequences to the device 1320 over the plurality of RUs through the transceiver 1316.

[0070] In some implementations, when parsing the plurality of coded bit sequences, the processor 1312 may parse the plurality of coded bit sequences with respect to one or more RU sizes having corresponding interleaver parameters and tone mapper parameters.

[0071] In some implementations, the plurality of interleavers may include a BCC interleaver. Additionally, the plurality of tone mappers may include an LDPC tone mapper.

[0072] In some implementations, the interleaver parameters and the tone mapper parameters may include interleaver parameters and tone mapper parameters specified in the IEEE 802.11ax standard for Wi-Fi (eg, parameters specified in Tables 27-34 and 27-35 of the IEEE 802.11ax standard).

[0073] Illustrative Process

[0074] Fig.14 An example process 1400 is shown in accordance with an embodiment of the present disclosure. Process 1400 may represent an aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1400 may represent an aspect of the proposed concepts and schemes related to a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communications in accordance with the present disclosure. Process 1400 may include one or more operations, actions, or functions shown in one or more of blocks 1410, 1420, and 1430. Although shown as discrete blocks, the various blocks of process 1400 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. In addition, the blocks / sub-blocks of process 1400 may be arranged in accordance with Fig.14The process 1400 may be performed in the order shown or in other orders. In addition, one or more blocks / sub-blocks of the process 1400 may be performed repeatedly or iteratively. The process 1400 may be implemented by or in the device 1310 and the device 1320, or by any variation thereof. The process 1400 may start at block 1410.

[0075] At 1410, process 1400 may involve performing joint encoding of a plurality of information bits to generate a plurality of coded bit sequences. Process 1400 may proceed from 1410 to 1420.

[0076] At 1420 , process 1400 may include processing the plurality of coded bit sequences by interleaving and tone mapping the plurality of RUs with respect to the plurality of RUs based on either or both of an aggregate-RU and a single-RU to generate a plurality of processed bit sequences. Process 1400 may proceed from 1420 to 1430 .

[0077] At 1430 , process 1400 may include transmitting, via transceiver 1316 , the plurality of processed bit sequences to device 1320 over the plurality of RUs.

[0078] In some embodiments, when processing multiple coded bit sequences, process 1400 may involve interleaving and tone mapping the coded bit sequences on an aggregate-RU basis by performing specific operations. For example, process 1400 may include interleaving the multiple coded bit sequences relative to the aggregate of multiple RUs to provide multiple interleaved bit sequences. In addition, process 1400 may involve tone mapping the multiple interleaved bit sequences relative to the aggregate of multiple RUs to provide multiple processed bit sequences. In addition, process 1400 may include parsing the multiple processed bit sequences.

[0079] In some embodiments, when interleaving a plurality of coded bit sequences, process 1400 may involve interleaving the plurality of coded bit sequences with respect to one or more RU sizes having corresponding one or more interleaver parameters.

[0080] In some embodiments, one or more RU sizes may include 26-tone RU and 106-tone RU for a total of 132 data subcarriers (e.g., Nsd=132). In this case, one or more interleaver parameters may include the number of interleaver matrix columns being 21 (e.g., Ncol=21) and the number of interleaver matrix rows being a multiple of 6 (e.g., Nrow=6*Nbpscs).

[0081] In some embodiments, when tone mapping multiple interleaved bit sequences, process 1400 may involve tone mapping the multiple interleaved bit sequences relative to one or more RU sizes having corresponding one or more tone mapper parameters.

[0082] In some implementations, one or more RU sizes may include a 106-tone RU and a 26-tone RU. In this case, one or more tone mapper parameters include a distance between tones of 6 (DTM=6).

[0083] In some implementations, one or more RU sizes may include a 484-tone RU and a 242-tone RU. In this case, one or more tone mapper parameters include a distance between tones of 18 (DTM=18).

[0084] In some embodiments, when processing multiple coded bit sequences, process 1400 may include interleaving and tone mapping the coded bit sequences based on a single-RU by performing specific operations. For example, process 1400 may include parsing the multiple coded bit sequences to multiple interleavers of processor 1312 by a parser of processor 1312, each interleaver corresponding to a corresponding one of the multiple RUs. In addition, process 1400 may include interleaving corresponding coded bit sequences from the multiple coded bit sequences by each of the multiple interleavers to provide a corresponding interleaved bit sequence to a corresponding one of the multiple tone mappers of processor 1312, each tone mapper corresponding to a corresponding one of the multiple RUs. In addition, process 1400 may involve tone mapping the corresponding interleaved bit sequence by each of the multiple tone mappers to provide a corresponding processed bit sequence in a plurality of processed bit sequences.

[0085] In some implementations, when parsing a plurality of coded bit sequences, process 1400 may include parsing the plurality of coded bit sequences with respect to one or more RU sizes having corresponding interleaver parameters and tone mapper parameters.

[0086] In some embodiments, the plurality of interleavers may include a BCC interleaver. In addition, the plurality of tone mappers may include an LDPC tone mapper. In this case, the interleaver parameters and the tone mapper parameters may include the interleaver parameters and the tone mapper parameters specified in the IEEE 802.11ax specification for Wi-Fi (e.g., the parameters specified in Tables 27-34 and 27-35 of the IEEE 802.11ax standard).

[0087] Fig.15An example process 1500 is shown in accordance with an embodiment of the present disclosure. Process 1500 may represent an aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1500 may represent an aspect of the proposed concepts and schemes related to a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communications in accordance with the present disclosure. Process 1500 may include one or more operations, actions, or functions shown in one or more of blocks 1510, 1520, and 1530 and sub-blocks 1522, 1524, and 1526. Although shown as discrete blocks, the various blocks of process 1500 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. In addition, the blocks / sub-blocks of process 1500 may be as shown. Fig.11 The process 1500 may be performed in the order shown or in other orders. In addition, one or more blocks / sub-blocks of the process 1500 may be performed repeatedly or iteratively. The process 1500 may be implemented by or in the device 1310 and the device 1320, or by any variation thereof. For illustrative purposes only and without limiting the scope, the process 1500 is described below in the context of a device 1310 implemented in or as a STA 110 and a device 1320 implemented in or as an AP 120 in a network environment 100 according to one or more IEEE 802.11 standards. The process 1500 may start at block 1510.

[0088] At 1510, process 1500 may involve processor 1312 of device 1310 performing joint encoding of a plurality of information bits to generate a plurality of coded bit sequences. Process 1500 may proceed from 1510 to 1520.

[0089] At 1520, process 1500 may include processor 1312 processing the plurality of coded bit sequences by interleaving and tone mapping the plurality of coded bit sequences relative to a plurality of RUs allocated to device 1310 (e.g., device 1320 as AP 120) based on the aggregate-RU, as shown at 1522, 1524, and 1526, to generate a plurality of processed bit sequences based on the aggregate-RU. Process 1500 may proceed from 1520 to 1530.

[0090] At 1530 , process 1500 may include processor 1312 transmitting the plurality of processed bit sequences to device 1320 via transceiver 1316 over the plurality of RUs.

[0091] At 1522, process 1500 may include processor 1312 interleaving the plurality of coded bit sequences with respect to the aggregation of the plurality of RUs via an interleaver of processor 1312 to provide a plurality of interleaved bit sequences. Process 1500 may proceed from 1522 to 1524.

[0092] At 1524, process 1500 may involve processor 1312, via a tone mapper of processor 1312, tone mapping the plurality of interleaved bit sequences relative to an aggregation of the plurality of RUs to provide a plurality of processed bit sequences. Process 1500 may proceed from 1524 to 1526.

[0093] At 1526 , process 1500 may include processor 1312 parsing the plurality of processed bit sequences via a parser of processor 1312 .

[0094] In some embodiments, when interleaving a plurality of coded bit sequences, process 1500 may involve processor 1312 interleaving the plurality of coded bit sequences via a BCC interleaver of processor 1312 with respect to one or more RU sizes having corresponding one or more interleaver parameters.

[0095] In some embodiments, one or more RU sizes may include 26-tone RU and 106-tone RU for a total of 132 data subcarriers (e.g., Nsd=132). In this case, one or more interleaver parameters may include the number of interleaver matrix columns being 21 (e.g., Ncol=21) and the number of interleaver matrix rows being a multiple of 6 (e.g., Nrow=6*Nbpscs).

[0096] In some embodiments, when tone mapping multiple interleaved bit sequences, process 1500 may involve processor 1312, via an LDPC tone mapper of processor 1312, tone mapping the multiple interleaved bit sequences relative to one or more RUs having corresponding one or more tone mapper parameters.

[0097] In some implementations, one or more RU sizes may include a 106-tone RU and a 26-tone RU. In this case, one or more tone mapper parameters may include a distance between tones of 6 (DTM=6).

[0098] In some implementations, one or more RU sizes may include a 484-tone RU and a 242-tone RU. In this case, one or more tone mapper parameters may include a distance between tones of 18 (DTM=18).

[0099] Fig.16An example process 1600 is shown in accordance with an embodiment of the present disclosure. Process 1600 may represent an aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1600 may represent an aspect of the proposed concepts and schemes related to a joint coding scheme with an interleaver and a tone mapper for multi-RU operation in wireless communications in accordance with the present disclosure. Process 1600 may include one or more operations, actions, or functions shown in one or more of blocks 1610, 1620, and 1630 and sub-blocks 1622, 1624, and 1626. Although shown as discrete blocks, the various blocks of process 1600 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. In addition, the blocks / sub-blocks of process 1600 may be Fig.16 110, or in another order. In addition, one or more blocks / sub-blocks of process 1600 may be repeatedly or iteratively performed. Process 1600 may be implemented by or in device 1310 and device 1320, or by any variation thereof. For illustrative purposes only and without limiting the scope, process 1600 is described below in the context of a device 1310 implemented in or as STA110 and a device 1320 implemented in or as AP120 in a network environment 100 according to one or more IEEE 802.11 standards. Process 1600 may start at block 1610.

[0100] At 1610, process 1600 may involve processor 1312 of device 1310 performing joint encoding of a plurality of information bits to generate a plurality of coded bit sequences. Process 1600 may proceed from 1610 to 1620.

[0101] At 1620, process 1600 may include processor 1312 processing the plurality of coded bit sequences by interleaving and tone mapping the plurality of coded bit sequences relative to a plurality of RUs assigned to device 1310 (e.g., device 1320 as AP 120) on a single-RU basis to generate a plurality of processed bit sequences, as shown at 1622, 1624, and 1626. Process 1600 may proceed from 1620 to 1630.

[0102] At 1630 , process 1600 may include processor 1312 sending the plurality of processed bit sequences to device 1320 via transceiver 1316 over the plurality of RUs.

[0103] At 1622, process 1600 may include processor 1312 parsing the plurality of coded bit sequences to a plurality of interleavers of processor 1312 via a parser of processor 1312, each interleaver corresponding to a respective one of the plurality of RUs. Process 1600 may proceed from 1622 to 1624.

[0104] At 1624, process 1600 may include processor 1312 interleaving a corresponding coded bit sequence in the plurality of coded bit sequences via each of the plurality of interleavers to provide the corresponding interleaved bit sequence to a corresponding tone mapper in a plurality of tone mappers of processor 1312, wherein each tone mapper corresponds to a corresponding one of the plurality of RUs. Process 1600 may proceed from 1624 to 1626.

[0105] At 1626, process 1600 may include processor 1312 tone mapping, via each of a plurality of tone mappers, a corresponding interleaved bit sequence to provide a corresponding processed bit sequence of a plurality of processed bit sequences.

[0106] In some implementations, when parsing a plurality of coded bit sequences, process 1600 may involve processor 1312 parsing the plurality of coded bit sequences with respect to one or more RU sizes having corresponding interleaver parameters and tone mapper parameters.

[0107] In some implementations, the plurality of interleavers may include a BCC interleaver. Additionally, the plurality of tone mappers may include an LDPC tone mapper.

[0108] In some implementations, the interleaver parameters and the tone mapper parameters may include the interleaver parameters and the tone mapper parameters specified in the IEEE 802.11ax standard for Wi-Fi (eg, the parameters specified in Tables 27-34 and 27-35 of the IEEE 802.11ax standard).

[0109] Additional Notes

[0110] The subject matter described herein sometimes represents different components, which are contained in or connected to other different components. It is understood that the described structure is only an example, and in fact, it can be implemented by many other structures to achieve the same function. Conceptually, the arrangement of any components that achieve the same function is actually "associated" to achieve the desired function. Therefore, regardless of the structure or intermediate components, any two components combined to achieve a specific function are considered to be "interrelated" to achieve the desired function. Similarly, any two associated components are considered to be "operably connected" or "operably coupled" to achieve a specific function. Any two components that can be associated with each other are also considered to be "operably coupled" to achieve a specific function. Any two components that can be associated with each other are also considered to be "operably coupled" to achieve a specific function. Specific examples of operable connections include, but are not limited to, physically pairable and / or physically interacting components, and / or wirelessly interactive and / or wirelessly interactive components, and / or logically interactive and / or logically interactive components.

[0111] Furthermore, with respect to the use of substantially any plural and / or singular terms, those skilled in the art can translate from the plural to the singular and / or from the singular to the plural as appropriate to the context and / or application. For clarity, the various singular / plural permutations are expressly set forth herein.

[0112] In addition, it will be understood by those skilled in the art that, in general, the terms used in the present disclosure, especially in the claims, and the subject matter of the claims, are generally used as "open" terms, for example, "including" should be interpreted as "including but not limited to", "having" should be interpreted as "at least having", "including" should be interpreted as "including but not limited to", etc. It will be further understood by those skilled in the art that if a specific number of claim contents are planned to be introduced, it will be clearly indicated in the claim, and it will not be displayed in the absence of such contents. For example, to aid understanding, the following claims may contain the phrases "at least one" and "one or more" to introduce the contents of the claims. However, the use of these phrases should not be understood to imply the use of "one" or "an" to introduce the claim contents and limit the scope of any particular patent. Even when the same claim includes the introductory phrases "one or more" or "at least one", the indefinite article, such as "one" or "an", should be interpreted as indicating at least one or more, and the same is true for the use of the explicit description used to introduce the claim. In addition, even if a specific number of introductory contents are explicitly cited, it will be recognized by those skilled in the art that such contents should be interpreted as indicating the number cited, for example, "two references" without other modifications means at least two references, or two or more references. In addition, when using expressions similar to "at least one of A, B, and C", it is usually expressed in this way so that those skilled in the art can understand the expression, for example, "a system includes at least one of A, B, and C" will include but not limited to a system with A alone, a system with B alone, a system with C alone, a system with A and B, a system with A and C, a system with B and C, and / or a system with A, B, and C, etc. It will be further understood by those skilled in the art that any separated words and / or phrases represented by two or more alternative terms, whether in the specification, the claims, or the drawings, should be understood to include the possibility of one of these terms, one of them, or both of these terms. For example, "A or B" should be understood as the possibility of "A", or "B", or "A and B".

[0113] As can be seen from the foregoing, various embodiments have been described in the present disclosure for illustrative purposes, and various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope is indicated by the claims.

Claims

1. A coding method, comprising: performing joint encoding on the plurality of information bits to provide a plurality of coded bits; Processing the plurality of coded bits by interleaving and tone mapping the plurality of coded bits relative to a plurality of resource units based on an aggregated resource unit to generate a plurality of processed bits, wherein processing the plurality of coded bits comprises: interleaving and tone mapping the plurality of coded bits based on the aggregated resource unit is: interleaving the plurality of coded bits relative to an aggregation of the plurality of resource units, comprising interleaving the plurality of coded bits relative to a plurality of resource units having corresponding one or more interleaver parameters through a binary convolutional code interleaver; and tone mapping relative to the aggregation of the plurality of resource units to provide a plurality of processed bits; and transmitting the plurality of processed bits over the plurality of resource units, Wherein the sizes of the plurality of resource units include 26-tone resource units and 106-tone resource units for a total of 132 data subcarriers, and wherein the one or more interleaver parameters include the number of columns of the interleaver matrix being 21, and the number of rows of the interleaver matrix being a multiple of 6.

2. A coding method, comprising: performing joint encoding on the plurality of information bits to provide a plurality of coded bits; Processing the plurality of coded bits to generate a plurality of processed bits by interleaving and tone mapping the plurality of coded bits relative to a plurality of resource units based on an aggregated resource unit, wherein processing the plurality of coded bits comprises: interleaving and tone mapping the plurality of coded bits based on the aggregated resource unit is: interleaving the plurality of coded bits relative to an aggregation of the plurality of resource units; and tone mapping relative to the aggregation of the plurality of resource units to provide a plurality of processed bits comprises tone mapping relative to a size of the plurality of resource units having corresponding one or more tone mapper parameters by a low density parity-check tone mapper; and transmitting the plurality of processed bits over the plurality of resource units, The sizes of the plurality of resource units include 106-tone resource units and 26-tone resource units, and the one or more tone mapper parameters include a distance between tones of 6.

3. A coding method, comprising: performing joint encoding on the plurality of information bits to provide a plurality of coded bits; Processing the plurality of coded bits to generate a plurality of processed bits by interleaving and tone mapping the plurality of coded bits relative to a plurality of resource units based on an aggregated resource unit, wherein processing the plurality of coded bits comprises: interleaving and tone mapping the plurality of coded bits based on the aggregated resource unit is: interleaving the plurality of coded bits relative to an aggregation of the plurality of resource units; and tone mapping relative to the aggregation of the plurality of resource units to provide a plurality of processed bits, comprising tone mapping relative to a size of the plurality of resource units having corresponding one or more tone mapper parameters by a low density parity-check tone mapper; and transmitting the plurality of processed bits over the plurality of resource units, Wherein the sizes of the plurality of resource units include 484-tone resource units and 242-tone resource units, and wherein the one or more tone mapper parameters include a distance between tones of 18.

4. A coding method comprising: performing, by a processor of the device, joint encoding on the plurality of information bits to provide a plurality of coded bits; as well as Processing, by the processor, the plurality of coded bits to generate a plurality of processed bits by interleaving and tone mapping the plurality of coded bits relative to a plurality of resource units allocated to the device based on the aggregated resource unit via: interleaving, by an interleaver of the processor, the plurality of coded bits relative to an aggregation of the plurality of resource units; Tone mapping is performed, by a tone mapper of the processor, relative to the aggregation of the plurality of resource units to provide the plurality of processed bits.

5. The encoding method according to claim 4, characterized in that Interleaving the plurality of coded bits includes interleaving the plurality of coded bits with respect to sizes of a plurality of resource units having corresponding one or more interleaver parameters via a binary convolutional code interleaver.

6. The encoding method according to claim 5, characterized in that The sizes of the plurality of resource units include 26-tone resource units and 106-tone resource units for a total of 132 data subcarriers, and wherein the one or more interleaver parameters include the number of columns of the interleaver matrix being 21, and the number of rows of the interleaver matrix being a multiple of 6.

7. The encoding method according to claim 4, characterized in that The tone mapping includes tone mapping, by a low density parity-check tone mapper, relative to sizes of a plurality of resource units having corresponding one or more tone mapper parameters.

8. The encoding method according to claim 7, characterized in that The sizes of the plurality of resource units include 106-tone resource units and 26-tone resource units, and wherein the one or more tone mapper parameters include a distance between tones of 6.

9. The encoding method according to claim 7, characterized in that: The sizes of the plurality of resource units include 484-tone resource units and 242-tone resource units, and wherein the one or more tone mapper parameters include a distance between tones of 18.

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