Network timing method and device for multi-core asynchronous system and computer program product

Abstract

The invention is suitable for the technical field of network timing, and provides a network timing method and device for a multi-core asynchronous system and a computer program product, and the method comprises the steps: synchronizing the system mother time of the multi-core asynchronous system with a time service source; executing time keeping operation on the system mother time; the interruption of the plurality of cores is synchronized with the system mother time on the basis of the clock difference between the interruption time within the second of the plurality of cores and the system mother time. According to the network timing method and device of the multi-core asynchronous system and the electronic equipment provided by the embodiment of the invention, the multi-core asynchronous operation system can be stably synchronized with the time service source, and the synchronization precision and the time keeping precision of each core can be greatly improved.

Description

Technical Field

[0001] The present application belongs to the field of network time synchronization technology, and in particular, relates to a network time synchronization method, device and computer program product for a multi-core asynchronous system. Background Art

[0002] In the power system, the secondary equipment network adopts the network jump mode and needs the device to be synchronized with the external clock source. The more common synchronization method is to synchronize the internal calculation sequence number (within seconds) with the external clock (within seconds). For example, if the device interruption is 4000 points / second, then the moment when the interruption sequence number 0 is triggered corresponds to the whole second 0, the interruption sequence number 1 corresponds to 250us, the interruption sequence number 2 corresponds to 500us... The interruption sequence number 3999 corresponds to 999ms750us, the interruption sequence number 4000 corresponds to 1s, and so on. The common network time synchronization methods for substations are PTP (Precision Time Protocol) or NTP (Network Time Protocol). In network time synchronization, the device establishes a UDP (User Datagram Protocol) connection with the timing device for query operations, and calculates the synchronization deviation based on the ping-pong principle for synchronization adjustment.

[0003] Direct network synchronization methods meet the time synchronization requirements of single-core and multi-core synchronous devices. However, for multi-functional integrated devices, there is a need for multi-core interrupt asynchronous operation. For example, the device has cores A, B, and C, and the corresponding interrupt trigger points are a point / second, b point / second, and c point / second, and a / b / c cannot be divided by each other. At this time, the interrupt operation between the three cores A / B / C is in an asynchronous state. The time synchronization process layer can only interact with a single-core timing source. In the case of multi-core asynchronous conditions, each core cannot be directly synchronized with the timing source. Therefore, it is necessary to invent a network time synchronization method for multi-core asynchronous system devices to achieve synchronization of each core with the timing source. Summary of the invention

[0004] The embodiments of the present application provide a network timing method, device and computer program product for a multi-core asynchronous system, which can solve the technical problem in the prior art that each core cannot be directly synchronized with the timing source in the case of multi-core asynchronous conditions.

[0005] In a first aspect, an embodiment of the present application provides a network timing method for a multi-core asynchronous system, comprising:

[0006] Synchronize the system master time of the multi-core asynchronous system with a timing source;

[0007] Performing timekeeping operations on the system master time;

[0008] Based on the clock differences within seconds between the interrupt times of the multiple cores and the system master time, the interrupts of the multiple cores are synchronized with the system master time.

[0009] In a possible implementation manner of the first aspect, synchronizing the interrupts of the multiple cores with the system master time based on the clock difference between the interrupt times of the multiple cores within seconds and the system master time includes:

[0010] The interruption intervals within seconds of the multiple cores are issued according to a preset rule, and the interruption time within seconds of the multiple cores is set to the number of interruptions within seconds plus the minimum number of system time units below the interruption;

[0011] Convert the system master time in a time format of less than seconds to an interrupt time format within seconds of the multiple cores;

[0012] Calculate the clock difference between the interruption time within 10000 seconds of the multiple cores and the system master time after format conversion, and express the clock difference between the interruption time within 10000 seconds of the multiple cores and the system master time after format conversion as the interruption sequence number deviation and the difference in the number of steps within the interruption;

[0013] The interrupt sequence number is adjusted based on the interrupt sequence number deviation, and the minimum time unit number of the system below the interrupt is adjusted based on the difference in the number of steps within the interrupt.

[0014] In a possible implementation manner of the first aspect, synchronizing the system master time of the multi-core asynchronous system with a timing source includes:

[0015] Set the system master time, which is shared by all cores and is the minimum system time unit number of seconds or less;

[0016] Select any core as the main core for system time synchronization and establish a network time synchronization user datagram protocol connection with the outside world;

[0017] Convert the system master time into the time format of Coordinated Universal Time and write it into the network synchronization message;

[0018] The clock difference between the system master time of the multi-core asynchronous system and the timing source is obtained through the network synchronization message interaction, and the system master time is calibrated based on the clock difference.

[0019] In a possible implementation manner of the first aspect, the punctual operation includes:

[0020] Determine whether the clock difference between the system master time and the timing source is smaller than a threshold value for multiple consecutive times, and if so, confirm that the multi-core asynchronous system enters a synchronous state;

[0021] Counting the clock differences of multiple network time calibrations after entering the synchronization state, and calculating the frequency difference between the system crystal oscillator and the timing source crystal oscillator according to the counted clock differences;

[0022] When the external synchronization signal is lost, compensation is performed based on the frequency difference between the system crystal oscillator and the timing source crystal oscillator.

[0023] In a possible implementation manner of the first aspect, synchronizing the interrupts of the multiple cores with the system master time includes:

[0024] A system master time synchronization flag and a system interrupt synchronization flag are set, and based on the system master time synchronization flag, whether the multiple cores are synchronized with the system master time is controlled; based on the system interrupt synchronization flag, the synchronization of the multiple cores with the system master time is stopped.

[0025] In a possible implementation manner of the first aspect, the method further includes: an error compensation operation; the error compensation operation includes:

[0026] For errors caused by cores whose interrupt thresholds cannot be divided evenly, every n interrupts compensate the interrupt intervals of the cores within seconds by one system minimum time unit.

[0027] In a second aspect, an embodiment of the present application provides a network timing device for a multi-core asynchronous system, including: a timing source synchronization module, a timekeeping module, and an interrupt synchronization module;

[0028] The timing source synchronization module is used to synchronize the system master time of the multi-core asynchronous system with the timing source;

[0029] The timekeeping module is used to perform timekeeping operations on the system master time;

[0030] The interrupt synchronization module is used to synchronize the interrupts of the multiple cores with the system master time based on the clock difference between the interrupt times of the multiple cores within seconds and the system master time.

[0031] In a third aspect, an embodiment of the present application provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the network timing method for a multi-core asynchronous system described in any one of the first aspects above is implemented.

[0032] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the network timing method for a multi-core asynchronous system described in any one of the first aspects above is implemented.

[0033] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a computer device, the computer device executes the network timing method for a multi-core asynchronous system described in any one of the first aspects above.

[0034] In an embodiment of the present application, by synchronizing the system master time of a multi-core asynchronous system with a timing source, it is possible to ensure that the interrupt time of all cores is consistent with an external clock source, thereby improving the synchronization of the entire system. Based on the punctual operation, the stability of the system master time can be maintained. By calculating the clock difference between the interrupt time of each core within seconds and the system master time, the interrupt time of each core is adjusted to synchronize it with the system master time. The coordination problem during multi-core asynchronous operation is solved, ensuring that the interrupts of different cores can be triggered at the precise moment of the system master time. The multi-core asynchronous operation system can be stably synchronized with the timing source, the synchronization accuracy of each core can reach within 1us, and the punctual accuracy can reach 4us in 10 minutes. This method is an effective supplement to the existing synchronization scheme and provides an effective synchronization scheme for asynchronous operation systems.

[0035] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 It is a flowchart of a network timing method for a multi-core asynchronous system provided by an embodiment of the present application;

[0038] Figure 2 It is a structural schematic diagram of a network timing device for a multi-core asynchronous system provided in an embodiment of the present application;

[0039] Figure 3 It is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0041] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0042] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0043] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0044] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0045] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0046] Figure 1 A schematic flow chart of a network time synchronization method for a multi-core asynchronous system provided by the present application is shown, which specifically includes the following steps.

[0047] S101, synchronizing the system master time of the multi-core asynchronous system with a timing source.

[0048] Multi-core asynchronous systems use multiple processor cores (i.e., multiple cores) to improve the computing performance and operational responsiveness of data processing. In such a system, each core can perform tasks independently, or multiple cores can work together to handle complex computing tasks. Asynchronous parallelism allows programs to perform multiple operations on different cores simultaneously without blocking the execution of other operations because of waiting for the completion of a certain operation. The design of multi-core asynchronous systems needs to consider the implementation of interrupt handling and synchronization mechanisms to ensure the correctness and efficiency of multi-tasking systems. Therefore, it is not difficult to see that network time synchronization for synchronization and interrupt time of multiple cores is also an indispensable step.

[0049] In an embodiment of the present invention, the system master time of a multi-core asynchronous system can be simply understood as the local time of the system, such as the local system master time. A timing source refers to a device or system for providing accurate time signals, which can be used to calibrate or synchronize other clock systems. A timing source can be an atomic clock, a GPS satellite, a radio tower, a national timing center, etc. They transmit accurate time information to users who need to synchronize time in various ways, such as radio waves, network signals, telephone lines, etc. The embodiment of the present invention needs to first synchronize the system master time (such as the encoding g_SysTime) of the multi-core asynchronous system with the timing source, so as to calibrate the system master time g_SysTime. It should be noted that this multi-core asynchronous system can adopt a 3-core asynchronous operation mode, with the core interrupt named core0 being 1200 points / second, the core interrupt named core1 being 4000 points / second, and the core interrupt named core2 being 1600 points / second. The interrupt sequence number of core0 is 0 to 1199, the interrupt sequence number of core1 is 0 to 3999, and the interrupt sequence number of core2 is 0 to 1599. The interrupt sequence number of each core must be aligned with the external second.

[0050] S102, performing timekeeping operations on the system master time.

[0051] Specifically, the system master time punctuality refers to maintaining a high-precision time standard in a computer system or network, and this time standard is usually synchronized with the international standard time (such as UTC, Universal Time Coordinated, Coordinated Universal Time). In the embodiment of the present invention, after the system master time synchronized with the timing source is obtained based on the above step 101, the system master time can be punctually operated, that is, the system master time can maintain a high-precision time standard for a long time, ensuring that the system master time is in a synchronized state with the timing source for a long time.

[0052] S103, based on the clock difference between the interruption time of the multiple cores and the system master time within one second, the interruptions of the multiple cores are synchronized with the system master time.

[0053] Among them, the embodiment of the present invention can calculate the interruption time of multiple cores within seconds, compare it with the system master time obtained by the synchronization correction in the aforementioned step 101, and make a difference, so as to obtain the difference between the two, that is, the clock difference between the interruption time of multiple cores within seconds and the system master time, and use the clock difference to adjust the interruption of multiple cores so that the interruption of multiple cores is synchronized with the system master time that has been calibrated through the network.

[0054] The network timing method for a multi-core asynchronous system provided by the embodiment of the present invention can enable the multi-core asynchronous operation system to be stably synchronized with the timing source, and the synchronization accuracy of each core can reach within 1us, and the timekeeping accuracy can reach 4us in 10 minutes. The method is an effective supplement to the existing synchronization solution and provides an effective synchronization solution for the asynchronous operation system.

[0055] In an optional embodiment, the above step 103 includes the following steps A1-A4.

[0056] Step A1: Send the interruption interval within seconds of multiple cores according to the preset rule, and set the interruption time within seconds of multiple cores to the number of interruptions within seconds plus the minimum time unit number of the system below the interruption.

[0057] Among them, the interrupt interval within seconds is usually generated by hardware timers, which send interrupt signals at a fixed frequency so that the operating system can regularly perform specific tasks, such as task scheduling, time synchronization, etc. The interrupt interval can be calculated by the following formula: Interrupt interval time (seconds) = 1 / interrupt frequency (Hz). In the embodiment of the present invention, the FPGA designs an interrupt time MT register per core, which is composed of the number of interrupts below seconds + the minimum system time unit number (tick number) below the interrupt, and the register is maintained by the FPGA. Among them, the concept of "interrupts below seconds" usually refers to the number of clock interrupts (ticks) occurring within one second. The minimum system time unit number (tick number) usually refers to the interval of the operating system clock interrupt, that is, the operating system clock sends an interrupt signal at a certain interval, and this time interval is tick. Tick is the basic unit of a fixed time interval in a computer system. Take core1 as an example: the interrupt is 4000 points / second, and the interrupt sequence number 0~3999 flips; the tick number below the interrupt flips 0~6249. When the tick number below the interrupt is 0, the FPGA triggers a system interrupt, so as to achieve the effect of aligning the interrupt with time. The embodiment of the present invention can be set according to the method: core0 is 1199_Int+20832_tick; core1 is 3999_Int+6249_tick; core2 is 1599_Int+15624_tick.

[0058] Step A2: Convert the system master time format of less than seconds into the interrupt time format of less than seconds for multiple cores.

[0059] Specifically, the system master time of each core interrupt triggering moment can be locked by FPGA, and the system master time in the second can also be converted into the interrupt time MT format in the second of each core. It can be understood that this step A2 is to unify the format of the system master time and the interrupt time in the second of multiple cores, so that both are expressed in the format of: interrupt number in the second + tick number in the interrupt, so as to facilitate the calculation of the clock difference between the two in the subsequent step A3.

[0060] Step A3: Calculate the clock difference between the interruption time within seconds of multiple cores and the system master time after format conversion, and express the clock difference between the interruption time within seconds of multiple cores and the system master time after format conversion as the interruption sequence number deviation and the difference in the number of steps within the interruption.

[0061] Furthermore, the clock difference between the interrupt time of each core and the system mother time after format conversion can be calculated, which includes the interrupt sequence number deviation Dif_Int and the tick difference within the interrupt (or also called the tick deviation within the interrupt) Dif_Tick. Specifically, the interrupt sequence number deviation usually refers to the difference between the expected interrupt sequence number and the actual interrupt sequence number during the interrupt processing process. The tick difference within the interrupt refers to the deviation of the system clock or the error of the timer between two interrupts (i.e., two adjacent ticks).

[0062] Step A4: adjust the interrupt sequence number based on the interrupt sequence number deviation, and adjust the minimum system time unit number below the interrupt based on the difference in the number of steps within the interrupt.

[0063] Among them, the clock error calculated in the above step A3 can be supplemented: the interrupt sequence number deviation Dif_Int can be adjusted directly, that is, each core can directly adjust the sequence number according to the interrupt sequence number deviation. In addition, each core can also adjust the minimum system time unit number (tick number) below the interrupt according to the intra-interrupt tick difference (or intra-interrupt tick deviation) Dif_Tick.

[0064] In an optional embodiment, the above step 101 may include the following steps B1-B4.

[0065] Step B1: Set the system master time, which is shared by all cores and is the system minimum time unit number in seconds or less.

[0066] For example, the system crystal oscillator in the embodiment of the present invention can be 25MHz, and the system master time g_SysTime is set in the format of seconds and 40ns below seconds. The system master time g_SysTime can be maintained by the FPGA and will increase automatically according to the beat of its own crystal oscillator.

[0067] Step B2: Select any core as the main core for system time synchronization, and establish a network time synchronization user datagram protocol connection with the outside.

[0068] The embodiment of the present invention can select any core in the multi-core asynchronous system as the main core of the system time synchronization. Continuing with the above example, core1 can be selected as the main core of the time synchronization, and a PTP (Precision Time Protocol) network time synchronization connection in the IEC1588 format is established with an external timing source. The connection is a user datagram protocol connection, that is, a UDP connection. Specifically, a time synchronization request can be sent every 1 second.

[0069] Step B3: Convert the system master time into the time format of Coordinated Universal Time and write it into the network synchronization message.

[0070] The embodiment of the present invention can change the system mother time g_SysTime into the UTC (Universal Time Coordinated) format and use it as the local time of the network time synchronization communication message. In other words, the system mother time g_SysTime converted into the UTC format is written into the network time synchronization message as the local time in the message.

[0071] Step B4: Obtain the clock difference between the system master time of the multi-core asynchronous system and the timing source through network synchronization message interaction, and calibrate the system master time based on the clock difference.

[0072] Specifically, the clock difference between the local time (ie, the system master time) and the timing source can be calculated according to the time calibration principle of IEC1588, and the system master time g_SysTime can be calibrated based on the clock difference.

[0073] In an optional embodiment, the "timekeeping operation" in the above step 102 may include the following steps C1-C3.

[0074] Step C1: determine whether the clock difference between the system master time and the timing source is smaller than the threshold for multiple consecutive times. If so, confirm that the multi-core asynchronous system enters the synchronous state.

[0075] The multiple times can be a preset number of times, such as 5 times; the threshold can also be a preset time length, such as 1us. That is, it can be determined whether the multi-core asynchronous system has entered the synchronous state by judging whether the clock difference between the system mother time g_SysTime and the timing source is less than 1us for 5 consecutive times.

[0076] Step C2: Count the clock errors of multiple network time calibrations after entering the synchronization state. At this time, the clock errors calculated within 100 calibrations can be counted, for example. The 100 clock errors can be used as a set of statistical data on the frequency deviation between the system mother time g_SysTime (such as the local clock) and the timing source (standard time). The frequency difference between the system crystal oscillator and the timing source crystal oscillator is calculated according to the statistical clock error. Among them, the frequency deviation is calculated as follows: the frequency deviation is calculated based on the statistical frequency deviation data set. It should be noted that in the embodiment of the present invention, the frequency deviation needs to retain decimal places.

[0077] Step C3: When the external synchronization signal is lost, compensation is performed based on the frequency difference between the system crystal oscillator and the timing source crystal oscillator.

[0078] For example, when the external time calibration request is not responded to for three consecutive times, that is, when the external synchronization signal is lost, the system master time enters the timekeeping state. Timekeeping compensation can be performed according to the frequency deviation calculated in the above step C2. For example, if the calculated crystal oscillator deviation is 2.34 ticks (1 tick = 40ns), the system compensates 2 ticks per second, 3 ticks per 10 seconds, and 4 ticks per 100 seconds. In this case, the system timekeeping accuracy can meet 4us for 10 minutes.

[0079] Optionally, in the above step A4, "adjusting the minimum time unit number of the system below the interruption according to the tick difference within the interruption" may include: constraining and compensating the tick difference within the interruption (Dif_Tick) according to a preset adjustment threshold. In other words, the interruption operation can be avoided by constraint compensation, and it is recommended that the adjustment threshold for each interruption be 25 ticks.

[0080] Optionally, in the above step 103, "synchronizing the interrupts of multiple cores with the system master time" may include: setting a system master time synchronization flag and a system interrupt synchronization flag, and based on the system master time synchronization flag, controlling whether the multiple cores are synchronized with the system master time, and based on the system interrupt synchronization flag, stopping the synchronization of the multiple cores with the system master time.

[0081] That is to say, by presetting the synchronization flag in advance, it is possible to define when the flag is set, the system will synchronize, or when the flag is set, the system will interrupt synchronization, so as to determine whether to start interrupt synchronization in a simple and clear way. For example, the system master time synchronization flag can be set to Syn_Top and the system interrupt synchronization flag can be set to Syn_Corex. Before the system is started and not synchronized, the system master time synchronization flag Syn_Top is 0, after synchronization, the system master time synchronization flag is 1, and after the synchronization signal source is lost, the system master time synchronization flag is 0. When the system master time synchronization flag Syn_Top is 0, each core is not synchronized with the system master time g_SysTime; when the system master time synchronization flag Syn_Top is 1, each core is synchronized with the system master time g_SysTime. Furthermore, when the system master time synchronization flag Syn_Top is 1, the system interrupt synchronization flag Syn_Corex is adjusted to 1 after each core completes synchronization; when the system master time synchronization flag Syn_Top is 0, the system interrupt synchronization flag Syn_Corex is adjusted to 0, and each core stops synchronizing with the system master time g_SysTime.

[0082] Optionally, the network timing method of the multi-core asynchronous system may further include: an error compensation operation, which may be added in the last step. The error compensation operation may include: for errors caused by cores whose interruption thresholds cannot be divided evenly, compensating the interruption intervals of multiple cores within seconds by one system minimum time unit for every n interruptions.

[0083] Specifically, the interrupt threshold usually refers to a threshold at which the CPU responds to an interrupt request during interrupt processing. When the priority of the interrupt is higher than this threshold, the CPU will respond to the interrupt and execute the corresponding interrupt service routine. This concept is particularly important in a multi-interrupt system because it involves the management of interrupt priorities, ensuring that high-priority interrupts can be processed in a timely manner, while low-priority interrupts can be temporarily shelved.

[0084] Since the cores whose interrupt thresholds cannot be divided evenly, there will be errors in which the decimal places are ignored. For example, the core0 interrupt is 1200 points / second, and the actual interrupt threshold is 20833.3333 ticks, and the decimal places are ignored. In this way, one tick deviation will be introduced for every three interrupts, and a deviation of 500 ticks (20us) will be introduced for one second. Therefore, in response to this error, the embodiment of the present invention can compensate for the interrupt interval MT of multiple cores within seconds by one system minimum time unit (number of ticks) for every three interrupts. This compensation does not depend on whether the external is synchronized, but compensates for the system's own errors.

[0085] The above describes in detail the network timing method for a multi-core asynchronous system provided by an embodiment of the present invention. The method can also be implemented by a corresponding device. The following describes in detail the network timing device for a multi-core asynchronous system provided by an embodiment of the present invention.

[0086] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0087] Corresponding to the network timing method for the multi-core asynchronous system described in the above embodiment, Figure 2 A structural block diagram of a network timing device for a multi-core asynchronous system provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0088] Reference Figure 2 The network timing device of the multi-core asynchronous system includes a timing source synchronization module 21, a timekeeping module 22 and an interrupt synchronization module 23.

[0089] The timing source synchronization module 21 is used to synchronize the system master time of the multi-core asynchronous system with the timing source.

[0090] The timekeeping module 22 is used to perform timekeeping operations on the system master time.

[0091] The interrupt synchronization module 23 is used to synchronize the interrupts of the multiple cores with the system master time based on the clock difference between the interrupt times of the multiple cores and the system master time within seconds.

[0092] Optionally, the interrupt synchronization module 23 includes: a sending interval unit, a master time conversion unit, a seed difference calculation unit and a synchronization adjustment unit.

[0093] The sending interval unit is used to send the interruption interval within seconds of the multiple cores according to a preset rule, and the interruption time within seconds of the multiple cores is set to the number of interruptions below seconds plus the minimum number of system time units below the interruption.

[0094] The master time conversion unit is used to convert the system master time below seconds into the interrupt time format within seconds of the multiple cores.

[0095] The difference calculation unit is used to calculate the clock difference between the interruption time of the multiple cores within seconds and the system master time, and express the clock difference between the interruption time of the multiple cores within seconds and the system master time as the interruption sequence number deviation and the difference in the number of steps within the interruption.

[0096] The synchronization adjustment unit is used for the multiple cores to adjust the interrupt sequence numbers according to the interrupt sequence number deviation, and to adjust the minimum system time unit number below the interrupt according to the difference in the number of steps within the interrupt.

[0097] Optionally, the timing source synchronization module 21 includes: a system master time setting unit, a connection establishment unit, a conversion unit and a calibration unit.

[0098] Set the system master time unit, which is used to set the system master time. The system master time is shared by all cores and is the system minimum time unit number of seconds and below.

[0099] A connection unit is established to select any core as the main core for system time synchronization and to establish a network time synchronization user datagram protocol connection with the outside.

[0100] The conversion unit is used to convert the system master time into the time format of the coordinated universal time and write it into the network synchronization message.

[0101] A calibration unit is used to obtain the clock difference between the system master time of the multi-core asynchronous system and the timing source through the network synchronization message interaction, and calibrate the system master time based on the clock difference.

[0102] Optionally, the timekeeping operation includes: determining whether the clock difference between the system master time and the timing source is less than a threshold for multiple consecutive times, and if so, confirming that the multi-core asynchronous system has entered a synchronous state; counting the clock differences of multiple network time calibrations after entering the synchronous state, and calculating the frequency difference between the system crystal oscillator and the timing source crystal oscillator according to the counted clock differences; and when the external synchronization signal is lost, compensating based on the frequency difference between the system crystal oscillator and the timing source crystal oscillator.

[0103] Optionally, the interrupt synchronization module 23 further includes: a synchronization flag setting unit.

[0104] A synchronization flag setting unit is used to set a system master time synchronization flag and a system interrupt synchronization flag, and based on the system master time synchronization flag, controls whether the multiple cores are synchronized with the system master time, and based on the system interrupt synchronization flag, stops the multiple cores from synchronizing with the system master time.

[0105] Optionally, the device further includes: an error compensation operation module; the error compensation operation module includes: a compensation unit.

[0106] The compensation unit is used to compensate the interruption interval within seconds of the plurality of cores by one system minimum time unit for every n interruptions, for errors caused by the cores whose interruption thresholds cannot be divided evenly.

[0107] The device provided by the embodiment of the present invention can make the multi-core asynchronous operation system stably synchronize with the timing source, the synchronization accuracy of each core can reach within 1us, and the timekeeping accuracy can reach 4us in 10 minutes. The device is an effective supplement to the existing synchronization solution and provides an effective synchronization solution for the asynchronous operation system.

[0108] It should be noted that the information interaction, execution process and other contents between the above-mentioned modules are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0109] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0110] An embodiment of the present application also provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.

[0111] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0112] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0114] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0115] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0116] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0117] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0118] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

[0119] Figure 3 This is a schematic diagram of the structure of a computer device provided in one embodiment of the present application. Figure 3 As shown, the computer device of this embodiment includes: at least one processor 30 ( Figure 3 Only one is shown), a memory 31 and a computer program 32 stored in the memory 31 and executable on the at least one processor 30, wherein the processor 30 implements the steps in any of the above-mentioned embodiments of the network timing method for a multi-core asynchronous system when executing the computer program 32.

[0120] The computer device may include, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will appreciate that Figure 3 It is only an example of a computer device and does not constitute a limitation of the computer device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0121] The processor 30 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0122] In some embodiments, the memory 31 may be an internal storage unit of the computer device, such as a hard disk or memory of the computer device. In other embodiments, the memory 31 may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the computer device. Further, the memory 31 may also include both an internal storage unit of the computer device and an external storage device. The memory 31 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 31 may also be used to temporarily store data that has been output or is to be output.

[0123] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A network timing method for a multi-core asynchronous system, characterized in that: include: Synchronize the system master time of the multi-core asynchronous system with a timing source; Performing timekeeping operations on the system master time; Based on the clock differences within seconds between the interrupt times of the multiple cores and the system master time, the interrupts of the multiple cores are synchronized with the system master time.

2. The network timing method for a multi-core asynchronous system according to claim 1, characterized in that: The step of synchronizing the interrupts of the multiple cores with the system master time based on the clock difference between the interrupt times of the multiple cores within seconds and the system master time comprises: The interruption intervals within seconds of the multiple cores are issued according to a preset rule, and the interruption time within seconds of the multiple cores is set to the number of interruptions within seconds plus the minimum number of system time units below the interruption; Convert the system master time in a time format of less than seconds to an interrupt time format within seconds of the multiple cores; Calculate the clock difference between the interruption time within 1000 seconds of the multiple cores and the system master time after format conversion, and express the clock difference between the interruption time within 1000 seconds of the multiple cores and the system master time after format conversion as the interruption sequence number deviation and the difference in the number of steps within the interruption; The interrupt sequence number is adjusted based on the interrupt sequence number deviation, and the minimum time unit number of the system below the interrupt is adjusted based on the difference in the number of steps within the interrupt.

3. The network timing method for a multi-core asynchronous system according to claim 1, characterized in that: The step of synchronizing the system master time of the multi-core asynchronous system with a timing source comprises: Set the system master time, which is shared by all cores and is the minimum system time unit number of seconds or less; Select any core as the main core for system time synchronization and establish a network time synchronization user datagram protocol connection with the outside world; Convert the system master time into the time format of Coordinated Universal Time and write it into the network synchronization message; The clock difference between the system master time of the multi-core asynchronous system and the timing source is obtained through the network synchronization message interaction, and the system master time is calibrated based on the clock difference.

4. The network timing method for a multi-core asynchronous system according to claim 1, characterized in that: The timekeeping operation includes: Determine whether the clock difference between the system master time and the timing source is smaller than a threshold value for multiple consecutive times, and if so, confirm that the multi-core asynchronous system enters a synchronous state; Counting the clock differences of multiple network time calibrations after entering the synchronization state, and calculating the frequency difference between the system crystal oscillator and the timing source crystal oscillator according to the counted clock differences; When the external synchronization signal is lost, compensation is performed based on the frequency difference between the system crystal oscillator and the timing source crystal oscillator.

5. The network timing method for a multi-core asynchronous system according to claim 1, characterized in that: The step of synchronizing the interrupts of the plurality of cores with the system master time comprises: A system master time synchronization flag and a system interrupt synchronization flag are set, and based on the system master time synchronization flag, whether the multiple cores are synchronized with the system master time is controlled; based on the system interrupt synchronization flag, the synchronization of the multiple cores with the system master time is stopped.

6. The network timing method for a multi-core asynchronous system according to claim 1, characterized in that: Also includes: Error compensation operation; The error compensation operation includes: For errors caused by cores whose interrupt thresholds cannot be divided evenly, every n interrupts compensate the interrupt intervals of the cores within seconds by one system minimum time unit.

7. A network timing device for a multi-core asynchronous system, characterized in that: include: Timing source synchronization module, timekeeping module and interrupt synchronization module; The timing source synchronization module is used to synchronize the system master time of the multi-core asynchronous system with the timing source; The timekeeping module is used to perform timekeeping operations on the system master time; The interrupt synchronization module is used to synchronize the interrupts of the multiple cores with the system master time based on the clock difference between the interrupt times of the multiple cores within seconds and the system master time.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that When the computer program product is executed on a computer device, the computer device is caused to execute the method according to any one of claims 1 to 6.

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