FSK communication demodulation method and system

Abstract

The invention provides an FSK communication demodulation method and system, and the method comprises the steps: obtaining a to-be-demodulated signal, and enabling the to-be-demodulated signal to be determined based on an FSK analog signal; filtering the to-be-demodulated signal through a first filter to filter out a first burr signal, the length of the first filter being determined based on the width of the first burr signal; filtering the to-be-demodulated signal filtered by the first filter through a second filter so as to filter out a second glitch signal, the length of the second filter being determined based on the width of the second glitch signal, and the filtering time delay of each filtering of the to-be-demodulated signal satisfying a similarity requirement; performing period detection on the to-be-demodulated signal filtered by the second filter; and determining an output demodulation result based on the detection result. According to the FSK communication demodulation method, the structure is simple, and demodulation processing can be accurately and effectively carried out on the to-be-demodulated signal.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of oil field drilling, and in particular to an FSK communication demodulation method and system. Background Art

[0002] In directional drilling operations in oilfield development, drilling tools are usually composed of various functional short sections. In order to reduce IO ports, reduce wiring harnesses and reduce maintenance costs, single-bus communication is often used. Single-bus communication integrates the power supply and communication signals of the drilling tools into one wire, and uses frequency shift keying (FSK) signal modulation to achieve power line carrier communication. FSK has good anti-fading and anti-attenuation performance, and is simple to implement.

[0003] Existing demodulation methods include: coherent demodulation and incoherent demodulation.

[0004] The coherent demodulation algorithm of FSK signals uses a multiplier to multiply the carrier signal with the same carrier frequency and phase as the transmitting end with the received modulated signal, and then filter it through a low-pass filter, and finally obtain the baseband signal after sampling and judgment. Coherent demodulation requires obtaining a coherent carrier, and the circuit design is complex.

[0005] Non-coherent demodulation includes: frequency detection method, zero-crossing detection method, differential detection method and frequency counting method.

[0006] The frequency discrimination method uses amplitude transformation to represent the frequency change of the FSK signal. The amplitude change obtained by the transformation is detected by the amplitude detection method to obtain the baseband signal. This method has a high bit error rate.

[0007] The differential detection method is that the input signal first passes through a bandpass filter to filter out useless signals outside the band, and then is divided into two paths. One path is sent to the multiplier after a delay, and the other path is directly sent to the multiplier. Finally, after multiplication, the high-frequency components are filtered out by a low-pass filter, and the baseband signal can be obtained. This method has very high requirements on the accuracy of the delay network and is not easy to implement.

[0008] The zero-crossing detection method detects the number of times a signal passes through the zero point per unit time, and measures the frequency by the number of times a signal passes through the zero point per unit time. After the input signal to be demodulated is limited, differentiated, and rectified, a pulse sequence is obtained, which corresponds to the frequency change of the received signal, thereby obtaining a rectangular wave of a certain width, and then passing through a low-pass filter to filter out high-order harmonics, and finally after sampling and judgment, the original baseband signal can be obtained.

[0009] However, the circuit modules in the petroleum industry require small circuit size and low power consumption, which limits the use of the above solutions. In addition, general FSK demodulation chips or PLL chips cannot withstand high temperatures above 125°C, so they are also limited when used in underground operating equipment in the petroleum industry. Summary of the invention

[0010] The invention provides an FSK communication demodulation method and system which has a simple structure and can accurately and effectively perform demodulation processing on a signal to be demodulated.

[0011] In order to solve the above technical problems, an embodiment of the present invention provides an FSK communication demodulation method, comprising:

[0012] Obtaining a signal to be demodulated, wherein the signal to be demodulated is determined based on the FSK analog signal;

[0013] Performing filtering processing on the signal to be demodulated by using a first filter to filter out a first glitch signal, wherein the length of the first filter is determined based on the width of the first glitch signal;

[0014] The signal to be demodulated after being filtered by the first filter is filtered by a second filter to filter out a second glitch signal, wherein the length of the second filter is determined based on the width of the second glitch signal, and the filtering delay of each filtering of the signal to be demodulated meets the similarity requirement;

[0015] Performing period detection on the signal to be demodulated after filtering by the second filter;

[0016] The demodulation result to be output is determined based on the detection result.

[0017] In some embodiments, the method further comprises:

[0018] determining a first width of the first glitch signal;

[0019] A length of a first filter is determined based on the first width, and the length of the first filter is greater than the first width.

[0020] In some embodiments, the method further comprises:

[0021] determining a second width of the second glitch signal;

[0022] The length of the second filter is determined based on the second width, the length of the second filter is greater than the second width, the second width is greater than the width of the first glitch signal, and the length of the second filter is greater than the length of the first filter.

[0023] In some embodiments, the first filter and the second filter are both low-pass filters, and the first filter and the second filter are both composed of shift registers and gate circuits. The number of bits of the shift registers in the first filter and the second filter is the same as the length of the corresponding filter.

[0024] In some embodiments, filtering the signal to be demodulated by using a first filter to filter out the first glitch signal includes:

[0025] The shift register in the first filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the first length of the first filter, outputs a sequence to the gate circuit in the first filter, and the gate circuit determines the level output result based on the sequence;

[0026] The method includes filtering the signal to be demodulated after being filtered by the first filter by using a second filter to filter out a second burr signal, including:

[0027] The shift register in the second filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the second length of the second filter, the sequence is output to the gate circuit in the second filter, and the gate circuit determines the level output result based on the sequence;

[0028] The judgment logic of the gate circuit includes: if the values ​​in the sequence all correspond to high levels, then a high level is output; if the values ​​in the sequence all correspond to low levels, then a low level is output; in other cases, the last judgment result is output.

[0029] In some embodiments, the performing period detection on the signal to be demodulated after filtering by the second filter includes:

[0030] Performing edge detection on the signal to be demodulated after filtering by the second filter, and calculating the clock counts of two adjacent rising edges;

[0031] The period is determined based on the clock counting result.

[0032] In some embodiments, determining the period based on the clock counting result includes:

[0033] If the clock count is within the first threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK high frequency;

[0034] If the clock count is within the second threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK low frequency;

[0035] If the clock count is outside the first threshold range and the second threshold range, determining the frequency of the signal to be demodulated after filtering by the second filter as the last determination result;

[0036] The period is determined based on the frequency.

[0037] In some embodiments, the method further comprises:

[0038] At least every n level time sequences in the detection result form a code element, where n is an integer and is at least 8;

[0039] The detection result including the code element is filtered through a third filter to filter out discrete abnormal values, and the third filter is composed of a shift register and a gate circuit.

[0040] In some embodiments, obtaining the signal to be demodulated includes:

[0041] Obtain the FSK pulse signal transmitted by the limit comparator;

[0042] The FSK pulse signal is binarized to form the signal to be demodulated.

[0043] Another embodiment of the present invention also provides an FSK communication demodulation system, including:

[0044] A limiting comparator, used for obtaining a signal to be demodulated, wherein the signal to be demodulated is determined based on the FSK analog signal;

[0045] A first filter, used for filtering the signal to be demodulated to filter out a first glitch signal, wherein the length of the first filter is determined based on the width of the first glitch signal;

[0046] a second filter, configured to filter the signal to be demodulated after being filtered by the first filter to filter out the second glitch signal, wherein the length of the second filter is determined based on the width of the second glitch signal, and the filtering delay of each filtering of the signal to be demodulated meets the similarity requirement;

[0047] A counter, used for performing period detection on the signal to be demodulated after filtering by the second filter;

[0048] The discriminator is used to determine the output demodulation result according to the detection result.

[0049] Based on the disclosure of the above embodiments, it can be known that the beneficial effects of the embodiments of the present invention include performing graded and multiple filtering on the demodulated signal by using multi-stage low-pass filtering, thereby effectively eliminating glitch signals of different widths, while ensuring that the signal delay and positive and negative pulse widths after filtering are relatively stable, thereby reducing the bit error rate; and by also performing low-pass filtering on the result after judgment, the glitch signal in the judgment result can be effectively filtered out, thereby improving the accuracy of the result; in addition, by using a digital shift register and a gate circuit to realize the construction of a low-pass filter, the complexity of the filter circuit design can be greatly reduced.

[0050] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0051] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 The figure is a flow chart of the FSK communication demodulation method in the embodiment of the present invention.

[0054] Figure 2 The figure is a schematic diagram of the application flow of the FSK communication demodulation method in an embodiment of the present invention.

[0055] Figure 3 This is a schematic diagram of a first filter circuit in the FSK communication demodulation method in an embodiment of the present invention.

[0056] Figure 4 It is a structural diagram of the FSK communication demodulation system in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but are not intended to limit the present invention.

[0058] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope and spirit of the present disclosure will occur to those skilled in the art.

[0059] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0060] These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment given as a non-limiting example, with reference to the accompanying drawings.

[0061] It should also be understood that, although the invention has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the invention that have the characteristics recited in the claims and are therefore within the scope of protection defined thereby.

[0062] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0063] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0064] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0065] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0066] like Figure 1 As shown, an embodiment of the present invention provides an FSK communication demodulation method, comprising:

[0067] S1: Obtain a signal to be demodulated, where the signal to be demodulated is determined based on an FSK analog signal;

[0068] S2: filtering the signal to be demodulated by using a first filter to filter out a first glitch signal, wherein the length of the first filter is determined based on the width of the first glitch signal;

[0069] S3: filtering the signal to be demodulated after being filtered by the first filter through a second filter to filter out the second glitch signal, wherein the length of the second filter is determined based on the width of the second glitch signal, and the filtering delay of each filtering of the signal to be demodulated meets the similarity requirement;

[0070] S4: performing period detection on the signal to be demodulated after filtering by the second filter;

[0071] S5: Determine the demodulation result to be output based on the detection result.

[0072] Based on the above content, it can be seen that the solution of this embodiment is to use multi-stage low-pass filtering to perform graded multiple filtering on the demodulated signal, thereby effectively eliminating burr signals of different widths, while ensuring that the signal delay after filtering is consistent, the positive and negative pulse widths are relatively stable, and the bit error rate is effectively reduced.

[0073] In one embodiment, obtaining the signal to be demodulated includes:

[0074] S6: Obtain the FSK pulse signal transmitted by the limit comparator;

[0075] S7: Binarize the FSK pulse signal to form the signal to be demodulated.

[0076] like Figure 2 As shown, the FSK analog signal in this embodiment first passes through the limit comparator to process the FSK analog signal into an FSK pulse signal, and then performs binarization processing on the FSK pulse signal to form a binary signal as a demodulated signal.

[0077] Furthermore, the filter in this embodiment needs to be pre-configured, and different filters are used to filter out different burr signal specifications. For example, for the first filter, the method further includes:

[0078] S8: Determine a first width of the first glitch signal;

[0079] S9: Determine a length of a first filter based on the first width, wherein the length of the first filter is greater than the first width.

[0080] In this embodiment, the first filter is a low-pass filter. When configuring the first filter, the first width of the first glitch signal is first determined based on historical prior data, that is, the glitch signal specifications in the signal are determined, and the width of the glitch signal to be filtered out is determined. Assuming that the first width is 2, when the current filtering needs to filter out glitch signals with a width not greater than 2, the system can determine the candidate length of the first filter based on this, such as 3, 4, etc. Then, based on the principle that the length of the first filter is greater than the first width, and the configuration cost is reduced and the filtering efficiency is improved, the system can further determine that the length of the first filter is 3 from the candidate lengths. At this time, the system can output the length of the first filter as 3 for user reference.

[0081] Further, when configuring the second filter, the method further includes:

[0082] S10: Determine a second width of the second glitch signal;

[0083] S11: determining a length of a second filter based on the second width, wherein the length of the second filter is greater than the second width, the second width is different from a width of the first glitch signal, and the length of the second filter is different from a length of the first filter.

[0084] Similarly, in this embodiment, the second width of the second glitch signal is first determined based on historical prior data, that is, the glitch signal specifications in the signal are determined, and the width of the glitch signal to be filtered out is determined. Assuming that the second width is 6, when the current filtering needs to filter out glitch signals with a width not greater than 6, the system can determine the candidate length of the second filter based on this, such as 7, 8, 9, etc. Then the system can further determine the length of the first filter to be 7 from the candidate lengths based on the principle that the length of the second filter is greater than the second width, the second width is different from the first width, the length of the second filter is different from the length of the first filter, and the configuration cost is reduced and the filtering efficiency is improved. At this time, the system can output the length of the second filter for user reference.

[0085] The above-mentioned glitch signal width is not unique and can be determined according to actual conditions.

[0086] When applied, the first filter can filter the binary signal to remove glitches with a width less than 2 clock cycles. The second filter can filter the binary signal to remove glitches with a width less than 6 clock cycles, while ensuring that the data delay of each filtering is basically consistent.

[0087] Since the filter length has an impact on the edge, assuming that the filter length is N, it can filter out glitches with a width of N-1, but it may also cause jitter with a width of N-1, which has an impact on the frequency measurement using the rising edge width. If the difference between the two frequency counts N_wid is relatively small, in order to prevent the edge jitter introduced by the glitch filter, the filter length N cannot be set too large, and it is appropriate to set N<=floor(N_wid / 2). For example, if a low-pass filter with a design length of 3 (less than or equal tofloor(N_wid / 4), iffloor(N_wid / 4)<=2, then this level of filter is not set) is used to filter the binary signal, it can filter out glitches with a width less than 2 clock cycles; for example, if a low-pass filter with a design length of 7 (less than or equal tofloor(N_wid / 2)) is used to filter the binary signal, this step can filter out glitches with a width less than 6 clock cycles. If N_Wid<=8, only one filter needs to be designed, and the length is less than fl oor(N_wid / 2). That is, if the lengths of the glitch signals to be filtered are similar, only one filter needs to be designed to filter out all the glitch signals.

[0088] In another embodiment, the first filter and the second filter in this embodiment are both low-pass filters, and the first filter and the second filter are both composed of a shift register and a gate circuit, and the number of bits of the shift register in the first filter and the second filter is the same as the length of the corresponding filter. For example, if the length of the first filter is 3, then the length of the corresponding shift register is 3. If the length of the second filter is 7, then the length of the corresponding shift register is 7.

[0089] When applied, such as Figure 3 As shown, filtering the signal to be demodulated by using a first filter to filter out the first glitch signal includes:

[0090] S12: The shift register in the first filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the first length of the first filter, outputs a sequence to a gate circuit in the first filter, and the gate circuit determines a level output result based on the sequence;

[0091] The method includes filtering the signal to be demodulated after being filtered by the first filter by using a second filter to filter out a second burr signal, including:

[0092] S13: The shift register in the second filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the second length of the second filter, outputs a sequence to a gate circuit in the second filter, and the gate circuit determines a level output result based on the sequence;

[0093] The judgment logic of the gate circuit includes: if the values ​​in the sequence all correspond to high levels, then a high level is output; if the values ​​in the sequence all correspond to low levels, then a low level is output; in other cases, the last judgment result is output.

[0094] For example, Figure 3 As shown, the shift register (length N = 2, 3, ...) shifts the input to the left by 1 bit each time it receives a clock signal. The gate circuit (NAND, NOR) judges the sequence formed by the clock signal. If the sequence (N bits), that is, the received signal is all high level, such as 111, the output is high level. If the sequence (N bits) is all low level, such as 000, the output is low level. In other cases, the previous result is output.

[0095] This embodiment scheme realizes the construction of low-pass filter by using digital shift register and gate circuit, which can greatly reduce the complexity of filter circuit design, reduce cost and save energy consumption.

[0096] In another embodiment, the performing period detection on the signal to be demodulated after filtering by the second filter includes:

[0097] S14: performing edge detection on the signal to be demodulated after filtering by the second filter, and calculating clock counts of two adjacent rising edges;

[0098] S15: Determine the period based on the clock counting result.

[0099] That is, edge detection is performed on the filtered pulse, and the time interval between two adjacent rising edges is calculated. The time interval is specifically quantified by the clock count cnt.

[0100] Specifically, determining the period based on the clock counting result includes:

[0101] S16: If the clock count is within the first threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK high frequency;

[0102] S17: If the clock count is within the second threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK low frequency;

[0103] S18: If the clock count is outside the first threshold range and the second threshold range, determining the frequency of the signal to be demodulated after filtering by the second filter as the last determination result;

[0104] S19: Determine the period based on the frequency.

[0105] Exemplarily, the first threshold range is [N_fH - N_wid, N_mid), where N_fH = floor(clk_m / fH), floor(·) is the floor function, fH is the BFSK high frequency, and the corresponding clock count is a positive integer. Also, N_fH < N_fL, and the greater the difference between N_fH and N_fL, the easier it is to distinguish the two frequencies. fL is the BFSK low frequency, and the corresponding clock count is a positive integer, N_fL = floor(clk_m / fL). N_wid is the difference in frequency counts between the two frequencies and is a positive integer, N_wid = abs(N_fL - N_fH), where abs(·) is the absolute value function. N_mid is the median of the frequency counts of the two frequencies and is a positive integer, N_mid = floor((N_fH + N_fL) / 2). The second threshold range is [N_mid, N_fL + N_wid). After calculating the first threshold range and the second threshold range through the above formulas, the system can then discriminate the obtained detection results, determine the discrimination result for characterizing the signal frequency, and finally calculate and determine the period value based on this frequency.

[0106] Further, the method further includes:

[0107] S20: Group at least every n levels of the detection result into a symbol, where n is an integer and at least 8;

[0108] S21: Filter the detection result containing the symbol through a third filter to filter out discrete outliers, and the third filter is composed of a shift register and a gate circuit.

[0109] For example, in this embodiment, at least 8 levels of the detection structure obtained in the previous step are grouped into a symbol, and the detection result containing the symbol is filtered through a third filter to filter out a few discrete abnormal results to obtain the final result. The third filter in this embodiment is also a low-pass filter, and its structure is also composed of a digital shift register and a gate circuit in cooperation. In this embodiment, by performing low-pass filtering on the determined result, the glitch signals in the determination result can be effectively filtered out, improving the result accuracy.

[0110] As Figure 4 shown, another embodiment of the present invention simultaneously provides an FSK communication demodulation system, including:

[0111] A limiting comparator for obtaining a signal to be demodulated, where the signal to be demodulated is determined based on an FSK analog signal;

[0112] A first filter for filtering the signal to be demodulated to filter out first glitch signals, and the length of the first filter is determined based on the width of the first glitch signals;

[0113] a second filter, configured to filter the signal to be demodulated after being filtered by the first filter to filter out the second glitch signal, wherein the length of the second filter is determined based on the width of the second glitch signal, and the filtering delay of each filtering of the signal to be demodulated meets the similarity requirement;

[0114] A counter, used for performing period detection on the signal to be demodulated after filtering by the second filter;

[0115] The discriminator is used to determine the output demodulation result according to the detection result.

[0116] In some embodiments, the method further comprises:

[0117] determining a first width of the first glitch signal;

[0118] A length of a first filter is determined based on the first width, and the length of the first filter is greater than the first width.

[0119] In some embodiments, the system further comprises:

[0120] The processor is used to determine a second width of the second glitch signal; determine a length of a second filter based on the second width, wherein the length of the second filter is greater than the second width, the second width is greater than the width of the first glitch signal, and the length of the second filter is greater than the length of the first filter.

[0121] In some embodiments, the first filter and the second filter are both low-pass filters, and the first filter and the second filter are both composed of shift registers and gate circuits. The number of bits of the shift registers in the first filter and the second filter is the same as the length of the corresponding filter.

[0122] In some embodiments, filtering the signal to be demodulated by using a first filter to filter out the first glitch signal includes:

[0123] The shift register in the first filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the first length of the first filter, outputs a sequence to the gate circuit in the first filter, and the gate circuit determines the level output result based on the sequence;

[0124] The method includes filtering the signal to be demodulated after being filtered by the first filter by using a second filter to filter out a second burr signal, including:

[0125] The shift register in the second filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the second length of the second filter, the sequence is output to the gate circuit in the second filter, and the gate circuit determines the level output result based on the sequence;

[0126] The judgment logic of the gate circuit includes: if the values ​​in the sequence all correspond to high levels, then a high level is output; if the values ​​in the sequence all correspond to low levels, then a low level is output; in other cases, the last judgment result is output.

[0127] In some embodiments, the performing period detection on the signal to be demodulated after filtering by the second filter includes:

[0128] Performing edge detection on the signal to be demodulated after filtering by the second filter, and calculating the clock counts of two adjacent rising edges;

[0129] The period is determined based on the clock counting result.

[0130] In some embodiments, determining the period based on the clock counting result includes:

[0131] If the clock count is within the first threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK high frequency;

[0132] If the clock count is within the second threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK low frequency;

[0133] If the clock count is outside the first threshold range and the second threshold range, determining the frequency of the signal to be demodulated after filtering by the second filter as the last determination result;

[0134] The period is determined based on the frequency.

[0135] In some embodiments, the discriminator is further used to group at least every n level time sequences in the detection result into a code element, where n is an integer and is at least 8;

[0136] The system further comprises:

[0137] The third filter is used to filter the detection result containing the code element to filter out discrete abnormal values, and the third filter is composed of a shift register and a gate circuit.

[0138] In some embodiments, obtaining the signal to be demodulated includes:

[0139] Obtain the FSK pulse signal transmitted by the limit comparator;

[0140] The FSK pulse signal is binarized to form the signal to be demodulated.

[0141] In addition, it will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0142] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or multiple boxes.

[0143] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0144] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

Claims

1. A FSK communication demodulation method, characterized in that: include: Obtaining a signal to be demodulated, wherein the signal to be demodulated is determined based on the FSK analog signal; Performing filtering processing on the signal to be demodulated by using a first filter to filter out a first glitch signal, wherein the length of the first filter is determined based on the width of the first glitch signal; The signal to be demodulated after being filtered by the first filter is filtered by a second filter to filter out a second glitch signal, wherein the length of the second filter is determined based on the width of the second glitch signal, and the filtering delay of each filtering of the signal to be demodulated meets the similarity requirement; Performing period detection on the signal to be demodulated after filtering by the second filter; The demodulation result to be output is determined based on the detection result.

2. The FSK communication demodulation method according to claim 1, characterized in that: The method further comprises: determining a first width of the first glitch signal; A length of a first filter is determined based on the first width, and the length of the first filter is greater than the first width.

3. The FSK communication demodulation method according to claim 1, characterized in that: The method further comprises: determining a second width of the second glitch signal; The length of the second filter is determined based on the second width, the length of the second filter is greater than the second width, the second width is greater than the width of the first glitch signal, and the length of the second filter is greater than the length of the first filter.

4. The FSK communication demodulation method according to claim 1, characterized in that: The first filter and the second filter are both low-pass filters, and are both composed of a shift register and a gate circuit. The number of bits of the shift registers in the first filter and the second filter is the same as the length of the corresponding filter.

5. The FSK communication demodulation method according to claim 4, characterized in that: The filtering process of the signal to be demodulated by using a first filter to filter out a first glitch signal includes: The shift register in the first filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the first length of the first filter, outputs a sequence to the gate circuit in the first filter, and the gate circuit determines the level output result based on the sequence; The method includes filtering the signal to be demodulated after being filtered by the first filter by using a second filter to filter out a second burr signal, including: The shift register in the second filter shifts one bit each time it receives a clock signal, and when the number of shifted bits is equal to the second length of the second filter, the sequence is output to the gate circuit in the second filter, and the gate circuit determines the level output result based on the sequence; The judgment logic of the gate circuit includes: if the values ​​in the sequence all correspond to high levels, then a high level is output; if the values ​​in the sequence all correspond to low levels, then a low level is output; in other cases, the last judgment result is output.

6. The FSK communication demodulation method according to claim 1, characterized in that: The performing period detection on the signal to be demodulated after filtering by the second filter comprises: Performing edge detection on the signal to be demodulated after filtering by the second filter, and calculating the clock counts of two adjacent rising edges; The period is determined based on the clock counting result.

7. The FSK communication demodulation method according to claim 6, characterized in that: The determining the period based on the clock counting result comprises: If the clock count is within the first threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK high frequency; If the clock count is within the second threshold range, determining that the frequency of the signal to be demodulated after filtering by the second filter is a BFSK low frequency; If the clock count is outside the first threshold range and the second threshold range, determining the frequency of the signal to be demodulated after filtering by the second filter as the last determination result; The period is determined based on the frequency.

8. The FSK communication demodulation method according to claim 1 or 4, characterized in that: The method further comprises: At least every n level time sequences in the detection result form a code element, where n is an integer and is at least 8; The detection result including the code element is filtered through a third filter to filter out discrete abnormal values, and the third filter is composed of a shift register and a gate circuit.

9. The FSK communication demodulation method according to claim 1, characterized in that: The obtaining of the signal to be demodulated comprises: Obtain the FSK pulse signal transmitted by the limit comparator; The FSK pulse signal is binarized to form the signal to be demodulated.

10. An FSK communication demodulation system, characterized in that: include: A limiting comparator, used for obtaining a signal to be demodulated, wherein the signal to be demodulated is determined based on the FSK analog signal; A first filter, used for filtering the signal to be demodulated to filter out a first glitch signal, wherein the length of the first filter is determined based on the width of the first glitch signal; a second filter, configured to filter the signal to be demodulated after being filtered by the first filter to filter out the second glitch signal, wherein the length of the second filter is determined based on the width of the second glitch signal, and the filtering delay of each filtering of the signal to be demodulated meets the similarity requirement; A counter, used for performing period detection on the signal to be demodulated after filtering by the second filter; The discriminator is used to determine the output demodulation result according to the detection result.

Images