Adaptive cache queue optimization method and device based on 104 protocol data and electronic equipment

Abstract

The invention provides an adaptive cache queue optimization method and device based on 104 protocol data and electronic equipment. According to the implementation scheme, the comprehensive priority of first data is determined based on attributes such as the data type, the time sensitivity and the data priority of the first data; based on the data sending frequency of each first cache queue in the plurality of first cache queues, merging the first cache queues to obtain a merged queue; determining an insertion sequence of the first data based on the total number of the arranged data in the combined queue and the comprehensive priority of the first data so as to insert the first data into the combined queue; based on the start bit data and the last bit data of each first cache queue, splitting the merged queue into which the data is inserted, so as to determine and obtain each updated first cache queue based on each split queue; and based on a 104 protocol, respectively sending the data in each updated first cache queue. According to the invention, the data transmission performance can be optimized.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a method, device and electronic device for optimizing a cache queue based on 104 protocol data self-adaptation. Background Art

[0002] The 104 protocol is a widely used communication protocol in power systems, used to achieve data transmission and control between power equipment. In distribution network automation, the reliable transmission of 104 protocol data is crucial for the safe and stable operation of the power grid. As a protocol based on the TCP / IP protocol, the 104 protocol plays an important role in power systems.

[0003] In practical applications, especially under weak network conditions, the 104 protocol faces many challenges. Due to the high network latency, high packet loss rate, unstable bandwidth, and large number of devices (tens of thousands of devices in a city), the traditional TCP / IP-based 104 protocol performs poorly in terms of data transmission reliability and success rate under weak network conditions. This has a serious impact on key areas such as distribution network automation, which may lead to inaccurate equipment status monitoring, control command transmission failure, and other problems, thus affecting the safe and stable operation of the power grid.

[0004] In addition, since the 104 protocol is the current protocol of the power system, it cannot be replaced in the short term considering the complexity and stability requirements of the power system. This requires finding an effective solution to optimize the performance of data transmission under weak network conditions without changing the 104 protocol itself and the application interface. Summary of the invention

[0005] The present invention provides a method, device and electronic device for optimizing a cache queue based on 104 protocol data adaptively, which can solve at least one of the above technical problems.

[0006] According to one aspect of the present invention, a method for optimizing a cache queue based on adaptive 104 protocol data is provided, comprising: Determine the data type, time sensitivity, data priority, data structure, and data production method of the first data based on the 104 protocol; Determining a comprehensive priority of the first data based on a data type, time sensitivity, data priority, data structure, and data production method of the first data; Based on the data sending frequency of each of the first cache queues in the plurality of first cache queues, the plurality of first cache queues are merged to obtain a merged queue; Determining an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; Inserting the first data into the merge queue based on the insertion order of the first data to obtain the merge queue after the data is inserted; Based on the start bit data and the end bit data of each of the first cache queues, the merged queue after the data is inserted is split to obtain a plurality of split queues; Based on each of the split queues, updating each of the first cache queues to obtain each updated first cache queue; Based on the 104 protocol and the updated data sending frequency of each of the first cache queues, the data in each of the updated first cache queues are sent respectively.

[0007] According to another aspect of the present invention, there is provided a device for optimizing cache queues based on 104 protocol data, comprising: A data attribute determination module, for determining the data type, time sensitivity, data priority, data structure and data production method of the first data based on the 104 protocol; a comprehensive priority determination module, configured to determine the comprehensive priority of the first data based on the data type, time sensitivity, data priority, data structure and data production method of the first data; A queue merging module, configured to merge the plurality of first cache queues based on a data sending frequency of each of the plurality of first cache queues to obtain a merged queue; an insertion order determination module, configured to determine an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; A data insertion module, used for inserting the first data into the merge queue based on the insertion order of the first data, to obtain the merge queue after the data is inserted; A queue splitting module, used for splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues; A queue updating module, configured to update each of the first cache queues based on each of the split queues to obtain each updated first cache queue; The data sending module is used to send the data in each updated first cache queue based on the 104 protocol and the data sending frequency of each updated first cache queue.

[0008] The technical solution of the present invention is adopted to set multiple first cache queues with different data transmission frequencies. When the first data is parsed and obtained, the comprehensive priority of the first data is determined based on the data type, time sensitivity, data priority, data structure and data production method of the first data under the 104 protocol, and the multiple first cache queues are arranged and merged into a merged queue. The insertion order of the first data in the merged queue is determined by using the comprehensive priority of the first data and the total amount of data in the merged queue. The first data is inserted into the merged queue according to the insertion order. Then, according to the starting bit data and the last bit data of each first cache queue before the original merger, the merged queue is split, and multiple split queues can be formed. Finally, according to each split queue, the first cache queues corresponding to each other before the merger are updated to obtain each updated first cache queue. In this way, for the first data to be sent, it is not simply arranged in the cache queue according to the level of its comprehensive priority, but the data is inserted into the queue by merging, inserting and splitting the cache queues. In this way, even if the comprehensive priority of the first data to be sent is low, it may be inserted into a front position in a cache queue due to the influence of other factors, thereby optimizing the data transmission performance.

[0009] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to better understand the present invention and do not constitute a limitation of the present invention. Figure 1 It is a flow chart of a method for optimizing cache queues based on 104 protocol data self-adaptation according to an embodiment of the present invention; Figure 2 is a schematic diagram of a first sequential queue according to an embodiment of the present invention; Figure 3 is a schematic diagram of a distribution network automation terminal according to an embodiment of the present invention; Figure 4 It is a structural block diagram of a device for adaptively optimizing cache queues based on 104 protocol data according to an embodiment of the present invention; Figure 5 The block diagram is a block diagram of an electronic device for implementing the method according to the embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following is a description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be appreciated by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present invention. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0012] Figure 1 It is a flow chart of a method for optimizing cache queues based on 104 protocol data adaptively according to an embodiment of the present invention.

[0013] like Figure 1 As shown, the adaptive cache queue optimization method based on protocol data 104 may include: S110, determining a data type, time sensitivity, data priority, data structure, and data production method of the first data based on the 104 protocol; S120, determining a comprehensive priority of the first data based on a data type, time sensitivity, data priority, data structure, and data production method of the first data; S130, merging the multiple first cache queues based on the data sending frequency of each of the multiple first cache queues to obtain a merged queue; S140, determining an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; S150, inserting the first data into the merge queue based on the insertion order of the first data, to obtain the merge queue after the data is inserted; S160, splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each first cache queue to obtain a plurality of split queues; S170, based on each split queue, updating each first cache queue to obtain each updated first cache queue; S180 , based on the 104 protocol and the data sending frequency of each updated first cache queue, respectively send the data in each updated first cache queue.

[0014] It can be understood that the first data may be any data in the distribution network, and the data is 104 protocol data.

[0015] Exemplarily, the data types under the 104 protocol may include telemetry data, remote control data, remote adjustment data, etc.

[0016] Exemplarily, the time sensitivity under the 104 protocol refers to the validity period of the data, for example, valid within one minute, valid within two minutes, etc.

[0017] For example, the data priority level under the 104 protocol may include high, medium and low levels, or may be a numerical level.

[0018] Exemplarily, the type of data structure under the protocol 104 may include binary, decimal or structured data.

[0019] Exemplarily, the data production methods under the 104 protocol may include frequency-based production and on-demand production.

[0020] Exemplarily, based on the data type, time sensitivity, data priority, data structure and data production method of the first data, the data type score, time sensitivity score, data priority score, data structure score and data production method score are determined respectively. Based on the data type weight, time sensitivity weight, data priority weight, data structure weight and data production method weight, the data type score, time sensitivity score, data priority score, data structure score and data production method score are weighted and summed respectively to determine the comprehensive priority of the first data.

[0021] Exemplarily, the comprehensive priority of the first data may be a scoring value.

[0022] Exemplarily, the first cache queue may be any cache queue in a buffer area waiting to send data. The data sending frequencies of each of the multiple first cache queues are different. For example, the data sending frequency of cache queue Q1 is to send data every two seconds, the data sending frequency of cache queue Q2 is to send data every 1 minute, and the data sending frequency of cache queue Q3 is to send data every 1 hour.

[0023] Exemplarily, in the above step S130, all first cache queues may be directly merged. Alternatively, based on the relationship between the comprehensive priority or time sensitivity of the first data and each first cache queue, some cache queues may be selected from multiple first cache queues for merging. After merging the queues, the above insertion and splitting steps may be performed. Data is sent based on the splitting steps and the remaining cache queues that are not involved in the queue.

[0024] Exemplarily, in a merged queue, the higher the data sending frequency of the cache queues is, the closer the cache queues are in the merged queue.

[0025] like Figure 2 As shown, cache queue Q1 is sorted before cache queue Q2, and cache queue Q2 is sorted before cache queue Q3, thus forming a merged queue.

[0026] For any data P1, P2 or P3, its insertion position in the merge queue can be determined according to the comprehensive priority of the data P1, P2 or P3, and the data is inserted into the merge queue according to the insertion position. For example, the data P1, P2 or P3 is inserted into the merge queue to form a merge queue after the data is inserted.

[0027] It can be understood that the starting bit data of the first cache queue before the update is the same as the starting bit data of the first cache queue after the update, and the last bit data of the first cache queue before the update is the same as the last bit data of the first cache queue after the update. In this way, according to such requirements, each cache queue in the second sequential queue can be split to obtain the updated first cache queue. Each updated first cache queue is a split queue.

[0028] Of course, in actual operation, the identification information of the above data can be queued, the identification can be inserted, and the queue can be split, so that the data processing efficiency can be improved.

[0029] Exemplarily, according to the 104 protocol, based on the updated data sending frequency of the first cache queue, the data in the updated first cache queue are sent respectively.

[0030] According to the above implementation, multiple first cache queues with different data sending frequencies are set. When the first data is parsed and obtained, the comprehensive priority of the first data is determined based on the data type, time sensitivity, data priority, data structure and data production method of the first data under the 104 protocol, and the multiple first cache queues are arranged and merged into a merged queue. The insertion order of the first data in the merged queue is determined by using the comprehensive priority of the first data and the total amount of data in the merged queue. The first data is inserted into the merged queue according to the insertion order, and then, according to the starting bit data and the last bit data of each original first cache queue before merging, the merged queue is split, which can be a plurality of split queues. Finally, the first cache queues before merging corresponding to each split queue are updated according to each split queue to obtain each updated first cache queue. In this way, the first data to be sent is not simply arranged in the cache queue according to its comprehensive priority, but the data is inserted into the queue by merging, inserting and splitting the cache queue. In this way, even if the comprehensive priority of the first data to be sent is low, it may be inserted into a front position in the cache queue due to other factors, or even if the comprehensive priority is high, it may be inserted into a back position in the cache queue due to other factors. Thus, data transmission performance can be optimized.

[0031] In one embodiment, the above-mentioned method of merging multiple first cache queues based on the data sending frequency of each first cache queue in the multiple first cache queues to obtain a merged queue includes: based on the data sending frequency of each first cache queue in the multiple first cache queues, determining at least one second cache queue in the multiple first cache queues in which there is a mapping relationship between the data sending frequency and the comprehensive priority of the first data; based on the data sending frequency of each second cache queue, determining the merging order of each second cache queue; based on the merging order of each second cache queue, merging the queues of each second cache queue to obtain a merged queue.

[0032] Exemplarily, a comprehensive priority may correspond to multiple data transmission frequencies. For example, if the priority falls between 80 and 90, it corresponds to multiple data transmission frequencies of sending data once every 10 minutes, once every 15 minutes, and once every 30 minutes. Then, the cache queues corresponding to each of these multiple data transmission frequencies are used as the second cache queue.

[0033] It can be understood that the second cache queue is one of the multiple first cache queues. The second cache queue is a queue to be merged.

[0034] Exemplarily, the higher the data sending frequency of the second cache queue is, the higher the merging order of the second cache queue is.

[0035] According to the above implementation, based on the mapping relationship between the data transmission frequency and the comprehensive priority of the first data, the queues to be merged are screened out from the multiple first cache queues, and the queues to be merged are merged according to the data transmission frequency of the queues to obtain a merged queue. In this way, while ensuring the insertion effect of the queue, the number of queues to be merged can be reduced, and the post-splitting actions can be reduced, thereby improving the efficiency of queue optimization.

[0036] In one embodiment, the above-mentioned merging of multiple first cache queues based on the data sending frequency of each first cache queue in the multiple first cache queues to obtain a merged queue includes: determining the matching degree between each first cache queue and the first data based on the data sending frequency of each first cache queue in the multiple first cache queues and the time sensitivity of the first data; determining at least one third cache queue in the multiple first cache queues based on the matching degree between each first cache queue and the first data; determining the merging order of each third cache queue based on the data sending frequency of each third cache queue; and merging each third cache queue based on the merging order of each third cache queue to obtain a merged queue.

[0037] Exemplarily, the higher the time sensitivity of the first data, the higher the data transmission frequency of the first cache queue, the higher the matching degree between the two. The lower the time sensitivity of the first data, the lower the data transmission frequency of the first cache queue, the higher the matching degree between the two. The higher the time sensitivity of the first data, the lower the data transmission frequency of the first cache queue, the lower the matching degree between the two. The lower the time sensitivity of the first data, the higher the data transmission frequency of the first cache queue, the lower the matching degree between the two.

[0038] Exemplarily, a distance formula may be used to calculate the distance between the data sending frequency of the first cache queue and the time sensitivity of the first time, and based on the distance between the two, the matching degree between the first cache queue and the first data is determined.

[0039] Exemplarily, based on the matching degree between each first cache queue and the first data, a cache queue with a matching degree greater than a preset matching degree threshold among the multiple first cache queues is used as the third cache queue.

[0040] It can be understood that the third cache queue is one of the multiple first cache queues. The third cache queue is a queue to be merged. The second cache queue in the above embodiment and the third cache queue in this example are queues to be merged, and there may be overlapping queues between the two.

[0041] Exemplarily, the higher the data sending frequency of the third cache queue is, the higher the merging order of the third cache queue is.

[0042] According to the above implementation, the data transmission frequency of each first cache queue and the time sensitivity of the first data are used to determine the matching degree between each first cache queue and the first data. Then, the matching degree is used to select queues to be merged from each first cache queue, and the merging order of each queue to be merged is determined according to the data transmission frequency of each queue to be merged, so as to merge the queues.

[0043] Based on the data transmission frequency of each first cache queue in multiple first cache queues and the time sensitivity of the first data, determine the matching degree between each first cache queue and the first data; based on the matching degree between each first cache queue and the first data, determine at least one third cache queue in multiple first cache queues; based on the data transmission frequency of each third cache queue, determine the merging order of each third cache queue; based on the merging order of each third cache queue, merge each third cache queue to obtain a merged queue. In this way, it can be ensured that the first data can be inserted into the queue whose data transmission frequency matches its time sensitivity, and the number of queues that need to be merged can be reduced, as well as the post-splitting actions, thereby improving the efficiency of queue optimization.

[0044] In one embodiment, the above-mentioned determination of the insertion order of the first data based on the total number of arranged data in the merged queue and the comprehensive priority of the first data may include: determining the sorting percentage of the first data based on the ratio between the comprehensive priority of the first data and a preset comprehensive priority upper limit; determining the arrangement order of the first data based on the product of the total number of arranged data in the first sequence queue and the sorting percentage of the first data.

[0045] Exemplarily, the comprehensive priority of the first data may be a score between 0 and 100, and the upper limit of the comprehensive priority is 100.

[0046] Exemplarily, the comprehensive priority of the first data may be an integer level between 1 and 10, and the upper limit of the combined priority is 10.

[0047] Exemplarily, if the product of the total number of arranged data in the merged queue and the ranking percentage of the first data is not an integer, it can be rounded to obtain a corresponding integer arrangement order.

[0048] According to the above implementation, the first data can be inserted once to determine its cache queue and its position in the cache queue according to its priority, that is, the data sending frequency of the first data and its position in the cache queue corresponding to the data sending frequency are determined.

[0049] In one embodiment, it also includes: determining the target queue length of each first cache queue based on the data insertion frequency of each first cache queue; when the queue length of a fourth cache queue among the multiple first cache queues is greater than the target queue length of the fourth cache queue, clearing data on the fourth cache queue so that the queue length of the fourth cache queue after data clearing matches its target queue length.

[0050] It can be understood that the fourth cache queue is a cache queue among the multiple first cache queues. The fourth cache queue is a queue whose queue length is greater than its corresponding target queue length, that is, a queue whose queue length exceeds its predicted storage space length. The fourth cache queue has redundant data, which needs to be cleared, which can avoid congestion in the data transmission channel, thereby improving data transmission efficiency.

[0051] Exemplarily, at regular intervals, the target queue length of each first cache queue may be determined based on the data insertion frequency of each first cache queue.

[0052] For example, Figure 2 As shown, the target queue lengths of the cache queues Q1, Q2 and Q3 can be adjusted. If the actual queue length of the cache queue exceeds the target queue length, data can be cleared for the cache queue.

[0053] Exemplarily, the faster the data insertion frequency of the first cache queue is, the longer the target queue length of the first cache queue is.

[0054] It can be understood that the queue length is the total amount of data in the queue. The target queue length is the upper limit of the total amount of data in the queue.

[0055] It can be understood that the second cache queue is any queue among the multiple first cache queues whose queue length is greater than its corresponding target queue length.

[0056] It can be understood that when the queue length of the second cache queue is greater than its corresponding target queue length, the cache space of the second cache queue is insufficient.

[0057] Exemplarily, the cache space capacity of each first cache queue is set based on the target queue length of the first cache queue.

[0058] According to the above embodiment, based on the data insertion frequency of the cache queue, the total upper limit of the data that can be arranged in the cache queue is adjusted in real time to ensure that the size of the queue can adapt to the change in the data generation speed. In addition, when the cache space of the queue is insufficient, the queue can be cleared to avoid data congestion in the cache queue.

[0059] In one embodiment, based on the data insertion frequency of each first cache queue, the target queue length of each first cache queue is determined, including: based on the data insertion frequency of the first cache queue, an adjustment coefficient is determined; based on the product of the data insertion frequency of the first cache queue and the adjustment coefficient, and the basic queue length corresponding to the first cache queue, the target queue length of the first cache queue is determined.

[0060] Exemplarily, different cache queues have corresponding basic queue lengths that are different.

[0061] For example, different data insertion frequencies have different corresponding adjustment coefficients. The faster the frequency, the larger the adjustment coefficient.

[0062] Exemplarily, the data insertion frequency may be the frequency of data insertion into the cache queue. Alternatively, it may be considered as the update frequency of the cache queue. If the cache queue is updated once each time data is inserted into the cache queue. If no new data is inserted into the queue after the queue participates in the aforementioned merging, inserting and splitting steps, the queue may be considered as an unupdated queue although it is nominally an updated queue. Alternatively, the data insertion frequency may be considered as the frequency of data generation. For example, the amount of data generated per second.

[0063] Exemplarily, the product of the data insertion frequency and the adjustment coefficient of the first cache queue is summed with 1, and the sum is multiplied by the basic queue length corresponding to the first cache queue to obtain the target queue length of the first cache queue.

[0064] According to the above implementation, the target queue length of the first cache queue can be accurately adjusted.

[0065] In one embodiment, data cleaning is performed on the fourth cache queue, including: determining historical feedback data of the corresponding historical data based on the attribute information of each second data in each fourth cache queue; determining a comprehensive score of each second data based on the load score of the operating system, the feedback score of the historical feedback data corresponding to each second data, and the dimension score of each information in the attribute information of each second data; based on the comprehensive score of each second data, cleaning the second data in the fourth cache queue whose comprehensive score does not meet the preset comprehensive score condition.

[0066] Exemplarily, the attribute information of the second data is the same as the attribute information of the historical data corresponding to the second data. For example, the data type, time sensitivity, data priority, data structure, data generation frequency and data usage of the second data are the same as the data type, time sensitivity, data priority, data structure, data generation frequency and data usage of the corresponding historical data.

[0067] Exemplarily, the historical feedback data of the historical data is the data sent by the sending end to the receiving end and fed back by the receiving end.

[0068] Exemplarily, the embodiment of the present invention can be applied to a distribution network automation terminal as a transmitter. The operating system is the operating system of the transmitter. The load score of the operating system can be determined according to the ratio between the current load of the operating system and the preset load upper limit. For example, the higher the load of the operating system, the lower the score. When the load of the operating system is high, the cache size corresponding to the queue needs to be reduced to reduce the load.

[0069] Exemplarily, the corresponding score is calculated according to the sending return time of the feedback data of each type of transmission protocol. For example, the slower the feedback, the lower the score.

[0070] Exemplarily, the attribute information of the data includes data type, time sensitivity, data priority, data structure, data generation frequency and data usage method.

[0071] For example, different data types have different scores. Remote control data may have a higher score because it is usually more critical.

[0072] For example, the time sensitivity of data is the validity period of the data. The shorter the validity period of the data, the higher the corresponding dimension score.

[0073] Illustratively, the higher the priority, the higher the score.

[0074] Exemplarily, the data structure may be structured data or binary data. For example, structured data may be easier to process, so the score may be slightly lower; while binary data may require more storage space and processing time, so the score may be slightly higher.

[0075] For example, data generated at a high frequency may have a lower score because the space it occupies in the cache will be quickly replaced by new data.

[0076] Exemplarily, the score is calculated based on how the data is used. For example, a scenario using the latest data may give a higher score to the latest generated data, while a scenario using the oldest data may give a higher score to the oldest data.

[0077] Exemplarily, a weighted sum is taken of the load score of the operating system, the feedback score of the historical feedback data corresponding to the second data, and the dimensional score of each information in the attribute information of the second data to obtain a comprehensive score of the second data.

[0078] Exemplarily, when the cache space is insufficient, the data items with the lowest comprehensive scores are deleted first. For example, a threshold may be set, and when the comprehensive score of a data item is lower than the threshold, it is regarded as low-priority data that can be deleted.

[0079] According to the above implementation, the importance of the data, i.e., the above comprehensive score, can be determined dynamically based on the system load, the speed of the feedback data, and the attribute information of the data itself. When the cache space of the queue is insufficient, the data with a low comprehensive score can be deleted first based on the comprehensive score of the data.

[0080] In one embodiment, the above-mentioned merged queue after the data is inserted is split based on the starting bit data and the last bit data of each first cache queue to obtain multiple split queues, including: based on the starting bit data and the last bit data of the first cache queue, the corresponding target starting bit data and the target last bit data are determined in the merged queue after the data is inserted; in the merged queue after the data is inserted, the queue from the target starting bit data to the target last bit data is intercepted to obtain a split queue.

[0081] Exemplarily, the identifier of the start bit data can be used to determine the target start bit data with the same identifier in the merge queue, and the identifier of the end bit data can be used to determine the target end bit data with the same identifier in the merge queue.

[0082] It is understandable that for each first cache queue, data search can be performed according to the steps of this example and then the queue can be intercepted, so that multiple split queues can be obtained. Subsequently, based on the multiple split queues and the remaining first cache queues not involved in the merger, the final updated first cache queues are determined together.

[0083] According to the above implementation, a queue corresponding to the original queue before merging can be split, so that the final updated first cache queues can be determined based on the split queues and the remaining first cache queues that did not participate in the merger. Therefore, the data in each queue can be sent in combination with the sending frequency of the updated first cache queue.

[0084] Figure 3 It is a structural diagram of a distribution network automation terminal according to an embodiment of the present invention.

[0085] like Figure 3 As shown, any method of the embodiment of the present invention can be applied to Figure 2 In the distribution network automation terminal in the system, the cache optimization and data transmission of the distribution network data are realized. The distribution network automation terminal can be a sending end or a receiving end, and the above method is applied to the sending end.

[0086] When the distribution network automation terminal generates 104 protocol data, the data parsing / processing module parses the data according to the business. The policy executor writes the 104 protocol data into the corresponding hierarchical priority queue based on the parsing information and the cache queue allocation strategy and waits for it to be sent. At the same time, the data acquisition module collects the feedback information of the current system load and the feedback information of the data transmission, and submits it to the policy executor. The executor cleans and streamlines the data in the queue according to the cache occupancy size of the current hierarchical priority queue, the message type and the collected feedback information, optimizes the cache occupancy space and adjusts the position of the data (message) in the cache.

[0087] According to the above implementation mode, by comprehensively considering multiple factors such as data type (telemetry, remote control, remote adjustment, etc.), data time sensitivity requirements (such as valid within 1 minute), data priority, data content type (such as structured data, binary data, etc.), data generation method (production by frequency, production by demand, etc.), operating system load, data transmission feedback, etc., the sender cache queue is dynamically configured and adjusted in real time to ensure that important data is stored in the cache queue and sent first, and ultimately optimize the 104 protocol data transmission efficiency based on the characteristics of high network latency, high packet loss rate, unstable bandwidth and a large number of devices (such as tens of thousands of devices in a city) in a weak network environment, and support reliable data transmission under large-scale device access and weak network conditions.

[0088] Figure 4It is a structural block diagram of a 104 protocol data-adaptive cache queue optimization device according to an embodiment of the present invention.

[0089] like Figure 4 As shown, the adaptive cache queue optimization device based on 104 protocol data includes: A data attribute determination module 410, for determining the data type, time sensitivity, data priority, data structure, data production method and data usage method of the first data based on the 104 protocol; A comprehensive priority determination module 420, configured to determine the comprehensive priority of the first data based on the data type, time sensitivity, data priority, data structure, data production method and data usage method of the first data; A queue merging module 430, configured to merge the plurality of first cache queues based on the data sending frequency of each of the plurality of first cache queues to obtain a merged queue; An insertion order determination module 440, configured to determine an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; A data inserting module 450, configured to insert the first data into the merge queue based on the insertion order of the first data, to obtain the merge queue after the data is inserted; A queue splitting module 460 is used to split the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain multiple split queues; A queue updating module 470, configured to update each of the first cache queues based on each of the split queues to obtain each updated first cache queue; The data sending module 480 is used to send the data in each updated first cache queue based on the 104 protocol and the data sending frequency of each updated first cache queue.

[0090] In one implementation, the queue merging module 430 includes: A first queue to be merged determining unit, configured to determine, based on the data sending frequencies of each of the first cache queues in the plurality of first cache queues, at least one second cache queue in which a mapping relationship exists between the data sending frequency and the comprehensive priority of the first data among the plurality of first cache queues; A first merging order determining unit, configured to determine a merging order of each of the second cache queues based on a data sending frequency of each of the second cache queues; The first merging unit is configured to merge the second cache queues based on a merging order of the second cache queues to obtain a merged queue.

[0091] In one implementation, the queue merging module 430 includes: a matching degree determining unit, configured to determine a matching degree between each of the first cache queues and the first data based on a data sending frequency of each of the first cache queues in a plurality of first cache queues and a time sensitivity of the first data; a second queue-to-be-merged determining unit, configured to determine at least one third cache queue from among the plurality of first cache queues based on a matching degree between each of the first cache queues and the first data; A second merging order determining unit, configured to determine a merging order of each of the third cache queues based on a data sending frequency of each of the third cache queues; The first merging unit is used to merge the third cache queues based on the merging order of the third cache queues to obtain a merged queue.

[0092] In one implementation, the arrangement order determination module includes: a percentage determination unit, configured to determine a ranking percentage of the first data based on a ratio between the comprehensive priority of the first data and a preset comprehensive priority upper limit; The sequence determination unit is used to determine the insertion sequence of the first data based on the product of the total number of arranged data in the merge queue and the sorting percentage of the first data.

[0093] In one embodiment, it further includes: a target queue length determination module, configured to determine a target queue length of each of the first cache queues based on a data insertion frequency of each of the first cache queues; A data cleaning module is used to clean up data on a fourth cache queue among the multiple first cache queues when the queue length of the fourth cache queue is greater than the target queue length of the fourth cache queue, so that the queue length of the fourth cache queue after data cleaning matches its target queue length.

[0094] In one implementation, the target queue length determination module includes: an adjustment coefficient determining unit, configured to determine an adjustment coefficient based on a data insertion frequency of the first cache queue; The length determining unit is used to determine a target queue length of the first cache queue based on a product of a data insertion frequency of the first cache queue and the adjustment coefficient, and a basic queue length corresponding to the first cache queue.

[0095] In one embodiment, the data cleaning module includes: A historical feedback data determining unit, configured to determine historical feedback data of the historical data corresponding to each of the second data in each of the fourth cache queues based on the attribute information of the second data; a comprehensive scoring unit, configured to determine a comprehensive score of each of the second data based on a load score of the operating system, a feedback score of the historical feedback data corresponding to each of the second data, and a dimension score of each of the information in the attribute information of each of the second data; A data cleaning unit is used to clean up the second data in the fourth cache queue whose comprehensive scores do not meet the preset comprehensive scoring conditions based on the comprehensive scores of each second data.

[0096] In one implementation, the queue splitting module 460 includes: a start and end data determining unit, configured to determine corresponding target start and end data in the merge queue after data insertion based on the start and end data of the first cache queue; The queue screenshot unit is used to intercept the queue from the target starting position data to the target last position data in the merged queue after the data is inserted, so as to obtain the split queue.

[0097] For the description of specific functions and examples of each module and submodule of the system in the embodiment of the present invention, reference can be made to the relevant description of the corresponding steps in the above method embodiment, which will not be repeated here.

[0098] In the technical solution of the present invention, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0099] According to an embodiment of the present invention, the present invention also provides a system and a readable storage medium.

[0100] Figure 5A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0101] like Figure 5 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0102] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0103] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a cache queue optimization method based on 104 protocol data adaptation. For example, in some embodiments, the cache queue optimization method based on 104 protocol data adaptation may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the cache queue optimization method based on 104 protocol data adaptation described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the adaptive cache queue optimization method based on the protocol data 104 in any other appropriate manner (eg, by means of firmware).

[0104] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0105] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0106] In the context of the present invention, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0107] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0108] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0109] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0110] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0111] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing cache queues based on 104 protocol data adaptively, characterized in that: include: Determine the data type, time sensitivity, data priority, data structure, and data production method of the first data based on the 104 protocol; Determining a comprehensive priority of the first data based on a data type, time sensitivity, data priority, data structure, and data production method of the first data; Based on the data sending frequency of each of the first cache queues in the plurality of first cache queues, the plurality of first cache queues are merged to obtain a merged queue; Determining an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; Inserting the first data into the merge queue based on the insertion order of the first data to obtain the merge queue after the data is inserted; Based on the start bit data and the end bit data of each of the first cache queues, the merged queue after the data is inserted is split to obtain a plurality of split queues; Based on each of the split queues, updating each of the first cache queues to obtain each updated first cache queue; Based on the 104 protocol and the updated data sending frequency of each of the first cache queues, the data in each of the updated first cache queues are sent respectively.

2. The method according to claim 1, characterized in that The step of merging the plurality of first cache queues based on the data sending frequency of each of the plurality of first cache queues to obtain a merged queue includes: Based on the data sending frequency of each of the first cache queues in the plurality of first cache queues, determining at least one second cache queue in the plurality of first cache queues having a mapping relationship between the data sending frequency and the comprehensive priority of the first data; Determining a merging order of each of the second cache queues based on a data sending frequency of each of the second cache queues; Based on the merging order of each of the second cache queues, each of the second cache queues is queue-merged to obtain a merged queue.

3. The method according to claim 1, characterized in that The step of merging the plurality of first cache queues based on the data sending frequency of each of the plurality of first cache queues to obtain a merged queue includes: Determining a matching degree between each of the first cache queues and the first data based on a data sending frequency of each of the first cache queues in the plurality of first cache queues and a time sensitivity of the first data; Based on the matching degree between each of the first cache queues and the first data, determining at least one third cache queue among the plurality of first cache queues; Determining a merging order of each of the third cache queues based on a data sending frequency of each of the third cache queues; Based on the merging order of each of the third cache queues, each of the third cache queues is queue-merged to obtain a merged queue.

4. The method according to claim 1, characterized in that: The determining the insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data includes: Determining a ranking percentage of the first data based on a ratio between the comprehensive priority of the first data and a preset comprehensive priority upper limit; An insertion order of the first data is determined based on a product of a total number of arranged data in the merge queue and a sorting percentage of the first data.

5. The method according to claim 1, characterized in that Also includes: Determining a target queue length of each of the first cache queues based on a data insertion frequency of each of the first cache queues; When the queue length of a fourth cache queue among the multiple first cache queues is greater than the target queue length of the fourth cache queue, data is cleaned up on the fourth cache queue so that the queue length of the fourth cache queue after data cleaning matches its target queue length.

6. The method according to claim 5, characterized in that The determining, based on the data insertion frequency of each of the first cache queues, a target queue length of each of the first cache queues includes: Determining an adjustment coefficient based on a data insertion frequency of the first cache queue; A target queue length of the first cache queue is determined based on a product of a data insertion frequency of the first cache queue and the adjustment coefficient, and a basic queue length corresponding to the first cache queue.

7. The method according to claim 5, characterized in that The clearing data from the fourth cache queue includes: Determine historical feedback data of the historical data corresponding to each of the second data in each of the fourth cache queues based on the attribute information of the second data; Determine the comprehensive score of each second data based on the load score of the operating system, the feedback score of the historical feedback data corresponding to each second data, and the dimension score of each information in the attribute information of each second data; Based on the comprehensive scores of each piece of second data, data cleaning is performed on the second data in the fourth cache queue whose comprehensive scores do not meet the preset comprehensive scoring conditions.

8. The method according to claim 1, characterized in that The method further comprises: splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues, including: Based on the start bit data and the end bit data of the first cache queue, determining the corresponding target start bit data and the target end bit data in the merge queue after the data is inserted; In the merged queue after the data is inserted, the queue from the target starting data to the target last data is intercepted to obtain the split queue.

9. A 104 protocol data-based adaptive cache queue optimization device, characterized in that: include: A data attribute determination module, for determining the data type, time sensitivity, data priority, data structure and data production method of the first data based on the 104 protocol; a comprehensive priority determination module, configured to determine the comprehensive priority of the first data based on the data type, time sensitivity, data priority, data structure and data production method of the first data; A queue merging module, configured to merge the plurality of first cache queues based on a data sending frequency of each of the plurality of first cache queues to obtain a merged queue; an insertion order determination module, configured to determine an insertion order of the first data based on the total amount of arranged data in the merge queue and the comprehensive priority of the first data; A data insertion module, used for inserting the first data into the merge queue based on the insertion order of the first data, to obtain the merge queue after the data is inserted; A queue splitting module, used for splitting the merged queue after the data is inserted based on the start bit data and the end bit data of each of the first cache queues to obtain a plurality of split queues; A queue updating module, configured to update each of the first cache queues based on each of the split queues to obtain each updated first cache queue; The data sending module is used to send the data in each updated first cache queue based on the 104 protocol and the data sending frequency of each updated first cache queue.

10. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

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