Device structure of semiconductor device, preparation method and electronic equipment

Abstract

The invention discloses a preparation method of a semiconductor device and electronic equipment, and the method comprises the steps: alternately stacking a plurality of insulating layers and metal layers on a substrate, and forming a laminated structure; forming a plurality of transistors arranged in a multilayer array in the laminated structure, wherein each transistor comprises a through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layers respectively cover the side walls of the first isolation layer and the second isolation layer to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular to a device structure, a preparation method and an electronic device of a semiconductor device. Background Art

[0002] 3D (3 Dimensions) memory is an emerging form of memory. It is a semiconductor memory device that accumulates layers based on stacking technology. Compared with planar memory, the storage density of 3D memory is increased, thereby reducing the production cost per GB (Gigabyte). Summary of the invention

[0003] The embodiment of the present application provides a device structure, a preparation method and an electronic device of a semiconductor device, which can realize 3D stacking and effectively improve the driving current. The technical solution is as follows:

[0004] In one aspect, a method for preparing a semiconductor device is provided, the method comprising:

[0005] Alternately stacking a plurality of insulating layers and metal layers on a substrate to form a laminated structure;

[0006] A plurality of transistors arranged in a multilayer array are formed in the stacked structure, and the transistors include a through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

[0007] In some embodiments, after forming the stacked structure, the method further comprises:

[0008] A capacitor is prepared on one side of the transistor in the stacked structure to form a semiconductor device, and the capacitor is connected to the transistor.

[0009] In some embodiments, forming a transistor in the stacked structure includes:

[0010] Depositing a protective layer on the surface of the stacked structure; removing the protective layer material on the surface of a specified area, wherein the specified area is related to the position of the transistor;

[0011] Etching the stacked structure to form a plurality of through holes;

[0012] Oxidizing the stacked structure so that the metal layer exposed on the inner wall of the through hole is oxidized to form the first isolation layer and the second isolation layer;

[0013] Depositing a channel material on the first isolation layer and the second isolation layer to form the first channel, the second channel, the third channel and the fourth channel;

[0014] Depositing a gate dielectric material on the first channel, the second channel, the third channel and the fourth channel to form a gate dielectric layer;

[0015] The through hole is etched to expose the insulating layer of the through hole, and a metal gate material is deposited on the gate dielectric layer to form a metal gate layer.

[0016] In some embodiments, etching the stacked structure to form the plurality of through holes comprises:

[0017] Etching the stacked structure in a direction perpendicular to the substrate to obtain a plurality of through holes;

[0018] The stacked structure is wet-etched to narrow the metal layers exposed in the plurality of through holes.

[0019] In some embodiments, after oxidizing the stacked structure so that the metal layer exposed on the inner wall of the through hole is oxidized and before depositing the channel material on the first isolation layer and the second isolation layer, the method further includes:

[0020] The oxidized metal layer in the through hole is etched so that the metal layer is exposed on the sidewall of the through hole except the first isolation layer and the second isolation layer in the through hole.

[0021] In some embodiments, after depositing the metal gate material on the gate dielectric layer, the method further comprises:

[0022] A trench structure is formed in the stacked structure; and an isolation material is filled in the through hole and the trench.

[0023] In some embodiments, the material of the channel layer is a metal oxide semiconductor material.

[0024] In another aspect, a semiconductor device is provided, comprising:

[0025] Substrate and laminate structure;

[0026] The stacked structure is located on the substrate; the stacked structure comprises:

[0027] A plurality of memory cell arrays stacked in a direction perpendicular to the substrate and a plurality of bit lines extending in a first direction parallel to the substrate, each layer of the memory cell array comprising a plurality of memory cells arranged in an array, each of the bit lines being connected to at least one column of the memory cells arranged in the first direction; wherein each of the memory cells comprises a transistor;

[0028] The transistor includes: a through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

[0029] In some embodiments, the storage unit further includes: a capacitor;

[0030] The capacitor is connected to an end of the transistor in the memory cell away from the bit line.

[0031] In some embodiments, along a column of the memory cells arranged perpendicular to the substrate, the gates of the transistors are connected to form a word line.

[0032] In some embodiments, two columns of memory cells arranged along the first direction and adjacent to each other along a second direction parallel to the substrate share one bit line, wherein the first direction intersects the second direction.

[0033] In another aspect, a transistor is provided, the transistor comprising:

[0034] A through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer;

[0035] The first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

[0036] In some embodiments, the material of the channel layer is a metal oxide semiconductor material.

[0037] In one aspect, an electronic device is provided, wherein the electronic device comprises a memory device, and the memory device comprises a semiconductor device manufactured according to any of the above-mentioned methods for manufacturing a semiconductor device.

[0038] In some embodiments, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

[0039] The beneficial effects brought by the technical solution provided in the embodiments of the present application include at least:

[0040] It is possible to prepare a semiconductor device with multiple channels and a stacked arrangement, that is, a 3D memory, which can improve the driving current of the memory. Moreover, the three-dimensional stacking design increases the storage density of the 3D memory and reduces the production cost per GB. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 is a schematic diagram of a semiconductor device and a transistor provided by an exemplary embodiment of the present application;

[0043] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an exemplary embodiment of the present application;

[0044] Figure 3 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0045] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an exemplary embodiment of the present application;

[0046] Figure 5 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0047] Figure 6 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0048] Figure 7 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0049] Figure 8 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0050] Fig. 9 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0051] Fig.10 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0052] Fig.11 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0053] Fig.12 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0054] Fig.13 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0055] Fig.14 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0056] Fig.15 is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application;

[0057] Fig.16 It is a schematic diagram of relevant steps in the preparation process provided by the exemplary embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0059] The present application embodiment provides a semiconductor device, referring to Figure 1 , Figure 1 Figure (A) shows the structure of a semiconductor device, which includes a substrate 100 and a stacked structure 101, the stacked structure 101 is located on the substrate 100, and the stacked structure 101 includes: a plurality of memory cell arrays stacked in a direction perpendicular to the substrate and a plurality of bit lines 102 extending in a first direction parallel to the substrate, the first direction is parallel to the upper surface of the substrate 100, each layer of the memory cell array includes a plurality of memory cells 103 arranged in an array, and each bit line 102 is connected to at least one column of memory cells 103 arranged in the first direction; wherein each memory cell 103 includes a transistor 104; Figure 1 Taking the enlarged top view of the memory cell 103 in part (A) as an example, referring to FIG. (B), the transistor 104 in the memory cell 103 includes:

[0060] A through hole 105, a first isolation layer 106, a second isolation layer 107, a channel layer 108, a gate dielectric layer 109 and a metal gate layer 110; the first isolation layer 106 and the second isolation layer 107 are located on two opposite side walls of the through hole 105, and the channel layer 108 covers the side walls of the first isolation layer 106 and the second isolation layer 107 respectively to form a first channel 111, a second channel 112, a third channel 113 and a fourth channel 114; the gate dielectric layer 109 covers the channel layer 108; and the metal gate layer 110 covers the gate dielectric layer 109.

[0061] In the process of constructing the transistor 104, since the sidewalls of the through hole 105 other than the first isolation layer 106 and the second isolation layer 107 are embedded in the stacked structure 101, such parts cannot be observed in the enlarged top view (B), and only the sidewalls of the through hole 105 where the first isolation layer 106 and the second isolation layer 107 are located can be observed;

[0062] Wherein, the storage unit further includes: a capacitor 115;

[0063] The capacitor 115 is connected to an end of the transistor 104 in the memory cell 103 that is away from the bit line 102 .

[0064] Among them, in a column of storage cells 103 arranged vertically to the substrate 100, the gates of the transistors 104 are connected to form a word line, and the metal gate layer 110 serves as the word line, that is, the switch of the transistor 104, to connect the transistors 104 in the same string; the bit line 102 serves as the data signal write line to connect the transistors 104 in the same string.

[0065] Two columns of memory cells 103 arranged along a first direction and adjacent to each other along a second direction parallel to the substrate 100 share a bit line, wherein the first direction intersects the second direction.

[0066] The material used for the channel layer 108 in the transistor 104 is a metal oxide semiconductor material. The material of the metal oxide may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 104 is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO (Indium Gallium Oxide), IZO (IndiumZinc Oxide), IZOx and other materials, as long as the leakage current of the transistor 104 can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0067] In an embodiment of the present application, a method for preparing a semiconductor device is provided. Optionally, the method for preparing a semiconductor device is mainly used in a preparation process of a 3D memory.

[0068] Combined with the above introduction to semiconductor devices, Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes the following steps.

[0069] Step 201 , alternately stacking a plurality of insulating layers and metal layers on a substrate to form a stacked structure.

[0070] The bottom insulating layer is in contact with the substrate. By stacking transistors on the substrate, the device area can be reduced and the device density can be increased, making 3D memory possible.

[0071] Combined with reference Figure 3 , Figure 3 (A1) shows that a first insulating layer 301, a first metal layer 302, a second insulating layer 303, a second metal layer 304, a third insulating layer 305 and a third metal layer 306 are sequentially stacked on a substrate 300. Optionally, the first direction is a bit line direction. Figure 3 (A2) shows a two-dimensional cross-sectional view of the stacked structure observed along the first direction.

[0072] It should be noted that the above Figure 3 This is only a schematic diagram of a multi-layer stack. In some embodiments, the specific number of stacked layers is determined based on the device design.

[0073] Step 202, forming a plurality of transistors arranged in a multilayer array in the stacked structure, the transistor comprising a through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite side walls of the through hole; the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; the metal gate layer covers the gate dielectric layer.

[0074] In some embodiments, the layers in the transistor are in a surrounding relationship, wherein the first isolation layer and the second isolation layer are consistent in structure and material. Since each isolation layer has two side walls, the entire transistor has four side walls, that is, when a channel layer is formed on the side wall, four channels can be obtained. Furthermore, subsequent gate dielectric layers and metal gate layers are also formed in sequence by covering the outside of the channel layer where the four channels are located.

[0075] Combined with reference Figure 1 , Figure 1Part (B) shows the structure of the transistor as viewed in the vertical direction.

[0076] The method provided in the embodiment of the present application can prepare a semiconductor device with multiple channels and a stacked arrangement, that is, a 3D memory, which can improve the driving current of the memory. Moreover, the three-dimensional stacking design realizes an increase in the storage density of the 3D memory and reduces the production cost per GB.

[0077] Figure 4 1 is a flow chart of a method for preparing a semiconductor device provided by an exemplary embodiment of the present application, the method comprising:

[0078] Step 401 , alternately stacking a plurality of insulating layers and metal layers on a substrate to form a stacked structure.

[0079] The above-mentioned alternating stacking means first stacking an insulating layer on the substrate and then stacking a metal layer, and the stacking of the metal layer and the insulating layer is performed alternately so that a metal layer is stacked between every two insulating layers, and the top layer of the stacked structure is a metal layer.

[0080] In some embodiments, based on oxidation characteristics, easily oxidized metals such as Ti (titanium), Mo (molybdenum), and Ta (tantalum) may be selected in the metal layer.

[0081] Combined with reference Figure 3 , Figure 3 (A1) shows a three-dimensional structure diagram of a first insulating layer 301, a first metal layer 302, a second insulating layer 303, a second metal layer 304, a third insulating layer 305 and a third metal layer 306 stacked in sequence on a substrate. Optionally, the first direction is a bit line direction, Figure 3 (A2) shows a two-dimensional plan view of the (A1) structure observed along the first direction.

[0082] Step 402: depositing a protective layer material on the surface of the stacked structure.

[0083] In some embodiments, the material of the protective layer may be Nitride (titanium nitride). The material of the protective layer may also be other substances that do not react with the metal stack. The selection of the material of the protective layer is not limited in the embodiments of the present application.

[0084] In some embodiments, the surface of the stacked structure is covered with a protective layer material by an ALD (Atomic Layer Deposition) process or a chemical vapor deposition technique.

[0085] Combined with reference Figure 5 , Figure 5 (A1) shows a three-dimensional structural diagram of a stacked structure on which a protective layer material 500 is deposited. Figure 5 (A2) shows a two-dimensional plan view of the (A1) structure observed along the first direction.

[0086] Step 403, removing the protective layer material on the surface of a designated area, where the designated area is related to the position of the transistor.

[0087] The designated area is used to prepare transistors, and the area is in the shape of a long strip, the width of the strip matches the width of the transistor, and the length of the strip is consistent with the width of the stacked structure.

[0088] In some embodiments, based on the photolithography process, the protective layer material on the surface of the designated area is removed according to the size required by the transistor. The number of designated areas is determined based on the preparation requirements, and the embodiments of the present application do not limit this.

[0089] Combined with reference Figure 6 , Figure 6 (A1) shows a three-dimensional structural diagram of the stacked structure without the surface protection layer material of the designated area 600. Figure 6 (A2) shows a two-dimensional plan view of the (A1) structure observed along the first direction.

[0090] Step 404, etching the stacked structure in a direction perpendicular to the substrate to obtain a plurality of through holes.

[0091] Wherein, based on the dry etching process, the stacked structure is etched in a designated area to obtain through holes, and the widths of the multiple through holes are consistent from top to bottom.

[0092] In some embodiments, a size of the via in a direction perpendicular to the substrate matches a size of the transistor.

[0093] Combined with reference Figure 7 , Figure 7 (A1) shows a three-dimensional schematic diagram of a stacked structure with the same stack width of through holes 700, wherein 300 is a substrate. Optionally, the vertical direction is the word line direction, Figure 7 (A2) shows a two-dimensional top view of the (A1) structure observed along the vertical direction, wherein, during the construction of the transistor, since the side walls of the through hole 700 other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (A2), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0094] Step 405 , wet-etching the stacked structure to narrow the metal layers exposed in the plurality of through holes.

[0095] Among them, based on the isotropy of wet etching, the width of the lateral etching of the metal layer can be close to the depth of the longitudinal etching, so that the metal layer in the stacked structure is uniformly narrowed.

[0096] It can be understood that after the etching operation is performed, a through-hole structure for forming a transistor can be observed along the vertical direction.

[0097] Combined with reference Figure 8 , Figure 8 (A1) shows a three-dimensional structure diagram after etching the stacked structure in the vertical direction. Figure 8 (A2) shows a two-dimensional top view of the (A1) structure observed along the vertical direction, wherein, during the construction of the transistor, since the side walls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (A2), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0098] As can be seen from the top view, the width of the metal layer 801 in the through hole is smaller than the width of the insulating layer 802 .

[0099] Step 406 , oxidizing the stacked structure so that the metal layer exposed on the inner wall of the through hole is oxidized to form a first isolation layer and a second isolation layer.

[0100] Among them, the through hole is exposed outside the protective layer, so through oxidation treatment, the metal layer of the through hole can form metal oxide to form a first isolation layer and a second isolation layer. The metal oxide is an insulator and can isolate the channel layer materials subsequently deposited on both sides to form a multi-channel semiconductor device.

[0101] Among them, based on the anodizing process, the oxidation treatment can be achieved by utilizing the electrochemical principle to generate metal oxides.

[0102] In some embodiments, Ti (titanium), Mo (molybdenum), or Ta (tantalum) may be selected based on the metal in the metal layer. Accordingly, the oxide produced after oxidation may be TiO x (titanium oxide), MoO x (Molybdenum oxide), TaO x (Tantalum oxide), these metal oxides act as insulators and are used to provide support.

[0103] Combined with reference Fig. 9 , Fig. 9 (A1) shows a three-dimensional structural diagram of a stacked structure of a metal oxide layer 900 obtained after oxidizing the metal layer. Fig. 9(A2) shows a two-dimensional top view of the (A1) structure observed along the vertical direction, wherein, during the construction of the transistor, since the side walls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (A2), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0104] In addition, after the oxidation step, an etching process is performed before depositing the channel material to etch the oxidized metal layer in the through hole, so that the side walls of the through hole except the first isolation layer and the second isolation layer in the through hole are exposed to the metal layer, and one side of the exposed metal layer is used to connect the bit line, and the other side is used to connect the capacitor, so that the metal layer can be in good contact with the bit line and the capacitor.

[0105] Step 407 , depositing a channel material on the first isolation layer and the second isolation layer to form a first channel, a second channel, a third channel, and a fourth channel.

[0106] In some embodiments, the channel material is generally selected from metal oxide semiconductor materials with high electrical stability to maintain the electrical performance of the device during the stacking process, wherein the first channel, the second channel, the third channel and the fourth channel are composed of IGZO (Indium Gallium Zinc Oxide).

[0107] In some embodiments, the channel material is deposited on the surface of the through hole by an ALD (Atomic Layer Deposition) process or a chemical vapor deposition technique.

[0108] Combined with reference Fig.10 , Fig.10 (A1) shows a three-dimensional structural diagram of the stacked structure after the channel material 1000 is deposited. Fig.10 (A2) shows a two-dimensional top view of (A1) observed along the vertical direction. Fig.10 (A3) is Fig.10 The enlarged view of the portion 1001 in (A2) shows the first channel 1002, the second channel 1003, the third channel 1004, the fourth channel 1005, the first isolation layer 1006 and the second isolation layer 1007, wherein the materials used for the four channels are all channel material 1000. In the process of constructing the transistor, since the side walls of the through hole except the first isolation layer and the second isolation layer are embedded in the stacked structure, such parts cannot be observed in the top view (A2) and the enlarged top view (A3), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0109] Step 408 , depositing a gate dielectric material on the first channel, the second channel, the third channel, and the fourth channel to form a gate dielectric layer.

[0110] The gate dielectric material is a high-K material, which is used as a dielectric between the first channel, the second channel, the third channel and the fourth channel in the transistor and the connected gate.

[0111] In some embodiments, the channel material is deposited on the surface of the through hole by an ALD (Atomic Layer Deposition) process or a chemical vapor deposition technique.

[0112] Combined with reference Fig.11 , Fig.11 (A1) shows a three-dimensional structural diagram of the stacked structure after the gate dielectric material 1100 is deposited. Fig.11 (A2) shows a two-dimensional top view of the (A1) structure observed along the vertical direction. Fig.11 (A3) is Fig.11 The enlarged view of the portion 1101 in (A2) shows the gate dielectric material 1100 covering the channel layer to form a gate dielectric layer, wherein, during the construction of the transistor, since the side walls of the through hole except the first isolation layer and the second isolation layer are embedded in the stacked structure, this portion cannot be observed in the top view (A2) and the enlarged top view (A3), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0113] Step 409 , etching the through hole to expose the insulating layer of the through hole, and depositing a metal gate material on the gate dielectric layer to form a metal gate layer.

[0114] In some embodiments, the protruding portion on the inner sidewall of the through hole is etched so that the sidewall in the through hole exposes the insulating layer. In particular, since the wet etching makes the metal layer narrower, the first isolation layer and the second isolation layer formed by oxidation are narrower than the insulating layer, so there will be a protruding portion at the position where the insulating layer is located in the through hole. After the channel material and the gate dielectric material are deposited, the channel material and the gate dielectric material will also be deposited on the protruding portion of the insulating layer. The protruding portion is etched to expose the insulating layer, and the channel material deposited on the protruding portion can be removed. The exposed insulating layer is used to separate the channel material in the through hole. The etching operation is used to remove parasitic MOS (MOSFET, metal-oxide semiconductor field effect transistor) in the vertical direction.

[0115] Combined with reference Fig.12 , Fig.12 (A1) shows a three-dimensional structural diagram of the stacked structure after etching the protruding insulating layer. Fig.12(A2) shows a two-dimensional top view of (A1) observed along the vertical direction, wherein 1100 is still the gate dielectric material, Fig.12 (A3) is Fig.12 The enlarged view of the 1200 portion in (A2) shows the three-dimensional structure of the through hole after etching the protruding insulating layer, wherein, in the process of constructing the transistor, since the side walls of the through hole except the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (A2) and the enlarged top view (A3), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0116] A metal gate material is further deposited on the outer layer of the original gate dielectric material to form a metal gate layer, and the gates formed by the metal gate layer in the same through hole are connected to form a word line. Optionally, the deposition of the metal gate material is achieved by an ALD process.

[0117] Combined with reference Fig.13 , Fig.13 (A1) shows a three-dimensional structural diagram of the stacked structure after depositing the metal gate material. Fig.13 (A2) shows a two-dimensional top view of (A1) observed along the vertical direction. Fig.13 (A3) is Fig.13 The enlarged view of the portion 1300 in (A2) shows the metal gate material 1301 covering the gate dielectric layer to form a metal gate layer, wherein, in the process of constructing the transistor, since the side walls of the through hole except the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (A2) and the enlarged top view (A3), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0118] Step 410 , forming a trench structure in the stacked structure after the metal gate layer is deposited.

[0119] In some embodiments, a stacked structure between two transistors arranged in a horizontal direction is etched, wherein the stacked structure between the two transistors includes a stacked structure between two transistors in a first region and a second region, to obtain a trench structure.

[0120] The trench is filled with oxide to insulate adjacent transistors.

[0121] Combined with reference Fig.14 , Fig.14 (A1) shows a three-dimensional structure diagram after etching the stacked structure, wherein 1400 is the formed groove structure. Fig.14(A2) shows a two-dimensional top view of the (A1) structure observed along the vertical direction, wherein, during the construction of the transistor, since the side walls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (A2), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0122] Step 411 , filling the through holes and trenches with isolation materials.

[0123] The isolation material used for filling has insulating properties and is used to support the through-hole structure of the transistor.

[0124] Combined with reference Fig.15 , Fig.15 (A) shows a three-dimensional structural diagram of the stacked structure after the isolation material 1500 is filled and polished. It can be seen from the figure that the unetched part of the stacked structure still has a protective layer 500. Fig.15 (B) shows a two-dimensional top view of the (A) structure observed along the vertical direction, wherein, during the construction of the transistor, since the side walls of the through hole other than the first isolation layer and the second isolation layer are embedded in the interior of the stacked structure, this part cannot be observed in the top view (B), and only the side walls of the through hole where the first isolation layer and the second isolation layer are located can be observed.

[0125] Step 412, removing the remaining protective layer on the surface of the laminated structure.

[0126] In some embodiments, the residual protective layer material on the surface of the stacked structure is etched away by a dry etching process.

[0127] The protective layer is used to protect the part of the stacked structure that does not need to be etched to avoid being damaged during the etching process. In addition, the protective layer can also protect the metal layer under this layer to avoid being oxidized during the oxidation process.

[0128] Combined with reference Fig.16 , Fig.16 The three-dimensional structure diagram of the stacked structure after removing the protective layer is shown. It can be seen from the figure that after removing the protective layer, the top third metal layer 306 is exposed.

[0129] Step 413, preparing a capacitor on one side of the transistor in the stacked structure to form a semiconductor device, wherein the capacitor is connected to the transistor.

[0130] In some embodiments, after any of the above etching or filling steps, a CMP (Chemical Mechanical Polishing) process may be used to perform a flattening operation to ensure the smoothness of the stacked structure, thereby ensuring the airtightness of the device.

[0131] Combined with reference Figure 1 , Figure 1 (A) shows a three-dimensional structure diagram of a semiconductor device. The example in the figure shows that four transistor strings are prepared at one time. Therefore, it can be seen that capacitors 115 are added on both sides, that is, capacitors are added on one side of each transistor. In some embodiments, the method of adding capacitors matches the preparation requirements.

[0132] The method provided in the embodiment of the present application can prepare a semiconductor device that maintains electrical stability, that is, a 3D memory. Based on the method of simultaneously preparing multiple transistors, a multi-channel memory is obtained, which can increase the current of the driving current. In addition, IGZO has the characteristics of an amorphous substance. It is selected as the channel material with a stable process, and more layers can be stacked while maintaining stable electrical properties. In addition, the three-dimensional stacking design realizes an increase in the storage density of the 3D memory and reduces the production cost per GB.

[0133] On the other hand, an electronic device is provided, wherein the electronic device includes a logic device, wherein the logic device includes the semiconductor device provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc.

[0134] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

[0135] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.

[0136] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0137] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: Alternately stacking a plurality of insulating layers and metal layers on a substrate to form a laminated structure; A plurality of transistors arranged in a multilayer array are formed in the stacked structure, and the transistors include a through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

2. The method according to claim 1, characterized in that After forming the stacked structure, the method further comprises: A capacitor is prepared on one side of the transistor in the stacked structure to form a semiconductor device, and the capacitor is connected to the transistor.

3. The method according to claim 1, characterized in that The forming of a transistor in the stacked structure comprises: Depositing a protective layer on the surface of the stacked structure; removing the protective layer material on the surface of a specified area, wherein the specified area is related to the position of the transistor; Etching the stacked structure to form a plurality of through holes; Oxidizing the stacked structure so that the metal layer exposed on the inner wall of the through hole is oxidized to form the first isolation layer and the second isolation layer; Depositing a channel material on the first isolation layer and the second isolation layer to form the first channel, the second channel, the third channel and the fourth channel; Depositing a gate dielectric material on the first channel, the second channel, the third channel and the fourth channel to form a gate dielectric layer; The through hole is etched to expose the insulating layer of the through hole, and a metal gate material is deposited on the gate dielectric layer to form a metal gate layer.

4. The method according to claim 3, characterized in that The etching of the stacked structure to form a plurality of through holes comprises: Etching the stacked structure in a direction perpendicular to the substrate to obtain a plurality of through holes; The stacked structure is wet-etched to narrow the metal layers exposed in the plurality of through holes.

5. The method according to claim 3, characterized in that: After oxidizing the stacked structure to oxidize the metal layer exposed on the inner wall of the through hole and before depositing the channel material on the first isolation layer and the second isolation layer, the method further includes: The oxidized metal layer in the through hole is etched so that the metal layer is exposed on the sidewall of the through hole except the first isolation layer and the second isolation layer in the through hole.

6. The method according to claim 3, characterized in that After depositing a metal gate material on the gate dielectric layer, the method further comprises: A trench structure is formed in the stacked structure; and an isolation material is filled in the through hole and the trench.

7. The method according to claim 1, characterized in that The material of the channel layer is a metal oxide semiconductor material.

8. A semiconductor device, characterized in that: include: Substrate and laminate structure; The stacked structure is located on the substrate; The laminated structure comprises: A plurality of memory cell arrays stacked in a direction perpendicular to the substrate and a plurality of bit lines extending in a first direction parallel to the substrate, each layer of the memory cell array comprising a plurality of memory cells arranged in an array, each of the bit lines being connected to at least one column of the memory cells arranged in the first direction; wherein each of the memory cells comprises a transistor; The transistor includes: a through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

9. The semiconductor device according to claim 8, characterized in that The storage unit also includes: capacitance; The capacitor is connected to an end of the transistor in the memory cell away from the bit line.

10. The semiconductor device according to claim 8, characterized in that In a column of the memory cells arranged vertically to the substrate, the gates of the transistors are connected to form a word line.

11. The semiconductor device according to claim 8, characterized in that Two columns of memory cells arranged along the first direction and adjacent to each other along a second direction parallel to the substrate share one bit line, wherein the first direction intersects the second direction.

12. A transistor, characterized in that: include: A through hole, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer, and a metal gate layer; The first isolation layer and the second isolation layer are located on two opposite side walls of the through hole, and the channel layer covers the side walls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

13. The transistor according to claim 12, characterized in that The material of the channel layer is a metal oxide semiconductor material.

14. An electronic device, characterized in that: The electronic device comprises a memory device, and the memory device comprises a semiconductor device manufactured according to the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

15. The electronic device according to claim 14, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

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