Semiconductor device and preparation method thereof
By introducing carbon dopants and silicon materials into the bit line structure of DRAM devices, the problem of embedded bit lines degradation at high temperatures is solved, and the thermal stability and performance of semiconductor devices are significantly improved.
Patent Information
- Application Number
- CN202411721894.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-11
AI Technical Summary
In a vertical transistor architecture, embedded bit lines are prone to deterioration in high-temperature oxidation processes and capacitive annealing heat treatment, affecting the performance of DRAM devices.
A bit line structure of a semiconductor device is designed, including a first portion and a second portion, the first portion consisting of silicide and carbon dopant, and the second portion consisting of silicon. This structure improves thermal stability through carbon dopants, reduces the adverse effects of high temperature on the bit lines, and facilitates the epitaxial growth of subsequent film layers through silicon material.
It effectively reduces the degradation of the bit line structure and improves the thermal stability and performance of semiconductor devices.
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Figure CN119815828A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Some DRAM devices use vertical transistors. However, in this architecture, the buried bit line is formed before the gate stack is deposited and the capacitor is annealed. It must withstand the heat of the gate high-temperature oxidation process and the capacitor annealing heat treatment, which can easily cause the bit line to degrade and thus affect the performance of the DRAM device. Summary of the invention
[0003] The purpose of this application is to at least solve the problem of poor performance of semiconductor devices. This purpose is achieved through the following technical solutions:
[0004] The first aspect of the present application provides a semiconductor device, comprising:
[0005] substrate;
[0006] A bit line structure is formed on the substrate, the bit line structure includes a first part and a second part, the second part is located on a side of the first part away from the substrate, the first part includes silicide and carbon dopant, and the second part includes silicon.
[0007] In the semiconductor device provided by the present application, a bit line structure is formed on a substrate, and the bit line structure includes a first part and a second part, the first part includes silicide and carbon dopant, the carbon dopant is located inside the first part and / or on the surface of the first part, and the carbon dopant makes the thermal stability of the first part higher, thereby reducing the adverse effect of high temperature on the bit line structure during the preparation of subsequent film layers, and reducing the degradation of the bit line structure. The material of the second part includes silicon, and does not include carbon dopant and silicide, so that it is convenient to continue epitaxial growth of subsequent film layers. The bit line of the semiconductor device is not easy to degrade after being heated, and the performance is significantly improved.
[0008] The second aspect of the present application also provides a method for preparing a semiconductor device, comprising:
[0009] providing a semiconductor substrate;
[0010] Patterning the semiconductor substrate to form a substrate and a bit line forming portion located at one side of the substrate, wherein the bit line forming portion includes a first forming portion and a second forming portion located at a side of the first forming portion away from the substrate;
[0011] forming a protective structure on a surface of the second forming portion facing away from the semiconductor substrate and on a side surface of the second forming portion;
[0012] forming a carbon structure layer, the carbon structure layer at least in contact with a side surface of the first molded portion, the carbon structure layer including a contact surface in contact with the first molded portion;
[0013] forming a bit line metal layer, wherein the bit line metal layer is in contact with at least one side of the contact surface facing away from the first forming portion;
[0014] The bit line forming part is thermally treated so that the first forming part becomes a first portion and the second forming part becomes a second portion, the first portion includes silicide and carbon dopant, and the second portion includes silicon. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0016] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;
[0017] Figure 2 A top view of a semiconductor device provided in an embodiment of the present application;
[0018] Figure 3 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;
[0019] Figure 4 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;
[0020] Figures 5 to 9 A schematic diagram of film layer changes during the preparation process of a semiconductor device provided in an embodiment of the present application.
[0021] The reference numerals are as follows:
[0022] 1. Semiconductor device; 11. Substrate; 12. Bit line structure; 121. First part; 122. Second part; 13. Isolation layer; 14. Transistor; 141. Source region; 142. Drain region; 143. Channel region; 15. Barrier layer; 16. Semiconductor substrate; 17. Bit line forming part; 171. First forming part; 172. Second forming part; 173. Isolation forming part; 18. Protection structure; 19. Carbon structure layer; 20. Bit line metal layer; 21. Capacitor. DETAILED DESCRIPTION
[0023] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0024] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.
[0025] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.
[0026] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.
[0027] It has been found that in the past few decades, the advancement of lithography technology has been one of the main driving forces for the aggressive miniaturization of dynamic random access memory (DRAM). However, due to the lack of lithography tools that can provide reasonable costs and high yields, miniaturization technology has become increasingly difficult to maintain its trend. In order to circumvent patterning problems and continue to reduce chip size, it has been proposed to use a cell architecture that replaces traditional horizontal transistors with vertical transistors to achieve further expansion of DRAM technology. However, in this architecture, the buried bit line is formed before the deposition of the gate stack and capacitor annealing, and it is bound to withstand the heat of the gate high temperature oxidation process and the capacitor annealing heat treatment, which can easily cause the degradation of the bit line, thereby affecting the performance of the DRAM device. Therefore, the present application provides a semiconductor device and a method for preparing the same to improve the performance of the semiconductor device.
[0028] like Figure 1 As shown, according to an embodiment of the present application, a semiconductor device 1 is proposed, including a substrate 11 and a bit line structure 12, the bit line structure 12 is formed on the substrate 11, the bit line structure 12 includes a first part 121 and a second part 122, the second part 122 is located on the side of the first part 121 away from the substrate 11, the first part 121 includes silicide and carbon dopants, and the second part 122 includes silicide.
[0029] In the semiconductor device 1 provided in the present application, the bit line structure 12 is formed on the substrate 11, and the bit line structure 12 includes a first part 121 and a second part 122. The first part 121 includes silicide and carbon dopants. The carbon dopants are located inside the first part 121 and / or on the surface of the first part 121. The carbon dopants make the thermal stability of the first part 121 higher, thereby reducing the adverse effects of high temperature on the bit line structure 12 during the preparation of subsequent film layers, and reducing the degradation of the bit line structure 12. The material of the second part 122 includes silicon, and does not include carbon dopants and silicides, so that it is convenient to continue epitaxial growth of subsequent film layers. The bit line structure 12 of the semiconductor device 1 is not easy to degrade after being heated, and the thermal stability is greatly improved, so that the performance of the semiconductor device 1 is significantly improved.
[0030] Specifically, the substrate 11 may include a silicon material or a silicon germanium material doped with N-type ions.
[0031] Specifically, Figure 2 As shown, the bit line structure 12 may be a strip structure extending in a direction perpendicular to the thickness of the substrate 11 .
[0032] In a possible implementation, Figure 1 As shown, an isolation layer 13 is also included. The isolation layer 13 is located between the bit line structure 12 and the substrate 11 .
[0033] In the above embodiment, by forming an isolation layer 13 between the bit line structure 12 and the substrate 11, the isolation between the bit line structure 12 and the substrate 11 can be achieved. The isolation layer 13 is used to protect the substrate 11 and prevent the bit line structure 12 from causing adverse effects on the substrate 11 during the preparation process.
[0034] In a possible implementation, Figure 1 As shown, there are multiple bit line structures 12 , which are arranged at intervals, and there are multiple isolation layers 13 , which correspond to the bit line structures 12 one by one.
[0035] In the above embodiment, the semiconductor device 1 may include a plurality of bit line structures 12, and the plurality of bit line structures 12 are arranged at intervals on the substrate 11 to avoid mutual interference. There are a plurality of isolation layers 13, and the isolation layer 13 and the substrate 11 may be made of the same material, and the isolation layer 13, the substrate 11, and the bit line structure 12 may be an integrated structure.
[0036] The isolation layers 13 correspond to the bit line structures 12 one by one. On the one hand, each bit line structure 12 is isolated from the substrate 11, thereby reducing the adverse effects of each bit line on the substrate 11 during the preparation process. On the other hand, multiple isolation layers 13 are arranged at intervals to isolate adjacent isolation layers 13, thereby preventing the bit line structures 12 corresponding to adjacent isolation layers 13 from affecting each other.
[0037] In a possible implementation, Figure 3 As shown, the semiconductor device 1 also includes a transistor 14, which includes a source region 141, a drain region 142 and a channel region 143. The source region 141 is integrally formed with the bit line structure 12, the channel region 143 is located on the side of the second portion 122 away from the substrate 11 and the channel region 143 is in contact with the second portion 122, and the drain region 142 is located on the side of the channel region 143 away from the substrate 11.
[0038] In the above embodiment, the transistor 14 is a vertical transistor 14, including a source region 141, a channel region 143 and a drain region 142 formed on the substrate 11, wherein the source region 141 and the bit line structure 12 may be an integrally formed one-piece structure, that is, the bit line structure 12 and the source region 141 are reused. The channel region 143 is located on the side of the bit line structure 12 away from the substrate 11, and is in contact with the second portion 122 in the bit line structure 12. Since the second portion 122 includes silicon, the channel region 143 and the drain region 142 may be epitaxially grown above the second portion 122.
[0039] Specifically, the semiconductor device 1 may be a storage semiconductor device 1, and may include a transistor 14 and a capacitor 21 connected to the transistor 14. The transistor 14 further includes a gate, and the gate may be arranged around the channel region 143. The semiconductor device 1 further includes a word line, and the word line is connected to the gate. A high-temperature oxidation process is used in the preparation process of the gate, and the first part 121 of the bit line structure 12 includes silicide and carbon dopants. The carbon dopants make the first part 121 have a higher thermal stability, thereby reducing the adverse effect of the high temperature of the gate during the preparation process on the bit line structure 12.
[0040] The capacitor 21 in the semiconductor device 1 is formed on the side of the drain region 142 facing away from the substrate 11. The capacitor 21 uses an annealing process. The first portion 121 of the bit line structure 12 includes silicide and carbon dopants. The carbon dopants make the first portion 121 have higher thermal stability, thereby reducing the adverse effects of high temperature of the gate during the preparation process on the bit line structure 12.
[0041] In a possible implementation, Figure 3 As shown, the semiconductor device 1 further includes a barrier layer 15 located on the substrate 11 . The barrier layer 15 is disposed adjacent to the isolation layer 13 , and the barrier layer 15 contacts the sidewall of the isolation layer 13 . The barrier layer 15 and the isolation layer 13 have the same thickness.
[0042] In the above embodiment, the semiconductor device 1 further includes a barrier layer 15, which is used to cover the area of the substrate 11 where the bit line structure 12 is not set, so as to prevent the bit line structure 12 from causing adverse effects on the area of the substrate 11 not covered by the bit line structure 12 during the preparation process.
[0043] The present application also provides a method for preparing a semiconductor device 1, such as Figure 4 As shown, including:
[0044] S200, such as Figure 5 As shown, a semiconductor substrate 16 is provided.
[0045] Specifically, the semiconductor substrate 16 includes a base, and the base includes silicon, germanium, or a silicon-germanium alloy, etc. N-type impurities are implanted into the base and activated to form the semiconductor substrate 16. The N-type impurities can be implanted into the base by an ion implantation process or an in-situ doping process, wherein the ion implantation process includes but is not limited to advanced ion implantation processes such as cold implantation.
[0046] S400, such as Figure 6 As shown, the semiconductor substrate 16 is patterned to form a substrate 11 and a bit line forming part 17 located on one side of the substrate 11 . The bit line forming part 17 includes a first forming part 171 and a second forming part 172 located on a side of the first forming part 171 away from the substrate 11 .
[0047] Specifically, the semiconductor substrate 16 may be patterned by a photolithography process. The bit line forming portion 17 may be a stripe structure extending in a direction perpendicular to the thickness direction of the substrate 11 .
[0048] S600, such as Figure 7 As shown, a protection structure 18 is formed on a surface of the second formed portion 172 facing away from the semiconductor substrate 11 and on a side surface of the second formed portion 172 .
[0049] Specifically, the first forming part 171 is used to form the first portion 121 of the bit line structure 12, and the second forming part 172 is used to form the second portion 122 of the bit line structure 12. The protection structure 18 is used to protect the second forming part 172 to prevent the subsequent preparation process of the first forming part 171 from affecting it.
[0050] S800, such as Figure 8 As shown, a carbon structure layer 19 is formed, and the carbon structure layer 19 at least contacts the side surface of the first molded portion 171 , and the carbon structure layer 19 includes a contact surface that contacts the first molded portion 171 .
[0051] S1000, such as Fig. 9 As shown, a bit line metal layer 20 is formed, and the bit line metal layer 20 is in contact with at least one side of the contact surface facing away from the first formed portion 171 .
[0052] Specifically, the material of the bit line metal layer 20 includes cobalt, or the material of the bit line metal layer 20 includes cobalt and titanium.
[0053] S1200 , heat-treating the bit line forming portion 17 so that the first forming portion 171 becomes the first portion 121 and the second forming portion 172 becomes the second portion 122 . The first portion 121 includes silicide and carbon dopant, and the second portion 122 includes silicon.
[0054] In the preparation method of the semiconductor device 1 provided in the present application, by forming a carbon structure layer 19 and a bit line metal layer 20 on the side of the second molded part 172, and heat treating the bit line molded part 17 to form a silicide, the presence of the carbon structure layer 19 can isolate the second molded part 172 and the bit line metal layer 20, thereby preventing the second molded part 172 from directly contacting the bit line metal layer 20 to form an oxide. The provision of the carbon structure layer 19 can inhibit the generation of oxides between the second molded part 172 and the bit line metal layer 20, so that the thermal stability of the first part 121 formed after the heat treatment of the second molded part 172 is better. During the annealing process, the material of the first molded part 171 reacts with the bit line metal to form a silicide, and the carbon structure layer 19 is located in or on the surface of the silicide to form a carbon dopant. At the same time, the second molded part 172 is protected by the protection structure 18 to prevent the second molded part 172 from contacting the carbon structure layer 19 and the bit line metal layer 20, so as to prevent the silicon material of the second molded part 172 from changing and forming silicide after heat treatment, so as to facilitate the subsequent generation of subsequent film layers by epitaxial growth.
[0055] Specifically, the heat treatment includes rapid thermal annealing, laser annealing, and the like.
[0056] In a feasible implementation manner, the carbon structure layer 19 is formed by a deposition process.
[0057] Specifically, the thickness of the carbon structure layer 19 is H, 1 nm ≤ H ≤ 2 nm.
[0058] Specifically, the thickness of the carbon structure layer 19 may be 1 nm, 1.1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 1 nm, 1.9 nm, 2 nm, etc.
[0059] In the above embodiment, if the thickness of the carbon structure layer 19 is too thin, it is not possible to achieve a good effect of isolating the first molded part 171 from the bit line metal layer 20, and if it is too thick, it affects the formation of silicide. When the thickness of the carbon structure layer 19 is 1nm to 2nm, it is possible to achieve both the isolation effect of the first molded part 171 from the bit line metal layer 20 and the silicide formation effect.
[0060] In one feasible implementation, the bit line metal layer 20 is formed by a chemical vapor deposition process.
[0061] The conventional bit line metal layer 20 formed by physical vapor deposition (PVD) process has poor coverage of the step position, and it is difficult to form uniform silicide subsequently. In the embodiment provided by the present application, the bit line metal layer 20 is formed by chemical vapor deposition (CVD) process to improve the uniformity of the bit line metal layer 20, and the bit line metal layer 20 formed by chemical vapor deposition (CVD) process has strong coverage of the step position.
[0062] In a possible implementation, Figures 7 to 9 As shown, the bit line forming part 17 further includes an isolation forming part 173 located between the first forming part 171 and the substrate 11; the method for preparing the semiconductor device 1 further includes:
[0063] A barrier layer 15 is formed on the substrate 11 and is located between adjacent isolation molding parts 173 , wherein the barrier layer 15 has the same thickness as that of the isolation molding parts 173 ;
[0064] The bit line forming portion 17 is heat-treated, and the isolation forming portion 173 becomes the isolation layer 13 .
[0065] In the above embodiment, the isolation molding part 173 is formed simultaneously with the bit line molding part 17, so that the preparation process can be simplified. After the heat treatment, the isolation molding part 173 becomes the isolation layer 13. The isolation molding part 173 is used to isolate the substrate 11 from the first molding part 171 to prevent the first molding part 171 from causing adverse effects on the substrate 11 during the heat treatment process. Specifically, a carbon structure layer 19 is formed on the side wall of the first molding part 171, and a bit line metal layer 20 is formed on the surface of the carbon structure layer 19 on the side away from the first molding part 171. During the heat treatment process, the bit line metal layer 20 reacts with the silicon material in the first molding part 171 to form a silicide, and the carbon structure layer 19 is located in or on the surface of the silicide, so that the first molding part 171 becomes the first part 121. The isolation molding part 173 can isolate the bit line metal layer 20 and the like from penetrating downward from the first molding part 171 and reacting with the substrate 11, thereby protecting the substrate 11. In the above embodiment, a barrier layer 15 is formed between adjacent isolation molding parts 173, and the barrier layer 15 is used to cover the portion of the substrate 11 that is not covered by the isolation molding part 173, and to cover the side wall of the isolation molding part 173, so as to prevent the carbon structure layer 19 and / or the bit line metal layer 20 from contacting the substrate 11 and the isolation molding part 173 during the process of forming the carbon structure layer 19 and the bit line metal layer 20, thereby protecting the substrate 11 and the isolation molding part 173, preventing the isolation molding part 173 and the substrate 11 from forming silicide during the heat treatment process, that is, preventing the properties of the isolation molding part 173 and the substrate 11 from changing.
[0066] In a possible implementation, Figure 8As shown, the carbon structure layer 19 covers a surface of the protection structure 18 facing away from the second shaped portion 172 and a surface of the barrier layer 15 facing away from the substrate 11 .
[0067] In the above embodiment, since the barrier layer 15 is provided, the carbon structure layer 19 can be prepared in its entirety, so that the carbon structure layer 19 partially covers the surface of the side of the protection structure 18 away from the second molded portion 172, partially covers the surface of the side of the barrier layer 15 away from the substrate 11, and most importantly, part of the carbon structure layer 19 covers the side surface of the first molded portion 171. The method of preparing the carbon structure layer 19 in its entirety can simplify the preparation process.
[0068] In a possible implementation, Fig. 9 As shown, the bit line metal layer 20 covers a surface of the carbon structure layer 19 facing away from the substrate 11 and a surface of the carbon structure layer 19 facing away from the bit line forming portion 17 .
[0069] In the above embodiment, since the barrier layer 15 is provided, the bit line metal layer 20 can be prepared in the whole surface during the preparation, so that the bit line metal layer 20 partially covers the surface of the carbon structure layer 19 on the side away from the bit line forming part 17, and partially covers the surface of the carbon structure layer 19 on the side away from the substrate 11. Most importantly, part of the bit line metal layer 20 covers the surface of the carbon structure layer 19 on the side away from the first forming part 171. The method of preparing the bit line metal layer 20 on the whole surface can simplify the preparation process.
[0070] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A semiconductor device, characterized in that: include: substrate; A bit line structure is formed on the substrate, the bit line structure includes a first part and a second part, the second part is located on a side of the first part away from the substrate, the first part includes silicide and carbon dopant, and the second part includes silicon.
2. The semiconductor device according to claim 1, wherein: An isolation layer is also included, and the isolation layer is located between the bit line structure and the substrate.
3. The semiconductor device according to claim 2, characterized in that There are a plurality of bit line structures, and the plurality of bit line structures are arranged at intervals. There are a plurality of isolation layers, and the isolation layers correspond to the bit line structures one by one.
4. The semiconductor device according to claim 3, characterized in that It also includes a transistor, which includes a source region, a drain region and a channel region, the source region is integrally formed with the bit line structure, the channel region is located on a side of the second portion away from the substrate and the channel region contacts the second portion, and the drain region is located on a side of the channel region away from the substrate.
5. The semiconductor device according to claim 3, characterized in that It also includes a barrier layer, which is located on the substrate. The barrier layer is adjacent to the isolation layer and contacts the side wall of the isolation layer. The barrier layer and the isolation layer have the same thickness.
6. A method for preparing a semiconductor device, characterized in that: include: providing a semiconductor substrate; Patterning the semiconductor substrate to form a substrate and a bit line forming portion located at one side of the substrate, wherein the bit line forming portion includes a first forming portion and a second forming portion located at a side of the first forming portion away from the substrate; forming a protective structure on a surface of the second forming portion facing away from the semiconductor substrate and on a side surface of the second forming portion; forming a carbon structure layer, the carbon structure layer at least in contact with a side surface of the first molded portion, the carbon structure layer including a contact surface in contact with the first molded portion; forming a bit line metal layer, wherein the bit line metal layer is in contact with at least one side of the contact surface facing away from the first forming portion; The bit line forming part is thermally treated so that the first forming part becomes a first portion and the second forming part becomes a second portion, the first portion includes silicide and carbon dopant, and the second portion includes silicon.
7. The method for preparing a semiconductor device according to claim 6, characterized in that: The thickness of the carbon structure layer is H, 1nm≤H≤2nm.
8. The method for preparing a semiconductor device according to claim 6, characterized in that: The bit line metal layer is formed by a chemical vapor deposition process.
9. The method for preparing a semiconductor device according to claim 6, wherein: The bit line forming part further includes an isolation forming part located between the first forming part and the substrate; The method for preparing the semiconductor device further includes: forming a barrier layer between adjacent isolation molding parts on the substrate, wherein the barrier layer has the same thickness as that of the isolation molding parts; The bit line forming portion is subjected to heat treatment, and the isolation forming portion becomes an isolation layer.
10. The method for preparing a semiconductor device according to claim 9, characterized in that: The carbon structure layer covers a surface of the protection structure facing away from the second molded portion and a surface of the barrier layer facing away from the substrate.
11. The method for preparing a semiconductor device according to claim 9, characterized in that: The bit line metal layer covers a surface of the carbon structure layer on one side facing away from the substrate and a surface of the carbon structure layer on one side facing away from the bit line forming portion.
12. The method for preparing a semiconductor device according to claim 6, characterized in that: The material of the bit line metal layer includes cobalt, or the material of the bit line metal layer includes cobalt and titanium.