Preparation method of metal oxide semiconductor device
By forming a stacked structure on the semiconductor material layer of the LDMOS device and performing ion implantation and annealing, the mutual constraint problem between the breakdown voltage and the on-resistance is solved, and a high breakdown voltage and low on-resistance are achieved.
Patent Information
- Application Number
- CN202411951409.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-11
AI Technical Summary
While the existing LDMOS devices increase the breakdown voltage, the on-resistance increases, making it difficult to optimize the process to further improve performance.
By forming a stacked structure on the semiconductor material layer, using this as a mask for ion implantation into the forming body region, followed by annealing and wet etching to remove the isolation layer and anti-reflection layer, avoiding doping ion loss and interlayer reaction.
It effectively avoids the increase in device on-resistance, while maintaining low on-resistance and not affecting the performance of reverse bias withstand voltage.
Smart Images
Figure CN119815858A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a metal oxide semiconductor device. Background Art
[0002] DMOS devices have the advantages of fast switching speed, low loss, and high reliability, and are suitable for application in the field of high-voltage switch technology. Laterally diffused metal oxide semiconductor (LDMOS) devices in DMOS devices are technically compatible with complementary metal oxide semiconductor (CMOS) devices, so they have more advantages in practical applications. High-performance LDMOS devices need to have high breakdown voltage and low on-resistance. However, there is a mutually constrained relationship between breakdown voltage and on-resistance. For example, in order to increase the breakdown voltage of the device, it is usually necessary to increase the length of the drift region, and the increase in the length of the drift region will lead to an increase in the on-resistance of the device.
[0003] At present, in order to obtain higher performance LDMOS devices, it is usually necessary to optimize the layout size, physical morphology and doping concentration of related areas of the device. The on-resistance of LDMOS devices is closely related to substrate resistance, gate structure, drift region doping concentration and body region doping concentration. Therefore, how to optimize the process to further improve the performance of LDMOS devices is a technical problem that needs to be solved urgently. Summary of the invention
[0004] In view of this, an embodiment of the present application provides a method for preparing a metal oxide semiconductor device to solve at least one problem existing in the background technology.
[0005] In a first aspect, an embodiment of the present application provides a method for preparing a metal oxide semiconductor device, the method comprising:
[0006] providing a semiconductor material layer;
[0007] A stacked structure is formed on the semiconductor material layer, wherein the stacked structure has an opening exposing a portion of the semiconductor material layer; the stacked structure comprises a dielectric layer, a polysilicon layer, an isolation layer, an anti-reflection layer and a first photoresist layer stacked in sequence, wherein the isolation layer is made of silicon oxide, and the anti-reflection layer is made of silicon oxynitride;
[0008] Using the stacked structure as a mask, ion implantation is performed into the semiconductor material layer through the opening to form a body region of a first conductivity type;
[0009] performing annealing treatment on the body region;
[0010] The isolation layer and the anti-reflection layer are removed by a wet etching process.
[0011] In conjunction with the first aspect of the present application, in an optional implementation manner, the thickness of the isolation layer is 100 angstroms to 200 angstroms.
[0012] In conjunction with the first aspect of the present application, in an optional implementation manner, the temperature of the annealing treatment is 1000°C to 1150°C.
[0013] In combination with the first aspect of the present application, in an optional implementation, the wet etching solution used in the wet etching process includes phosphoric acid.
[0014] In combination with the first aspect of the present application, in an optional implementation, in the process of removing the isolation layer and the anti-reflection layer by the wet etching process, the wet etching rate of the isolation layer is greater than the wet etching rate of the anti-reflection layer.
[0015] In conjunction with the first aspect of the present application, in an optional implementation manner, before performing the annealing treatment on the body region, the method further includes:
[0016] The first photoresist layer is removed.
[0017] In conjunction with the first aspect of the present application, in an optional implementation manner, before performing the annealing treatment on the body region, the method further includes:
[0018] An ion implantation process is performed to form a second conductive type doped region in the body region extending from the surface of the semiconductor material layer to the interior of the semiconductor material layer, wherein the extension depth of the doped region in the thickness direction of the semiconductor material layer is less than the extension depth of the body region in the thickness direction of the semiconductor material layer.
[0019] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:
[0020] A source region of a second conductivity type is formed in the body region and extends from the surface of the semiconductor material layer to the interior of the semiconductor material layer. The doping concentration of the source region is greater than the doping concentration of the doping region, and the edge of the source region is located inside the doping region.
[0021] In conjunction with the first aspect of the present application, in an optional implementation manner, before removing the isolation layer and the anti-reflection layer by the wet etching process, the method further includes:
[0022] forming a second photoresist layer on the anti-reflective layer;
[0023] The stacked structure is etched using the second photoresist layer as a mask to form a gate structure.
[0024] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:
[0025] A metal silicide is formed on the surface of the gate structure.
[0026] The preparation method of the metal oxide semiconductor device provided in the embodiment of the present application includes providing a semiconductor material layer; forming a stacked structure on the semiconductor material layer, the stacked structure having an opening exposing a portion of the semiconductor material layer; the stacked structure includes a dielectric layer, a polysilicon layer, an isolation layer, an anti-reflection layer and a first photoresist layer stacked in sequence, the material of the isolation layer includes silicon oxide, and the material of the anti-reflection layer includes silicon oxynitride; using the stacked structure as a mask, ion implanting the semiconductor material layer through the opening to form a body region of the first conductivity type; annealing the body region; and removing the isolation layer and the anti-reflection layer by a wet etching process. In the embodiment of the present application, after the body region is annealed, the isolation layer and the anti-reflection layer are removed by a wet etching process, so that the problem of easy loss of doped ions in the body region during the wet etching process can be avoided, thereby avoiding the increase of the on-resistance of the device. At the same time, by arranging an isolation layer between the polysilicon layer and the anti-reflection layer, the problem of the anti-reflection layer being difficult to remove due to the reaction between the anti-reflection layer and the polysilicon layer during the annealing process can be avoided, thereby affecting the contact resistance of the gate structure formed subsequently. In the embodiments of the present application, by improving the preparation process, a low on-resistance is maintained without affecting the reverse bias withstand voltage of the device.
[0027] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0029] Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor material layer in a metal oxide semiconductor device during the preparation process in the related art;
[0030] Figure 2 A schematic diagram of a cross-sectional structure of an opening formed during the preparation process of a metal oxide semiconductor device in the related art;
[0031] Figure 3 A schematic cross-sectional structure diagram of a second photoresist layer formed during the preparation process of a metal oxide semiconductor device in the related art;
[0032] Figure 4 A schematic diagram of a cross-sectional structure of a gate structure formed during the preparation process of a metal oxide semiconductor device in the related art;
[0033] Figure 5 A schematic diagram of a cross-sectional structure of a metal oxide semiconductor device in the related art in which an anti-reflection layer is removed during the preparation process;
[0034] Figure 6 It is a schematic diagram of the cross-sectional structure of a metal oxide semiconductor device in the related art after the body region is annealed during the preparation process;
[0035] Figure 7 A scanning electron microscope image of a gate structure of a metal oxide semiconductor device in the related art;
[0036] Figure 8 A schematic diagram of a process for preparing a metal oxide semiconductor device provided in an embodiment of the present application;
[0037] Fig. 9 A schematic diagram of a cross-sectional structure of a semiconductor material layer provided during the preparation process of the metal oxide semiconductor device provided in an embodiment of the present application;
[0038] Fig.10 A schematic cross-sectional structure diagram of a first photoresist layer formed during the preparation process of a metal oxide semiconductor device provided in an embodiment of the present application;
[0039] Fig.11 A schematic cross-sectional structure diagram of a stacked structure formed during the preparation process of a metal oxide semiconductor device provided in an embodiment of the present application;
[0040] Fig.12 A schematic diagram of a cross-sectional structure of a body region formed during the preparation process of a metal oxide semiconductor device provided in an embodiment of the present application;
[0041] Fig.13 A schematic cross-sectional structure diagram of removing the first photoresist layer during the preparation process of the metal oxide semiconductor device provided in an embodiment of the present application;
[0042] Fig.14 A schematic diagram of the cross-sectional structure of the metal oxide semiconductor device provided in an embodiment of the present application after the body region is annealed during the preparation process;
[0043] Fig.15 A schematic diagram of a cross-sectional structure of a second photoresist layer formed during the preparation process of a metal oxide semiconductor device provided in an embodiment of the present application;
[0044] Fig.16A schematic cross-sectional structure diagram of a gate structure formed during the preparation process of a metal oxide semiconductor device provided in an embodiment of the present application;
[0045] Fig.17 A schematic diagram of the cross-sectional structure of the metal oxide semiconductor device provided in an embodiment of the present application, wherein the isolation layer and the anti-reflection layer are removed during the preparation process;
[0046] Fig.18 A schematic diagram of the cross-sectional structure of the metal oxide semiconductor device provided in the embodiment of the present application during the preparation process in which the sidewalls, source region, drain region and metal silicide are formed;
[0047] Fig.19 A scanning electron microscope image of the gate structure of the metal oxide semiconductor device provided in an embodiment of the present application.
[0048] Description of reference numerals:
[0049] 100, semiconductor material layer; 101, drift region; 102, body region; 103, doping region; 104, source region; 105, drain region; 110, first well region; 120, second well region; 130, reduced surface electric field region; 140, first shallow trench isolation structure; 150, second shallow trench isolation structure; 20, initial stacked structure; 200, stacked structure; 201, dielectric layer; 202, polysilicon layer; 203, anti-reflective layer; 204, first photoresist layer; 205, isolation layer; 210, second photoresist layer; 220, gate structure; 230, sidewall; 240, metal silicide; 250, field oxide layer; 260, field plate; 300, opening. DETAILED DESCRIPTION
[0050] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.
[0051] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0052] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0053] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.
[0054] Spatially relative terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0056] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.
[0057] Figures 1 to 6 The cross-sectional structure diagram of a metal oxide semiconductor device in the related art during the preparation process. The preparation method of the metal oxide semiconductor device in the related art includes the following steps:
[0058] Step S1: Please refer to Figure 1 A drift region 101 is formed in the semiconductor material layer 100, and an initial stacked structure 20 is formed on the semiconductor material layer 100. The initial stacked structure 20 includes a dielectric layer 201, a polysilicon layer 202, an anti-reflective coating 203 (DARC) and a first photoresist layer 204 stacked in sequence, wherein the material of the anti-reflective layer 203 is silicon oxynitride;
[0059] Step S2: Please refer to Figure 2 , using the first photoresist layer 204 as a mask, sequentially etching the anti-reflection layer 203, the polysilicon layer 202 and the dielectric layer 201 to form an opening 300 exposing a portion of the drift region 101, and the remaining dielectric layer 201, the polysilicon layer 202, the anti-reflection layer 203 and the first photoresist layer 204 form a stacked structure 200;
[0060] Step S3: Please continue to refer to Figure 2 , using the stacked structure 200 as a mask, firstly, B is implanted into the drift region 101 through the opening 300 to form a body region 102 of the first conductivity type, and then As is implanted into the body region 102 through the opening 300 to form a doped region 103 of the second conductivity type, wherein the extension depth of the doped region 103 in the thickness direction of the semiconductor material layer 100 is less than the extension depth of the body region 102 in the thickness direction of the semiconductor material layer 100;
[0061] Step S4: Please refer to Figure 3 , removing the first photoresist layer 204 and forming a second photoresist layer 210 on the stacked structure 200;
[0062] Step S5: Please refer to Figure 4 , using the second photoresist layer 210 as a mask, etching the stacked structure 200 to form a gate structure 220; removing the second photoresist layer 210;
[0063] Step S6: Please refer to Figure 5 , using a wet etching process to remove the anti-reflection layer 203, specifically, using a phosphoric acid wet process to remove the anti-reflection layer 203;
[0064] Step S7: Please refer to Figure 6 , the body region 102 and the doped region 103 are annealed.
[0065] The inventors found in their research that since the doping ions in the body region 102 and the doping region 103 are in a free state in the semiconductor material layer 100 and are not bound by hybrid covalent bonds, in step S6, when the anti-reflection layer 203 is removed by a wet etching process, the doping ions in the body region 102 and the doping region 103 will be lost, which will in turn increase the on-resistance of the device. The inventors changed the annealing treatment of the body region 102 and the doping region 103 in step S7 to be performed before step S6, so as to fix the doping ions in the body region 102 and the doping region 103 by annealing, thereby avoiding the problem of doping ions in the body region 102 and the doping region 103 being lost when the anti-reflection layer 203 is removed by a wet etching process. However, the inventors have found that during the annealing process (specifically, keeping at 1100° C. for 30 seconds), the anti-reflection layer 203 (silicon oxynitride) reacts with the polysilicon layer 202, making the anti-reflection layer 203 very dense, and it is difficult to remove the anti-reflection layer 203 by wet etching later, which further makes it difficult to form a continuous and complete metal silicide 240 on the polysilicon layer 202. For details, please refer to Figure 7 From the SEM image of the gate structure of the LDMOS device, it can be seen that the metal silicide 240 is formed only in a small area on the surface of the gate polysilicon layer 202 (eg Figure 7 This will increase the contact resistance of the gate structure 220, thereby reducing the conduction performance of the device.
[0066] Based on this, an embodiment of the present application provides a method for preparing a metal oxide semiconductor device. Figure 8 A schematic flow chart of a method for preparing a metal oxide semiconductor device provided in an embodiment of the present application; as shown in the figure, the method comprises:
[0067] Step S101, providing a semiconductor material layer;
[0068] Step S102, forming a stacked structure on the semiconductor material layer, the stacked structure having an opening exposing a portion of the semiconductor material layer; the stacked structure comprises a dielectric layer, a polysilicon layer, an isolation layer, an anti-reflection layer and a first photoresist layer stacked in sequence, the isolation layer comprises silicon oxide, and the anti-reflection layer comprises silicon oxynitride;
[0069] Step S103, using the stacked structure as a mask, ion implantation is performed into the semiconductor material layer through the opening to form a body region of the first conductivity type;
[0070] Step S104, performing annealing treatment on the body region;
[0071] Step S105: removing the isolation layer and the anti-reflection layer by a wet etching process.
[0072] It can be understood that, through the above method, after the body region is annealed, a wet etching process is used to remove the isolation layer and the anti-reflection layer, so that the problem of easy loss of doped ions in the body region during the wet etching process can be avoided, thereby avoiding the increase in the on-resistance of the device. At the same time, by providing an isolation layer between the polysilicon layer and the anti-reflection layer, the problem of the anti-reflection layer being difficult to remove due to the reaction between the anti-reflection layer and the polysilicon layer during the annealing process, which in turn affects the contact resistance of the gate structure formed subsequently, can be avoided. In the embodiment of the present application, by improving the preparation process, a low on-resistance is maintained without affecting the reverse bias withstand voltage of the device.
[0073] First, please refer to Fig. 9 , execute step S101 to provide a semiconductor material layer 100.
[0074] For example, the material of the semiconductor material layer 100 may be single crystal silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon germanium or silicon carbide, etc. The conductivity type of the semiconductor material layer 100 may be P type or N type.
[0075] In some specific embodiments, please continue to refer to Fig. 9 A first well region 110 may be formed in the semiconductor material layer 100 , and the conductivity type of the first well region 110 is different from the conductivity type of the semiconductor material layer 100 .
[0076] Specifically, when the conductivity type of the semiconductor material layer 100 is P-type, the conductivity type of the first well region 110 is N-type, and when the conductivity type of the semiconductor material layer 100 is N-type, the conductivity type of the first well region 110 is P-type. Subsequently, the device can be fabricated in the first well region 110 to be isolated from the semiconductor material layer 100, thereby better ensuring the performance of the device. In a specific embodiment, the conductivity type of the semiconductor material layer 100 is P-type, and the conductivity type of the first well region 110 is N-type.
[0077] In the actual preparation process, the first well region 110 can be formed by injecting corresponding types of impurity elements into the semiconductor material layer 100. For example, the first well region 110 can be formed by injecting impurities P into the semiconductor material layer 100, wherein the energy of the ion implantation can be, for example, 1200 KeV, and the dose of the ion implantation can be 1E12 ions / cm 2 -1E13ions / cm 2 .
[0078] In some specific embodiments, please continue to refer to Fig. 9 A second well region 120 may be formed in the semiconductor material layer 100, and the conductivity type of the second well region 120 is the same as that of the semiconductor material layer 100. In this way, the semiconductor material layer 100 may be connected through the second well region 120, for example, the semiconductor material layer 100 may be grounded.
[0079] In some specific embodiments, please continue to refer to Fig. 9 A drift region 101 may be formed in the semiconductor material layer 100. The conductivity type of the drift region 101 is different from the conductivity type of the semiconductor material layer 100. In a specific embodiment, the conductivity type of the drift region 101 is N-type.
[0080] In the actual preparation process, the drift region 101 can be formed by implanting corresponding types of impurity elements into the semiconductor material layer 100. For example, P can be implanted into the semiconductor material layer 100 to form the drift region 101, wherein the energy of the ion implantation can be 30KeV-600KeV, and the dose of the ion implantation can be 1E12ions / cm 2 -1E13ions / cm 2 .
[0081] In some specific embodiments, please continue to refer to Fig. 9 The semiconductor material layer 100 may include a reduced surface field region 130 located below the drift region 101, and the reduced surface field region 130 has a different conductivity type from the drift region 101. The reduced surface field region 130 may also be called a Resurf (reduce surface field) region, which can assist in the depletion of the drift region 101, effectively adjust the electric field of the drift region 101, flatten the peak electric field on the surface of the semiconductor material layer 100, and further improve the withstand voltage level of the device.
[0082] In the actual preparation process, for example, before forming the drift region 101, the corresponding type of impurity elements may be implanted into the semiconductor material layer 100 to form the RESURF region 130. For example, B may be implanted into the semiconductor material layer 100 to form the RESURF region 130, wherein the energy of the ion implantation may be 800KeV-1200KeV, and the dose of the ion implantation may be 1E13ions / cm 2 -1E14ions / cm 2 .
[0083] It should be noted that Fig. 9The adjacent Resurf region and the drift region 101 are only an example, and in some other embodiments of the present application, there may be a gap between the Resurf region and the drift region 101. It is understood that the size of the gap here can be set by those skilled in the art according to actual needs.
[0084] In some specific embodiments, please continue to refer to Fig. 9 A first shallow trench isolation structure 140 may be formed between the first well region 110 and the second well region 120. In this way, the active region may be defined by the first shallow trench isolation structure 140 to isolate adjacent devices, thereby avoiding electrical interference between adjacent devices and improving the stability of the device.
[0085] In some specific embodiments, please continue to refer to Fig. 9 A second shallow trench isolation structure 150 may be formed between the drift region 101 and the first well region 110. This may further improve the withstand voltage level of the device.
[0086] In the actual preparation process, the formation process of the first shallow trench isolation structure 140 and the second shallow trench isolation structure 150 can be, for example, first using photolithography and etching processes to form trenches in the semiconductor material (not shown in the figure), and then using a deposition process to fill silicon oxide in the trenches.
[0087] Next, please refer to Fig.10 and Fig.11 , perform step S102 to form a stacked structure 200 on the semiconductor material layer 100, the stacked structure 200 having an opening 300 exposing a portion of the semiconductor material layer 100; the stacked structure 200 includes a dielectric layer 201, a polysilicon layer 202, an isolation layer 205, an anti-reflection layer 203 and a first photoresist layer 204 stacked in sequence, the material of the isolation layer 205 includes silicon oxide, and the material of the anti-reflection layer 203 includes silicon oxynitride.
[0088] In the actual preparation process, for example, a dielectric layer 201, a polysilicon layer 202, an isolation layer 205, an anti-reflection layer 203 and a photoresist layer (not shown in the figure) can be sequentially formed on the semiconductor material layer 100 by a deposition process; then, the photoresist layer is patterned by a photolithography process to form a first photoresist layer 204 (please refer to Fig.10 ); Next, using the first photoresist layer 204 as a mask, the anti-reflection layer 203, the isolation layer 205, the polysilicon layer 202 and the dielectric layer 201 are sequentially etched to form an opening 300, and the remaining dielectric layer 201, the polysilicon layer 202, the isolation layer 205, the anti-reflection layer 203 and the first photoresist layer 204 form a stacked structure 200 (please refer to Fig.11 ).
[0089] It is worth noting that in the embodiment of the present application, the side surface of the first photoresist layer 204 close to the opening 300 needs to be kept as vertical as possible, that is, as parallel to the thickness direction of the semiconductor material layer 100 as possible, so as to facilitate the subsequent ion implantation through the opening 300 of the stacked structure 200 to form the body region 102. Specifically, the angle between the side surface of the first photoresist layer 204 close to the opening 300 and the surface of the semiconductor material layer 100 can be 88 degrees to 92 degrees.
[0090] Exemplarily, the material of the dielectric layer 201 may be silicon oxide, for example. In the case where the material of the dielectric layer 201 is silicon oxide, in addition to forming the dielectric layer 201 by a deposition process, a thermal oxidation process (specifically, for example, furnace thermal oxidation) may be used to form the dielectric layer 201. In this way, a more compact dielectric layer 201 may be formed, thereby improving the performance of the gate structure formed subsequently. The thickness of the dielectric layer 201 may be, for example, 120 angstroms to 150 angstroms. The thickness of the polysilicon layer 202 may be, for example, 2000 angstroms. The thickness of the anti-reflection layer 203 may be determined according to the thickness of the first photoresist layer 204, and specifically, the thickness of the anti-reflection layer 203 may be, for example, 200 angstroms to 400 angstroms. The thickness of the first photoresist layer 204 may be determined according to the implantation depth of the subsequent body region, and specifically, the thickness of the first photoresist layer 204 may be, for example, greater than or equal to 24000 angstroms.
[0091] It can be understood that when the thickness of the isolation layer 205 is too small, it may affect the effect of the isolation layer 205 in isolating the polysilicon layer 202 and the anti-reflection layer 203, and the requirements for the actual preparation process are relatively high. When the thickness of the isolation layer 205 is too large, it will increase the difficulty and time of the subsequent wet etching process to remove the isolation layer 205. Therefore, in some specific embodiments, the thickness of the isolation layer 205 can be 100 angstroms-200 angstroms.
[0092] Next, please refer to Fig.12 , executing step S103 , using the stacked structure 200 as a mask, ion implantation is performed into the semiconductor material layer 100 through the opening 300 to form a body region 102 of the first conductivity type.
[0093] In the embodiment of the present application, ion implantation is performed using the stacked structure 200 including the first photoresist layer 204 as a mask, and the pattern of the first photoresist layer 204 can be consistent with the pattern of ion implantation. This can avoid the problem of changes in the pattern transfer due to overlay errors during the process of transferring the pattern of the first photoresist layer 204 to the dielectric layer 201, the polysilicon layer 202, the isolation layer 205 and the anti-reflection layer 203 to form the opening 300, thereby affecting the accuracy of the ion implantation pattern.
[0094] It can be understood that in the actual preparation process, since the side of the first photoresist layer 204 close to the opening 300 can be kept as vertical as possible, when performing the ion implantation process, the ion implantation angle of the body region 102 can be 0 degrees, that is, the ion implantation is performed along the thickness direction of the semiconductor material layer 100, so that the effect and controllability of the ion implantation process can be improved. Exemplarily, the energy of the ion implantation of the body region 102 can be, for example, 30KeV-300KeV, and specifically, for example, a step implantation method can be used, and the ion implantation dose can be, for example, 1E12ions / cm 2 -1E13ions / cm 2 .
[0095] Of course, the present application does not exclude the situation that after removing the first photoresist layer 204 in the stacked structure 200 , ions are implanted into the semiconductor material layer 100 through the opening 300 using the stacked structure 200 as a mask to form the body region 102 .
[0096] In some embodiments, please refer to Fig.12 Before annealing the body region 102, the method for preparing the metal oxide semiconductor device may further include: performing an ion implantation process to form a second conductive type doping region 103 in the body region 102 extending from the surface of the semiconductor material layer 100 to the interior of the semiconductor material layer 100, wherein the extension depth of the doping region 103 in the thickness direction of the semiconductor material layer 100 is less than the extension depth of the body region 102 in the thickness direction of the semiconductor material layer 100.
[0097] In the embodiment of the present application, a doping region 103 having a conductivity type different from that of the body region 102 is formed on the surface of the body region 102, which can improve the linear region current of the LDMOS device, thereby further improving the conductive performance of the device. In addition, the doping region 103 is formed before the annealing process, so that the doping region 103 and the body region 102 can be annealed simultaneously later, which can also avoid the problem that the doping ions of the doping region 103 are easily lost during the subsequent wet etching process to remove the isolation layer 205 and the anti-reflection layer 203.
[0098] In the actual preparation process, the stacked structure 200 can be used as a mask to implant corresponding types of impurity elements into the surface layer of the body region 102 to form the doped region 103. For example, As can be implanted into the body region 102 to form the doped region 103, wherein the energy of the ion implantation can be 10KeV-15KeV, and the ion implantation dose can be 1E14ions / cm 2 -1E15ions / cm 2 .
[0099] In some embodiments, please refer to Fig.13Before annealing the body region 102, the method for preparing the metal oxide semiconductor device further includes: removing the first photoresist layer 204. This can prevent the first photoresist layer 204 from being denatured during the annealing process, thereby preventing the problem of increased difficulty in removing the first photoresist layer 204 due to the denaturation of the first photoresist layer 204.
[0100] In the actual preparation process, for example, a dry process and / or a wet process may be used to remove the first photoresist layer 204. It is understood that when a wet process is used to remove the first photoresist layer 204, the selected wet cleaning solution should not affect the doping ions in the body region 102. In a specific embodiment, a dry process may be used to remove the first photoresist layer 204.
[0101] Next, please refer to Fig.14 , execute step S104 to perform annealing treatment on the body region 102.
[0102] In the embodiment of the present application, the doping ions injected into the body region 102 can be activated by annealing, and the injected doping ions can diffuse to both sides to form a channel region, and the doping ions can be better fixed in the body region 102. In this way, the problem that the doping ions in the body region 102 are easily lost in the subsequent wet etching process can be avoided. In addition, by providing an isolation layer 205 between the polysilicon layer 202 and the anti-reflection layer 203, the problem that the anti-reflection layer 203 reacts with the polysilicon layer 202 during the annealing process, resulting in the difficulty in removing the anti-reflection layer 203, thereby affecting the contact resistance of the gate structure 220 formed subsequently can be avoided.
[0103] As mentioned above, the ion implantation angle of the body region 102 can be 0 degrees. Thus, the length of the channel formed by diffusion during the annealing process will not be affected by the thickness of the first photoresist layer 204 and the size of the pattern opening 300 , so the switching voltage of the device can be controlled more accurately.
[0104] For example, the annealing process may include a rapid thermal annealing (RTA) process. In some embodiments, the temperature of the annealing process may be 1000° C. to 1150° C. The high temperature annealing process is performed to better activate and fix the doping ions in the body region 102 .
[0105] Furthermore, the annealing time may be, for example, 30 seconds, so that the annealing effect can be better guaranteed and the length of the channel region can be controlled within a suitable range.
[0106] In some embodiments, before removing the isolation layer 205 and the anti-reflection layer 203 by a wet etching process, the method for preparing the metal oxide semiconductor device may further include the following steps:
[0107] First, please refer to Fig.15 , forming a second photoresist layer 210 on the anti-reflection layer 203;
[0108] Secondly, please refer to Fig.16 , the stacked structure 200 is etched using the second photoresist layer 210 as a mask to form a gate structure 220 .
[0109] In the embodiment of the present application, the ion implantation process of the body region 102 and the process of etching the stacked structure 200 use the same anti-reflection layer 203, which can simplify the process and reduce the cost. It should be noted that the surface layer of the body region 102 covered by the gate structure 220 is used as the channel region.
[0110] Specifically, the process of forming the second photoresist layer 210 can be understood by referring to the process of forming the first photoresist layer 204, which will not be described in detail here. The process of etching the stacked structure 200 can adopt a dry etching process, such as a plasma etching process. Fig.16 , remove the second photoresist layer 210.
[0111] Finally, please refer to Fig.17 , perform step S105 to remove the isolation layer 205 and the anti-reflection layer 203 using a wet etching process.
[0112] In the embodiment of the present application, since the body region 102 is first annealed, the doped ions in the body region 102 are activated and fixed, and by providing an isolation layer 205 between the polysilicon layer 202 and the anti-reflection layer 203, it is possible to avoid the reaction between the anti-reflection layer 203 and the polysilicon layer 202 during the annealing process, which causes the anti-reflection layer 203 to become dense. Therefore, the isolation layer 205 and the anti-reflection layer 203 can be easily removed by a wet etching process. In this case, the wet etching process will not cause the doped ions in the body region 102 to be lost, and the isolation layer 205 and the anti-reflection layer 203 are removed more completely, which can avoid the problem in the related art that the anti-reflection layer 203 is difficult to remove, resulting in difficulty in forming the metal silicide 240 on the polysilicon layer 202 and the high resistance of the formed metal silicide 240.
[0113] In some embodiments, the isolation layer 205 and the anti-reflection layer 203 are removed by a wet etching process. The isolation layer 205 may be removed by a wet etching process, and the anti-reflection layer 203 falls off as the isolation layer 205 is removed. In this way, the wet etching solution can be selected mainly according to the isolation layer 205, which can simplify the preparation of the wet etching solution. For example, the material of the isolation layer 205 includes silicon oxide, and the wet etching solution may include hydrofluoric acid, for example.
[0114] In some embodiments, the isolation layer 205 and the anti-reflection layer 203 are removed by a wet etching process, which may be a wet etching process to remove the isolation layer 205 and the anti-reflection layer 203. That is, the wet etching solution may be selected according to the materials of the isolation layer 205 and the anti-reflection layer 203, so that the isolation layer 205 and the anti-reflection layer 203 may be removed simultaneously by the wet etching solution, thereby increasing the efficiency of removing the isolation layer 205 and the anti-reflection layer 203.
[0115] Specifically, the wet etching solution used in the wet etching process may include phosphoric acid. Because in the present application, by setting the isolation layer 205 between the polysilicon layer 202 and the anti-reflection layer 203, it is possible to avoid the reaction between the anti-reflection layer 203 and the polysilicon layer 202 during the annealing process, causing the anti-reflection layer 203 to become dense, so phosphoric acid can be used to better remove the anti-reflection layer 203. In the process of the anti-reflection layer 203 being removed by the wet etching solution, the surface of the isolation layer 205 will gradually be exposed, so that the contact area between the wet etching solution and the isolation layer 205 can be increased, so that the wet etching rate of the isolation layer 205 can be further accelerated, and finally the efficiency of removing the isolation layer 205 and the anti-reflection layer 203 is improved.
[0116] In some embodiments, during the process of removing the isolation layer 205 and the anti-reflection layer 203 by a wet etching process, the wet etching rate of the isolation layer 205 is greater than the wet etching rate of the anti-reflection layer 203. In this way, the isolation layer 205 and the anti-reflection layer 203 can be removed faster, further improving the process efficiency.
[0117] In some embodiments, please refer to Fig.18 The method for manufacturing a metal oxide semiconductor device may further include: forming a sidewall 230 on the side of the gate structure 220. In this way, the sidewall of the polysilicon in the gate structure 220 can be protected by the sidewall 230.
[0118] The sidewall spacer 230 can be prepared by a sidewall spacer 230 preparation process well known to those skilled in the art, which will not be described in detail herein. For example, in a direction away from the gate structure 220, the sidewall spacer 230 may include silicon oxide and silicon nitride stacked in sequence, and the thickness of the silicon oxide and silicon nitride may be set according to actual needs. In a specific embodiment, the thickness of the silicon oxide is 200 angstroms, and the thickness of the silicon nitride is 1000 angstroms.
[0119] In some embodiments, please refer to Fig.18 The method for preparing a metal oxide semiconductor device may further include: forming a second conductive type source region 104 in the body region 102 extending from the surface of the semiconductor material layer 100 to the inside of the semiconductor material layer 100 , the doping concentration of the source region 104 is greater than the doping concentration of the doping region 103 , and the edge of the source region 104 is located inside the doping region 103 .
[0120] In the embodiment of the present application, the doping concentration of the doping region 103 is lower than the doping concentration of the source region 104, and therefore can also be referred to as a lightly doped region 103. Since the source region 104 and the doping region 103 have the same conductivity type, and the doping region 103 is located on both sides of the source region 104, the on-resistance of the device can be further reduced.
[0121] In some embodiments, please refer to Fig.18 The method for preparing the metal oxide semiconductor device may further include: forming a drain region 105 in the semiconductor material layer 100 .
[0122] In some embodiments, please refer to Fig.18 The method for preparing a metal oxide semiconductor device may further include: forming a metal silicide 240 on a surface of the gate structure 220 .
[0123] Since the isolation layer 205 and the anti-reflection layer 203 on the polysilicon layer 202 are completely removed, a complete metal silicide 240 can be formed on the surface of the gate structure 220, thereby effectively reducing the contact resistance of the gate structure 220. Fig.19 From the scanning electron microscope image of the gate structure of the LDMOS device, it can be seen that a continuous and complete metal silicide (such as Fig.19 (shown in the solid line frame).
[0124] The technical solution of the present application is compatible with the layout design and process flow of most current LDMOS devices, and the LDMOS device manufactured using the preparation process in the present application can solve the problem of high resistance of the metal silicide 240 on the surface of the gate structure 220 while reducing the on-resistance of the device while occupying the same layout area.
[0125] In the actual preparation process, for example, a metal silicide barrier layer (not shown in the figure) may be formed first, the metal silicide barrier layer exposes the surface of the gate structure 220, and then a metal material layer (not shown in the figure) may be formed on the surface of the gate structure 220, and then a high-temperature heat treatment may be performed to make the polysilicon in the gate structure 220 react with the metal material layer to form a metal silicide 240. By way of example, the material of the metal material layer may include at least one of titanium, cobalt, nickel, and platinum.
[0126] In some embodiments, please refer to Fig.18The method for preparing the metal oxide semiconductor device may further include: forming a field oxide layer 250 , wherein the field oxide layer 250 is located between the source region 104 and the drain region 105 , and extends from above the drift region 101 to above a portion of the gate structure 220 .
[0127] In the actual preparation process, the field oxide layer 250 can cover the drift region 101 located between the gate structure 220 and the drain region 105. In this way, the field oxide layer 250 can also serve as a metal silicide barrier layer, thereby facilitating the formation of a metal silicide layer on the surface of the gate structure 220 and the exposed surface of the semiconductor material layer 100 (such as the surface of the source region 104 and the drain region 105), which can further simplify the process.
[0128] In some embodiments, please refer to Fig.18 The method for preparing the metal oxide semiconductor device may further include: forming a field plate 260 connected to the field oxide layer 250. In this way, the electric field of the drift region 101 can be adjusted by the field plate 260, thereby further improving the breakdown voltage of the device.
[0129] The field oxide layer 250 and the field plate 260 may be prepared by using the preparation processes of the field oxide layer 250 and the field plate 260 well known to those skilled in the art, which will not be described in detail herein.
[0130] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.
Claims
1. A method for preparing a metal oxide semiconductor device, characterized in that: The method comprises: providing a semiconductor material layer; A stacked structure is formed on the semiconductor material layer, wherein the stacked structure has an opening exposing a portion of the semiconductor material layer; the stacked structure comprises a dielectric layer, a polysilicon layer, an isolation layer, an anti-reflection layer and a first photoresist layer stacked in sequence, wherein the isolation layer is made of silicon oxide, and the anti-reflection layer is made of silicon oxynitride; Using the stacked structure as a mask, ion implantation is performed into the semiconductor material layer through the opening to form a body region of a first conductivity type; performing annealing treatment on the body region; The isolation layer and the anti-reflection layer are removed by a wet etching process.
2. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: The thickness of the isolation layer is 100 angstroms to 200 angstroms.
3. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: The annealing treatment is performed at a temperature of 1000°C to 1150°C.
4. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: The wet etching solution used in the wet etching process includes phosphoric acid.
5. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: In the process of removing the isolation layer and the anti-reflection layer by the wet etching process, the wet etching rate of the isolation layer is greater than the wet etching rate of the anti-reflection layer.
6. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: Before performing the annealing process on the body region, the method further includes: The first photoresist layer is removed.
7. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: Before performing the annealing process on the body region, the method further includes: An ion implantation process is performed to form a second conductive type doped region in the body region extending from the surface of the semiconductor material layer to the interior of the semiconductor material layer, wherein the extension depth of the doped region in the thickness direction of the semiconductor material layer is less than the extension depth of the body region in the thickness direction of the semiconductor material layer.
8. The method for preparing a metal oxide semiconductor device according to claim 7, characterized in that: The method further comprises: A source region of a second conductivity type is formed in the body region and extends from the surface of the semiconductor material layer to the interior of the semiconductor material layer. The doping concentration of the source region is greater than the doping concentration of the doping region, and the edge of the source region is located inside the doping region.
9. The method for preparing a metal oxide semiconductor device according to claim 1, characterized in that: Before removing the isolation layer and the anti-reflection layer by the wet etching process, the method further includes: forming a second photoresist layer on the anti-reflective layer; The stacked structure is etched using the second photoresist layer as a mask to form a gate structure.
10. The method for preparing a metal oxide semiconductor device according to claim 9, characterized in that: The method further comprises: A metal silicide is formed on the surface of the gate structure.