A p-gate structure normally-off GaN HEMT device and a preparation method thereof

Abstract

The application discloses a p-type gate structure normally-off GaN HEMT device and a preparation method thereof. The device comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a spacer layer and a barrier layer which are sequentially grown; a source electrode and a drain electrode are arranged above the barrier layer, and a first recess is arranged between the source electrode and the drain electrode; an AlN layer is arranged above the barrier layer, the source electrode, the drain electrode and the first recess; a first CuCrO2 layer is arranged above the AlN layer, a first passivation layer is arranged above the AlN layer, the source electrode, the first CuCrO2 layer and the drain electrode, a gate recess is arranged on the upside of the first passivation layer and the first CuCrO2 layer; a second CuCrO2 layer is arranged above the first CuCrO2 layer, and a gate electrode is arranged above the second CuCrO2 layer; a second passivation layer is arranged above the gate electrode; a floating field plate is arranged above the second passivation layer; a third passivation layer is arranged above the floating field plate; a source field plate is arranged above the source electrode; and a drain interconnection layer is arranged above the drain electrode. The application solves the problems of low threshold voltage and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a p-type gate structure normally-off GaN HEMT device and a preparation method. BACKGROUND

[0002] Compared with traditional silicon-based materials and second-generation semiconductors (represented by gallium arsenide), gallium nitride material becomes one of the first choices of third-generation semiconductors due to its larger band gap, higher voltage resistance, charge density and electron mobility. Especially, the heterojunction device (high electron mobility transistor) composed of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) has excellent performance. Due to the material properties of gallium nitride, the positive and negative charges are not in the center and have spontaneous polarization, and when the gallium nitride forms a heterojunction with aluminum gallium nitride, the piezoelectric polarization effect caused by stress leads to the formation of a triangular potential well at the AlGaN / GaN interface, which binds the electron beam therein and generates a natural conductive channel. Therefore, the GaN HEMT (High Electron Mobility Transistor) device is generally a normally-on device.

[0003] Power devices are divided into normally-on (depletion type) and normally-off (enhancement type) two types according to the value of the gate bias voltage applied when the device is turned on. Normally-on devices are generally in an on state when no gate bias is applied, and often require a negative bias to turn off the device, which will increase the static power consumption in the circuit and also increase the design cost and difficulty of the circuit. Normally-off devices only work when a positive bias is applied, and when no bias is applied, the device is off. Compared with normally-on devices, normally-off AlGaN / GaN HEMT has good failure protection function, fast switching speed and low reverse conduction loss, and has more safety and energy saving advantages in practical application, which can effectively reduce the complexity of circuit design, and therefore has more outstanding research value, use value and broader market.

[0004] The common means for realizing the normally-off GaN HEMT device at present include P-GaN gate structure, recessed gate structure, fluorine ion implantation and cascode structure. The most representative method for realizing the normally-off GaN HEMT device is the p-type gate technology. The technology was first proposed by Toyota in 2007, and then gradually developed into one of the mainstream commercial technologies. The normally-off device of this kind is prepared by depositing a p-GaN cap layer doped with Mg ions on the AlGaN barrier layer, and then depositing a metal on the cap layer to form a gate. There are still some problems for the P-GaN gate structure: on the one hand, since the AlGaN and GaN materials have similar material properties, the etching selectivity between them is difficult to optimize, so it is difficult to control the etching depth, the roughness and uniformity of the etched surface, and the etching damage caused by dry etching will also reduce the electrical performance and reliability of the AlGaN / GaN HEMT. Secondly, the threshold voltage (V th ) of the p-GaN gate device is relatively low (about 1V), which is due to the difficulty in activating Mg doping in GaN, so the low hole concentration may limit the further increase of V th .

[0005] In recent years, many intrinsic p-type metal oxides (stannous oxide, nickel oxide, cuprous oxide) have been used to replace the p-type GaN cap layer to realize the normally-off GaN HEMT. These p-type metal oxides can be grown using a magnetron sputtering technique, and then a P-type gate is formed by a stripping technique. On the one hand, the magnetron sputtering process is simple and low in cost. Secondly, without etching or compatible with wet etching process can greatly avoid etching damage. However, most binary p-type metal oxides have a deep level formed by O-2p orbit of the material itself, which easily traps holes, and the strong electronegativity of oxygen atoms also binds the movement of holes, so the hole concentration is low and the hole mobility is low, which leads to a low threshold voltage of the prepared GaN HEMT device. SUMMARY

[0006] Therefore, the purpose of the present application is to provide a p-type gate structure normally-off GaN HEMT device, which solves the problems of low threshold voltage, etching damage, low conductivity of ordinary binary p-type oxides, and small threshold voltage forward shift caused by low hole carrier concentration of the traditional P-GaN gate technology.

[0007] In order to achieve the above technical purposes, the technical scheme adopted by the present application is:

[0008] The application provides a p-type gate structure normally-off GaN HEMT device, which comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a spacer layer, a barrier layer, a source, a drain, an AlN layer, a first CuCrO2 layer, a first passivation layer, a second CuCrO2 layer, a gate, a second passivation layer, a floating field plate, a third passivation layer, a source field plate and a drain interconnection layer.

[0009] The substrate, the nucleation layer, the buffer layer, the channel layer, the spacer layer and the barrier layer are sequentially stacked from bottom to top.

[0010] The left side of the barrier layer is provided with a source recess, the right side of the barrier layer is provided with a drain recess, and a first recess is arranged between the source recess and the drain recess and close to the drain recess.

[0011] The source is arranged on the source recess, and the drain is arranged on the drain recess.

[0012] The left side of the barrier layer, the left side of the spacer layer, the left side of the channel layer and the upper left side of the buffer layer are provided with a left isolation groove, and the right side of the barrier layer, the right side of the spacer layer, the right side of the channel layer and the upper right side of the buffer layer are provided with a right isolation groove.

[0013] The AlN layer is arranged on the barrier layer, the source and the drain, and forms a second recess at the first recess.

[0014] The first CuCrO2 layer is arranged above part of the AlN layer and between the source and the drain and close to the second recess.

[0015] The first passivation layer covers the AlN layer, the source, the first CuCrO2 layer, the drain and the second recess.

[0016] The middle part of the first passivation layer to the upper surface of the first CuCrO2 layer is provided with a gate recess.

[0017] The second CuCrO2 layer is arranged directly below the gate recess and on the middle part of the upper side of the first CuCrO2 layer, the lower side of the gate is arranged in the gate recess and above the second CuCrO2 layer, and the upper side of the gate is arranged above part of the first passivation layer.

[0018] The second passivation layer covers the first passivation layer and the gate.

[0019] The lower side of the floating field plate is arranged in the second passivation layer and right of the gate and directly above the second recess, and the upper side of the floating field plate is arranged above part of the second passivation layer and directly above the gate.

[0020] The third passivation layer covers the second passivation layer and the floating field plate.

[0021] A source electrode window is formed in a region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the source electrode, and a lower side of the source field plate is arranged in the source electrode window and an upper side of the source field plate is arranged above part of the third passivation layer;

[0022] A drain electrode window is formed in a region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the drain electrode, and a lower side of the drain interconnection layer is arranged in the drain electrode window and an upper side of the drain interconnection layer is arranged above part of the third passivation layer.

[0023] Further, the material of the substrate comprises one of sapphire, silicon, gallium nitride, silicon carbide, ceramic poly-aluminum nitride composite material, insulating silicon base and diamond;

[0024] The material of the nucleation layer is aluminum nitride;

[0025] The material of the buffer layer is one of iron-containing or carbon-doped gallium nitride, AlN and GaN superlattice grown by alternately growing multiple layers, and Al x1 Ga 1-x1 N;

[0026] The material of the channel layer is gallium nitride;

[0027] The material of the barrier layer is Al x2 Ga 1-x2 N, and x2 is 0.1-0.25;

[0028] The source electrode and the drain electrode adopt one of a Ti / Al / Ni / Au multilayer metal structure, a Ti / Al / TiN multilayer metal structure, a Ti / Al / Ti / Au multilayer metal structure and a Ti / Al / Ti / TiN multilayer metal structure;

[0029] The gate electrode adopts one of a Ti / Al multilayer metal structure, a Ti / Au multilayer metal structure and a TiN / Al / TiN multilayer metal structure;

[0030] The material of the first passivation layer, the second passivation layer and the third passivation layer comprises one or more of silicon dioxide, silicon nitride and aluminum oxide;

[0031] The material of the floating field plate is TiN;

[0032] The material of the drain interconnection layer is a TiN / Al / TiN multilayer metal structure.

[0033] Further, the thickness of the nucleation layer is 1-3 nm;

[0034] The thickness of the buffer layer is 1-6 μm;

[0035] The thickness of the channel layer is 50-500nm;

[0036] The thickness of the barrier layer is 10-20nm;

[0037] The thickness of the first and second passivation layers is 50-300nm;

[0038] The thickness of the third passivation layer is 300nm-600nm;

[0039] The thickness of the AlN layer is 2-5nm;

[0040] The thickness of the first CuCrO2 layer is 80-150nm;

[0041] The thickness of the floating field plate is 80-150nm.

[0042] Further, the width of the nucleation layer is the same as the width of the substrate;

[0043] The width of the buffer layer is the same as the width of the nucleation layer;

[0044] A mesa is formed in the upper side of the buffer layer;

[0045] The width of the channel layer is the same as the width of the mesa;

[0046] The width of the spacer layer is the same as the width of the channel layer;

[0047] The width of the barrier layer is the same as the width of the spacer layer.

[0048] Further, the distance between the source and the left sidewall of the first CuCrO2 layer is smaller than the distance between the source and the left sidewall of the gate, the distance between the drain and the right sidewall of the first CuCrO2 layer is smaller than the distance between the drain and the right sidewall of the gate; the distance between the first CuCrO2 layer and the source is smaller than the distance between the first CuCrO2 layer and the drain, and the distance between the gate and the source is smaller than the distance between the gate and the drain.

[0049] Further, the floating field plate is in an inverted L shape, and the source field plate and the drain interconnection layer are in a T shape.

[0050] Further, the upper surface of the second CuCrO2 layer is flush with the upper surface of the first CuCrO2 layer, the hole concentration of the first CuCrO2 layer is 10 18 -10 20 cm -3 , and the hole concentration of the second CuCrO2 layer is 10 16 -10 18 cm -3 .

[0051] The application further provides a preparation method of the p-gate structure normally-off GaN HEMT device.

[0052] Step 1: sequentially epitaxially growing a nucleation layer, a buffer layer, a channel layer, a spacer layer and a barrier layer on the substrate from bottom to top;

[0053] Step 2: etching a source recess and a drain recess on the left side and the right side of the barrier layer respectively, etching a first recess on the barrier layer between the source recess and the drain recess and close to the drain recess, preparing a source above the source recess and a drain above the drain recess;

[0054] Step 3: isolating the left upper side of the buffer layer, the left side of the channel layer, the left side of the spacer layer and the left side of the barrier layer, and the right upper side of the buffer layer, the right side of the channel layer, the right side of the spacer layer and the right side of the barrier layer by ion implantation or etching, and performing high-temperature annealing;

[0055] Step 4: depositing an AlN layer on the barrier layer, the source and the drain, and forming a second recess at the first recess;

[0056] Step 5: preparing a first CuCrO2 layer above part of the AlN layer and between the source and the drain and close to the second recess, and performing high-temperature annealing on the first CuCrO2 layer;

[0057] Step 6: preparing a first passivation layer on the surface of the AlN layer, the source, the first CuCrO2 layer, the drain and the second recess;

[0058] Step 7: opening a gate recess in the middle of the first passivation layer to the upper surface of the first CuCrO2 layer, forming a second CuCrO2 layer below the gate recess and on the upper side of the first CuCrO2 layer after oxygen plasma treatment, and preparing a gate above the second CuCrO2 layer in the gate recess to form a Schottky contact;

[0059] Step 8: preparing a second passivation layer above the first passivation layer and the gate;

[0060] Step 9: preparing a floating field plate on the second passivation layer and the gate;

[0061] Step 10: preparing a third passivation layer above the second passivation layer and the floating field plate;

[0062] Step 11, a source electrode window is opened in the region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the source electrode, and a drain electrode window is opened in the region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the drain electrode;

[0063] Step 12, a source electrode field plate is deposited in the source electrode window, and a drain electrode interconnection layer is deposited in the drain electrode window.

[0064] Further, the epitaxial growth in the step 1 adopts one of MOCVD, HVPE and MBE; the ion implantation in the step 3 uses F ion or N ion implantation; the deposition of the AlN layer in the step 4 adopts a low-temperature deposition process; the preparation of the first CuCrO2 layer in the step 5 adopts a radio frequency magnetron sputtering process; the preparation of the first passivation layer in the step 6 adopts a low-temperature deposition process or a high-temperature low-pressure process; the preparation of the second passivation layer in the step 8 adopts a low-temperature deposition process; the preparation of the third passivation layer in the step 10 adopts a low-temperature deposition process; and the opening of the gate recess, the source electrode window and the drain electrode window in the steps 7 and 11 adopts ICP etching technology.

[0065] Further, before the preparation of the source electrode and the drain electrode in the step 2, the source electrode recess, the drain electrode recess and the first recess are treated by using an inorganic solution or an organic solution, the inorganic solution is HF solution, HCL / H2O2 solution, KOH solution or TMAH solution, and the organic solution is NMP solution.

[0066] By using the technical solution, the present application has the following beneficial effects compared with the prior art.

[0067] 1. The CuCrO2 gate structure is used to replace the traditional p-GaN gate structure, which provides a feasible way for realizing normally-off devices, and the method effectively avoids the problems of surface state, roughness and depth caused by p-GaN doping and etching.

[0068] 2. Compared with Cu2O and NiO, CuCrO2 has a higher hole concentration, about 10 20 cm -3 , which can more effectively deplete the two-dimensional electron gas formed by the AlGaN / GaN heterojunction structure, so that the normally-off device can be realized without external bias.

[0069] 3. The present application provides a feasible exploration idea for the research of normally-off (enhancement mode) devices, and opens up a new application prospect of ternary p-type TCO material gate structure in normally-off AlGaN / GaN HEMT devices.

[0070] 4. The introduction of floating field plate and source field plate, and the etching of the first recess, effectively optimizes the electric field concentration effect of the gate leakage edge, while the inverted "L" type field plate can redistribute the electric field, improving the overall device breakdown.

[0071] 5. Using the AlN layer to passivate the device, greatly improving the channel two-dimensional electron gas, while its high thermal conductivity is combined with the recess to enhance the device heat dissipation effect, greatly improving the device performance.

[0072] 6. The intrinsic p-type metal oxide CuCrO2 has a high degree of electron orbital hybridization, which can form a hybrid energy level, reducing the binding effect of O-2p orbital on holes, and can obtain a high hole concentration and a high hole mobility, which is beneficial to realize the normally-off AlGaN / GaN HEMT device in principle. Secondly, the forbidden band width of CuCrO2 can reach about 3.4eV, which can form a good heterostructure with gallium nitride. CuCrO2 thin film can also be prepared by magnetron sputtering, and P-CuCrO2 gate can be obtained by stripping technology. By adjusting the related parameters of magnetron sputtering, the hole concentration of the prepared CuCrO2 thin film can be adjusted from 10 15 -10 20 cm -3 Adjustment. At the same time, through the oxygen plasma treatment, the concentration of the thin film will be reduced, effectively expanding the gate depletion region and improving the gate breakdown voltage, while for the gold half contact, FP emission can be effectively avoided, the leakage current is reduced, and the gate reliability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0074] Figure 1 is a structural schematic diagram of the substrate, nucleation layer, buffer layer, channel layer, spacer layer and barrier layer provided by the embodiment of the present application.

[0075] Figure 2 is a structural schematic diagram of etching the source recess, drain recess and first recess on the barrier layer in Figure 1 .

[0076] Figure 3 is a schematic diagram of preparing the source and drain on the source recess and drain recess in Figure 2 .

[0077] Figure 4 is a structural schematic diagram of etching the source recess, drain recess and first recess on the barrier layer in Figure 3Structural diagram of etching the left isolation layer and the right isolation layer.

[0078] Figure 5 Structural diagram of preparing an AlN layer on the barrier of Figure 4

[0079] Figure 6 Structural diagram of preparing a first CuCrO2 layer on the AlN layer of Figure 5

[0080] Figure 7 Structural diagram of preparing a first passivation layer on the AlN layer and the first CuCrO2 layer of Figure 6

[0081] Figure 8 Structural diagram of etching a gate recess on the first passivation layer and the first CuCrO2 layer of Figure 7

[0082] Figure 9 Structural diagram of preparing a second CuCrO2 layer on the gate recess of Figure 8

[0083] Figure 10 Structural diagram of preparing a gate on the second CuCrO2 layer of Figure 9

[0084] Figure 11 Structural diagram of preparing a second passivation layer on the first passivation layer and the gate of Figure 10

[0085] Figure 12 Structural diagram of preparing a floating field plate on the second passivation layer of Figure 11

[0086] Figure 13 Structural diagram of preparing a third passivation layer on the second passivation layer and the floating field plate of Figure 12

[0087] Figure 14 Structural diagram of preparing a source window and a drain window above the source and the drain of Figure 13

[0088] Figure 15 Structural diagram of a p-type gate structure normally-off GaN HEMT device provided by an embodiment of the application.

[0089] Figure 16 (a) in the structural diagram is a band diagram of a normally-on GaN HEMT device; Figure 16 (b) in the structural diagram is a band diagram of a normally-off GaN HEMT device with a p-CuCrO2 gate structure. ​​​​​​​​​​

[0090] Explanation of reference numerals in the drawings:

[0091] 1-substrate, 2-nucleation layer, 3-buffer layer, 4-channel layer, 5-spacer layer, 6-barrier layer, 7-source electrode, 8-drain electrode, 9-AlN layer, 10-first CuCrO2 layer, 11-first passivation layer, 12-second CuCrO2 layer, 13-gate electrode, 14-second passivation layer, 15-floating field plate, 16-third passivation layer, 17-source field plate, 18-drain interconnection layer, 19-source recess, 20-drain recess, 21-first recess, 22-left isolation groove, 23-right isolation groove, 24-second recess, 25-gate recess, 26-source window, 27-drain window. DETAILED DESCRIPTION

[0092] The application will be further described below in conjunction with the drawings and examples. It is particularly pointed out that the following examples are only for illustrating the application, but not for limiting the scope of the application. Similarly, the following examples are only part of the examples of the application, but not all the examples, and all other examples obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0093] Please refer to Figure 15 The p-type gate structure normally-off GaN HEMT device of the application comprises a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a spacer layer 5, a barrier layer 6, a source electrode 7, a drain electrode 8, an AlN layer 9, a first CuCrO2 layer 10, a first passivation layer 11, a second CuCrO2 layer 12, a gate electrode 13, a second passivation layer 14, a floating field plate 15, a third passivation layer 16, a source field plate 17, and a drain interconnection layer 18 (equivalent to a drain field plate).

[0094] The substrate 1, the nucleation layer 2, the buffer layer 3, the channel layer 4, the spacer layer 5, and the barrier layer 6 are sequentially stacked from bottom to top;

[0095] The left side of the barrier layer 6 is provided with a source recess 19, the right side of the barrier layer 6 is provided with a drain recess 20, and a first recess 21 is arranged between the source recess 19 and the drain recess 20 and close to the drain recess 20;

[0096] The source electrode 7 is located on the source recess 19, and the drain electrode 8 is located on the drain recess 20;

[0097] The left side of the barrier layer 6, the left side of the spacer layer 5, the left side of the channel layer 4, and the left upper side of the buffer layer 3 are provided with a left isolation groove 22, and the right side of the barrier layer 6, the right side of the spacer layer 5, the right side of the channel layer 4, and the right upper side of the buffer layer 3 are provided with a right isolation groove 23;

[0098] The AlN layer 9 is located on the barrier layer 6, the source 7 and the drain 8, and forms a second recess 24 at the first recess 21;

[0099] The first CuCrO2 layer 10 is located above part of the AlN layer 9, between the source 7 and the drain 8, and close to the second recess 24;

[0100] The first passivation layer 11 covers the AlN layer 9, the source 7, the first CuCrO2 layer 10, the drain 8 and the second recess 24;

[0101] The middle part of the first passivation layer 11 is provided with a gate recess 25 above the upper surface of the first CuCrO2 layer 10;

[0102] The second CuCrO2 layer 12 is located directly below the gate recess 25 and on the upper side of the first CuCrO2 layer 10;

[0103] The lower side of the gate 13 is located in the gate recess 25 and above the second CuCrO2 layer 12, and the upper side of the gate 13 is located above part of the first passivation layer 11;

[0104] The second passivation layer 14 covers the first passivation layer 11 and the gate 13;

[0105] The lower side of the floating field plate 15 is located in the second passivation layer 14 and to the right of the gate 13 and directly above the second recess 24, and the upper side of the floating field plate 15 is located above part of the second passivation layer 14 and directly above the gate 13;

[0106] The third passivation layer 16 covers the second passivation layer 14 and the floating field plate 15;

[0107] The region of the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 above the source 7 is provided with a source window 26, and the lower side of the source field plate 17 is located in the source window 26 and the upper side thereof is located above part of the third passivation layer 16;

[0108] The region of the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 above the drain 8 is provided with a drain window 27, and the lower side of the drain interconnection layer 18 is located in the drain window 27 and the upper side thereof is located above part of the third passivation layer 16.

[0109] In the embodiment, the material of the substrate 1 includes one of sapphire, silicon, gallium nitride, silicon carbide, ceramic poly-aluminum nitride composite material, insulating silicon base and diamond;

[0110] The material of the nucleation layer 2 is aluminum nitride;

[0111] The material of the buffer layer 3 is one of iron-containing or carbon-doped gallium nitride, an AlN and GaN multilayer alternately grown superlattice and Al x1 Ga 1-x1 N, x1 is in the range of 0 < x1 < 1;

[0112] The material of the channel layer 4 is gallium nitride;

[0113] The material of the barrier layer 6 is Al x2 Ga 1-x2 N, x2 is in the range of 0.1-0.25;

[0114] The source electrode 7 and the drain electrode 8 adopt one of a Ti / Al / Ni / Au multilayer metal layer-by-layer structure (i.e. Ti, Al, Ni and Au are layer-by-layer from bottom to top), a Ti / Al / TiN multilayer metal layer-by-layer structure (i.e. Ti, Al and TiN are layer-by-layer from bottom to top), a Ti / Al / Ti / Au multilayer metal layer-by-layer structure (i.e. Ti, Al, Ti and Au are layer-by-layer from bottom to top) and a Ti / Al / Ti / TiN multilayer metal layer-by-layer structure (i.e. Ti, Al, Ti and TiN are layer-by-layer from bottom to top);

[0115] The gate electrode 13 adopts one of a Ti / Al multilayer metal layer-by-layer structure (i.e. Ti and Al are layer-by-layer from bottom to top), a Ti / Au multilayer metal layer-by-layer structure (i.e. Ti and Au are layer-by-layer from bottom to top) and a TiN / Al / TiN multilayer metal layer-by-layer structure (i.e. TiN, Al and TiN are layer-by-layer from bottom to top);

[0116] The material of the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 includes one or more of silicon dioxide, silicon nitride and aluminum oxide;

[0117] The material of the floating field plate 15 is TiN;

[0118] The material of the drain interconnection layer 18 is a TiN / Al / TiN multilayer metal layer-by-layer structure (i.e. TiN, Al and TiN are layer-by-layer from bottom to top).

[0119] In the embodiment, the thickness of the nucleation layer 2 is 1-3 nm;

[0120] The thickness of the buffer layer 3 is 1-6 μm;

[0121] The thickness of the channel layer 4 is 50-500 nm;

[0122] The thickness of the barrier layer 6 is 10-20 nm;

[0123] The thickness of the first passivation layer 11 and the second passivation layer 14 is 50-300nm;

[0124] The thickness of the third passivation layer 16 is 300nm-600nm;

[0125] The thickness of the AlN layer 9 is 2-5nm;

[0126] The thickness of the first CuCrO2 layer 10 is 80-150nm;

[0127] The thickness of the floating field plate 15 is 80-150nm.

[0128] In this embodiment, the width of the nucleation layer 2 is the same as the width of the substrate 1;

[0129] The width of the buffer layer 3 is the same as the width of the nucleation layer 2;

[0130] A mesa is formed in the upper side of the buffer layer 3;

[0131] The width of the channel layer 4 is the same as the width of the mesa;

[0132] The width of the spacer layer 5 is the same as the width of the channel layer 4;

[0133] The width of the barrier layer 6 is the same as the width of the spacer layer 5.

[0134] In this embodiment, the distance between the source 7 and the left sidewall of the first CuCrO2 layer 10 is smaller than the distance between the source 7 and the left sidewall of the gate 13, and the distance between the drain 8 and the right sidewall of the first CuCrO2 layer 10 is smaller than the distance between the drain 8 and the right sidewall of the gate 13; the distance between the first CuCrO2 layer 10 and the source 7 is smaller than the distance between the first CuCrO2 layer 10 and the drain 8, which means that the first CuCrO2 layer 10 is located between the source 7 and the drain 8 and closer to the source 7; the left and right sides of the first CuCrO2 layer 10 generally represent the left and right sides of the gate, and a larger Lgd (the distance between the first CuCrO2 layer 10 and the drain 8) can bring a higher device breakdown, and a smaller Lgs (the distance between the first CuCrO2 layer 10 and the source 7) can result in a small resistance and a stronger current regulation ability, so it is closer to the source 7. Due to the distance relationship between the first CuCrO2 layer 10, the source 7 and the drain 8, the distance between the gate 13 and the source 7 is smaller than the distance between the gate 13 and the drain 8.

[0135] In the embodiment, the floating field plate 15 is in an inverted L shape, and the source field plate 17 and the drain interconnection layer 18 are in a T shape. The structure can optimize the electric field distribution, reduce the probability of electron tunneling from the barrier layer 6 between the gate 13 and the drain 8 to the surface traps, hinder the formation of the dummy gate effect, weaken the dummy gate effect, and effectively inhibit the current collapse effect of the device.

[0136] In the embodiment, the upper surface of the second CuCrO2 layer 12 is flush with the upper surface of the first CuCrO2 layer 10, the hole concentration of the first CuCrO2 layer 10 is 10 18 -10 20 cm -3 , and the hole concentration of the second CuCrO2 layer 12 is 10 16 -10 18 cm -3 .

[0137] As Figures 1 to 15 shown, the application also provides a preparation method of the p-type gate structure normally-off GaN HEMT device. The method needs to provide the p-type gate structure normally-off GaN HEMT device as described above, and includes the following steps:

[0138] Step 1: sequentially epitaxially growing a nucleation layer 2, a buffer layer 3, a channel layer 4, a spacer layer 5 and a barrier layer 6 on the substrate 1 from bottom to top; the epitaxial growth is performed by using one of MOCVD, HVPE and MBE;

[0139] Step 2: etching a source recess 19 and a drain recess 20 on the left side and the right side of the barrier layer 6 respectively, and etching a first recess 21 on the barrier layer 6 between the source recess 19 and the drain recess 20 and close to the drain recess 20; after etching, treating the source recess 19, the drain recess 20 and the first recess 21 by using an inorganic solution or an organic solution to repair the etching damage; the inorganic solution is an HF solution, an HCL / H2O2 solution, a KOH solution or a TMAH solution, and the organic solution is an NMP solution. Through the solution treatment, the interface roughness can be effectively improved, the etching damage can be optimized, the ohmic contact can be effectively optimized, and the contact resistance can be reduced. Then, a source 7 is prepared above the source recess 19, and a drain 8 is prepared above the drain recess 20; the source 7 and the drain 8 preferably adopt one of a Ti / Al / Ni / Au multilayer metal stacked structure, a Ti / Al / TiN multilayer metal stacked structure, a Ti / Al / Ti / Au multilayer metal stacked structure and a Ti / Al / Ti / TiN multilayer metal stacked structure;

[0140] Step 3, isolation is performed by ion implantation or etching on the left upper side of the buffer layer 3, the left side of the channel layer 4, the left side of the spacer layer 5 and the left side of the barrier layer 6, and the right upper side of the buffer layer 3, the right side of the channel layer 4, the right side of the spacer layer 5 and the right side of the barrier layer 6, and preferably F ion or N ion implantation is used; high temperature annealing is performed after ion implantation to repair lattice damage;

[0141] Step 4, an AlN layer 9 is deposited on the barrier layer 6, the source 7 and the drain 8 by a low-temperature deposition process, and a second recess 24 is formed at the first recess 21;

[0142] Step 5, a first CuCrO2 layer 10 is prepared between the source 7 and the drain 8 above part of the AlN layer 9 and close to the second recess 24 using a radio frequency magnetron sputtering process, and high temperature annealing is performed; the growth parameters for growing the first CuCrO2 layer 10 using the radio frequency magnetron sputtering process are as follows: Ar atmosphere 70 sccm, target material is CuCrO2 target, sputtering pressure is 2.0 Pa, and p-type CuCrO2 film is grown at room temperature. After the magnetron sputtering operation, the first CuCrO2 layer 10 is stripped and then subjected to rapid thermal annealing treatment at a temperature of 700-900℃ for 5 min.

[0143] Step 6, a first passivation layer 11 is prepared on the surface of the AlN layer 9, the source 7, the first CuCrO2 layer 10, the drain 8 and the second recess 24 using a low-temperature deposition process or a high-temperature low-pressure process; the low-temperature deposition process is an inductively coupled plasma chemical vapor deposition process or an atomic layer deposition device (ALD), the reaction chamber temperature in the inductively coupled plasma chemical vapor deposition (PECVD) is 100-350℃, and the reaction chamber temperature in the atomic layer deposition device (ALD) is 50-450℃; the high-temperature low-pressure deposition process is a low-pressure chemical vapor deposition (LPCVD), and the temperature of the reaction chamber is 650-800℃.

[0144] Step 7, a gate recess 25 is opened in the middle of the first passivation layer 11 to the upper surface of the first CuCrO2 layer 10 using ICP etching technology, and a second CuCrO2 layer 12 is formed below the gate recess 25 and on the upper side of the first CuCrO2 layer 10 after oxygen plasma treatment; then a gate 13 is prepared on the second CuCrO2 layer 12 in the gate recess 25 to form a Schottky contact; the gate 13 adopts one of a Ti / Al multilayer metal stacked structure, a Ti / Au multilayer metal stacked structure and a TiN / Al / TiN multilayer metal stacked structure;

[0145] Step 8, a second passivation layer 14 is prepared above the first passivation layer 11 and the gate 13 using a low-temperature deposition process;

[0146] Step 9, preparing a floating field plate 15 on the second passivation layer 14 and the gate 13;

[0147] Step 10, preparing a third passivation layer 16 above the second passivation layer 14 and the floating field plate 15 using a low-temperature deposition process;

[0148] Step 11, etching the regions of the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 above the source 7 using ICP etching technology to open a source window 26; etching the regions of the AlN layer 9, the first passivation layer 11, the second passivation layer 14 and the third passivation layer 16 above the drain 8 using ICP etching technology to open a drain window 27;

[0149] Step 12, depositing a source field plate 17 in the source window 26 and depositing a drain interconnection layer 18 in the drain window 27.

[0150] The principle of the p-type gate structure normally-off GaN HEMT device structure of the application is that:

[0151] As shown in Figure 16 (a), it is the energy band structure diagram of a normally-on AlGaN / GaN HEMT device, due to the polarization reaction of the GaN material, the conduction band of the GaN is curved, forms an electron potential well with the AlGaN, and the potential well is below the Fermi level; as shown in Figure 16 (b), with the introduction of CuCrO2, the holes of the material itself will deplete the 2DEG in the channel below, causing the energy band to move up, and the potential well to be higher than the Fermi level, thus causing the threshold voltage to be positive. Using the ternary compound CuCrO2 gate structure to replace the traditional p-GaN, p-Cu2O or p-NiO gate structure, due to the formation of a new hybrid orbital, the restriction of the O-2p orbital on the hole is effectively reduced, and the hole carrier concentration is greatly improved. The hole concentration can be as high as 10 20 cm -3 , greater than the hole concentration of Cu2O, which can more effectively deplete the two-dimensional electron gas under the channel, so that the device realizes normally-off device without external bias. At the same time, its energy band structure is similar to that of NiO, and the band gap is larger than that of Cu2O. After oxygen plasma treatment, the hole concentration will decrease. For the gate 13, the work function is consistent, the potential barrier height is certain, and the decrease of the hole concentration can effectively avoid tunneling, reduce the leakage of the gate 13, and effectively improve the breakdown of the gate 13.

[0152] Example 1

[0153] Referring to Figure 15The p-gate structure normally-off GaN HEMT device of the embodiment includes a substrate 1, which is silicon in this example; and a nucleation layer 2 (AlN in this example), a buffer layer 3 (carbon-doped GaN in this example), a channel layer 4 (GaN in this example), a spacer layer 5 (AlN in this example), and a barrier layer 6 (AlGaN in this example) are sequentially grown on the substrate 1 from bottom to top. 0.18 Ga 0.82 N); the barrier layer 6 is provided with a source electrode 7 and a drain electrode 8 at two ends above the barrier layer 6, the source electrode 7 is on the left side, and the drain electrode 8 is on the right side; a first recess 21 is arranged between the source electrode 7 and the drain electrode 8 close to the drain electrode 8; an AlN layer 9 is arranged above the barrier layer 6, the source electrode 7, the drain electrode 8, and the first recess 21 to form a second recess 24; a first CuCrO2 layer 10 is arranged above the AlN layer 9; a first passivation layer 11 (SiN in this example) is arranged above the AlN layer 9, the source electrode 7, the first CuCrO2 layer 10, the drain electrode 8, and the second recess 24; a gate recess 25 is arranged in the middle of the first passivation layer 11 and the upper middle of the first CuCrO2 layer 10; a second CuCrO2 layer 12 is arranged in the gate recess 25 above the first CuCrO2 layer 10; a gate electrode 13 is arranged in the gate recess 25 above the second CuCrO2 layer 12; a second passivation layer 14 (SiN in this example) is arranged above the gate electrode 13; a floating field plate 15 is arranged above the second passivation layer 14; a third passivation layer 16 (SiO2 in this example) is arranged above the floating field plate 15; a source field plate 17 is arranged above the source electrode 7 and part of the third passivation layer 16; and a drain interconnection layer 18 is arranged above the drain electrode 8 and part of the third passivation layer 16. x x The preparation method of the p-gate structure normally-off GaN HEMT device includes the following steps.

[0154] The preparation method of the p-gate structure normally-off GaN HEMT device includes the following steps. Figures 1 to 15

[0155] (1) Silicon is provided as the substrate 1, the thickness of the substrate 1 is 1000 μm, and single-side polishing standard RCA cleaning is performed, in which organic cleaning is first performed, and acetone and ethanol solutions are used for ultrasonic cleaning; secondly, standard RCA cleaning is used. First, a sulfuric acid: hydrogen peroxide = 3:1 solution is used for cleaning; then a hydrofluoric acid and water 1:20 solution is used for cleaning at room temperature; and finally, an ammonia water, hydrogen peroxide and water 1:1:5 solution is used for cleaning. The cleaning function can remove organic matter and oxides on the surface; the substrate 1 is 6 inches, and silicon is used as the substrate 1 because of its low cost, good electrical and thermal conductivity, and mature application in the industry, which is conducive to the hetero-integration of silicon-based devices.

[0156] ​​(2) On the silicon substrate 1, using metal organic chemical vapor phase epitaxy (MOCVD), in the reaction chamber, using trimethylaluminum (TMAl), trimethylgallium (TMGa), ammonia (NH3) as Al source, Ga source, N source, hydrogen (H2) and nitrogen (N2) as carrier gas, from top to bottom, growing 1 nm thick nucleation layer 2 (in this case, using AlN), 5.2 μm thick buffer layer 3 (in this case, using carbon-doped GaN), 200 nm thick channel layer 4 (in this case, using GaN), 0.5 nm thick spacer layer 5 (in this case, using AlN) and 15 nm thick barrier layer 6 (in this case, using Al 0.18 Ga 0.82 N). Among them, the nucleation layer 2 is to guide the newly formed crystal nucleus, promote the growth of the crystal grain, and improve the crystallinity of the material; the buffer layer 3 is to reduce the defect density of the epitaxial layer and increase the breakdown voltage of the device; the channel layer 4 is to form a natural conductive channel at the interface between the upper spacer layer 5 and the barrier layer 6, that is, to form a 2DEG.

[0157] (3) Organic and inorganic cleaning of the silicon-based AlGaN epitaxial wafer.

[0158] (4) After photolithography and development, using inductively coupled plasma (ICP) technology, Cl-based dry etching of the barrier layer 6, etching out the ohmic grooves of the source electrode 7 and the drain electrode 8 (i.e. the source electrode groove 19 and the drain electrode groove 20), and the first groove 21 with a depth of about 5-10 nm on the side of the source electrode groove 19 and the drain electrode groove 20 close to the drain electrode groove 20. After etching, TMAH solution or KOH solution is used for etching damage repair. In this case, the first groove 21 optimizes the gate-drain electric field distribution and improves the breakdown voltage of the overall device. The first groove 21 can be etched multiple times to form a stepped groove, effectively optimizing the gate-drain electric field distribution.

[0159] (5) After the source electrode groove 19 and the drain electrode groove 20 are developed by double-layer photoresist lithography, Ti / Al / Ni / Au multilayer metal is deposited on the surface of the barrier layer 6 in the source electrode groove 19 and the drain electrode groove 20 by electron beam evaporation equipment, and after lift-off process, annealing at 850°C for 45s, the source electrode 7 and the drain electrode 8 with ohmic contact are formed; the first layer of Ti reacts with Al, GaN or AlGaN diffused to the surface to form TiN, and AlTi3 is also produced, forming N vacancies on the barrier layer 6, which increases the electron concentration of the metal contact surface with AlGaN, similar to N-type doping, promoting the formation of ohmic contact; the role of Ni is to block the downward diffusion of Au and reduce the reaction between Au and Al; the role of Al is to form an alloy with Ti, which has low resistivity and improves the good conductivity effect; the role of Au is to prevent Ti and Al from being oxidized, improving the thermal stability of the ohmic contact.

[0160] (6) After photoresist development, N ion implantation is performed on the left upper side of the buffer layer 3, the left side of the channel layer 4, the left side of the spacer layer 5, and the left side of the barrier layer 6, and on the right upper side of the buffer layer 3, the right side of the channel layer 4, the right side of the spacer layer 5, and the right side of the barrier layer 6, using an ion implantation device, followed by rapid thermal annealing to repair lattice damage, with an annealing temperature of 700-850°C.

[0161] (7) A 3 nm thick AlN layer 9 is deposited using an atomic layer deposition device, which increases the polarization of the III-V compound through the AlN layer 9, increases the concentration of the channel two-dimensional electron gas, improves the current, and reduces the overall resistance, while the AlN has high thermal conductivity, which, in combination with the first groove 21, effectively improves the heat dissipation of the device.

[0162] (8) After double-layer resist photoresist development, a CuCrO2 window is defined, and a radio frequency magnetron sputtering table is used, with a radio frequency power of 100 W, a pure CuCrO2 target is used in the reaction chamber, high-purity Ar is used as the reaction gas, the gas flow is 70 sccm, the sputtering gas pressure is 2.0 Pa, and the CuCrO2 thin film is grown at room temperature. After that, the first CuCrO2 layer 10 in the gate 13 area is left through the lift-off process, with a thickness of 80 nm-100 nm, and rapid thermal annealing is performed on it in an oxygen atmosphere, with a temperature of 700-850°C.

[0163] (9) A 100 nm-300 nm thick first passivation layer 11 (SiN is used in this example) is grown using a low-pressure chemical vapor deposition device under the conditions of a power of 450 W, a temperature of 700-850°C, and a pressure of 12.5 Pa, using SiH4 and NH3 gas. x )。

[0164] (10) After photoresist development, the gate groove 25 is defined, and the first passivation layer 11 above the first CuCrO2 layer 10 and the middle part of the upper side of the first CuCrO2 layer 10 are opened using inductive coupled plasma (ICP) technology, which separates the first passivation layer 11 into left and right areas.

[0165] (11) The first CuCrO2 layer 10 is subjected to oxygen plasma treatment, with a power of 500 W and an O2 flow rate of 20 sccm; the upper layer is oxidized, the hole concentration is reduced, and it becomes the second CuCrO2 layer 12, and the lower layer maintains the original high hole concentration.

[0166] (12) After the double-layer photoresist lithography and development, the gate 13 area is defined, and Ti / Au metal is plated by using an electron beam evaporation device. After a stripping process, a Schottky gate 13 is obtained. Ti is selected as the metal for preparing the Schottky gate because its work function is greatly different from that of the CuCrO2 material. Au is introduced to prevent metal oxidation and to reduce the resistance of the gate 13.

[0167] (13) A 100 nm-300 nm thick second passivation layer 14 (SiN x is used in this example) is grown by using SiH4 and NH3 gases under the conditions of a power of 450 W, a temperature of 350°C, and a pressure of 12.5 Pa by using a plasma chemical vapor deposition device. x Compared with the single-layer SiN x , the stacked passivation of SiN and AlN can reduce the leakage current and effectively improve the breakdown.

[0168] (14) A TiN floating field plate 15 with a thickness of 80-150 nm is obtained by using a MOCVD device and a stripping process. The floating field plate 15 with a reverse "L" shape is supported by the first groove 21 based on etching, optimizes the electric field distribution of the gate leakage, greatly improves the breakdown voltage of the device, reduces the probability of electron tunneling from the gate 13 to the surface trap through the barrier layer 6 between the gate 13 and the drain 8, hinders the formation of the dummy gate effect, weakens the dummy gate effect, and effectively suppresses the current collapse effect of the device.

[0169] (15) A 300 nm-600 nm thick third passivation layer 16 (SiN x is used in this example) is grown by using SiH4 and NH3 gases under the conditions of a power of 450 W, a temperature of 350°C, and a pressure of 12.5 Pa by using a plasma chemical vapor deposition device.

[0170] (16) After lithography and development, the source window 26 and the drain window 27 are defined, and the first passivation layer 11, the second passivation layer 14, and the third passivation layer 16 are etched by using an inductively coupled plasma (ICP) technology, a F-based dry etching method, and a Cl-based dry etching method. The source 7 and the drain 8 are perforated.

[0171] (17) After the double-layer photoresist lithography and development, the source field plate 17 area is defined, and TiN / Al / TiN metal is plated by using a MOCVD device. After a stripping process, the source field plate 17 and the drain interconnection layer 18 are obtained. The thickness of the first layer of TiN is 80-100 nm, the thickness of Al is 200-500 nm, and the thickness of the top TiN is 120-180 nm. The source field plate 17 greatly improves the breakdown voltage of the device.

[0172] In this example, the width Wg of the gate 13 is 100 μm, the length Lg of the gate 13 is 5 μm, the distance Lgs between the gate 13 and the source 7 is 3 μm, the distance Lgd between the gate 13 and the drain 8 is 16 μm, and the metal length Ls of the source 7 and the drain 8 is Lg = 3 μm.

[0173] The above merely describes some embodiments of the present application, and is not intended to limit the protection scope of the present application. Any equivalent device or equivalent process transformation, or direct or indirect application in other related technical fields, which is made according to the content of the present application specification and drawings, is also included in the patent protection scope of the present application.

Claims

1. A p-gate structure normally-off GaN HEMT device, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. The substrate, the nucleation layer, the buffer layer, the channel layer, the spacer layer and the barrier layer are sequentially stacked from bottom to top. The left side of the barrier layer is provided with a source recess, the right side of the barrier layer is provided with a drain recess, and a first recess is arranged between the source recess and the drain recess and close to the drain recess. The source is arranged on the source recess, and the drain is arranged on the drain recess. The left side of the barrier layer, the left side of the spacer layer, the left side of the channel layer and the left upper side of the buffer layer are provided with a left isolation groove, and the right side of the barrier layer, the right side of the spacer layer, the right side of the channel layer and the right upper side of the buffer layer are provided with a right isolation groove. The AlN layer is arranged on the barrier layer, the source and the drain and forms a second recess at the first recess. The first CuCrO2 layer is arranged above part of the AlN layer and between the source and the drain and close to the second recess. The first passivation layer covers the AlN layer, the source, the first CuCrO2 layer, the drain and the second recess. The middle part of the first passivation layer to the upper surface of the first CuCrO2 layer is provided with a gate recess. The second CuCrO2 layer is arranged directly below the gate recess and on the upper side of the first CuCrO2 layer. The lower side of the gate is arranged in the gate recess and above the second CuCrO2 layer, and the upper side of the gate is arranged above part of the first passivation layer. The second passivation layer covers the first passivation layer and the gate. The lower side of the floating field plate is arranged in the second passivation layer and right of the gate and directly above the second recess, and the upper side of the floating field plate is arranged above part of the second passivation layer and directly above the gate. The third passivation layer covers the second passivation layer and the floating field plate. The region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the source is provided with a source window, and the lower side of the source field plate is arranged in the source window and the upper side thereof is arranged above part of the third passivation layer. The region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the drain is provided with a drain window, and the lower side of the drain interconnection layer is arranged in the drain window and the upper side thereof is arranged above part of the third passivation layer. The material of the substrate comprises one of sapphire, silicon, gallium nitride, silicon carbide, ceramic poly-aluminum nitride composite material, insulating silicon base and diamond.

2. A p-gate normally-off GaN HEMT device as claimed in claim 1, wherein, The material of the nucleation layer is aluminum nitride. The material of the channel layer is gallium nitride. The material of the buffer layer is one of iron-containing or carbon-doped gallium nitride, AlN and GaN multilayer alternately grown superlattice and Al x1 Ga 1-x1 N The source and the drain adopt one of a Ti / Al / Ni / Au multilayer metal sequential stacking structure, a Ti / Al / TiN multilayer metal sequential stacking structure, a Ti / Al / Ti / Au multilayer metal sequential stacking structure and a Ti / Al / Ti / TiN multilayer metal sequential stacking structure. The material of the barrier layer is Al x2 Ga 1-x2 N, x2 is 0.1-0.25; ​ The gate is one of Ti / Al multi-layer metal, Ti / Au multi-layer metal and TiN / Al / TiN multi-layer metal; The material of the first, second and third passivation layers comprises one or more of silicon dioxide, silicon nitride and aluminum oxide; The material of the floating field plate is TiN; The material of the drain interconnection layer is TiN / Al / TiN multi-layer metal.

3. A p-gate normally-off GaN HEMT device as claimed in claim 1, wherein, The thickness of the nucleation layer is 1-3 nm; The thickness of the buffer layer is 1-6 μm; The thickness of the channel layer is 50-500 nm; The thickness of the barrier layer is 10-20 nm; The thickness of the first and second passivation layers is 50-300 nm; The thickness of the third passivation layer is 300-600 nm; The thickness of the AlN layer is 2-5 nm; The thickness of the first CuCrO2 layer is 80-150 nm; The thickness of the floating field plate is 80-150 nm.

4. A p-gate normally-off GaN HEMT device as claimed in claim 1, wherein, The width of the nucleation layer is the same as the width of the substrate; The width of the buffer layer is the same as the width of the nucleation layer; The upper side of the buffer layer is formed with a mesa; The width of the channel layer is the same as the width of the mesa; The width of the spacer layer is the same as the width of the channel layer; The width of the barrier layer is the same as the width of the spacer layer.

5. A p-gate normally-off GaN HEMT device as claimed in claim 1, wherein, The distance between the source and the left sidewall of the first CuCrO2 layer is smaller than the distance between the source and the left sidewall of the gate, the distance between the drain and the right sidewall of the first CuCrO2 layer is smaller than the distance between the drain and the right sidewall of the gate, the distance between the first CuCrO2 layer and the source is smaller than the distance between the first CuCrO2 layer and the drain, and the distance between the gate and the source is smaller than the distance between the gate and the drain.

6. A p-gate normally-off GaN HEMT device as claimed in claim 1, wherein, The floating field plate is in an inverted L shape, and the source field plate and the drain interconnection layer are in a T shape.

7. A p-gate structure normally-off GaN HEMT device as claimed in claim 1, wherein, The upper surface of the second CuCrO2 layer is flush with the upper surface of the first CuCrO2 layer, the hole concentration of the first CuCrO2 layer being 10 18 -10 20 cm -3 , the hole concentration of the second CuCrO2 layer being 10 16 -10 18 cm -3 .

8. A method for fabricating a p-gate normally-off GaN HEMT device, characterized in that, The method provides a p-type gate structure normally-off GaN HEMT device according to any one of claims 1-7, and comprises the following steps: Step 1, epitaxially growing a nucleation layer, a buffer layer, a channel layer, a spacer layer and a barrier layer on the substrate from bottom to top; Step 2, etching a source recess and a drain recess on the left side and the right side of the barrier layer respectively, etching a first recess on the barrier layer between the source recess and the drain recess and close to the drain recess, and preparing a source above the source recess and a drain above the drain recess; Step 3, isolating the left upper side of the buffer layer, the left side of the channel layer, the left side of the spacer layer and the left side of the barrier layer, and the right upper side of the buffer layer, the right side of the channel layer, the right side of the spacer layer and the right side of the barrier layer by ion implantation or etching, and performing high-temperature annealing; Step 4, depositing an AlN layer on the barrier layer, the source and the drain, and forming a second recess at the first recess; Step 5, preparing a first CuCrO2 layer above part of the AlN layer and between the source and the drain and close to the second recess, and performing high-temperature annealing on the first CuCrO2 layer; Step 6, preparing a first passivation layer on the surface of the AlN layer, the source, the first CuCrO2 layer, the drain and the second recess; Step 7, a gate recess is formed in the middle of the first passivation layer to the upper surface of the first CuCrO2 layer, a second CuCrO2 layer is formed by oxygen plasma treatment under the gate recess and on the upper side of the first CuCrO2 layer, and a gate is prepared on the second CuCrO2 layer in the gate recess to form a Schottky contact; Step 8, a second passivation layer is prepared on the first passivation layer and the gate; Step 9, a floating field plate is prepared on the second passivation layer and the gate; Step 10, a third passivation layer is prepared on the second passivation layer and the floating field plate; Step 11, a source window is formed in the region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the source, and a drain window is formed in the region of the AlN layer, the first passivation layer, the second passivation layer and the third passivation layer above the drain; Step 12, a source field plate is deposited in the source window, and a drain interconnection layer is deposited in the drain window.

9. The method of claim 8, wherein the p-gate structure is formed by depositing a p-type gate layer on the surface of the GaN layer, and etching the p-type gate layer to form a p-gate structure. The epitaxial growth in step 1 adopts one of MOCVD, HVPE and MBE; the ion implantation in step 3 uses F ion or N ion implantation; the deposition of the AlN layer in step 4 adopts a low-temperature deposition process; the preparation of the first CuCrO2 layer in step 5 adopts a radio frequency magnetron sputtering process; the preparation of the first passivation layer in step 6 adopts a low-temperature deposition process or a high-temperature low-pressure process; the preparation of the second passivation layer in step 8 adopts a low-temperature deposition process; the preparation of the third passivation layer in step 10 adopts a low-temperature deposition process; and the formation of the gate recess, the source window and the drain window in steps 7 and 11 adopts ICP etching technology.

10. The method for fabricating a normally-off GaN HEMT device with a p-type gate structure as described in claim 8, characterized in that, In step 2, before the source and the drain are prepared, the source recess, the drain recess and the first recess are treated with an inorganic solution or an organic solution, the inorganic solution is HF solution, HCL / H2O2 solution, KOH solution or TMAH solution, and the organic solution is NMP solution.

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