Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a first channel layer and a second channel layer spaced apart from each other in a first direction and each including a two-dimensional (2D) semiconductor material; a first source electrode between the first channel layer and the second channel layer to contact the first channel layer and the second channel layer at the same time; a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and to be simultaneously in contact with the first channel layer and the second channel layer; a first gate electrode disposed in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer; and a first gate insulating layer surrounding the first gate electrode in the first internal space.

Description

Technical Field

[0001] Various non-limiting example embodiments generally relate to semiconductor devices and / or methods of fabricating semiconductor devices. Background Art

[0002] A transistor is a semiconductor device having an electrical switching function and is used in various integrated circuit devices including memory devices, driver integrated circuits (ICs), logic devices, etc. In order to increase the integration of IC devices, the space occupied by transistors included in IC devices is rapidly reduced. In this way, the channel length of the transistor is reduced and / or the thickness of the layer forming the transistor is also reduced.

[0003] Because silicon semiconductors reach a limit in physically reducing gate length, three-dimensional (3D) structures have been proposed that can increase the direct contact area of ​​the gate around the channel to obtain additional gate control.

[0004] Additionally or alternatively, interest in two-dimensional (2D) semiconductors, which are thin semiconductor materials with better gate control than silicon, has increased. Processing methods have been sought to fabricate 3D transistor structures using 2D semiconductor materials. Summary of the invention

[0005] Provided are a semiconductor device and / or a method of manufacturing a semiconductor device by using a two-dimensional (2D) semiconductor material.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to some example embodiments, a semiconductor device is provided, comprising: a first channel layer and a second channel layer arranged to be spaced apart in a first direction, wherein the first channel layer comprises a first two-dimensional (2D) semiconductor material and the second channel layer comprises a second 2D semiconductor material that is the same as or different from the first 2D semiconductor material; a first source electrode between the first channel layer and the second channel layer to contact the first channel layer and the second channel layer at the same time; a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and to contact the first channel layer and the second channel layer at the same time; a first gate electrode in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer; and a first gate insulating layer surrounding the first gate electrode in the first internal space.

[0008] Alternatively or additionally, according to various example embodiments, an electronic device is provided, the electronic device including a semiconductor device and a controller configured to control the semiconductor device, wherein the semiconductor device includes: a first channel layer and a second channel layer arranged to be spaced apart in a first direction, wherein the first channel layer includes a first two-dimensional (2D) semiconductor material and the second channel layer includes a second 2D semiconductor material that is the same as or different from the first 2D semiconductor material; a first source electrode, between the first channel layer and the second channel layer to simultaneously contact the first channel layer and the second channel layer; a first drain electrode, between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and to simultaneously contact the first channel layer and the second channel layer; a first gate electrode, in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer; and a first gate insulating layer surrounding the first gate electrode in the first internal space.

[0009] Alternatively or additionally, according to various example embodiments, a method for manufacturing a semiconductor device is provided, comprising: forming a first channel layer comprising a first two-dimensional (2D) semiconductor material; and forming a first source electrode and a first drain electrode contacting the first channel layer and spaced apart from each other; forming a second channel layer, the second channel layer contacting the first source electrode and the first drain electrode, spaced apart from the first channel layer, and comprising a second 2D semiconductor material that is the same as or different from the first 2D semiconductor material; conformally forming a first gate insulating layer along an inner wall of a first internal space surrounded by the first channel layer, the second channel layer, the first source electrode, and the first drain electrode; and forming a first gate electrode in an area surrounded by the first gate insulating layer in the first internal space. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of certain non-limiting example embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a partially cutaway perspective view schematically illustrating a structure of a semiconductor device according to some example embodiments;

[0012] Figure 2 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to some example embodiments;

[0013] FIG. 3A to FIG. 3J are diagrams for describing a method of manufacturing a semiconductor device according to some example embodiments;

[0014] FIG. 4A to FIG. 4D are diagrams for describing a method of manufacturing a semiconductor device according to some example embodiments;

[0015] Figure 5It is a cross-sectional transmission electron micrograph of a fabricated semiconductor device;

[0016] Figure 6 is a schematic block diagram of a display driver integrated circuit (IC) (DDI) and a display device including the DDI according to some example embodiments;

[0017] Figure 7 is a circuit diagram of a complementary metal oxide semiconductor (CMOS) inverter according to some example embodiments;

[0018] Figure 8 is a circuit diagram of a CMOS static random access memory (SRAM) device according to some example embodiments;

[0019] Fig. 9 is a circuit diagram of a CMOS NAND circuit according to some example embodiments;

[0020] Fig.10 is a block diagram of an electronic device according to some example embodiments; and

[0021] Fig.11 is a block diagram of an electronic device according to some example embodiments. DETAILED DESCRIPTION

[0022] Some embodiments will now be referred to in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this respect, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Statements such as "at least one of ... " modify the entire element list when after the element list, without modifying the individual elements in the list.

[0023] The present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments of the present disclosure can be modified in various ways and can be embodied in many different forms. In the accompanying drawings, the same reference numerals represent the same components, and the sizes of the components in the accompanying drawings may be exaggerated for ease of explanation.

[0024] Hereinafter, it will be understood that when a layer, region or component is referred to as being “on” or “over” another layer, region or component, it may be in contact with and directly on the other layer, region or component, or intervening layers, regions or components may be present.

[0025] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. These terms do not limit the fact that the materials or structures of the components are different from each other.

[0026] Unless the context clearly has a different meaning, expressions used in the singular include plural expressions. It will be further understood that when a part is said to "include" another part, the part may not exclude the other part but may further include the other part unless the context otherwise indicates.

[0027] Furthermore, the terms "... unit" and "... module" used herein indicate a unit for processing at least one function or operation, and this can be implemented by hardware or software or a combination of hardware and software.

[0028] The use of the term "above" and similar indicative terms may correspond to both the singular and the plural.

[0029] In addition, unless otherwise specified herein or unless the context is clearly contradictory, the steps of all methods described herein can be performed in any suitable order. In addition, the use of all exemplary terms (e.g., etc.) is only used to describe the technical spirit in detail, and the scope of rights is not limited by these terms unless the context is limited by the claims.

[0030] Figure 1 is a partially cut-away perspective view schematically illustrating a structure of a semiconductor device 100 according to some example embodiments.

[0031] The semiconductor device 100 includes a first channel layer 131 and a second channel layer 132 spaced apart from each other, and a first source electrode 151 and a first drain electrode 161 disposed between the first channel layer 131 and the second channel layer 132 to simultaneously contact the first channel layer 131 and the second channel layer 132, respectively. In some example embodiments, the first source electrode 151 may function as a drain electrode, and the first drain electrode may function as a source electrode; example embodiments are not limited thereto.

[0032] The first gate electrode 191 is disposed in an inner space surrounded by the first source electrode 151 , the first drain electrode 161 , the first channel layer 131 , and the second channel layer 132 , and the first gate insulating layer 171 surrounding the first gate electrode 191 is disposed.

[0033] The lower gate electrode 110 and the lower insulating layer 120 may be disposed below the first channel layer 131, and the upper insulating layer 180 and the upper gate electrode 115 may be disposed or at least partially disposed on the second channel layer 132. The lower gate electrode 110 may be formed on a substrate SU. The substrate SU may be a semiconductor substrate, and may include, but is not limited to, one or more of silicon, germanium, silicon germanium, oxide, nitride, and the like.

[0034] The semiconductor device 100 according to various example embodiments uses a two-dimensional (2D) semiconductor material as a channel, and provides a structure in which the 2D semiconductor material is in contact with source and drain surfaces.

[0035] Hereinafter, a detailed structure of the semiconductor device 100 is described below.

[0036] The first channel layer 131 and the second channel layer 132 are spaced apart from each other in a first direction (Z direction). The first channel layer 131 and the second channel layer 132 each include a 2D semiconductor material, for example, may be composed of a 2D semiconductor material. The first channel layer 131 may include the same 2D material as the second channel layer 132 and / or may include a material different from that of the second channel layer 132.

[0037] The 2D semiconductor material included in the first channel layer 131 and the second channel layer 132 may include an N-type 2D semiconductor (such as MoS 2 、MoSe 2 、MoTe 2 , WS 2 etc.) and P-type 2D semiconductors (such as WSe 2 、MoTe 2 , PtSe 2 One or more of the above).

[0038] The first channel layer 131 and the second channel layer 132 may adopt various 2D semiconductor materials. For example, a transition metal dichalcogenide (TMD) material may be used as a 2D semiconductor material. TMD may include a metal element selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and Pb and a chalcogen element selected from the group consisting of S, Se and Te. Alternatively or additionally, one or more of graphene, black phosphorus, amorphous boron nitride, phosphorene, etc. may be used as a 2D semiconductor material.

[0039] The 2D semiconductor material may be doped, for example, with a p-type dopant (such as boron) or an n-type dopant (such as phosphorus and / or arsenic) to adjust the mobility. Here, for example, p-type dopants and n-type dopants used in graphene, carbon nanotubes (CNTs), etc. may be used. The p-type dopant or the n-type dopant may be doped using ion implantation or chemical doping methods.

[0040] When the semiconductor device 100 is used as a field effect transistor, the 2D semiconductor material is used to realize a short channel length CL. The channel length CL (or physical channel length) represents the length of the channel region in the direction (X direction) in which the source electrode and the drain electrode are spaced apart from each other, that is, Figure 1 As shown, it represents the length of the first gate electrode 191 in the X direction. According to the miniaturization trend of electronic devices, the channel length has been reduced. As the channel length becomes shorter, problems caused by the short channel effect arise. It may be advantageous to reduce the thickness of the channel region so as to effectively reduce or help reduce the channel length and prevent or improve the above-mentioned problems. To this end, 2D semiconductor materials are used in the first channel layer 131 and the second channel layer 132, so that a reduced or minimum channel length that can be achieved can be set (for example, it can be set as short as possible).

[0041] 2D semiconductor materials have excellent electrical properties, so even when the thickness is reduced to the nanoscale, their characteristics will not change greatly, and high mobility can be maintained. 2D semiconductor materials may have a single layer, three layers or a multilayer structure. Each layer in the 2D semiconductor material may have an atomic thickness (e.g., a single atomic layer thickness). The number of layers of the 2D semiconductor material used in the first channel layer 131 and the second channel layer 132 may be set in consideration of the performance of the channel and the total thickness of the channel.

[0042] The thickness of the first channel layer 131 and the second channel layer 132 may be about 10 nm (100 angstroms) or less, for example, 5 nm (50 angstroms) or less or 3 nm (30 angstroms) or less. The thickness of the first channel layer 131 and the second channel layer 132 is not limited to the above examples and may be further reduced. The thickness of the first channel layer 131 may be the same as or different from the thickness of the second channel layer 132 (thicker or thinner than the thickness of the second channel layer 132).

[0043] The channel length CL may be 10 nm or less or 8 nm or less. Alternatively, the channel length CL may also be 7 nm or less, 5 nm or less, or 3 nm or less. However, example embodiments are not limited thereto.

[0044] The first source electrode 151 and the first drain electrode 161 may be arranged such that lower surfaces of the first source electrode 151 and the first drain electrode 161 may contact the first channel layer 131 , and upper surfaces of the first source electrode 151 and the first drain electrode 161 may contact the second channel layer 132 .

[0045] When the 2D semiconductor material is included in the first channel layer 131 and the second channel layer 132, the 2D semiconductor material may not be easy to electrically contact the first source electrode 151 and the first drain electrode 161 through a general semiconductor manufacturing process. A structure according to various example embodiments is provided so that the 2D semiconductor material can electrically contact the first source electrode 151 and the first drain electrode 161 based on an achievable manufacturing process. Figure 3A etc. describe its manufacturing method.

[0046] According to the above arrangement of the first source electrode 151, the first drain electrode 161, the first channel layer 131 and the second channel layer 132, an internal space surrounded by the first source electrode 151, the first drain electrode 161, the first channel layer 131 and the second channel layer 132 can be defined, and the first gate insulating layer 171 and the first gate electrode 191 are arranged in the internal space.

[0047] The first gate insulating layer 171 may be conformally formed along an inner wall of an inner space surrounded by the first source electrode 151 , the first drain electrode 161 , the first channel layer 131 , and the second channel layer 132 , and the first gate electrode 191 may be formed in the space surrounded by the first gate insulating layer 171 .

[0048] As described above, the first gate electrode 191 and the lower gate electrode 110 are respectively arranged on the upper and lower portions of the first channel layer 131, and the upper gate electrode 115 and the first gate electrode 191 are arranged on the upper and lower portions of the second channel layer 132. The first channel layer 131 and the second channel layer 132 include a 2D semiconductor material, and thus, the above arrangement may be provided as or substantially arranged as a gate all around (GAA) structure.

[0049] The first gate insulating layer 171 , the lower insulating layer 120 , and the upper insulating layer 180 all serve as a gate insulating material, and may independently include various insulating materials that may serve as a gate insulating material.

[0050] The insulating material may include a high-k dielectric material having a high dielectric constant greater than that of silicon oxide, and may include aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, etc. However, one or more embodiments are not limited to the above examples.

[0051] In some example embodiments, the insulating material may include a ferroelectric material; however, the example embodiments are not limited thereto. The ferroelectric material has a spontaneous dipole (electric dipole), that is, a spontaneous polarization, in a crystalline material structure because the charge distribution in the unit cell is non-centrosymmetric. Therefore, even when no external electric field is applied to the ferroelectric material, the ferroelectric material has a residual polarization attributed to the dipole. Alternatively or additionally, the polarization direction can be switched on a domain basis by an external electric field. The ferroelectric material may include, for example, at least one oxide selected from hafnium (Hf), silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd) and strontium (Sr). However, these materials are examples. In addition, the ferroelectric material may also include a dopant as needed.

[0052] When a ferroelectric material is used as a gate insulating material, the semiconductor device 100 may be or may correspond to a field effect transistor applied to a logic device or a memory device. Since the subthreshold swing (SS) of the semiconductor device 100 can be reduced by a negative capacitance effect due to the ferroelectric material, the semiconductor device 100 may function as a field effect transistor with improved performance and reduced size.

[0053] In some example embodiments, the gate insulating material may have a multi-layered structure including a high-k material and a ferroelectric material.

[0054] Materials included in the first gate insulating layer 171, the lower insulating layer 120, and the upper insulating layer 180 may be the same as or different from each other. Materials included in the first gate insulating layer 171, the lower insulating layer 120, and the upper insulating layer 180 may be respectively set to be suitable for detailed methods for forming the materials during a manufacturing process.

[0055] As shown, the upper insulating layer 180 is disposed in a region between the second channel layer 132 and the upper gate electrode 115 and may extend to side surfaces of the first source electrode 151 and the first drain electrode 161. However, example embodiments are not limited thereto.

[0056] The first gate electrode 191, the lower gate electrode 110, and the upper gate electrode 115 may independently include a metal material or a conductive oxide. Here, the metal material may include at least one selected from the group consisting of, for example, Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni or including, for example, Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

[0057] Materials included in the first gate electrode 191, the lower gate electrode 110, and the upper gate electrode 115 may be the same and / or different from each other. Materials included in the first gate electrode 191, the lower gate electrode 110, and the upper gate electrode 115 may be respectively set to be suitable for detailed methods for forming the materials during the manufacturing process.

[0058] The first source electrode 151 and the first drain electrode 161 may include a metal material having good (e.g., excellent) conductivity. For example, the first source electrode 151 and the first drain electrode 161 may each independently or simultaneously include a metal such as magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), etc. One or more or alloys thereof.

[0059] The substrate SU may include an insulating substrate or a semiconductor substrate having an insulating layer formed on its surface. The semiconductor substrate may include, for example, Si, Ge, SiGe, or a III-V semiconductor material. The substrate SU may include, for example, a silicon substrate having silicon oxide formed on its surface, but is not limited thereto. The substrate SU may be doped or may be undoped.

[0060] The semiconductor device 100 includes a multi-layer channel including a 2D semiconductor material, and may actually have a GAA structure. Figure 1 The semiconductor device 100 is shown to include two layers, for example, a first channel layer 131 and a second channel layer 132 , but may include more layers.

[0061] Figure 2 is a cross-sectional view schematically illustrating a structure of a semiconductor device 200 according to some example embodiments.

[0062] The semiconductor device 200 and Figure 1 The semiconductor device 100 is different in that the channel structure is arranged in three layers, and only the difference is described below.

[0063] The second source electrode 152 and the second drain electrode 162 are arranged on the second channel layer 132 to be spaced apart from each other. The second source electrode 152 and the second drain electrode 162 may be arranged to contact the upper surface of the second channel layer 132. The third channel layer 133 may be arranged to contact both the upper surface of the second source electrode 152 and the upper surface of the second drain electrode 162 at the same time.

[0064] According to the above arrangement of the second source electrode 152, the second drain electrode 162, the second channel layer 132 and the third channel layer 133, an internal space surrounded by the second source electrode 152, the second drain electrode 162, the second channel layer 132 and the third channel layer 133 can be defined, and the second gate insulating layer 172 and the second gate electrode 192 are arranged in the internal space.

[0065] The second gate insulating layer 172 can be formed along the inner wall of the internal space surrounded by the second source electrode 152, the second drain electrode 162, the second channel layer 132 and the third channel layer 133, for example, can be conformally formed along the inner wall of the internal space, and then, the second gate electrode 192 can be formed in the space surrounded by the second gate insulating layer 172.

[0066] The method of manufacturing a semiconductor device according to various example embodiments includes forming a source electrode and a drain electrode in contact with a channel layer formed of a 2D semiconductor material, and then forming a channel layer in contact with the source electrode and the drain electrode on the source electrode and the drain electrode. The above process can be repeated multiple times. Next, a gate insulating layer corresponding to the multiple channel layers can be formed, and multiple gate electrodes can also be formed.

[0067] A method of manufacturing a semiconductor device according to various example embodiments is described in detail below.

[0068] FIG. 3A to FIG. 3J are diagrams for describing a method of manufacturing a semiconductor device according to some example embodiments.

[0069] refer to Figure 3A , providing a first channel layer 131 including a 2D semiconductor material.

[0070] The first channel layer 131 may be formed on the lower insulating layer 120, and the lower insulating layer 120 may be formed on the lower gate electrode 110. The lower gate electrode 110 may be formed on the substrate SU.

[0071] The first channel layer 131 may be directly formed on the lower insulating layer 120 , or may be manufactured on another substrate and then transferred onto the lower insulating layer 120 .

[0072] The 2D semiconductor material included in the first channel layer 131 may be formed by, for example, one or more of a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, etc. The first channel layer 131 may have a single-layer or multi-layer structure (e.g., a double-layer or triple-layer structure) including the 2D semiconductor material.

[0073] refer to Figure 3B, a metal material layer 140 is formed on the first channel layer 131. The metal material layer 140 may be formed by, for example, a chemical plating method and / or a sputtering method. However, example embodiments are not limited to the above examples.

[0074] refer to Figure 3C , a mask pattern layer 145 for patterning the metal material layer 140 is formed. The mask pattern layer 145 may include, for example, a photoresist material, and may have a pattern corresponding to the source electrode and the drain electrode to be manufactured. An etching process using the mask pattern layer 145 as a mask may be performed. The etching process may include wet etching and / or dry etching. After the etching process, when the mask pattern layer 145 is removed, as shown in FIG. Figure 3D As shown in , the first source electrode 151 and the first drain electrode 161 are provided to contact the upper surface of the first channel layer 131 .

[0075] exist FIG. 3B to FIG. 3D , the process of forming the first source electrode 151 and the first drain electrode 161 is described as a photolithography process as an example, but one or more embodiments are not limited thereto, for example, a lift-off process and / or a damascene process may be used.

[0076] The lift-off process may include, for example, forming a mask layer having a pattern corresponding to the reverse shape of the first source electrode 151 and the first drain electrode 161 to be formed on the first channel layer 131, and forming a metal material layer entirely on the first channel layer 131 provided with the mask layer. Next, when the mask layer is removed, the metal material on the mask layer is also removed, and a metal layer may be provided. Figure 3D The structure shown in .

[0077] The damascene process may include, for example, forming an oxide layer on the first channel layer 131, and then patterning the oxide layer so that the portions where the first source electrode and the first drain electrode are to be formed are opened. Next, a metal material layer is formed on the first channel layer 131 to a thickness that can completely cover the patterned oxide layer, and a chemical mechanical polishing (CMP) process may be performed.

[0078] refer to Figure 3E , a second channel layer 132 is formed on the first source electrode 151 and the first drain electrode 161. The second channel layer 132 may include one or more 2D semiconductor materials that are the same and / or different from the 2D semiconductor material included in the first channel layer 131, and may have a single-layer or multi-layer structure (e.g., a double-layer or triple-layer structure) including a 2D semiconductor material. The second channel layer 132 is formed to be suspended between the first source electrode 151 and the first drain electrode 161, and may be formed by transferring a separately manufactured 2D film. Therefore, a first internal space H1 surrounded by the first channel layer 131, the first source electrode 151, the first drain electrode 161, and the second channel layer 132 may be formed.

[0079] The sizes of the first source electrode 151 and the first drain electrode 161 may be appropriately set so that the second channel layer 132 contacts the first source electrode 151 and the first drain electrode 161 and may be suspended between the first source electrode 151 and the first drain electrode 161. For example, the sum of the lengths of the first source electrode 151 and the first drain electrode 161 in the lateral direction (X direction) may be greater than the length of the first inner space H1 in the lateral direction (X direction).

[0080] The length of the second channel layer 132 (e.g., the length in the direction (X direction) in which the first source electrode 151 and the first drain electrode 161 are spaced apart from each other) may be similar to the length (reference length) from the left end of the first source electrode 151 to the right end of the first drain electrode 161, or may be greater than or less than the reference length. The length of the second channel layer 132 may be, for example, about 90% to about 110% of the reference length. However, example embodiments are not limited thereto, and the lengths shown in the drawings are examples.

[0081] refer to Figure 3F , a second source electrode 152 and a second drain electrode 162 are formed on the second channel layer 132. The process of forming the second source electrode 152 and the second drain electrode 162 may be similar to the process of forming the first source electrode 151 and the first drain electrode 161 on the first channel layer 131; however, example embodiments are not limited thereto. The thickness of the second source electrode 152 and the second drain electrode 162 may be the same as the thickness of the first source electrode 151 and the first drain electrode 161 or greater than or less than the thickness of the first source electrode 151 and the first drain electrode 161.

[0082] refer to Figure 3G , a third channel layer 133 is formed on the second source electrode 152 and the second drain electrode 162 .

[0083] The third channel layer 133 includes a 2D semiconductor material. Similar to the second channel layer 132, the third channel layer 133 may be formed by a transfer process of a 2D film, and may be formed to be suspended between the second source electrode 152 and the second drain electrode 162 while being in contact with the upper portions of the second source electrode 152 and the second drain electrode 162. Thus, a second inner space H2 surrounded by the second channel layer 132, the second source electrode 152, the second drain electrode 162, and the third channel layer 133 may be formed.

[0084] The insulating material may be conformally formed on the inner wall of the first inner space H1 and the inner wall of the second inner space H2, and as shown in FIG. Figure 3HAs shown in , a first gate insulating layer 171 and a second gate insulating layer 172 may be formed. For example, the first gate insulating layer 171 and the second gate insulating layer 172 may be formed simultaneously by the same manufacturing process. The first gate insulating layer 171 and the second gate insulating layer 172 may include the same insulating material. The first gate insulating layer 171 and the second gate insulating layer 172 may be formed by an ALD method. However, one or more embodiments are not limited to the above examples.

[0085] During the process of forming the first gate insulating layer 171 and the second gate insulating layer 172, the upper insulating layer 180 may be at least partially formed. The upper insulating layer 180 may cover the upper surface of the third channel layer 133 and may be formed to extend to the sides of the first source electrode 151, the first drain electrode 161, the second source electrode 152, and the second drain electrode 162.

[0086] Two spaces respectively surrounded by the first gate insulating layer 171 and the second gate insulating layer 172 are positions where the first gate electrode and the second gate electrode are to be formed. The thickness of the first gate insulating layer 171 and the second gate insulating layer 172 may be determined in consideration of a channel length CL of a channel to be formed.

[0087] refer to Fig. 3I , a first gate electrode 191 surrounded by the first gate insulating layer 171 and a second gate electrode 192 surrounded by the second gate insulating layer 172 are formed. The first gate electrode 191 and the second gate electrode 192 may be formed by an ALD method and / or a plasma enhanced CVD (PECVD) process, but are not limited thereto.

[0088] refer to Figure 3J , an upper gate electrode 115 is formed on the upper insulating layer 180 .

[0089] The semiconductor device 200 manufactured above has a three-layer structure as an example, including a first channel layer 131, a second channel layer 132 and a third channel layer 133. Figure 2 As shown in , but one or more embodiments are not limited thereto.

[0090] For example, in Figure 3E In the embodiment, a first gate insulating layer 171 and a first gate electrode 191 may be formed to manufacture the Figure 1 The semiconductor device 100 is shown in FIG.

[0091] FIG. 4A to FIG. 4D are diagrams for describing a method of manufacturing a semiconductor device according to some example embodiments.

[0092] refer to Figure 4A ,exist Figure 3GIn an additional process of the process of , a third source electrode 153 and a third drain electrode 163 are formed on the third channel layer 133 , and a fourth channel layer 134 may be formed on the third source electrode 153 and the third drain electrode 163 .

[0093] As described above, a first internal space H1 surrounded by the first channel layer 131, the first source electrode 151, the first drain electrode 161 and the second channel layer 132, a second internal space H2 surrounded by the second channel layer 132, the second source electrode 152, the second drain electrode 162 and the third channel layer 133, and a third internal space H3 surrounded by the third channel layer 133, the third source electrode 153, the third drain electrode 163 and the fourth channel layer 134 may be provided.

[0094] The insulating material is conformally applied to the inner wall in each of the first to third inner spaces H1, H2 and H3, so that Figure 4B As shown in , a first gate insulating layer 171, a second gate insulating layer 172, and a third gate insulating layer 173 may be formed. The first gate insulating layer 171, the second gate insulating layer 172, and the third gate insulating layer 173 may be formed simultaneously in the same process. In addition, at least a portion of the upper insulating layer 180 may be formed. The size (e.g., length and / or width) of each of the first to third internal spaces H1, H2, and H3 may be the same as or different from each other.

[0095] refer to Figure 4C , a first gate electrode 191 , a second gate electrode 192 , and a third gate electrode 193 may be formed in a space surrounded by the first gate insulating layer 171 , the second gate insulating layer 172 , and the third gate insulating layer 173 , respectively.

[0096] refer to Figure 4D , an upper gate electrode 115 is formed on the upper insulating layer 180 , thereby providing a semiconductor device 300 having a basic GAA structure and four channel layers.

[0097] Figure 5 This is a transmission electron micrograph of a cross-section of a fabricated semiconductor device.

[0098] Identify the 2D semiconductor material MoS 2 A structure that makes good contact with each of the upper and lower surfaces of the source electrode material and the drain electrode material.

[0099] The semiconductor devices according to various example embodiments and the semiconductor devices provided by the manufacturing methods according to various example embodiments can exhibit improved (e.g., excellent) electrical performance with an ultra-small structure and can be applied to integrated circuit devices. The semiconductor devices according to various example embodiments can be used as logic transistors and can be applied to various electronic devices together with a controller that controls the logic transistors.

[0100] The semiconductor devices 100 , 200 , and 300 described above may be used in, for example, one or more of a driver integrated circuit of a display, a complementary metal oxide semiconductor (CMOS) inverter, a CMOS SRAM device, a CMOS NAND circuit, and / or other various electronic devices.

[0101] Figure 6 is a schematic block diagram of a display driver integrated circuit (IC) (DDI) 500 and a display device including the DDI according to some example embodiments.

[0102] refer to Figure 6 , the DDI 500 may include a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508. The controller 502 receives and decodes a command applied from a main processing unit (MPU) 522, and controls each block in the DDI 500 to implement an operation according to the command. The power supply circuit 504 generates a driving voltage in response to a control from the controller 502. The driver block 506 drives the display panel 524 by using the driving voltage generated by the power supply circuit 504 in response to a control from the controller 502. The display panel 524 may include, for example, a liquid crystal display panel, an organic light emitting device (OLED) panel, or a plasma display panel. The memory block 508 is a block for temporarily storing a command input to the controller 502 or a control signal output from the controller 502 and / or for storing required or used data, and may include one or more memories such as a RAM, a ROM, etc. The power supply circuit 504 and the driver block 506 may each include a memory according to the above reference. Figures 1 to 4D One of the semiconductor devices 100 , 200 , and 300 of the various example embodiments described, or a semiconductor device modified and combined therefrom.

[0103] Figure 7 is a circuit diagram of a CMOS inverter 600 according to some example embodiments.

[0104] refer to Figure 7 , the CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a PMOS transistor 620 and an NMOS transistor 630 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 610 may include a transistor according to the above reference Figures 1 to 4D One or more of the semiconductor devices 100 , 200 , and 300 of the various example embodiments described, or semiconductor devices modified and combined therefrom. Either or both of the PMOS transistor 620 and the NMOS transistor 630 may be implemented according to one or more of the semiconductor devices 100 , 200 , and 300 .

[0105] Figure 8 is a circuit diagram of a CMOS SRAM device 700 according to some example embodiments.

[0106] refer to Figure 8 , the CMOS SRAM device 700 includes a pair of driving transistors 710. Each of the pair of transistors 710 includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 700 may further include a pair of transmission transistors 740. The source of the transmission transistor 740 may be cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 that form the driving transistor 710. The power supply terminal Vdd is connected to the source of the PMOS transistor 720, and the ground terminal is connected to the source of the NMOS transistor 730. The word line WL may be connected to the gates of the pair of transmission transistors 740, and the bit line BL and the inverted bit line may be connected to the drains of the pair of transmission transistors 740, respectively. At least one of the driving transistor 710 and the transmission transistor 740 of the CMOS SRAM device 700 may include a transistor according to the above reference. Figures 1 to 4D One of the semiconductor devices 100 , 200 , and 300 of the various example embodiments described, or a semiconductor device modified and combined therefrom.

[0107] Fig. 9 is a circuit diagram of a CMOS NAND circuit 800 according to some example embodiments.

[0108] refer to Fig. 9 CMOS NAND circuit 800 may include a pair of CMOS transistors to which different input signals are transmitted. CMOS NAND circuit 800 may include the above reference Figures 1 to 4D One of the semiconductor devices 100 , 200 , and 300 of the various example embodiments described, or a semiconductor device modified and combined therefrom.

[0109] Fig.10 is a block diagram of an electronic device 900 according to some example embodiments.

[0110] refer to Fig.10 , the electronic device 900 includes a memory 910 and a memory controller 920. The memory controller 920 may control the memory 910 in response to a request from a host 930 to read data from the memory 910 and / or write data to the memory 910. At least one of the memory 910 and the memory controller 920 may include the above reference Figures 1 to 4DOne of the semiconductor devices 100 , 200 , and 300 of the various example embodiments described, or a semiconductor device modified and combined therefrom.

[0111] Fig.11 is a block diagram of an electronic device 1000 according to some example embodiments.

[0112] refer to Fig.11 The electronic device 1000 may be configured as a wireless communication device or a device capable of sending and / or receiving information in a wireless environment. The electronic device 1000 includes a controller 1010, an input / output device (I / O) 1020, a memory 1030, and a wireless interface 1040, which are connected to each other via a bus 1050.

[0113] The controller 1010 may include one or more of a microprocessor, a digital signal processor, and at least one similar processing device. The I / O 1020 may include at least one of a keypad, a keyboard, and a display. The memory 1030 may be used to store commands executed by the controller 1010. For example, the memory 1030 may be used to store user data. The electronic device 1000 may use the wireless interface 1040 to send / receive data via a wireless communication network. The wireless interface 1040 may include an antenna and / or a wireless transceiver. In some embodiments, the electronic device 1000 may be used in a communication interface protocol of a third generation communication system, for example, one or more of code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), extended time division multiple access (E-TDMA), and / or wideband code division multiple access (WCDMA). The electronic device 1000 may include a method according to the above reference. Figures 1 to 4D At least one of the semiconductor devices 100 , 200 , and 300 of the various example embodiments described, or a semiconductor device modified and combined therefrom.

[0114] The semiconductor device may realize a GAA structure by using a 2D semiconductor material.

[0115] Semiconductor devices can be used as logic transistors in various electronic devices.

[0116] According to the method of manufacturing a semiconductor device as described above, a semiconductor device having improved or excellent contact properties between a 2D semiconductor channel and a source electrode / drain electrode can be provided.

[0117] Any element and / or functional block disclosed above may include or be implemented in a processing circuit, the processing circuit being hardware such as including a logic circuit; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include electrical components such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include electrical components such as a logic gate, the logic gate including at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0118] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that no precision of the geometric shape is required, but rather a tolerance of the shape is within the scope of the present disclosure. In addition, when the words "generally" and "substantially" are used in conjunction with a material composition, it is intended that no precision of the material is required, but rather a tolerance of the material is within the scope of the present disclosure.

[0119] In addition, regardless of whether a value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the value or shape. Therefore, although the terms "same", "equivalent" or "equal" are used in the description of example embodiments, it should be understood that there may be some imprecision. Therefore, when an element or a value is referred to as being the same as or equal to another element, it should be understood that the element or value is the same as the other element or another value within the desired manufacturing or operating tolerance range (e.g., ±10%).

[0120] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0121] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0135404 filed in the Korean Intellectual Property Office on October 11, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first channel layer and a second channel layer spaced apart from each other in a first direction, the first channel layer comprising a first two-dimensional 2D semiconductor material and the second channel layer comprising a second 2D semiconductor material, the second 2D semiconductor material being the same as or different from the first 2D semiconductor material; a first source electrode between the first channel layer and the second channel layer to contact the first channel layer and the second channel layer at the same time; a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and to contact both the first channel layer and the second channel layer; a first gate electrode in a first inner space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer; as well as A first gate insulating layer surrounds the first gate electrode in the first inner space.

2. The semiconductor device according to claim 1, further comprising: a lower gate electrode; as well as A lower insulating layer is between the lower gate electrode and the first channel layer.

3. The semiconductor device according to claim 1, further comprising: an upper gate electrode; as well as An upper insulating layer is between the upper gate electrode and the second channel layer.

4. The semiconductor device according to claim 1, further comprising: A third channel layer is spaced apart from the second channel layer in the first direction and includes a third 2D semiconductor material, the third 2D semiconductor material being the same as or different from the first 2D semiconductor material and the same as or different from the second 2D semiconductor material.

5. The semiconductor device according to claim 4, further comprising: a second source electrode between the second channel layer and the third channel layer to contact the second channel layer and the third channel layer at the same time; a second drain electrode between the second channel layer and the third channel layer to be spaced apart from the second source electrode in the second direction and in contact with both the second channel layer and the third channel layer; a second gate electrode in a second inner space surrounded by the second source electrode, the second drain electrode, the second channel layer, and the third channel layer; as well as A second gate insulating layer surrounds the second gate electrode in the second inner space.

6. A semiconductor device according to claim 1, wherein the first 2D semiconductor material comprises one or more of MoS2, MoSe2, MoTe2, WS2, WSe2 and PtSe2, and the second 2D semiconductor material comprises one or more of MoS2, MoSe2, MoTe2, WS2, WSe2 and PtSe2.

7. A semiconductor device according to claim 1, wherein either or both of the first 2D semiconductor material and the second 2D semiconductor material include a metal element selected from Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and Pb and a chalcogen element selected from S, Se and Te. 8 . The semiconductor device according to claim 1 , wherein the first channel layer and the second channel layer each independently comprise a double-layer or triple-layer structure including the first 2D semiconductor material or the second 2D semiconductor material, respectively. 9 . The semiconductor device according to claim 1 , wherein the first channel layer and the second channel layer each independently have a thickness of 3 nm or less. 10 . The semiconductor device according to claim 1 , wherein a length of the first gate electrode in a direction in which the first source electrode and the first drain electrode are spaced apart from each other is 10 nm or less.

11. An electronic device comprising: Semiconductor devices; as well as a controller configured to control the semiconductor device, The semiconductor device comprises: A first channel layer and a second channel layer arranged to be spaced apart from each other in a first direction, the first channel layer comprising a first two-dimensional 2D semiconductor material, and the second channel layer comprising a second 2D semiconductor material that is the same as or different from the first 2D semiconductor material; a first source electrode between the first channel layer and the second channel layer to contact the first channel layer and the second channel layer at the same time; a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and to contact both the first channel layer and the second channel layer; a first gate electrode disposed in a first inner space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer; and A first gate insulating layer is arranged to surround the first gate electrode in the first inner space.

12. A method for manufacturing a semiconductor device, the method comprising: forming a first channel layer including a first two-dimensional (2D) semiconductor material; forming a first source electrode and a first drain electrode contacting the first channel layer and spaced apart from each other; forming a second channel layer, the second channel layer being in contact with the first source electrode and the first drain electrode, being spaced apart from the first channel layer, and comprising a second 2D semiconductor material that is the same as or different from the first 2D semiconductor material; conformally forming a first gate insulating layer along an inner wall of a first inner space surrounded by the first channel layer, the second channel layer, the first source electrode, and the first drain electrode; as well as A first gate electrode is formed in a region surrounded by the first gate insulating layer in the first inner space. 13 . The method of claim 12 , wherein the second channel layer is formed by transferring a separately manufactured 2D film to be suspended between the first source electrode and the first drain electrode.

14. The method according to claim 12, further comprising: forming an upper insulating layer on the second channel layer; as well as An upper gate electrode is formed on the upper insulating layer. 15 . The method of claim 14 , wherein the upper insulating layer and the first gate insulating layer are simultaneously formed in a same process step.

16. The method according to claim 12, further comprising: forming a second source electrode and a second drain electrode contacting the second channel layer and spaced apart from each other; as well as A third channel layer is formed, the third channel layer contacting the second source electrode and the second drain electrode, being spaced apart from the second channel layer, and including a third 2D semiconductor material that is the same as or different from the first 2D semiconductor material and the second 2D semiconductor material.

17. The method according to claim 16, further comprising: conformally forming a second gate insulating layer along an inner wall of a second inner space surrounded by the second channel layer, the third channel layer, the second source electrode, and the second drain electrode; as well as A second gate electrode is formed in a region surrounded by the second gate insulating layer in the second inner space.

18. The method of claim 17, wherein the first gate insulating layer and the second gate insulating layer are simultaneously formed in a same process step.

19. The method according to claim 17, further comprising: forming an upper insulating layer on the third channel layer; as well as An upper gate electrode is formed on the upper insulating layer.

20. The method of claim 12, further comprising: forming a lower gate electrode; as well as forming a lower insulating layer on the lower gate electrode, The first channel layer is formed on the lower insulating layer.

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