Manufacturing method of double-layer stacked oxide semiconductor device and semiconductor device

Abstract

The invention relates to the technical field of semiconductor device preparation, and discloses a double-layer stacked oxide semiconductor device manufacturing method and a semiconductor device, and the method comprises the steps: forming a bottom gate stack layer on a silicon substrate, and depositing a first gate dielectric layer; sequentially growing and patterning a first oxide layer and a first source-drain metal layer on the first gate dielectric layer; depositing a dielectric layer on the first source drain metal layer, etching the dielectric layer to form a through hole, and depositing and photoetching source electrode metal in the through hole to form a lower layer device; and depositing a second gate dielectric layer after annealing optimization is carried out on the lower-layer device, and sequentially growing and patterning a second oxide layer and a second source-drain metal layer on the second gate dielectric layer to form the double-layer stacked oxide semiconductor device. According to the method, the sub-threshold swing of the lower-layer device can be improved, the performance is improved, the threshold voltage stability is enhanced, the manufacturing method is simple, the cost is low, and the application range is wide.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a method for manufacturing a double-layer stacked oxide semiconductor device and a semiconductor device. Background Art

[0002] Metal-Oxide Semiconductor Thin-Film Transistor (MOS-TFT or OS-TFT) is a field effect transistor made of metal oxide materials, among which the most commonly used metal oxide is indium gallium zinc oxide (IGZO). Considering that such transistors have simple structures, low leakage and excellent mobility electrical characteristics, they can be modulated or doped to improve mobility, thereby enabling large-area low-temperature deposition. Therefore, such transistors are widely used in 3D-DRAM (three-dimensional dynamic random access memory), and in 3D-DRAM structures, transistors are usually stacked into a multi-layer structure to achieve higher storage density.

[0003] However, in the actual manufacturing process, the performance of the transistors in the lower layer is limited by the thermal budget of the upper layer transistor process, and the performance is often poor; and the annealing optimization performed after the device is prepared also has little effect on the lower layer transistors.

[0004] Therefore, a method for manufacturing a double-layer stacked oxide semiconductor device that can optimize the lower transistor during device preparation and improve the performance of the lower transistor is in urgent need of research. Summary of the invention

[0005] In view of this, the present application provides a method for manufacturing a double-layer stacked oxide semiconductor device and a semiconductor device, the main purpose of which is to solve the technical problem of poor performance of the lower transistor in the metal oxide semiconductor thin film transistor stacked into a multi-layer structure in the prior art.

[0006] In one aspect, the present invention provides a method for manufacturing a double-layer stacked oxide semiconductor device, comprising:

[0007] forming a bottom gate stack on a silicon substrate, and depositing a first gate dielectric layer on the bottom gate stack;

[0008] Growing and patterning a first oxide layer on the first gate dielectric layer, and then growing and patterning a first source-drain metal layer on the first oxide layer, wherein the first source-drain metal layer includes a source metal and a drain metal that are arranged opposite to each other;

[0009] Depositing a dielectric layer on the first source-drain metal layer, etching the dielectric layer on the source metal to form a through hole, and depositing and photolithography the source metal in the through hole to form a lower layer device;

[0010] The lower layer device is annealed and optimized, a second gate dielectric layer is deposited on the annealed optimized lower layer device, a second oxide layer is grown and patterned on the second gate dielectric layer, and a second source and drain metal layer is grown and patterned on the second oxide layer to form a double-layer stacked oxide semiconductor device.

[0011] Optionally, before forming the bottom gate stack on the silicon substrate, the method includes:

[0012] The silicon substrate is processed by a thermal oxidation process or a plasma enhanced chemical vapor deposition process to form a silicon dioxide film on the silicon substrate, and a silicon substrate is formed based on the silicon substrate and the silicon dioxide film.

[0013] Optionally, forming a bottom gate stack on a silicon substrate and depositing a first gate dielectric layer on the bottom gate stack includes:

[0014] Depositing metal on a silicon substrate by a sputtering deposition process or an atomic layer deposition process to form a metal gate;

[0015] Photolithography and etching the metal gate based on a preset gate pattern to form a bottom gate stack;

[0016] A first gate dielectric layer is deposited on the bottom gate stack by using an atomic layer deposition process, wherein the first gate dielectric layer is a high-K gate dielectric layer.

[0017] Optionally, the growing and patterning a first oxide layer on the first gate dielectric layer, and then growing and patterning a first source and drain metal layer on the first oxide layer, comprises:

[0018] Depositing and patterning a first oxide layer on the first gate dielectric layer based on a physical vapor deposition process, and introducing hydrogen ion doping during the deposition process using a plasma enhanced technology;

[0019] A first source-drain metal layer is deposited and patterned on the first oxide layer based on a physical vapor deposition process.

[0020] Optionally, depositing a dielectric layer on the first source-drain metal layer, etching the dielectric layer on the source metal to form a through hole, and depositing and photolithography the source metal in the through hole to form a lower layer device includes:

[0021] Depositing a dielectric layer on the first source-drain metal layer so that the dielectric layer covers the first source-drain metal layer, and polishing the dielectric layer by using a chemical mechanical polishing process;

[0022] At the place where the dielectric layer covers the source metal, the dielectric layer is etched in a vertical direction to form a through hole, and the source metal is deposited and photolithographically processed in the through hole so that the source metal overflows the through hole and is higher than the surface of the dielectric layer;

[0023] A lower layer device is formed based on the silicon substrate, the bottom gate stack, the first gate dielectric layer, the first oxide layer, the first source and drain metal layer and the dielectric layer.

[0024] Optionally, depositing a dielectric layer on the first source-drain metal layer so that the dielectric layer covers the first source-drain metal layer, and polishing the dielectric layer by using a chemical mechanical polishing process, includes:

[0025] Depositing a dielectric layer of a first preset thickness on the first source / drain metal layer based on a chemical vapor deposition process, wherein the dielectric layer is made of silicon dioxide material;

[0026] The dielectric layer is polished based on a chemical mechanical polishing process to remove a second preset thickness of the dielectric layer, wherein the first preset thickness is greater than the second preset thickness.

[0027] Optionally, the annealing optimization of the lower layer device includes:

[0028] Based on a preset gas component, the lower layer device is annealed for a preset time at a preset annealing temperature for optimization, wherein the preset gas component is oxygen, nitrogen, vacuum or air, the preset annealing temperature ranges from 200-400°C, and the preset time ranges from 30-120 minutes.

[0029] Another aspect of the present invention provides a semiconductor device, which is prepared based on any of the above-mentioned methods for manufacturing a double-layer stacked oxide semiconductor device, and comprises a lower layer device and an upper layer device stacked on the lower layer device;

[0030] The lower layer device comprises a silicon substrate, a bottom gate stack, a first gate dielectric layer, a first oxide layer, a first source-drain metal layer and a dielectric layer stacked in sequence from bottom to top, wherein the first source-drain metal layer comprises a source metal and a drain metal arranged opposite to each other, a through hole is opened on the dielectric layer by etching, and the source metal overflows the dielectric layer through the through hole;

[0031] The upper device comprises a second gate dielectric layer, a second oxide layer, and a second source-drain metal layer stacked in sequence from bottom to top, wherein the second gate dielectric layer is stacked on the dielectric layer and the source metal overflowing the dielectric layer;

[0032] The lower layer device is subjected to annealing optimization treatment.

[0033] Optionally, the silicon substrate includes a silicon base and a silicon dioxide film covering the silicon base;

[0034] The dielectric layer is made of silicon dioxide material;

[0035] The first gate dielectric layer and the second gate dielectric layer are both high-K gate dielectric layers;

[0036] The first oxide layer and the second oxide layer are both made of indium gallium zinc oxide material.

[0037] Optionally, the aspect ratio of the semiconductor device is 1:1-5:1;

[0038] The thickness of the first oxide layer and the second oxide layer is 15-25 nm;

[0039] The thickness of the first gate dielectric layer and the second gate dielectric layer is 2-10 nm.

[0040] The double-layer stacked oxide semiconductor device manufacturing method and semiconductor device provided by the present invention directly anneal and optimize the lower device during the manufacturing process, which can significantly improve the subthreshold swing of the lower device, improve the switching speed and energy efficiency of the semiconductor device, and can operate at a lower operating voltage, effectively improving the performance of the lower device; the precise graphic technology and annealing optimization technology are used to significantly enhance the threshold voltage stability of the lower device, reduce the threshold drift caused by factors such as temperature change, time aging or charge capture, and ensure that the device still maintains good performance after long-term operation; the entire preparation process is simple, fully utilizes the existing mature preparation technology, can be compatible with CMOS technology, simplifies the preparation process, reduces the optimization cost, and has a relatively wide range of applications. In summary, the above method can improve the subthreshold swing of the lower device, improve performance and enhance the threshold voltage stability, the manufacturing method is simple and low-cost, and has a relatively wide range of applications.

[0041] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] Figure 1 A schematic diagram showing a process of a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0044] Figure 2 A schematic diagram showing the formation of a silicon substrate in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0045] Figure 3 A schematic diagram showing a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention, wherein a bottom gate stack is formed on a silicon substrate;

[0046] Figure 4 A schematic diagram showing the deposition of a first gate dielectric layer on a bottom gate stack in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0047] Figure 5 A schematic diagram showing growing and patterning a first oxide layer on a first gate dielectric layer in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention is shown;

[0048] Figure 6 A schematic diagram showing growing and patterning a first source-drain metal layer on a first oxide layer in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0049] Figure 7 A schematic diagram showing a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention, in which a dielectric layer is deposited on a first source-drain metal layer and a source metal is deposited and photolithographically processed in a through hole;

[0050] Figure 8 A schematic diagram showing the deposition of a second gate dielectric layer on a lower device in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0051] Fig. 9 A schematic diagram showing the growth and patterning of a second oxide layer on a second gate dielectric layer in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0052] Fig.10 A schematic diagram showing growing and patterning a second source-drain metal layer on a second oxide layer in a method for manufacturing a double-layer stacked oxide semiconductor device provided by an embodiment of the present invention;

[0053] Fig.11A schematic diagram of the structure of a silicon-based heterogeneous device monolithic chip provided by an embodiment of the present invention is shown.

[0054] In the figure:

[0055] 1. silicon substrate; 101. silicon base; 102. silicon dioxide film;

[0056] 2. Bottom gate stack;

[0057] 3. A first gate dielectric layer;

[0058] 4. First oxide layer;

[0059] 5. First source-drain metal layer; 501. Source metal; 502. Drain metal;

[0060] 6. Dielectric layer;

[0061] 7. A second gate dielectric layer;

[0062] 8. Second oxide layer;

[0063] 9. Second source and drain metal layer. DETAILED DESCRIPTION

[0064] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0065] The present invention provides a method for manufacturing a double-layer stacked oxide semiconductor device, such as Figure 1 As shown, first, a bottom gate stack 2 is formed on a silicon substrate 1, and a first gate dielectric layer 3 is deposited on the bottom gate stack 2, then a first oxide layer 4 is grown and patterned on the first gate dielectric layer 3, and then a first source-drain metal layer 5 is grown and patterned on the first oxide layer 4, wherein the first source-drain metal layer 5 includes a source metal 501 and a drain metal 502 that are relatively arranged, then a dielectric layer 6 is deposited on the first source-drain metal layer 5, and the dielectric layer 6 is etched on the source metal 501 to form a through hole, and the source metal 501 is deposited and photolithographically formed in the through hole to form a lower device, and finally the lower device is annealed and optimized, and a second gate dielectric layer 7 is deposited on the annealed optimized lower device, a second oxide layer 8 is grown and patterned on the second gate dielectric layer 7, and then a second source-drain metal layer 9 is grown and patterned on the second oxide layer 8 to form a double-layer stacked oxide semiconductor device.

[0066] The double-layer stacked oxide semiconductor device manufacturing method provided by the present invention directly performs annealing optimization on the lower device during the manufacturing process, which can significantly improve the subthreshold swing (SS) of the lower device, improve the switching speed and energy efficiency of the semiconductor device, and can operate at a lower operating voltage, effectively improving the performance of the lower device; the precise graphic technology and annealing optimization technology are used to significantly enhance the threshold voltage stability of the lower device, reduce the threshold drift caused by factors such as temperature change, time aging or charge capture, and ensure that the device still maintains good performance after long-term operation; the entire preparation process is simple, fully utilizes the existing mature preparation technology, can be compatible with CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor) process, simplifies the preparation process, reduces the optimization cost, and has a relatively wide range of applications. In summary, the above method can improve the subthreshold swing of the lower device, improve performance and enhance the threshold voltage stability, the manufacturing method is simple and low-cost, and has a relatively wide range of applications.

[0067] Among them, the subthreshold swing refers to the slope of change of current in the subthreshold region when the gate voltage changes. A lower subthreshold swing means a steeper switching characteristic, thereby effectively improving the switching speed and energy efficiency of the lower-layer device.

[0068] The specific operation steps of the double-layer stacked oxide semiconductor device manufacturing method provided by the present invention are as follows:

[0069] Step 1: forming a silicon substrate 1.

[0070] Specifically, Figure 2 As shown, the silicon substrate 101 is processed by a thermal oxidation process or a plasma enhanced chemical vapor deposition process to form a silicon dioxide film 102 on the silicon substrate 101 , and a silicon substrate 1 is formed based on the silicon substrate 101 and the silicon dioxide film 102 .

[0071] In this embodiment, the silicon dioxide film 102 is formed on the silicon substrate 101 by a thermal oxidation process or a plasma enhanced chemical vapor deposition (PECVD) process, which is a key step in creating a high-quality insulating layer in semiconductor manufacturing. The thermal oxidation process is to place the silicon substrate 101 in a high temperature (usually 900°C to 1200°C) and high-purity oxygen environment, so that the silicon surface reacts with oxygen to generate a dense and uniform silicon dioxide film 102. The formed silicon dioxide film 102 has extremely high density and uniformity, and can provide excellent electrical properties. Its growth rate is controlled by factors such as temperature, time and oxygen partial pressure, ensuring that the thickness of the film can be precisely adjusted; while the plasma enhanced chemical vapor deposition process is at a lower temperature (usually 300°C to 400°C), by applying radio frequency power to generate plasma, activating the gas precursor (silane SiH and oxidant), decomposing and depositing it to form a silicon dioxide film 102. Both of the above process methods can produce high-quality silicon substrates 1, laying a foundation for the subsequent manufacture of semiconductor devices.

[0072] Step 2: forming a bottom gate stack 2 on the silicon substrate 1.

[0073] Specifically, Figure 3 As shown, metal is deposited on a silicon substrate 1 by a sputtering deposition process or an atomic layer deposition process to form a metal gate; the metal gate is photolithographically processed and etched based on a preset gate pattern to form a bottom gate stack 2.

[0074] In this embodiment, the sputtering deposition process specifically utilizes high-energy ions to bombard the target material so that atoms or molecules on the surface of the target material are sputtered out and deposited on the silicon substrate 1 to form a thin film. The sputtering deposition process can deposit various metals and their alloys, with a fast deposition rate, and the formed thin film usually has good mechanical properties; the atomic layer deposition process (ALD) alternately introduces two or more gaseous precursors into the reaction chamber so that these precursors undergo a self-limiting chemical reaction with the substrate surface, and a metal layer of nanometer thickness is constructed layer by layer. The atomic layer deposition process can achieve high-precision control and has good conformality; and whether the sputtering deposition process or the atomic layer deposition process is used, high-quality metal gates can be provided to ensure low resistivity and good conductivity, simplify the overall manufacturing process, reduce manufacturing complexity and cost, and effectively improve production efficiency; and by photolithography and etching the metal gate, very fine gate patterning can be achieved, ensuring the consistency and reliability of each device.

[0075] The present application deposits metal on the silicon substrate 1 by selecting a suitable deposition process, and then combines precise photolithography and etching techniques to form a bottom gate stack 2, which can significantly improve the electrical performance, reliability and manufacturing efficiency of the device. It not only supports multi-layer interconnection structures, but also optimizes patterning accuracy, providing a solid foundation for building high-performance and high-reliability semiconductor devices.

[0076] Step 3: depositing a first gate dielectric layer 3 on the bottom gate stack 2 .

[0077] Specifically, Figure 4 As shown, a first gate dielectric layer 3 is deposited on the bottom gate stack 2 by using an atomic layer deposition process, wherein the first gate dielectric layer 3 is a high-K gate dielectric layer.

[0078] In this embodiment, the high-K gate dielectric layer is generally made of a material with a higher dielectric constant, such as hafnium-based oxide (HfO) or aluminum oxide (AlO), which can provide a higher effective capacitance while maintaining a sufficient thickness, thereby allowing a thinner equivalent oxide layer thickness and reducing leakage current; and the high-K gate dielectric layer helps to maintain a stable threshold voltage, reducing threshold drift caused by factors such as temperature changes, time aging or charge capture; and the use of high-quality atomic layer deposition technology can reduce interface states and defects, improve carrier mobility, and the formed high-K gate dielectric layer has good mechanical strength and environmental resistance, thereby enhancing the long-term stability of the entire device.

[0079] Step 4: growing and patterning a first oxide layer 4 on the first gate dielectric layer 3 .

[0080] Specifically, Figure 5 As shown, the first oxide layer 4 is deposited and patterned on the first gate dielectric layer 3 based on a physical vapor deposition process, and hydrogen ion doping is introduced during the deposition process using a plasma enhanced technology.

[0081] In this embodiment, the material of the first oxide layer 4 is indium gallium zinc oxide (IGZO). The first oxide is used as a channel layer, and a physical vapor deposition process is used to adjust the ratio of In, Ga, Zn, and O, and hydrogen is doped through a plasma plasma injection process to increase the carrier concentration, improve the mobility, suppress the threshold voltage drift, and improve the device reliability. First, for the IGZO material, the composition of the final film can be accurately controlled by adjusting the ratio of different metal targets (In, Ga, Zn) and the oxygen partial pressure, and then the plasma is used to activate hydrogen atoms or molecules so that they have enough energy to penetrate the IGZO film and interact with the internal atoms. The main goal of hydrogen doping is to increase the carrier concentration, passivate defect states, and adjust the Fermi level of the material. Hydrogen can occupy oxygen vacancies or other defect positions to provide additional free electrons, thereby significantly increasing the carrier concentration. Hydrogen doping helps to reduce scattering centers, improve the carrier mobility, and thus improve the switching speed and efficiency of the device; it can also effectively passivate interface states and trap states, and reduce the impact of defects on the threshold voltage.

[0082] Step 5: growing and patterning a first source-drain metal layer 5 on the first oxide layer 4 .

[0083] Specifically, Figure 6 As shown, a first source-drain metal layer 5 is deposited and patterned on the first oxide layer 4 based on a physical vapor deposition process, wherein the first source-drain metal layer 5 includes a source metal 501 and a drain metal 502 that are oppositely arranged.

[0084] In this embodiment, a high-quality physical vapor deposition process can form a source metal 501 and a drain metal 502 with low resistivity, reduce resistance and improve current transmission efficiency. Through a precise patterning process, good contact between the first source and drain metal layer 5 and the first oxide layer 4 is ensured, thereby reducing contact resistance and improving the overall performance of the device.

[0085] Step 6: depositing a dielectric layer 6 on the first source-drain metal layer 5, and etching the dielectric layer 6 on the source metal 501 to form a through hole, and depositing and photolithography the source metal 501 in the through hole to form a lower layer device.

[0086] Specifically, Figure 7 As shown, a dielectric layer 6 is deposited on the first source-drain metal layer 5 so that the dielectric layer 6 covers the first source-drain metal layer 5, and the dielectric layer 6 is polished by a chemical mechanical polishing process; at the place where the dielectric layer 6 covers the source metal 501, the dielectric layer 6 is etched in a vertical direction to form a through hole, and the source metal 501 is deposited and photolithographically processed in the through hole so that the source metal 501 overflows the through hole and is higher than the surface of the dielectric layer 6; based on the silicon substrate 1, the bottom gate stack 2, the first gate dielectric layer 3, the first oxide layer 4, the first source-drain metal layer 5 and the dielectric layer 6, a lower layer device is formed.

[0087] In which, a dielectric layer 6 is deposited on the first source-drain metal layer 5 so that the dielectric layer 6 covers the first source-drain metal layer 5, and the dielectric layer 6 is polished using a chemical mechanical polishing process, including depositing a dielectric layer 6 of a first preset thickness on the first source-drain metal layer 5 based on a chemical vapor deposition process, wherein the dielectric layer 6 is a silicon dioxide material; and polishing the dielectric layer 6 based on a chemical mechanical polishing process to remove a second preset thickness of the dielectric layer 6, wherein the first preset thickness is greater than the second preset thickness.

[0088] In this embodiment, the dielectric layer 6 is made of silicon dioxide material. First, a dielectric layer 6 of a first preset thickness is deposited, and the first preset thickness is 1 μm. Then, the dielectric layer 6 is polished by a chemical mechanical polishing (CMP) process to remove a dielectric layer 6 of a second preset thickness, and the second preset thickness is 600 nm. Finally, a 400 nm dielectric layer 6 is formed on the first source and drain metal layer 5. The chemical mechanical polishing process combines chemical corrosion and mechanical grinding processes to make the surface of the dielectric layer 6 highly flat. The specific process includes using a grinding pad containing a corrosive chemical solution to remove excess dielectric material, and gradually polishing the surface through a rotational motion until the entire dielectric layer 6 becomes very flat. The high-quality dielectric layer 6 effectively isolates different conductive paths, prevents short circuits, and improves the stability of the circuit; then the dielectric layer 6 needs to be etched to form a through hole, that is, using a photosensitive material and a mask, the position of the through hole to be etched is defined on the dielectric layer 6, specifically the area covering the source metal 501, and then the dielectric material not protected by the photoresist is removed through selective etching technology to expose the source metal 501 below to form a through hole. After the etching is completed, the residual photoresist is removed to leave a through hole with a precise opening; finally, the source metal 501 is deposited and photolithographically processed in the through hole. During the deposition process, the source metal 501 overflows the through hole and is higher than the surface of the dielectric layer 6 to ensure reliable electrical connection.

[0089] Step 7: annealing and optimizing the lower layer device.

[0090] Specifically, based on a preset gas composition, the lower layer device is annealed for a preset time at a preset annealing temperature for optimization, wherein the preset gas composition is oxygen, nitrogen, vacuum or air, the preset annealing temperature ranges from 200-400°C, and the preset time ranges from 30-120 minutes.

[0091] In this embodiment, the prepared lower layer device is placed in an annealing furnace or special equipment, and the selected gas components are introduced according to preset conditions to ensure that the environment in the furnace meets the requirements. The temperature is gradually raised to a preset temperature and maintained at this temperature for a preset time to allow necessary physical and chemical changes to occur inside the material. After annealing is completed, the temperature is lowered at a prescribed rate to ensure that the material structure is stable, wherein the preset gas component is oxygen, nitrogen, vacuum or air, preferably oxygen; the preset annealing temperature range is 200-400°C, preferably 300°C; the preset time range is 30-120mins, preferably 60mins.

[0092] Step 8: depositing a second gate dielectric layer 7 on the lower device after annealing optimization.

[0093] In this embodiment, if Figure 8As shown, after the lower device completes annealing optimization, the upper device stacked on the lower device is prepared. The first step is to deposit the second gate dielectric layer 7. The second gate dielectric layer 7 is the same as the first gate dielectric layer 3, both of which are high-K gate dielectric layers. The specific operation steps can refer to step 3.

[0094] Step 9: growing and patterning a second oxide layer 8 on the second gate dielectric layer 7 .

[0095] In this embodiment, if Fig. 9 As shown, the second oxide layer 8 is grown and patterned on the second gate dielectric layer 7 based on the physical vapor deposition process. The specific operation steps can refer to step 4.

[0096] Step 10: grow and pattern a second source-drain metal layer 9 on the second oxide layer 8 to form a double-layer stacked oxide semiconductor device.

[0097] In this embodiment, if Fig.10 As shown, finally, a second source-drain metal layer 9 is grown and patterned on the second oxide layer 8. The specific operation steps can refer to step 5. The second source-drain metal layer 99 also includes relatively arranged source electrodes and drain electrodes to form an upper device. Finally, based on the annealed optimized lower and upper devices, the complete preparation process of the double-layer stacked oxide semiconductor device is completed.

[0098] On the other hand, the present invention provides a semiconductor device, which is prepared based on any of the above-mentioned double-layer stacked oxide semiconductor device manufacturing methods, and includes a lower device and an upper device stacked on the lower device; the lower device includes a silicon substrate 1, a bottom gate stack 2, a first gate dielectric layer 3, a first oxide layer 4, a first source-drain metal layer 5 and a dielectric layer 6 stacked in sequence from bottom to top, wherein the first source-drain metal layer 5 includes a source metal 501 and a drain metal 502 arranged opposite to each other, and a through hole is opened on the dielectric layer 6 by etching, and the source metal 501 overflows the dielectric layer 6 through the through hole; the upper device includes a second gate dielectric layer 7, a second oxide layer 8 and a second source-drain metal layer 9 stacked in sequence from bottom to top, wherein the second gate dielectric layer 7 is stacked on the dielectric layer 6 and the source metal 501 overflowing the dielectric layer 6; the lower device is subjected to annealing optimization treatment.

[0099] The semiconductor device provided in the present application can significantly improve its electrical performance, such as reducing threshold voltage drift, reducing leakage current and improving mobility, by preferentially performing annealing optimization treatment on the lower layer device, thereby providing a more stable foundation for the upper layer device, and the lower layer device that has undergone annealing optimization treatment has better thermal stability and chemical stability, reducing performance degradation during long-term use, and the stable underlying structure ensures the reliability of the entire double-layer device; by vertically stacking two independent oxide semiconductor devices, more functional units can be integrated per unit area, significantly improving the integration of the device and reducing the chip size; the preparation method is simple and the cost is low, so that the device has a wider application space.

[0100] Specifically, in the above embodiment, the silicon substrate 1 includes a silicon base 101 and a silicon dioxide film 102 covering the silicon base 101; the dielectric layer 6 is a silicon dioxide material; the first gate dielectric layer 3 and the second gate dielectric layer 7 are both high-K gate dielectric layers; the first oxide layer 4 and the second oxide layer 8 are both indium gallium zinc oxide materials.

[0101] In this embodiment, the silicon substrate 1 composed of the silicon base 101 and the silicon dioxide film 102 can effectively reduce the interface state density, improve the carrier mobility, maintain a stable threshold voltage, and reduce the threshold drift; the high-K gate dielectric layer provides a higher effective capacitance at a thinner physical thickness and significantly reduces the gate leakage current; the silicon dioxide dielectric layer 6 reduces parasitic capacitance and resistance, optimizes the signal transmission path, and enhances the durability and mechanical strength of the device; the IGZO oxide layer improves the mobility, improves the conductivity, and has strong flexibility.

[0102] Specifically, in the above embodiment, the aspect ratio of the semiconductor device is 1:1-5:1; the thickness of the first oxide layer 4 and the second oxide layer 8 is 15-25 nm; the thickness of the first gate dielectric layer 3 and the second gate dielectric layer 7 is 2-10 nm.

[0103] In this embodiment, a higher aspect ratio (such as 5:1) can significantly increase the channel width, thereby improving the current driving capability; while a relatively low aspect ratio (such as 1:1) helps to reduce the device size and support technology miniaturization. The present application can effectively control the short channel effect and reduce leakage current through a reasonable aspect ratio design; the thickness of the first oxide layer 4 and the second oxide layer 8 is 15-25nm, and the appropriate oxide layer thickness ensures that the carriers have sufficient migration space, thereby improving the mobility. The oxide layer with a certain thickness can reduce the interface state density to a certain extent, improve the carrier transport characteristics, and reduce the leakage current. The appropriate thickness helps to maintain thermal stability and prevent material performance degradation during high-temperature operation. The thickness range of 15-25nm provides a larger process window, ensuring stability and consistency during the manufacturing process; the thickness of the first gate dielectric layer 3 and the second gate dielectric layer 7 is 2-10nm, which can achieve higher gate capacitance, enhance the driving capability of the device, maintain a stable threshold voltage, and reduce the threshold drift caused by factors such as temperature changes and time aging, thereby ensuring good compatibility with existing CMOS processes and ensuring long-term reliability and durability.

[0104] The schematic diagram of the structure of the semiconductor device provided by the present application applied to a DRAM device is shown in FIG. Fig.11 As shown:

[0105] This image shows a schematic diagram of the structure of a thin-film transistor (TFT) based on indium gallium zinc oxide (IGZO). The following is an explanation of the structure:

[0106] The bottom layer is the substrate, i.e. the silicon substrate 101, which is the basic supporting layer of the entire device; on the substrate is a silicon dioxide (SiO2) film, which is covered on the substrate as an insulating layer to isolate other layers;

[0107] The silicon substrate 1 is stacked in sequence with: a write sub-line (WWL) which is a metal line used to control the switch state; a gate insulating layer (GI) which is another insulating material layer located between the IGZO layer and the gate; indium gallium zinc oxide (IGZO) which is a semiconductor layer used to conduct current; a write bit line (WBL) which is a metal line perpendicular to the write sub-line (WWL) and used to select a specific pixel; and a storage node (SN); the above layers are stacked to form a lower layer device;

[0108] The upper device is stacked on the lower device, and also includes a gate insulating layer (GI) and a semiconductor layer of indium gallium zinc oxide (IGZO), on which there are also a read bit line (RBL) and a ground line (GND).

[0109] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for manufacturing a double-layer stacked oxide semiconductor device, characterized in that: include: forming a bottom gate stack on a silicon substrate, and depositing a first gate dielectric layer on the bottom gate stack; Growing and patterning a first oxide layer on the first gate dielectric layer, and then growing and patterning a first source-drain metal layer on the first oxide layer, wherein the first source-drain metal layer includes a source metal and a drain metal that are arranged opposite to each other; Depositing a dielectric layer on the first source-drain metal layer, etching the dielectric layer on the source metal to form a through hole, and depositing and photolithography the source metal in the through hole to form a lower layer device; The lower layer device is annealed and optimized, a second gate dielectric layer is deposited on the annealed optimized lower layer device, a second oxide layer is grown and patterned on the second gate dielectric layer, and a second source and drain metal layer is grown and patterned on the second oxide layer to form a double-layer stacked oxide semiconductor device.

2. The method according to claim 1, characterized in that Before forming a bottom gate stack on the silicon substrate, the method includes: The silicon substrate is processed by a thermal oxidation process or a plasma enhanced chemical vapor deposition process to form a silicon dioxide film on the silicon substrate, and a silicon substrate is formed based on the silicon substrate and the silicon dioxide film.

3. The method according to claim 1, characterized in that The step of forming a bottom gate stack on a silicon substrate and depositing a first gate dielectric layer on the bottom gate stack comprises: Depositing metal on a silicon substrate by a sputtering deposition process or an atomic layer deposition process to form a metal gate; Photolithography and etching the metal gate based on a preset gate pattern to form a bottom gate stack; A first gate dielectric layer is deposited on the bottom gate stack by using an atomic layer deposition process, wherein the first gate dielectric layer is a high-K gate dielectric layer.

4. The method according to claim 1, characterized in that: The step of growing and patterning a first oxide layer on the first gate dielectric layer, and then growing and patterning a first source and drain metal layer on the first oxide layer, comprises: Depositing and patterning a first oxide layer on the first gate dielectric layer based on a physical vapor deposition process, and introducing hydrogen ion doping during the deposition process using a plasma enhanced technology; A first source-drain metal layer is deposited and patterned on the first oxide layer based on a physical vapor deposition process.

5. The method according to claim 1, characterized in that The step of depositing a dielectric layer on the first source-drain metal layer, etching the dielectric layer on the source metal to form a through hole, and depositing and photolithography the source metal in the through hole to form a lower layer device includes: Depositing a dielectric layer on the first source-drain metal layer so that the dielectric layer covers the first source-drain metal layer, and polishing the dielectric layer by using a chemical mechanical polishing process; At the place where the dielectric layer covers the source metal, the dielectric layer is etched in a vertical direction to form a through hole, and the source metal is deposited and photolithographically processed in the through hole so that the source metal overflows the through hole and is higher than the surface of the dielectric layer; A lower layer device is formed based on the silicon substrate, the bottom gate stack, the first gate dielectric layer, the first oxide layer, the first source and drain metal layer and the dielectric layer.

6. The method according to claim 5, characterized in that The step of depositing a dielectric layer on the first source-drain metal layer so that the dielectric layer covers the first source-drain metal layer, and polishing the dielectric layer by using a chemical mechanical polishing process comprises: Depositing a dielectric layer of a first preset thickness on the first source / drain metal layer based on a chemical vapor deposition process, wherein the dielectric layer is made of silicon dioxide material; The dielectric layer is polished based on a chemical mechanical polishing process to remove a second preset thickness of the dielectric layer, wherein the first preset thickness is greater than the second preset thickness.

7. The method according to claim 1, characterized in that The step of annealing and optimizing the lower layer device comprises: Based on a preset gas component, the lower layer device is annealed for a preset time at a preset annealing temperature for optimization, wherein the preset gas component is oxygen, nitrogen, vacuum or air, the preset annealing temperature ranges from 200-400°C, and the preset time ranges from 30-120 minutes.

8. A semiconductor device, characterized in that: Prepared based on the method for manufacturing a double-layer stacked oxide semiconductor device according to any one of claims 1 to 7, comprising a lower layer device and an upper layer device stacked on the lower layer device; The lower layer device comprises a silicon substrate (1), a bottom gate stack (2), a first gate dielectric layer (3), a first oxide layer (4), a first source-drain metal layer (5) and a dielectric layer (6) stacked in sequence from bottom to top, wherein the first source-drain metal layer (5) comprises a source metal (501) and a drain metal (502) arranged opposite to each other, a through hole is opened on the dielectric layer (6) by etching, and the source metal (501) overflows the dielectric layer (6) through the through hole; The upper layer device comprises a second gate dielectric layer (7), a second oxide layer (8) and a second source-drain metal layer (9) stacked in sequence from bottom to top, wherein the second gate dielectric layer (7) is stacked on the dielectric layer (6) and the source metal (501) overflowing from the dielectric layer (6); The lower layer device is subjected to annealing optimization treatment.

9. The semiconductor device according to claim 8, characterized in that The silicon substrate (1) comprises a silicon base (101) and a silicon dioxide film (102) covering the silicon base (101); The dielectric layer (6) is made of silicon dioxide material; The first gate dielectric layer (3) and the second gate dielectric layer (7) are both high-K gate dielectric layers; The first oxide layer (4) and the second oxide layer (8) are both made of indium gallium zinc oxide material.

10. The semiconductor device according to claim 8, characterized in that The aspect ratio of the semiconductor device is 1:1-5:1; The thickness of the first oxide layer (4) and the second oxide layer (8) is 15-25 nm; The thickness of the first gate dielectric layer (3) and the second gate dielectric layer (7) is 2-10 nm.

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