A semiconductor device and a method of fabricating the same

Abstract

This invention provides a semiconductor device and its fabrication method. The fabrication method includes the following steps: providing a semiconductor structure including a semiconductor layer and first and second dummy gate structures; the semiconductor layer includes first and second well regions located on the upper surface of the semiconductor layer; a first source and drain structure located on opposite sides of the first dummy gate structure are formed on the upper surface of the first well region; a second source and drain structure located on opposite sides of the second dummy gate structure is formed on the upper surface of the second well region; the first and second dummy gate structures are respectively located on the upper surfaces of the first and second well regions; forming a compressive stress layer covering the upper surface of the semiconductor structure; removing the first dummy gate structure and forming a first metal gate structure; removing the second dummy gate structure and forming a second metal gate structure; and forming the electrodes of the device. This invention improves the channel stress of the device by forming a compressive stress layer on the upper surface of the semiconductor structure and using the compressive stress layer to compress the portion of the first source and drain structure protruding from the upper surface of the first well region.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuit manufacturing, and relates to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the development of integrated circuit manufacturing technology, the size of semiconductor devices is getting smaller and smaller, and the requirements for the manufacturing process of the devices are getting higher and higher. In order to improve the performance of small-size devices, contact etching stop layer strain technology is widely used. At present, in the high-K metal gate (HKMG) device of 28nm and below process, the tensile stress contact etching stop layer strain (CESL) layer covering the surface of the dummy gate and the substrate is usually used to enhance the channel stress of N-type metal oxide semiconductor field effect transistor (NMOS), and the SiGe process is used to enhance the channel stress of P-type metal oxide semiconductor field effect transistor (PMOS). However, after the dummy gate is replaced by the metal gate, the tensile stress CESL layer is damaged, which leads to that the influence of the tensile stress CESL layer on the performance of NMOS is not obvious. In addition, due to the small volume of SiGe in PMOS, the stress is insufficient, which leads to that the performance of PMOS is lower than that of normal devices. At the same time, due to the high height of the SiGe protrusion, the effect of the tensile stress CESL layer is large, which leads to that the stress generated by SiGe is further reduced, and then the performance of PMOS is further reduced.

[0003] Therefore, it is urgent to find a preparation method of a semiconductor device which can improve the performance of a metal gate device. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor device and a preparation method thereof, which can solve the problem of low performance of the metal gate device of 28nm and below process in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a semiconductor device, which comprises the following steps:

[0006] A semiconductor structure comprising a semiconductor layer and first and second dummy gate structures arranged at intervals is provided, the semiconductor layer comprises at least one first well region of a first conductivity type and at least one second well region of a second conductivity type on the upper surface layer of the semiconductor layer, the upper surface layer of the first well region is formed with first source and drain structures located on the opposite sides of the first dummy gate structure, and the upper surface layer of the second well region is formed with second source and drain structures located on the opposite sides of the second dummy gate structure, and the first and second dummy gate structures are located on the upper surfaces of the first and second well regions, respectively;

[0007] A compressive stress layer covering the upper surface of the semiconductor structure is formed;

[0008] Remove the first dummy gate structure and form a first metal gate structure; remove the second dummy gate structure and form a second metal gate structure.

[0009] A first source electrically connected to the first source structure, a first drain electrically connected to the first drain structure, a second source electrically connected to the second source structure, a second drain electrically connected to the second drain structure, a first gate electrically connected to the first metal gate structure, and a second gate electrically connected to the second metal gate structure are formed.

[0010] Optionally, the first source structure is embedded in the upper surface of the semiconductor layer and the upper surface of the first source structure protrudes from the upper surface of the first well region, and the first drain structure is embedded in the upper surface of the first well region and the upper surface of the first drain structure protrudes from the upper surface of the first well region.

[0011] Optionally, the material of the first source structure includes SiGe; the material of the first drain structure includes SiGe.

[0012] Optionally, the thickness range of the compressive stress layer is:

[0013] Optionally, the compressive stress layer may be made of silicon nitride.

[0014] Optionally, the first dummy gate structure includes at least a first dielectric layer located on the upper surface of the first well region and a first dummy gate layer located on the upper surface of the first dielectric layer; the second dummy gate structure includes at least a second dielectric layer located on the upper surface of the second well region and a second dummy gate layer located on the upper surface of the second dielectric layer; the first metal gate structure includes at least a third dielectric layer and a first metal layer, the third dielectric layer covering the upper surface of the first well region between the first source structure and the first drain structure, and the first metal layer located on the upper surface of the third dielectric layer; the second metal gate structure includes at least a fourth dielectric layer and a second metal layer, the fourth dielectric layer covering the upper surface of the second well region between the second source structure and the second drain structure, and the second metal layer located on the upper surface of the fourth dielectric layer.

[0015] Optionally, the first metal layer and the second metal layer are made of different materials.

[0016] Optionally, after forming the compressive stress layer and before removing the first dummy gate structure and the second dummy gate structure, the method further includes the step of forming an interlayer dielectric layer covering the upper surface of the compressive stress layer.

[0017] Optionally, after forming the interlayer dielectric layer and before forming the first metal gate structure and the second metal gate structure, the method further includes the step of removing the compressive stress layer and the interlayer dielectric layer directly above the first dummy gate structure and the second dummy gate structure.

[0018] The present invention also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described above.

[0019] As described above, the semiconductor device and its fabrication method of the present invention improve the device fabrication process by forming a compressive stress layer on the upper surface of the semiconductor structure. Since the first source structure and the first drain structure protrude to a relatively high height from the upper surface of the first well region, the compressive stress layer covering the sidewalls of the first source structure and the first drain structure protruding from the first well region will compress the first source structure and the first drain structure. Subsequently, through the combination of the first source structure, the first drain structure and the compressive stress layer, the channel stress of the device formed in the first well region is enhanced, and the performance of the device formed in the first well region is improved without affecting the performance of the device formed in the second well region. This improves the overall performance of the device and has high industrial application value. Attached Figure Description

[0020] Figure 1 The diagram shown is a process flow chart of the method for fabricating the semiconductor device of the present invention.

[0021] Figure 2 The diagram shown is a cross-sectional view of the semiconductor structure used in the fabrication method of the semiconductor device of the present invention.

[0022] Figure 3 The diagram shows a cross-sectional structure after the formation of the compressive stress layer in the method for fabricating the semiconductor device of the present invention.

[0023] Figure 4 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the formation of the interlayer dielectric layer.

[0024] Figure 5 The diagram shows a cross-sectional view of the semiconductor device fabrication method of the present invention after removing the first dummy gate structure.

[0025] Figure 6 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the formation of the second metal gate structure.

[0026] Figure 7 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the formation of the insulating layer.

[0027] Figure 8 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the formation of each electrode.

[0028] Explanation of icon numbers

[0029] 1. Semiconductor Structure

[0030] 11 Substrate

[0031] 12 First Well Region

[0032] 121 First Source Structure

[0033] 1211 First Source Region

[0034] 122 First Leak Structure

[0035] 1221 First Leakage Zone

[0036] 123 First pseudo-grid structure

[0037] 124 First dielectric layer

[0038] 125 First pseudo-gate layer

[0039] 126 First side wall

[0040] 127 First Metal Grid Structure

[0041] 128 Third dielectric layer

[0042] 129 First Metal Layer

[0043] 13 Second Trap Zone

[0044] 131 Second Source Structure

[0045] 132 Second Leakage Structure

[0046] 133 Second pseudo-gate structure

[0047] 134 Second dielectric layer

[0048] 135 Second pseudo-gate layer

[0049] 136 Second side wall

[0050] 137 Second Metal Grid Structure

[0051] 138 Fourth dielectric layer

[0052] 139 Second Metal Layer

[0053] 14. Isolation Structure

[0054] 2. Compressive stress layer

[0055] 3 Interlayer dielectric layer

[0056] 4 Insulation layer

[0057] 5 First Source Pole

[0058] 51 Second Source Pole

[0059] 6 First Drain

[0060] 61 Second Drain

[0061] 7 First gate

[0062] 71 Second gate Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] Example 1

[0066] This embodiment provides a method for fabricating a semiconductor device, such as... Figure 1 The diagram shown is a process flow chart of the method for fabricating the semiconductor device, including the following steps:

[0067] S1: A semiconductor structure is provided, including a semiconductor layer and a first dummy gate structure and a second dummy gate structure spaced apart. The semiconductor layer includes at least one first well of a first conductivity type and at least one second well region of a second conductivity type located on the upper surface of the semiconductor layer. The upper surface of the first well region is formed with a first source structure of a second conductivity type and a first drain structure of a second conductivity type located on opposite sides of the first dummy gate structure. The upper surface of the second well region is formed with a second source structure of a first conductivity type and a second drain structure of a first conductivity type located on opposite sides of the second dummy gate structure. The first dummy gate structure and the second dummy gate structure are respectively located on the upper surfaces of the first well region and the second well region.

[0068] S2: Form a compressive stress layer covering the upper surface of the semiconductor structure;

[0069] S3: Remove the first dummy gate structure and form a first metal gate structure; remove the second dummy gate structure and form a second metal gate structure;

[0070] S4: Form a first source electrically connected to the first source structure, a first drain electrically connected to the first drain structure, a second source electrically connected to the second source structure, a second drain electrically connected to the second drain structure, a first gate electrically connected to the first metal gate structure, and a second gate electrically connected to the second metal gate structure.

[0071] Please see Figures 2 to 3 Steps S1 and S2 are performed as follows: A semiconductor structure 1 is provided, including a semiconductor layer and a first dummy gate structure 123 and a second dummy gate structure 133 arranged at intervals. The semiconductor layer includes at least one first well region 12 of a first conductivity type and at least one second well region 13 of a second conductivity type located on the upper surface of the semiconductor layer. A first source structure 121 of a second conductivity type and a first drain structure 122 of a second conductivity type are formed on the upper surface of the first well region 12, located on opposite sides of the first dummy gate structure 123. A second source structure 131 of a first conductivity type and a second drain structure 132 of a first conductivity type are formed on the upper surface of the second dummy gate structure 133, located on opposite sides of the second dummy gate structure 133. The first dummy gate structure 123 and the second dummy gate structure 133 are respectively located on the upper surfaces of the first well region 12 and the second well region 13. A compressive stress layer 2 is formed covering the upper surface of the semiconductor structure 1.

[0072] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type, meaning the device fabricated in the first well region 12 is a P-type device, and the device fabricated in the second well region 13 is an N-type device.

[0073] Specifically, such as Figure 2 The diagram shows a cross-sectional view of semiconductor structure 1. The semiconductor layer also includes a substrate 11. The first well region 12 and the second well region 13 are located on the upper surface of the substrate 11. The conductivity type of the substrate 11 can be a first conductivity type, a second conductivity type, or an intrinsic semiconductor.

[0074] Specifically, while ensuring device performance, the size, thickness, shape, and doping concentration of the substrate 11 can be selected according to the actual situation.

[0075] Specifically, the first well region 12 and the second well region 13 can be spaced apart, or the second well region 13 can be located on the upper surface of the first well region 12, or the first well region 12 can be located on the upper surface of the second well region 13. When the first well region 12 and the second well region 13 are spaced apart, an isolation structure 14 is usually provided between the first well region 12 and the second well region 13. When the second well region 13 is located on the upper surface of the first well region 12, the first source structure 121, the first drain structure 122 and the first dummy gate structure 123 are spaced apart from the second well region 13. When the first well region 12 is located on the upper surface of the second well region 13, the second source structure 131, the second drain structure 132 and the second dummy gate structure 133 are spaced apart from the first well region 12.

[0076] It should be noted that the isolation structure 14 that isolates the first well region 12 and the second well region 13 is usually a shallow trench isolation structure. Other suitable structures can also be used while ensuring device performance. No further restrictions will be placed here.

[0077] Specifically, both the first well region 12 and the second well region 13 are typically normal doped layers. While ensuring device performance, the thickness, size, shape, and doping concentration of the first well region 12 can be selected according to actual conditions; similarly, the thickness, size, shape, and doping concentration of the second well region 13 can be selected according to actual conditions. Here, "normal doping" refers to doping relative to light or heavy doping.

[0078] As an example, the first source structure 121 is embedded in the upper surface of the semiconductor layer and the upper surface of the first source structure 121 protrudes from the upper surface of the first well region 12, and the first drain structure 122 is embedded in the upper surface of the first well region 12 and the upper surface of the first drain structure 122 protrudes from the upper surface of the first well region 12.

[0079] Specifically, the first source structure 121 includes at least a second conductive type first source region 1211 whose bottom surface is at a predetermined distance below the upper surface of the first well region 12, and the first drain structure 122 includes at least a second conductive type first drain region 1221 whose bottom surface is at a predetermined distance below the upper surface of the first well region 12.

[0080] It should be noted that the first source region 1211 is usually located on the upper surface of the first source structure 121, and forms an ohmic contact with the subsequently formed first source electrode 5. Therefore, the first source region 1211 needs to be heavily doped. The first drain region 1221 is usually located on the upper surface of the first drain structure 122, and forms an ohmic contact with the subsequently formed first drain electrode 6. Therefore, the first drain region 1221 needs to be heavily doped.

[0081] Specifically, while ensuring device performance, the doping concentration and thickness of the first source region 1211 can be selected according to the actual situation; the doping concentration and thickness of the first drain region 1221 can be selected according to the actual situation.

[0082] As an example, the material of the first source structure 121 includes SiGe or other suitable semiconductor materials; the material of the first drain structure 122 includes SiGe or other suitable semiconductor materials. Preferably, both the first source structure 121 and the first drain structure 122 are made of SiGe, that is, the device is a strained silicon device.

[0083] It should be noted that, typically during the fabrication of the first source structure 121 and the first drain structure 122, a first groove and a second groove of a preset shape, preset size, and preset depth need to be formed on the upper surface of the first well region 12. Then, the first source structure 121 filling the first groove and the first drain structure 122 filling the second groove are formed. Furthermore, during the formation of the first source structure 121 and the first drain structure 122, a single-crystal SiGe layer filling the first groove and the second groove needs to be formed first, and ion implantation is performed on the upper surface of the single-crystal SiGe layer to obtain the first source region 1211 located on the upper surface of the single-crystal SiGe layer in the first groove and the first drain region 1221 located on the upper surface of the single-crystal SiGe layer in the second groove.

[0084] Specifically, the method for forming the first groove includes dry etching, wet etching, or other suitable methods; the method for forming the second groove includes dry etching, wet etching, or other suitable methods. Preferably, a combination of plasma etching (dry etching) and wet etching is used to simultaneously form sigma trenches with special cross-sectional shapes on both sides of the first dummy gate structure 123 that are opposite to each other, namely the first groove and the second groove.

[0085] Specifically, while ensuring device performance, the opening size, shape, and depth of the first and second grooves can be selected according to the actual situation.

[0086] As an example, the first dummy gate structure 123 includes at least a first dielectric layer 124 located on the upper surface of the first well region 12 and a first dummy gate layer 125 located on the upper surface of the first dielectric layer 124.

[0087] Specifically, the first dielectric layer 124 is made of silicon oxide, silicon nitride, or other suitable dielectric materials; the first dummy gate layer 125 is made of polysilicon or other suitable materials.

[0088] It should be noted that the outer periphery of the sidewall of the first dummy gate structure 123 is usually provided with a first sidewall 126 for improving the reliability of the device. The first sidewall 126 covers the sidewall of the stacked structure formed by the first dummy gate layer 125 and the first dielectric layer 124. The material of the first sidewall 126 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0089] Specifically, the top of the first sidewall 126 is flush with the top surface of the first dummy gate layer 125. While ensuring the performance of the subsequently fabricated devices, the thickness of the first dielectric layer 124 can be selected according to actual conditions; the thickness, size, and shape of the first dummy gate layer 125 can be selected according to actual conditions; and the thickness of the first sidewall 126 can be selected according to actual conditions. The thickness of the first dummy gate layer 125 refers to the distance between its upper and lower surfaces, and the thickness of the first sidewall 126 refers to the distance between the side of the first sidewall 126 adjacent to the first dummy gate layer 125 and the side facing away from the first dummy gate layer 125.

[0090] It should be noted that in embedded SiGe devices with a process technology typically not exceeding 28nm, the material of the second source structure 131 and the second drain structure 132 of the N-type device can be SiC, or it can be the same material as the second well region 13, i.e., ions are implanted into the second well region 13 to form a second source region and a second drain region with the opposite conductivity type to the second well region 13. In this embodiment, the upper surfaces of the second source structure 131 and the second drain structure 132 are flush with the upper surface of the second well region 13.

[0091] Specifically, the second source structure 131 and the second drain structure 132 usually need to form ohmic contacts with the subsequent formation of the second source and the second drain. Therefore, both the second source structure 131 and the second drain structure 132 are heavily doped regions. Under the premise of ensuring device performance, the thickness, shape, size and doping concentration of the second source structure 131 can be selected according to the actual situation; the thickness, shape, size and doping concentration of the second drain structure 132 can be selected according to the actual situation.

[0092] As an example, the second dummy gate structure 133 includes at least a second dielectric layer 134 located on the upper surface of the second well region 13 and a second dummy gate layer 135 located on the upper surface of the second dielectric layer 134.

[0093] Specifically, the material of the second dielectric layer 134 includes silicon oxide, silicon nitride, or other suitable dielectric materials; the material of the second dummy gate layer 135 includes polysilicon or other suitable materials.

[0094] It should be noted that a second sidewall 136 is usually provided around the sidewall of the second dummy gate structure 133 to improve the reliability of the device. The second sidewall 136 covers the sidewall of the stacked structure formed by the second dummy gate layer 135 and the second dielectric layer 134. The material of the second sidewall 136 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0095] Specifically, the top of the second sidewall 136 is flush with the top surface of the second dummy gate layer 135. While ensuring the performance of the subsequently fabricated devices, the thickness of the second dielectric layer 134 can be selected according to actual conditions; the thickness, size, and shape of the second dummy gate layer 135 can be selected according to actual conditions; and the thickness of the second sidewall 136 can be selected according to actual conditions. The thickness of the second dummy gate layer 135 refers to the distance between its upper and lower surfaces, and the thickness of the second sidewall 136 refers to the distance between the side of the first sidewall 126 adjacent to the second dummy gate layer 135 and the side facing away from the second dummy gate layer 135.

[0096] Specifically, such as Figure 3 The diagram shows a cross-sectional structure after the formation of the compressive stress layer 2. The compressive stress layer 2 covers the exposed upper surfaces of the first well region 12 and the second well region 13, as well as the exposed surfaces of the first dummy gate structure 123 and the second dummy gate structure 133. It also covers the exposed surfaces of the first source structure 121, the first drain structure 122, the second source structure 131, and the second drain structure 132. The method for forming the compressive stress layer 2 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0097] As an example, the thickness range of compressive stress layer 2 is... For example, the thickness of the compressive stress layer 2 can be Preferably, the thickness of the compressive stress layer 2 is

[0098] Specifically, by making the thickness of the compressive stress layer 2 within a certain range... This approach can improve the performance of the device formed in the first well region 12 while avoiding affecting the overall performance of the device.

[0099] As an example, the material of the compressive stress layer 2 may include silicon nitride or other suitable stress materials.

[0100] Specifically, during the formation of the compressive stress layer 2, by controlling the process parameters and formation environment of the compressive stress layer 2, the stress type generated by the compressive stress layer 2 is compressive stress. For example, when the compressive stress layer 2 is a silicon nitride layer, by keeping the proportion of nitrogen source low during the formation of the silicon nitride layer, a silicon nitride layer with compressive stress can be achieved. Alternatively, a silicon nitride layer with compressive stress can be formed by a low-temperature deposition environment or a low radio frequency.

[0101] Please see Figures 4 to 8Steps S3 and S4 are executed: the first dummy gate structure 123 is removed and the first metal gate structure 127 is formed; the second dummy gate structure 133 is removed and the second metal gate structure 137 is formed; a first source 5 electrically connected to the first source structure 121, a first drain 6 electrically connected to the first drain structure 122, a second source 51 electrically connected to the second source structure 131, a second drain 61 electrically connected to the second drain structure 132, a first gate 7 electrically connected to the first metal gate structure 127, and a second gate 71 electrically connected to the second metal gate structure 137 are formed.

[0102] As an example, such as Figure 4 As shown, this is a cross-sectional structural diagram after the formation of the interlayer dielectric layer 3. After the formation of the compressive stress layer 2 and before the removal of the first dummy gate structure 123 and the second dummy gate structure 133, the method further includes the step of forming an interlayer dielectric layer 3 covering the upper surface of the compressive stress layer 2.

[0103] Specifically, the methods for forming the interlayer medium layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0104] Specifically, the upper surface of the interlayer dielectric layer 3 is flush with and not lower than the upper surface of the compressive stress layer 2 directly above the first dummy gate structure 123 and the second dummy gate structure 133. The thickness of the interlayer dielectric layer 3 can be selected according to the actual situation while ensuring device performance.

[0105] As an example, after forming the interlayer dielectric layer 3 and before forming the first metal gate structure 127, the method further includes the step of removing the compressive stress layer 2 and the interlayer dielectric layer 3 directly above the first dummy gate layer 125 and the second dummy gate layer 135.

[0106] Specifically, after removing the compressive stress layer 2 and interlayer dielectric layer 3 directly above the first dummy gate structure 123 and the second dummy gate structure 133, the upper surfaces of the first dummy gate layer 125 and the second dummy gate layer 135, the upper surface of the remaining interlayer dielectric layer 3, and the exposed surface of the remaining compressive stress layer 2 are flush. The methods for removing the compressive stress layer 2 and interlayer dielectric layer 3 directly above the first dummy gate structure 123 and the second dummy gate structure 133 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods. Preferably, chemical mechanical polishing is used to remove the interlayer dielectric layer 3 and the compressive stress layer 2 directly above the first dummy gate structure 123 and the second dummy gate structure 133.

[0107] Specifically, such as Figure 5 The diagram shown is a cross-sectional view of the structure after removing the first dummy gate structure 123. The method for removing the first dummy gate layer 125 from the first dummy gate structure 123 includes dry etching, wet etching, or other suitable methods. Preferably, a dry etching process is used to remove the first dummy gate layer 125.

[0108] Specifically, after removing the first dielectric layer 124 from the first dummy gate structure 123, a first contact hole is formed, exposing the upper surface of the first well region 12. When the sidewalls of the first dummy gate structure 123 are provided with a first sidewall 126, the inner wall of the first contact hole is the first sidewall 126. When the sidewalls of the first dummy gate structure 123 are not provided with a first sidewall 126, the inner wall of the first contact hole is the interlayer dielectric layer 3. The method for removing the first dielectric layer 124 from the first dummy gate structure 123 includes dry etching, wet etching, or other suitable methods. Preferably, a dry etching process is used to remove the first dielectric layer 124.

[0109] As an example, the first metal gate structure 127 includes at least a third dielectric layer 128 and a first metal layer 129. The third dielectric layer 128 covers the upper surface of the first well region 12 between the first source structure 121 and the first drain structure 122, and the first metal layer 129 is located on the upper surface of the third dielectric layer 128.

[0110] It should be noted that after removing the first dielectric layer 124 and before forming the third dielectric layer 128, the step of forming a first buffer layer is also included. The first buffer layer at least covers the upper surface of the first well region 12 exposed by the bottom surface of the first contact hole.

[0111] Specifically, the first buffer layer is used to improve the interface state between the third dielectric layer 128 and the upper surface of the first well region 12 exposed by the bottom surface of the first contact hole. The material of the first buffer layer includes silicon oxynitride or other suitable dielectric materials.

[0112] Specifically, the first buffer layer also covers the inner wall of the first contact hole. The thickness of the first buffer layer can be selected according to the actual situation while ensuring device performance; the method of forming the first buffer layer can be selected according to the actual situation.

[0113] Specifically, the method for forming the third dielectric layer 128 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. Preferably, the third dielectric layer 128 is formed using atomic layer deposition.

[0114] Specifically, the methods for forming the first metal layer 129 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0115] Specifically, the method for removing the second dummy gate layer 135 in the second dummy gate structure 133 includes dry etching, wet etching, or other suitable methods. Preferably, a dry etching process is used to remove the second dummy gate layer 135.

[0116] Specifically, after removing the second dielectric layer 134 from the second dummy gate structure 133, a second contact hole is formed, exposing the upper surface of the second well region 13. When the second dummy gate structure 133 has a second sidewall 136 on its outer periphery, the inner wall of the second contact hole is the second sidewall 136. When the second dummy gate structure 133 does not have a second sidewall 136 on its outer periphery, the inner wall of the second contact hole is the interlayer dielectric layer 3. The method for removing the second dielectric layer 134 from the second dummy gate structure 133 includes dry etching, wet etching, or other suitable methods. Preferably, a dry etching process is used to remove the second dielectric layer 134.

[0117] As an example, such as Figure 6 The diagram shows a cross-sectional view of the second metal gate structure 137 after it has been formed. The second metal gate structure 137 includes at least a fourth dielectric layer 138 and a second metal layer 139. The fourth dielectric layer 138 covers the upper surface of the second well region 13 between the second source structure 131 and the second drain structure 132. The second metal layer 139 is located on the upper surface of the fourth dielectric layer 138.

[0118] It should be noted that after removing the second dielectric layer 134 and before forming the fourth dielectric layer 138, the step of forming a second buffer layer is also included. The second buffer layer at least covers the upper surface of the second well region 13 exposed by the bottom surface of the second contact hole.

[0119] Specifically, the second buffer layer is used to improve the interface state between the fourth dielectric layer 138 and the upper surface of the second well region 13 exposed by the bottom surface of the second contact hole. The material of the second buffer layer includes silicon oxynitride or other suitable dielectric materials.

[0120] Specifically, the second buffer layer also covers the inner wall of the second contact hole. The thickness of the second buffer layer can be selected according to the actual situation while ensuring device performance; the method of forming the second buffer layer can also be selected according to the actual situation.

[0121] Specifically, the method for forming the third dielectric layer 128 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. Preferably, the third dielectric layer 128 is formed using atomic layer deposition.

[0122] Specifically, the methods for forming the second metal layer 139 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0123] As an example, the first metal layer 129 and the second metal layer 139 are made of different materials so that the first metal layer 129 has a work function that matches the first well region 12, and the second metal layer 139 has a work function that matches the second well region 13.

[0124] It should be noted that, since the first metal layer 129 and the second metal layer 139 are made of different materials, the first metal gate structure 127 and the second metal gate structure 137 usually need to be formed in steps. The formation order of the first metal gate structure 127 and the second metal gate structure 137 can be selected according to the actual situation.

[0125] Specifically, such as Figure 7 As shown, this is a cross-sectional structural diagram after the insulating layer 4 is formed. After the first metal gate structure 127 and the second metal gate structure 137 are formed, and before the electrodes of the device are formed, the step of forming the insulating layer 4 that covers the interlayer dielectric layer 3, the compressive stress layer 2, the first metal gate structure 127 and the second metal gate structure 137 and exposes the upper surface is also included.

[0126] Specifically, the methods for forming the insulating layer 4 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0127] Specifically, the material of insulating layer 4 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The thickness of insulating layer 4 can be selected according to the actual situation while ensuring device performance.

[0128] Specifically, such as Figure 8 The diagram shown is a cross-sectional view of the structure after each electrode is formed. The methods for forming each electrode (first source 5, first drain 6, first gate 7, second source 51, second drain 61 and second gate 71) include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0129] Specifically, before forming the interlayer dielectric layer 3, a compressive stress film layer of a predetermined thickness is formed directly on the upper surface of the semiconductor structure 1. In metal gate devices with processes below 28nm, the portions of the first source structure 121 and the first drain structure 122 protruding from the first well region 12 have a larger dimension in the extension direction of the first metal gate structure 127, and the height of the first source structure 121 and the first drain structure 122 protruding from the upper surface of the first well region 12 is relatively higher. After forming the first metal gate structure 127, the first source electrode 5, and the first drain electrode 6, the compressive stress layer 2 covering the sidewalls of the portions of the first source structure 121 and the first drain structure 122 protruding from the first well region 12 is used to press the first source structure 121 and the first drain structure 122 respectively, generating a large compressive force on the first source structure 121 and the first drain structure 122, thereby increasing the channel stress in the arrangement direction of the first source structure 121 and the first drain structure 122 and improving the performance of the device in the first well region 12.

[0130] Specifically, since the second source structure 131 and the second drain structure 132 do not protrude from the upper surface of the second well region 13 or protrude to a small height from the upper surface of the second well region 13, and after the formation of the second metal gate structure 137, the second source electrode 51 and the second drain electrode 61, the compressive stress layer 2 in this region is destroyed, and the stress exerted by the compressive stress layer 2 on the second source structure 131 and the second drain structure 132 is small, the compressive stress layer 2 above the second well region 13 has no effect on the performance of the device formed in the second well region 13, thus ensuring the performance of the device formed in the second well region 13.

[0131] The semiconductor device fabrication method of this embodiment improves the device fabrication process by forming a compressive stress layer 2 covering the upper surface of the semiconductor structure 1. After forming the first source 5, the first drain 6, the first metal gate structure 127, the second source 51, the second drain 61, and the second metal gate structure 137, based on the high protrusion height of the first source structure 121 and the first drain structure 122 from the first well region 12, the compressive stress layer 2 covering the sidewalls of the first source structure 121 and the first drain structure 122 protruding from the first well region 12 is used to compress the first source structure 121 and the first drain structure 122. The first source structure 121 and the first drain structure 122, combined with the first source structure 121, the first drain structure 122 and the compressive stress layer 2, increase the channel stress of the device. This avoids the problem that the channel stress of the device in the first well region 12 is insufficient due to the formation of the first source electrode 5, the first drain electrode 6 and the first metal gate structure 127 and the small size of the first source structure 121 and the first drain structure 122, which would affect the performance of the device. Moreover, the formation of the compressive stress layer 2 has no effect on the performance of the device in the second well region 13, thus improving the overall performance of the device.

[0132] Example 2

[0133] This embodiment also provides a semiconductor device, such as Figure 8 The diagram shown is a cross-sectional view of the semiconductor device, which is fabricated using the semiconductor device fabrication method described above.

[0134] Specifically, the semiconductor device includes a semiconductor structure 1, a compressive stress layer 2, a first source 5, a first drain 6, a second source 51, a second drain 61, a first gate 7, and a second gate 71. The semiconductor structure 1 includes a semiconductor layer and a first metal gate structure 127 and a second metal gate structure 137 arranged at intervals. The semiconductor layer includes at least one first well of a first conductivity type and at least one second well region 13 of a second conductivity type located on the upper surface of the semiconductor layer. The upper surface of the first well region 12 has a first source structure 121 of a second conductivity type and a first drain structure 122 of a second conductivity type located on opposite sides of the first metal gate structure 127. The upper surface of the second well region 13 has a second source structure 13 of a first conductivity type located on opposite sides of the second metal gate structure 137. 1. A first conductive type second drain structure 132, a first metal gate structure 127 located on the upper surface of the first well region 12, and a second metal gate structure 137 located on the upper surface of the second well region 13; a compressive stress layer 2 covers the upper surface of the semiconductor structure 1, and the compressive stress layer 2 at the first metal gate structure 127 and the second metal gate structure 137 does not cover the upper surfaces of the first metal gate structure 127 and the second metal gate structure 137; a first source 5 is electrically connected to the first source structure 121, a first drain 6 is electrically connected to the first drain structure 122, a second source 51 is electrically connected to the second source structure 131, a second drain 61 is electrically connected to the second drain structure 132, a first gate 7 is electrically connected to the first metal gate structure 127, and a second gate 71 is electrically connected to the second metal gate structure 137.

[0135] It should be noted that the semiconductor structure 1 in this embodiment is the structure obtained by replacing the first dummy gate structure 123 and the second dummy gate structure 133 in the semiconductor structure 1 of embodiment 1 with the first metal gate structure 127 and the second metal gate structure 137, respectively.

[0136] Specifically, the semiconductor layer also includes a substrate 11, a first well region 12 and a second well region 13 located on the upper surface of the substrate 11, and the conductivity type of the substrate 11 can be a first conductivity type, a second conductivity type or an intrinsic semiconductor.

[0137] Specifically, the first well region 12 and the second well region 13 can be spaced apart, or the first well region 12 can be located on the upper surface of the second well region 13, or the second well region 13 can be located on the upper surface of the first well region 12. In this embodiment, the first well region 12 and the second well region 13 are spaced apart by a preset distance.

[0138] It should be noted that when the first well region 12 and the second well region 13 are usually arranged alternately, an isolation structure 14 is also provided between the first well region 12 and the second well region 13 to achieve isolation between the devices in the first well region 12 and the devices in the second well region 13. While ensuring device performance, the specific construction of the isolation structure 14 can be selected according to the actual situation.

[0139] Specifically, the material of the first source structure 121 includes SiGe or other suitable semiconductor materials, and the material of the first drain structure 122 includes SiGe or other suitable semiconductor materials. Preferably, both the first source structure 121 and the first drain structure 122 are made of SiGe, that is, the device is a strained silicon device.

[0140] It should be noted that, due to the characteristics of SiGe strain gauges, the first source structure 121 and the first drain 6 typically fill the two sigma trenches on opposite sides of the first metal gate structure 127, and the first source structure 121 and the first drain structure 122 protrude significantly from the first well region 12. The upper surface of the first source structure 121 has a first source region 1211 with a bottom surface lower than a predetermined distance from the upper surface of the first well region 12, and the upper surface of the first drain structure 122 has a first drain region 1221 with a bottom surface lower than a predetermined distance from the upper surface of the first well region 12.

[0141] Specifically, while ensuring device performance, the distance between the upper surface of the first source structure 121 and the upper surface of the first well region 12 can be selected according to actual conditions; the cross-sectional dimensions, cross-sectional shape, and thickness of the first source structure 121 can be selected according to actual conditions; the cross-sectional dimensions, cross-sectional shape, and thickness of the first drain structure 122 can be selected according to actual conditions; the distance between the upper surface of the first drain structure 122 and the upper surface of the first well region 12 can be selected according to actual conditions; the distance between the bottom surface of the first source region 1211 and the upper surface of the first well region 12 can be selected according to actual conditions; the distance between the bottom surface of the first drain region 1221 and the upper surface of the first well region 12 can be selected according to actual conditions. In this embodiment, the relevant parameters of the first source structure 121 and the first drain structure 122 are the same.

[0142] Specifically, the second source structure 131 and the second drain structure 132 are usually heavily doped regions of the first conductivity type. While ensuring device performance, the cross-sectional size, cross-sectional shape and thickness of the second source structure 131 can be selected according to the actual situation; the cross-sectional shape and thickness of the second drain structure 132 can be selected according to the actual situation.

[0143] Specifically, the semiconductor structure 1 also includes a first sidewall 126 covering the sidewall of the first metal gate structure 127 and a second sidewall 136 covering the sidewall of the second metal gate structure 137. The first sidewall 126 surrounds the first metal gate structure 127, and the upper surface of the first sidewall 126 is flush with the upper surface of the first metal gate structure 127. The second sidewall 136 surrounds the second metal gate structure 137, and the upper surface of the second sidewall 136 is flush with the upper surface of the second metal gate structure 137. The compressive stress layer 2 covers the side of the first sidewall 126 away from the sidewall of the first metal gate structure 127 and the side of the second sidewall 136 away from the sidewall of the second metal gate structure 137.

[0144] Specifically, the first metal gate structure 127 includes a third dielectric layer 128 and a first metal layer 129. The third dielectric layer 128 at least covers the upper surface of the first well region 12 between the first source structure 121 and the first drain structure 122, and the first metal layer 129 covers the upper surface of the third dielectric layer 128. The second metal gate structure 137 includes a fourth dielectric layer 138 and a second metal layer 139. The fourth dielectric layer 138 at least covers the upper surface of the second well region 13 between the second source structure 131 and the second drain structure 132, and the second metal layer 139 covers the upper surface of the fourth dielectric layer 138.

[0145] Specifically, when the semiconductor structure 1 is provided with a first sidewall 126 and a second sidewall 136, the third dielectric layer 128 also wraps the sidewall of the first metal layer 129, the first sidewall 126 covers the side of the third dielectric layer 128 away from the sidewall of the first metal layer 129, and the fourth dielectric layer 138 also includes the sidewall of the second metal layer 139, the second sidewall 136 covers the side of the fourth dielectric layer 138 away from the sidewall of the second metal layer 139.

[0146] It should be noted that a first buffer layer and a second buffer layer are usually provided between the third dielectric layer 128 and the first well region 12, and between the fourth dielectric layer 138 and the second well region 13, respectively. The first buffer layer is used to improve the interface state between the first well region 12 and the third dielectric layer 128, and the second buffer layer is used to improve the interface state between the fourth dielectric layer 138 and the second well region 13.

[0147] Specifically, the third dielectric layer 128 has a high K value, and the material of the third dielectric layer 128 includes tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate, or other suitable high K dielectric materials; the fourth dielectric layer 138 has a high K value, and the material of the fourth dielectric layer 138 includes tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate, or other suitable high K dielectric materials.

[0148] Specifically, the material of the first metal layer 129 is related to the conductivity type of the first well region 12. The Fermi level of the first metal layer 129 is close to the valence band top (P-type metal gate layer) of the first well region 12 to ensure the threshold voltage of the first metal gate structure 127. The material of the first metal layer 129 includes hafnium, zirconium, titanium, tantalum, aluminum, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, titanium nitride, tantalum nitride, or other suitable conductive materials; the second metal layer 139... The upper surface is flush with the interlayer dielectric layer 3. The material of the second metal layer 139 is related to the conductivity type of the second well region 13. The Fermi level of the second metal layer 139 is close to the valence band top (N-type metal gate layer) of the second well region 13 to ensure the threshold voltage of the second metal gate structure 137. The material of the second metal layer 139 includes hafnium, zirconium, titanium, tantalum, aluminum, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, titanium nitride, tantalum nitride, or other suitable conductive materials.

[0149] Specifically, the compressive stress layer 2 is made of silicon nitride or other suitable materials. Preferably, it has a thickness of [missing information]. A thin silicon nitride layer is used as the compressive stress layer 2.

[0150] Specifically, the semiconductor device also includes an interlayer dielectric layer 3 and an insulating layer 4 stacked sequentially. The interlayer dielectric layer 3 covers the upper surface of the compressive stress layer 2, and the upper surface of the interlayer dielectric layer 3 is flush with the upper surfaces of the first metal layer 129 and the second metal layer 139.

[0151] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0152] Specifically, the insulating layer 4 covers the exposed upper surfaces of the interlayer dielectric layer 3, the first metal gate structure 127, and the second metal gate structure 137. The first source electrode 5 penetrates the insulating layer 4, the interlayer dielectric layer 3, and the compressive stress layer 2 directly above the first source structure 121 to be electrically connected to the first source structure 121. The first drain electrode 6 penetrates the insulating layer 4, the interlayer dielectric layer 3, and the compressive stress layer 2 directly above the first drain structure 122 to be electrically connected to the first drain structure 122. The first gate electrode 7 penetrates the insulating layer directly above the first metal gate structure 127. 4. The second source 51 is electrically connected to the first metal layer 129 in the first metal gate structure 127. The second source 51 penetrates the insulating layer 4, the interlayer dielectric layer 3 and the compressive stress layer 2 directly above the second source structure 131 to be electrically connected to the second source structure 131. The second drain 61 penetrates the insulating layer 4, the interlayer dielectric layer 3 and the compressive stress layer 2 directly above the second drain structure 132 to be electrically connected to the second drain structure 132. The second gate 71 penetrates the insulating layer 4 directly above the second metal gate structure 137 to be electrically connected to the second metal layer 139.

[0153] Specifically, the materials of each electrode include titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials.

[0154] Specifically, the semiconductor device is fabricated using the semiconductor device fabrication method described in Example 1. The compressive stress layer 2 is used to compress the sidewalls of the first source structure 121 and the first drain structure 122 that protrude from the upper surface of the first well region 12, thereby increasing the channel stress of the device fabricated based on the first well region 12, improving the performance of the semiconductor device formed in the first well region 12, while not affecting the performance of the device formed in the second well region 13, thus improving the overall performance of the device.

[0155] The semiconductor device in this embodiment is fabricated using the semiconductor device fabrication method described in Embodiment 1, which improves the performance of the semiconductor device formed in the first well region 12 without affecting the performance of the device formed in the second well region 13.

[0156] In summary, the semiconductor device and its fabrication method of the present invention, by improving the device fabrication process, form a compressive stress layer on the upper surface of the semiconductor structure. Because the first source structure and the first drain structure protrude significantly from the upper surface of the first well region, the sidewalls covering the portions of the first source structure and the first drain structure protruding from the first well region are subjected to greater compressive stress from the compressive stress layer. Subsequently, the combination of the first source structure, the first drain structure, and the compressive stress layer increases the channel stress experienced by the device formed in the first well region. Furthermore, while improving the performance of the device fabricated in the first well region, it does not affect the performance of the device formed in the second well region, thus improving the overall performance of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0157] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor structure is provided, including a semiconductor layer and a first dummy gate structure and a second dummy gate structure spaced apart. The semiconductor layer includes at least one first well region of a first conductivity type and at least one second well region of a second conductivity type located on the upper surface of the semiconductor layer. A first source structure and a first drain structure are formed on opposite sides of the first dummy gate structure on the upper surface of the first well region. A second source structure and a second drain structure are formed on opposite sides of the second dummy gate structure on the upper surface of the second well region. The first dummy gate structure and the second dummy gate structure are respectively located on the upper surfaces of the first well region and the second well region. The first source structure is embedded in the upper surface of the semiconductor layer and the upper surface of the first source structure protrudes from the upper surface of the first well region. The first drain structure is embedded in the upper surface of the first well region and the upper surface of the first drain structure protrudes from the upper surface of the first well region. The material of the first source structure includes SiGe, and the material of the first drain structure includes SiGe. A compressive stress layer is formed covering the upper surface of the semiconductor structure. Through the combination of the first source structure, the first drain structure and the compressive stress layer, the channel stress of the device formed in the first well region is enhanced, and the performance of the device formed in the first well region is improved without affecting the performance of the device formed in the second well region. Remove the first dummy gate structure and form a first metal gate structure; remove the second dummy gate structure and form a second metal gate structure. A first source electrically connected to the first source structure, a first drain electrically connected to the first drain structure, a second source electrically connected to the second source structure, a second drain electrically connected to the second drain structure, a first gate electrically connected to the first metal gate structure, and a second gate electrically connected to the second metal gate structure are formed.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: The thickness of the compressive stress layer ranges from 100 Å to 150 Å.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that: The compressive stress layer is made of silicon nitride.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first dummy gate structure includes at least a first dielectric layer located on the upper surface of the first well region and a first dummy gate layer located on the upper surface of the first dielectric layer; the second dummy gate structure includes at least a second dielectric layer located on the upper surface of the second well region and a second dummy gate layer located on the upper surface of the second dielectric layer; the first metal gate structure includes at least a third dielectric layer and a first metal layer, the third dielectric layer covering the upper surface of the first well region between the first source structure and the first drain structure, and the first metal layer located on the upper surface of the third dielectric layer; The second metal gate structure includes at least a fourth dielectric layer and a second metal layer. The fourth dielectric layer covers the upper surface of the second well region between the second source structure and the second drain structure, and the second metal layer is located on the upper surface of the fourth dielectric layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that: The first metal layer and the second metal layer are made of different materials.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that: After the compressive stress layer is formed, and before the first dummy gate structure and the second dummy gate structure are removed, the method further includes the step of forming an interlayer dielectric layer covering the upper surface of the compressive stress layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that: After the interlayer dielectric layer is formed, and before the first metal gate structure and the second metal gate structure are formed, the method further includes the step of removing the compressive stress layer and the interlayer dielectric layer directly above the first dummy gate structure and the second dummy gate structure.

8. A semiconductor device, characterized in that, The semiconductor device is fabricated using the semiconductor device fabrication method as described in any one of claims 1 to 7.

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