Fabrication methods of stacked transistors, stacked transistors and semiconductor devices

Abstract

This application provides a method for fabricating a stacked transistor, a stacked transistor, and a semiconductor device. The method includes: forming a fin-like structure on a semiconductor substrate, the fin-like structure including a first portion and a second portion stacked along a first direction; forming at least one first transistor based on the first portion, the first transistor including a first drain structure, a first gate structure, and a first source structure arranged sequentially along a second direction; washing and removing the semiconductor substrate; forming at least one second transistor based on the second portion, the second transistor including a second drain structure, a second gate structure, and a second source structure arranged sequentially along the second direction; stacking the second gate structure and the first drain structure along the first direction; forming a first metal interconnect via connecting the second drain structure and the first gate structure, and forming a second metal interconnect via connecting the second gate structure and the first drain structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a method for fabricating stacked transistors, stacked transistors, and semiconductor devices. Background Technology

[0002] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] In some methods for fabricating stacked transistors, the active regions of two homogeneous transistor layers are formed by etching, and the stacked transistors are fabricated on both sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip-chip transistor" method. However, the front and back structures of the "self-aligned flip-chip transistor" have a mirror symmetry relationship, which makes the internal wiring of the transistor complex and extremely difficult to fabricate during the formation of decoupling capacitors based on the "self-aligned flip-chip transistor," and is also detrimental to the miniaturization of integrated circuits. Summary of the Invention

[0004] This application provides a method for fabricating stacked transistors, stacked transistors, and semiconductor devices, which realizes the interleaved design of two layers of homogeneous transistors. This allows the interconnects inside the decoupling capacitor to be realized using the first metal interconnect via and the second metal interconnect via, thereby effectively reducing the fabrication difficulty and not increasing the size of the transistor unit, which helps to further improve the integration level of the circuit.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a stacked transistor, comprising: forming a fin-like structure on a semiconductor substrate, wherein the fin-like structure includes a first portion and a second portion stacked along a first direction, the first portion being closer to the semiconductor substrate than the second portion; forming at least one first transistor based on the first portion, wherein the first transistor includes: a first drain structure, a first gate structure, and a first source structure arranged sequentially along a second direction; the second direction being perpendicular to the first direction; flipping and removing the semiconductor substrate; forming at least one second transistor based on the second portion, wherein the second transistor includes: a second source structure, a second gate structure, and a second drain structure arranged sequentially along the second direction; the second gate structure and the first drain structure are stacked along the first direction, and the second drain structure and the first gate structure are stacked along the first direction; forming a first metal interconnect via connecting the second drain structure and the first gate structure, and forming a second metal interconnect via connecting the second gate structure and the first drain structure.

[0006] In some possible implementations, forming at least one second transistor based on the second portion includes: forming a second source structure and a second drain structure alternately arranged in sequence along a second direction based on the second portion; forming a second gate structure and a second single-diffused isolation structure between the second source structure and the second drain structure based on the second portion, such that the second source structure, the second gate structure, the second drain structure, and the second single-diffused isolation structure are arranged in sequence; wherein the second single-diffused isolation structure is stacked with the first source structure along a first direction; the second source structure is stacked with the first single-diffused isolation structure in the first transistor along a first direction; a second gate structure and an adjacent second source structure and a second drain structure form a second transistor; the second single-diffused isolation structure is used to electrically isolate two adjacent second transistors.

[0007] In some possible implementations, based on the second portion, a second gate structure and a second monodiffusion isolation structure are formed between the second source structure and the second drain structure, including: based on the second portion, forming a second gate structure on top of the first source structure and the first drain structure; removing the second gate structure located on top of the first source structure, and depositing insulating material at the location where the second gate structure is removed to form the second monodiffusion isolation structure.

[0008] In some possible implementations, based on the second portion, forming a second source structure and a second drain structure that are alternately arranged in sequence along a second direction includes: forming a second drain structure on top of a first gate structure based on the second portion; and forming a second source structure on both sides of the second drain structure based on the second portion, so that the second source structure and the second drain structure are alternately arranged in sequence along a second direction.

[0009] In some possible implementations, forming at least one first transistor based on the first portion includes: forming a first drain structure and a first source structure arranged alternately in a second direction based on the first portion; forming a first gate structure and a first monodiffusion isolation structure between the first drain structure and the first source structure based on the first portion, such that the first monodiffusion isolation structure, the first drain structure, the first gate structure and the first source structure are arranged in sequence; the first monodiffusion isolation structure is used to electrically isolate two adjacent first transistors.

[0010] In some possible implementations, the second transistor includes a second drain metal; forming a first metal interconnect via connecting the second drain structure and the first gate structure; and forming a second metal interconnect via connecting the second gate structure and the first drain structure, including any of the following: forming a first metal interconnect via connecting the second drain structure and the first gate structure before forming the second drain metal; forming a second metal interconnect via connecting the second gate structure and the first drain structure before forming the second gate structure; forming a first metal interconnect via connecting the second drain structure and the first gate structure before forming the second drain metal; and forming a second metal interconnect via connecting the second gate structure and the first drain structure after forming the second gate structure; forming a first metal interconnect via connecting the second drain structure and the first gate structure after forming the second drain metal; and forming a second metal interconnect via connecting the second gate structure and the first drain structure before forming the second gate structure.

[0011] Secondly, embodiments of this application provide a stacked transistor, comprising: at least one first transistor and at least one second transistor, wherein the first transistor and the second transistor are stacked along a first direction; wherein the first transistor comprises: a first drain structure, a first gate structure, and a first source structure arranged sequentially along a second direction; the second direction is perpendicular to the first direction; the second transistor comprises: a second source structure, a second gate structure, and a second drain structure arranged sequentially along the second direction; the second drain structure and the first gate structure are stacked along the first direction, and a first metal interconnect via is provided between the second drain structure and the first gate structure; the second gate structure and the first drain structure are stacked along the first direction, and a second metal interconnect via is provided between the second gate structure and the first drain structure; the first metal interconnect via is used to connect the second drain structure and the first gate structure, and the second metal interconnect via is used to connect the second gate structure and the first drain structure.

[0012] In some possible implementations, the stacked transistors further include: a first monodiffusion isolation structure stacked with the second source structure along a first direction, and a second monodiffusion isolation structure stacked with the first source structure along a first direction; wherein the first monodiffusion isolation structure is used to electrically isolate two adjacent first transistors; and the second monodiffusion isolation structure is used to electrically isolate two adjacent second transistors.

[0013] In some possible implementations, at least one first transistor may be a plurality of first transistors, with two adjacent first transistors sharing a first source structure, and / or, when at least one second transistor may be a plurality of second transistors, two adjacent second transistors may share a second source structure.

[0014] Thirdly, embodiments of this application provide a semiconductor device, which includes: stacked transistors as described in the above embodiments.

[0015] In this embodiment, by utilizing both the front and back sides of a wafer to fabricate two layers of transistors, the integration density of the transistors is increased, further improving their integration performance. Furthermore, the staggered arrangement of the two layers allows for electrical connections between different structures within the transistors to be achieved simply by forming metal interconnect vias. Compared to related technologies that employ complex interconnect lines, this embodiment not only more easily meets the needs of different logic circuits and effectively reduces fabrication difficulty, but also does not increase the size of transistor units, thus contributing to further improvements in circuit integration.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 This is a schematic diagram of a first structure of stacked transistors in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of a second structure of stacked transistors in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of one circuit configuration of the decoupling capacitor in an embodiment of this application;

[0021] Figure 4 As in the embodiments of this application Figure 3 A schematic diagram of one layout of the decoupling capacitor is shown;

[0022] Figure 5 This is a schematic diagram of an implementation process of the method for fabricating stacked transistors in this application embodiment;

[0023] Figures 6 to 21 This is a schematic diagram of one fabrication process of the stacked transistor in the embodiments of this application.

[0024] The figures above are as follows: 10. Stacked transistor; 11. First transistor; 112. First source / drain structure; 1121. First source structure; 1122. First drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source / drain metal; 1151. First source metal; 1152. First drain metal; 116. First metal interconnect layer; 12. Two transistors; 122. Second source / drain structure; 1221. Second source structure; 1222. Second drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source / drain metal; 1251. Second source metal; 1252. Second drain metal; 126. Second metal interconnect layer; 13. Metal interconnect line; 131. First metal interconnect via; 132. Second metal interconnect via;

[0025] 20. Semiconductor substrate; 21. Fin structure; 211. First part; 212. Second part; 22. Shallow trench isolation structure; 23. First isolation structure; 24. First single-diffusion isolation structure; 25. Front dielectric layer; 26. Second dummy gate structure; 27. Second single-diffusion isolation structure; 28. Back dielectric layer; 29. ​​First dummy gate structure; 32. Insulating layer; 33. Carrier wafer. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0027] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0028] In one embodiment, there are two methods for fabricating stacked transistors: the first is a monolithic method, and the second is a sequential method.

[0029] The first approach fabricates N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs) on the same substrate without using wafer bonding technology. This dictates that transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Furthermore, the upper and lower transistor layers must be strictly on the same plane, with no alignment deviations. The advantage of this approach is its higher integration density. The disadvantages of this approach include the following two points: (1) the process is complex, requiring extensive development and optimization of process technologies; (2) the polarity of each transistor layer is fixed, necessitating two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0030] The second approach is based on wafer bonding and layer-by-layer fabrication. Specifically, the upper-layer transistor is fabricated by bonding a wafer to the top of a pre-fabricated lower-layer transistor, vertically stacking the two transistors. However, this approach requires strict temperature control during the thermal processing of the upper-layer transistor to avoid affecting the lower-layer transistor and interconnects. The advantage of this approach is that, thanks to wafer bonding, the device structure, channel orientation, and even the channel material used in the upper and lower layers of transistors can be optimized to achieve better and more compatible device performance.

[0031] To address the technical problems of the two aforementioned solutions, a "self-aligned flip-chip transistor" solution is proposed. This solution forms the active regions of homogeneous transistors in upper and lower layers through etching, and stacks transistors on both sides of the wafer through flipping, thereby overcoming the shortcomings of the two solutions.

[0032] For example, Figure 1 This is a schematic diagram of a first structure of stacked transistors in an embodiment of this application, wherein, Figure 1 (a), (b), and (c) are cross-sectional views of the stacked transistors at different locations. See also Figure 1 As shown, in a self-aligned flip-chip transistor, a first transistor 11 is formed on the front side of the wafer, and a second transistor 12 is formed on the back side of the wafer. The first transistor 11 and the second transistor 12 are arranged opposite to each other, and the first source-drain structure 112 in the first transistor 11 and the second source-drain structure 122 in the second transistor 12 are stacked along a first direction, and the first gate structure 114 in the first transistor 11 and the second gate structure 124 in the second transistor 12 are stacked along the first direction.

[0033] Figure 2 This is a schematic diagram of a second structure of stacked transistors in an embodiment of this application, wherein, Figure 2 (a), (b), and (c) are cross-sectional views of the stacked transistors at different locations. See also Figure 2 As shown in (a), in a self-aligned flip transistor, complex interconnect lines need to be set in the metal interconnect layer connecting the gate structure in order to realize the decoupling capacitor.

[0034] First, let's introduce decoupling capacitors.

[0035] In some embodiments, a decoupling capacitor is a capacitor installed at the power supply terminal of a component in a circuit. This capacitor can provide a more stable power supply and reduce the noise coupled from the component to the power supply terminal, thereby indirectly reducing the impact of the component's noise on other components.

[0036] In some embodiments, the decoupling capacitor may be composed of an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor connected in parallel. In one embodiment, the source and drain of the PMOS transistor are shorted and connected to the power supply VDD, and the gate is connected to the power supply VSS. Similarly, the source and drain of the NMOS transistor are connected to the power supply VSS, and the gate is connected to the power supply VDD.

[0037] In one embodiment, the decoupling capacitor may be composed of cross-coupled PMOS transistors and NMOS transistors, wherein the source of the PMOS transistor may be connected to the power supply VDD, and the source of the NMOS transistor may be connected to the power supply VSS.

[0038] Secondly, we introduce a method for implementing decoupling capacitors based on "self-aligned flip transistors".

[0039] See Figure 2 As shown in (b) and (c), in a "self-aligned flip transistor," in order to achieve decoupling capacitance, in addition to setting complex interconnects in the metal interconnect layer connecting the source and drain metals, it is also necessary to form metal interconnects 13 inside the stacked transistor. Here, compared to Figure 1 The stacked transistors shown Figure 2 The stacked transistors shown are extremely difficult to fabricate in order to realize the aforementioned metal interconnect 13. Furthermore, the source and drain metals need to be staggered, which occupies more space inside the stacked transistors and is not conducive to the miniaturization of integrated circuits.

[0040] It is evident that the method of forming decoupling capacitors based on "self-aligned flip transistors" has room for improvement. Therefore, this application provides a method for fabricating stacked transistors, stacked transistors, and a semiconductor device. This method utilizes an interleaved design of two layers of homogeneous transistors, allowing the interconnects within the decoupling capacitor to be realized using first and second metal interconnect vias. This effectively reduces fabrication difficulty without increasing the transistor unit size, thus contributing to further improvements in circuit integration.

[0041] Figure 3 This is a schematic diagram of one circuit configuration of the decoupling capacitor in an embodiment of this application. See also... Figure 3 As shown, two decoupling capacitors with a cross-coupling structure can be connected in parallel between the power supply VDD and the power supply VSS, denoted as the first decoupling capacitor Decap1 and the second decoupling capacitor Decap2, respectively. The first decoupling capacitor Decap1 can be composed of a PMOS transistor and an NMOS transistor. The PMOS transistor and the NMOS transistor can be stacked. The source of the PMOS transistor can be connected to the power supply VDD, the gate of the PMOS transistor can be connected to the drain of the NMOS transistor, the drain of the PMOS transistor can be connected to the gate of the NMOS transistor, and the source of the NMOS transistor can be connected to the power supply VSS. Similarly, the second decoupling capacitor Decap2 has the same structure as the first decoupling capacitor Decap1.

[0042] Figure 4 As in the embodiments of this application Figure 3 The diagram shows a layout of one type of decoupling capacitor. See [link / reference]. Figure 4 As shown, Figure 4 The diagram shows a first decoupling capacitor Decap1 and a second decoupling capacitor Decap2. Both Decap1 and Decap2 include two transistors, which may be composed of structures such as fin structures, gate structures, source / drain metals, single-diffusion isolation structures, interconnect lines in a metal interconnect layer, first metal interconnect vias, and second metal interconnect vias.

[0043] Here, according to Figure 4 As shown in the layout, the first decoupling capacitor Decap1 and the second decoupling capacitor Decap2 can be constructed from stacked transistors.

[0044] In a first aspect, embodiments of this application provide a method for fabricating stacked transistors. Figure 5 This is a schematic diagram illustrating one implementation process of the stacked transistor fabrication method in this application embodiment. See also... Figure 5 As shown, the fabrication method of stacked transistors may include:

[0045] Step S501: Form a fin structure on a semiconductor substrate, wherein the fin structure includes a first portion and a second portion stacked along a first direction, the first portion being closer to the semiconductor substrate than the second portion;

[0046] Step S502: Based on the first part, form at least one first transistor, wherein the first transistor includes: a first drain structure, a first gate structure and a first source structure arranged sequentially along a second direction; the second direction is perpendicular to the first direction;

[0047] Step S503: Wash the wafer and remove the semiconductor substrate;

[0048] Step S504: Based on the second part, at least one second transistor is formed, wherein the second transistor includes: a second drain structure, a second gate structure and a second source structure arranged sequentially along the second direction; the second drain structure and the first gate structure are stacked along the first direction, and the second gate structure and the first drain structure are stacked along the first direction.

[0049] Step S505: Form a first metal interconnect via connecting the second drain structure and the first gate structure, and form a second metal interconnect via connecting the second gate structure and the first drain structure; wherein, the first metal interconnect via is used to connect the second drain structure and the first gate structure, and the second metal interconnect via structure is used to connect the second gate structure and the first drain structure.

[0050] It should be noted that, Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be adjusted in order according to actual needs.

[0051] Figures 6 to 21 This is a schematic diagram illustrating one fabrication process of the stacked transistors in an embodiment of this application. For ease of understanding, Figures 6 to 21 (a) shows along Figure 4 A cross-sectional view along the direction of the dashed line AA'. Figures 6 to 21 (b) shows the route along Figure 2 A cross-sectional view along the direction of the dashed line BB'; Figures 6 to 20 (a) shows along Figure 4 A cross-sectional view along the direction of the dashed line CC'. Figures 6 to 21 (b) shows the route along Figure 2 A cross-sectional view along the direction of the dashed line DD'; the following will be combined with... Figures 3 to 21 The method for fabricating stacked transistors and the resulting stacked transistors provided in the embodiments of this application will be described by way of example.

[0052] In step S501, a fin structure 21 is formed on the semiconductor substrate 20.

[0053] Reference Figure 6 As shown, a semiconductor substrate 20 is provided. The semiconductor substrate 20 can be any semiconductor substrate such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator substrate. Furthermore, a plurality of fin-like structures 21 erected on the semiconductor substrate 20 can be formed thereon.

[0054] In some embodiments, when the stacked transistor 10 is a fin field-effect transistor, the above S501 may include: forming a semiconductor epitaxial layer on the surface of the semiconductor substrate 20 by an epitaxial growth process; etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the substrate, thereby forming a plurality of fin structures 21.

[0055] In some embodiments, when the stacked transistor 10 is a gate-all-around transistor, S301 may include: performing processes such as material layer deposition and epitaxial growth on the semiconductor substrate 20 to form a stacked structure on the semiconductor substrate 20. Subsequently, a single etching process may be used to etch the stacked structure to form a fin structure 21 on the semiconductor substrate 20.

[0056] In this embodiment, the stacked transistor 10 includes two layers of transistors (composed of a first transistor 11 and a second transistor 12), and the active structures of the two layers are formed by the same etching process. That is, the first active structure of the first transistor 11 and the second active structure of the second transistor 12 are formed by the same etching process. Therefore, a larger etching depth can be used when etching the semiconductor substrate 20. For example, the height of the fin structure 21 obtained by etching can be greater than 100 nm. It should be noted that the height of the fin structure 21 can be set according to actual conditions, and this embodiment does not specifically limit it.

[0057] It is understood that the fin structure 21 includes a first portion 211 and a second portion 212. The first portion 211 and the second portion 212 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20), with the second portion 212 being closer to the semiconductor substrate 20 than the first portion 211.

[0058] It is understood that the first portion 211 of the fin structure 21 is used in subsequent steps to form the active region of the first transistor 11; the second portion 212 of the fin structure 21 is used to form the active region of the second transistor 12.

[0059] It should be noted that the first transistor 11 is fabricated on the front side of the semiconductor substrate 20, and after the stacked transistors 10 are fabricated, the first transistor 11 is located on the lower layer of the stacked transistors 10. The second transistor 12 is the opposite of the first transistor 11.

[0060] In step S502, at least one first transistor 11 is formed based on the first portion 211.

[0061] In some embodiments, the first transistor 11 includes a first drain structure 1122, a first gate structure 114, and a first source structure 1121 arranged sequentially along a second direction; the second direction is perpendicular to the first direction.

[0062] It is understood that the first transistor 11 can be formed based on the first portion 211 of the fin structure 21. In one embodiment, when the first transistor 11 is a P-type (P-channel) field-effect transistor, the second transistor 12 can be an N-type (N-channel) field-effect transistor; when the first transistor 11 is an N-type field-effect transistor, the second transistor 12 can be a P-type field-effect transistor. The following explanation uses an N-type field-effect transistor as an example.

[0063] In some embodiments, see Figure 7 As shown, before forming the first transistor 11, an insulating material can be deposited on the semiconductor substrate 20 to form a shallow trench isolation (STI) structure 22. The shallow trench isolation structure 22 encloses the second portion 212 of the fin structure 21, exposing the first portion 211 of the active structure. The insulating material forming the shallow trench isolation structure 22 can be a silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0064] In some embodiments, step S502 may include: forming a first drain structure 1122 and a first source structure 1121 arranged alternately along a second direction based on the first portion 211; and forming a first gate structure 114 and a first monodiffusion isolation structure 24 between the first drain structure 1122 and the first source structure 1121 based on the first portion, so that the first monodiffusion isolation structure 24, the first drain structure 1122, the first gate structure 114, and the first source structure 1121 are arranged in sequence.

[0065] See Figure 8 As shown, based on Figure 7When the semiconductor structure shown forms at least one first transistor 11, a dummy gate material such as polycrystalline silicon or amorphous silicon can be deposited in the gate region of the front-side transistor to form a first dummy gate structure 29. After forming the first dummy gate structure 29, an insulating material can be deposited on the sidewalls of the first dummy gate structure 29 to form a first dummy gate sidewall covering the sidewalls of the first dummy gate structure 29.

[0066] In some embodiments, the material forming the dummy gate sidewall is silicon dioxide (SiO2).

[0067] See Figure 9 As shown, after forming the first dummy gate structure 29, a first source / drain structure 112 can be formed in the source / drain region between two adjacent first dummy gate structures 29, based on the first portion 211 of the fin structure 21. Here, the first source / drain structure 112 may include a first drain structure 1122 and a first source structure 1121. The first drain structure 1122 and the first source structure 1121 can be arranged alternately along the second direction within the front-side transistor.

[0068] Understandably, after forming the first dummy gate structure 29, the first dummy gate structure 29 can be used as a hard mask to form a source / drain trench in the source / drain region of the front-side transistor by etching the first portion 211 located in the source / drain region of the front-side transistor. Subsequently, strained materials such as silicon germanium or silicon carbide can be selectively epitaxially grown in the source / drain trench to fill the source / drain trench, and then the first source / drain structure 112 of the first transistor 11 is formed on the strained material by a heavy doping process.

[0069] In some embodiments, a first source / drain structure 112 is formed based on a source / drain groove, and a dielectric layer material can be deposited on the first source / drain structure 112 to form a first interlayer dielectric layer 113.

[0070] In one embodiment, the dielectric material forming the first interlayer dielectric layer 113 has high insulating properties. In one embodiment, the first interlayer dielectric layer 113 is formed by chemical vapor deposition or a high aspect ratio (HARP) trenching process. Using a high aspect ratio trenching process can increase the isolation effect of the first interlayer dielectric layer 113.

[0071] See Figure 10 As shown, after forming the first source / drain structure 112, the first dummy gate structure 29 can be removed, and dielectric material and metal material can be sequentially deposited at the location where the first dummy gate structure 29 is removed to form a first gate dielectric layer and a first gate metal layer, respectively. Here, the first gate dielectric layer and the first gate metal layer can constitute the first gate structure 114.

[0072] In some embodiments, the materials of the first gate dielectric layer and the first gate electrode layer can be set according to actual needs, and this application embodiment does not specifically limit them. For example, the first gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, each layer of which includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In one example, the first gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0073] See Figure 11 As shown, after forming the first gate structure 114, a first source / drain metal 115 can be formed. Here, the first source / drain metal 115 may include a first source metal 1151 and a first drain metal 1152. That is, after forming the first gate structure 114, metal material can be deposited on the first source structure 1121 to form the first source metal 1151; and metal material can be deposited on the first drain structure 1122 to form the first drain metal 1152.

[0074] See Figure 12 As shown, after forming the first source / drain metal 115, the first gate structure 114 located at the edge or between two first transistors 11 can be removed, and insulating material can be deposited at the location where the first gate structure 114 is removed to form a first monodiffusion isolation structure 24. Here, the first monodiffusion isolation structure 24 is used to electrically isolate two adjacent first transistors 11. Alternatively, the first monodiffusion isolation structure 24 is used to electrically isolate transistor units from other electronic components.

[0075] In some embodiments, the insulating material forming the first monodiffusion isolation structure 24 may be selected according to actual needs, and this application embodiment does not limit this.

[0076] Understandably, after obtaining the first monodiffused isolation structure 24, the first source structure 1121 and the first drain structure 1122 are located on both sides of a first gate structure 114. The first monodiffused isolation structure 24, the first drain structure 1122, the first gate structure 114, and the first source structure 1121 can be arranged sequentially.

[0077] It should be noted that when there are multiple first transistors 11 in the stacked transistors, the arrangement directions of the first single-diffused isolation structure 24, the first drain structure 1122, the first gate structure 114, and the first source structure 1121 in two adjacent first transistors 11 can be different. For example, the first single-diffused isolation structure 24, the first drain structure 1122, the first gate structure 114, and the first source structure 1121 in the first first transistor 11 are arranged sequentially along the second direction, and the first single-diffused isolation structure 24, the first drain structure 1122, the first gate structure 114, and the first source structure 1121 in the second first transistor 11 are arranged sequentially along the third direction. The third direction can be opposite to the second direction.

[0078] In some embodiments, see Figure 13 As shown, after forming the first gate structure 114 and the first source / drain metal 115, the method further includes: depositing a dielectric material on the first gate structure 114 and the first source / drain metal 115 to form a front dielectric layer 25; and forming the first metal interconnect layer 116 of the stacked transistor 10 on the front dielectric layer 25 using standard back-end processes for semiconductor fabrication (such as inter-interconnect dielectric deposition, metal line formation, lead-out pad formation, etc.).

[0079] In step S503, the semiconductor substrate 20 is flipped and removed.

[0080] It is understandable that after obtaining at least one first transistor 11, the first transistor 11 can be flipped so that the fabricated first transistor 11 is located at the bottom and the second part 212 of the fin structure 21 is located at the top, which facilitates the subsequent fabrication of the second transistor 12.

[0081] In one embodiment, see Figure 14 As shown, after completing the back-end processes of the first transistor 11, the first transistor 11 can be bonded to the carrier wafer 33. For example, an insulating material (such as silicon oxide) can be deposited on the first transistor 11 to form an insulating layer 32, and the insulating layer 32 can be bonded to the carrier wafer 33. Then, a wafer flipping process is performed, after which the first transistor 11 is located at the bottom. After the wafer flipping, processes such as polishing or chemical mechanical planarization can be used to remove the semiconductor substrate 20, exposing the second portion 212 of the fin structure 21.

[0082] In this embodiment, the bonded carrier wafer 33 can provide physical support for the flipped first transistor 11 after the wafer is flipped, effectively preventing the first transistor 11 from being broken by external force during the fabrication of the second transistor 12.

[0083] See Figure 15As shown, after removing the semiconductor substrate 20, the shallow trench isolation structure 22 can be thinned to form a first isolation structure 23, which can isolate the first transistor 11 and the second transistor 12 formed thereafter.

[0084] In step S504, at least one second transistor 12 is formed based on the second part 212.

[0085] In some embodiments, the second transistor includes a second source structure 1221, a second gate structure 124, and a second drain structure 1222 arranged sequentially along a second direction. The second transistor and the first transistor 11 are characterized by an alternating arrangement, that is, the gate region of the second transistor corresponds to the source-drain region of the first transistor 11, and the source-drain region of the second transistor corresponds to the gate region of the first transistor 11.

[0086] In some embodiments, the second source structure 1221 and the first single-diffusion isolation structure 24 are stacked along the first direction; the second gate structure 124 and the first drain structure 1122 are stacked along the first direction, and the second drain structure 1222 and the first gate structure 114 are stacked along the first direction.

[0087] It is understandable that the first transistor 11 can be formed based on the second part 212 of the fin structure 21. Taking the first transistor 11 as an N-type field-effect transistor as an example, the second transistor 12 can be a P-type field-effect transistor.

[0088] In some embodiments, step S504 may include: forming a second source structure 1221 and a second drain structure 1222 arranged alternately along a second direction based on the second portion 212; and forming a second gate structure 124 and a second monodiffusion isolation structure between the second source structure 1221 and the second drain structure 1222 based on the second portion, so that the second drain structure 1222, the second gate structure 124, the second source structure 1221 and the second monodiffusion isolation structure are arranged in sequence.

[0089] See Figure 16 As shown, based on Figure 15 When the semiconductor structure shown forms at least one second transistor 12, a dummy gate material such as polycrystalline silicon or amorphous silicon can be deposited in the gate region of the reverse transistor to form a second dummy gate structure 26. Here, the gate region of the reverse transistor corresponds to the source / drain region of the front transistor. After forming the second dummy gate structure 26, an insulating material can be deposited on the sidewalls of the second dummy gate structure 26 to form a second dummy gate sidewall covering the sidewalls of the second dummy gate structure 26.

[0090] In some embodiments, a second pseudo-gate structure 26 may be formed on the first drain structure 1122.

[0091] See Figure 17 As shown, after forming the second pseudo-gate structure 26, a second source / drain structure 122 can be formed in the source / drain region between two adjacent second pseudo-gate structures 26, based on the second portion of the fin structure 21. Here, the second source / drain structure 122 may include a second source structure 1221 and a second drain structure 1222. The second source structure 1221 and the second drain structure 1222 can be arranged alternately along the second direction within the reverse transistor.

[0092] In some embodiments, when forming the second source structure 1221 and the second drain structure 1222, the second drain structure 1222 may be formed on the first gate structure 114. The second source structure 1221 is formed on both sides of the second drain structure 1222, so that the second source structure 1221 and the second drain structure 1222 are arranged alternately along the second direction.

[0093] See Figure 18 As shown, after forming the second source / drain structure 122, the second dummy gate structure 26 can be removed, and dielectric material and metal material can be sequentially deposited at the location where the second dummy gate structure 26 is removed to form a second gate dielectric layer and a second gate metal layer, respectively. Here, the second gate dielectric layer and the second gate metal layer can constitute the second gate structure 124.

[0094] See Figure 19 As shown, after forming the second gate structure 124, a second source / drain metal 125 can be formed. Here, the second source / drain metal 125 may include a second source metal 1251 and a second drain metal 1252. That is, after forming the second gate structure 124, metal material can be deposited on the second source structure 1221 to form the second source metal 1251; and metal material can be deposited on the second drain structure 1222 to form the second drain metal 1252.

[0095] See Figure 20 As shown, after forming the second source / drain metal 125, the second gate structure 124 located on the first source structure 1121 is removed. Specifically, the second gate structure 124 located at the edge or between two second transistors 12 can be removed. An insulating material is then deposited at the location where the second gate structure 124 is removed to form a second monodiffused isolation structure 27. Here, the second monodiffused isolation structure 27 is used to electrically isolate two adjacent second transistors 12. Alternatively, the second monodiffused isolation structure 27 is used to electrically isolate transistor units from other electronic components.

[0096] Understandably, after obtaining the second monodiffused isolation structure 27, the second source structure 1221 and the second drain structure 1222 are located on both sides of a second gate structure 124. The second source structure 1221, the second gate structure 124, the second drain structure 1222, and the second monodiffused isolation structure 27 can be arranged sequentially along the second direction.

[0097] It should be noted that when there are multiple second transistors 12 in the stacked transistors, the arrangement directions of the second source structure 1221, second gate structure 124, second drain structure 1222, and second single-diffused isolation structure 27 in two adjacent second transistors 12 can be different. For example, the second source structure 1221, second gate structure 124, second drain structure 1222, and second single-diffused isolation structure 27 in the first second transistor 12 are arranged sequentially along the second direction, and the second source structure 1221, second gate structure 124, second drain structure 1222, and second single-diffused isolation structure 27 in the second second transistor 12 are arranged sequentially along the third direction. The third direction can be opposite to the second direction.

[0098] In some embodiments, see Figure 21 As shown, after forming the first gate structure 114 and the first source / drain metal 115, the method further includes: depositing a dielectric material on the first gate structure 114 and the first source / drain metal 115 to form a reverse dielectric layer 28; and forming a second metal interconnect layer 126 of the stacked transistor 10 on the reverse dielectric layer 28 using standard back-end processes for semiconductor fabrication (such as inter-interconnect dielectric deposition, metal line formation, lead-out pad formation, etc.).

[0099] It should be noted that the process of forming the structure in the second transistor 12 can also refer to the process of forming the relevant structure in the first transistor 11.

[0100] In step S505, see Figures 18 to 19 As shown, a first metal interconnect via 131 is formed to connect the second drain structure 1222 and the first gate structure 114, and a second metal interconnect via is formed to connect the second gate structure 124 and the first drain structure 1122.

[0101] Understandably, during the formation of the second transistor, a first metal interconnect via 131 connecting the second drain structure 1222 and the first gate structure 114 can also be formed, as well as a second metal interconnect via connecting the second gate structure 124 and the first drain structure 1122.

[0102] In some embodiments, step S505 may include: forming a first metal interconnect via 131 connecting the second drain structure 1222 and the first gate structure 114 before forming the second drain metal 1252, and forming a second metal interconnect via 132 connecting the second gate structure 124 and the first drain structure 1122 before forming the second gate structure 124.

[0103] Understandably, the first metal interconnect via 131 can be formed before the second drain metal 1252 is formed. The process of forming the first metal interconnect via 131 includes: etching the second interlayer dielectric layer 123 and the first isolation structure 23 surrounding the second drain structure 1222 until the first gate structure 114 is exposed, thereby forming the first via; etching the second interlayer dielectric layer 123 surrounding the second drain structure 1222 until the second drain structure 1222 is exposed, thereby forming the second drain metal via; the first via and the second drain metal via are connected; metal material is deposited in the first via to form the first metal interconnect via 131; metal material is deposited in the second drain metal via to form the second drain metal 1252.

[0104] Understandably, the second metal interconnect via 132 can be formed before the second gate structure 124 is formed. The process of forming the second metal interconnect via 132 includes: after removing the second dummy gate structure 26, etching the first isolation structure 23 located between the first transistor 11 and the second transistor 12, and the first interlayer dielectric layer 113 encapsulating the first drain structure 1122, until the first source metal 1151 is exposed to form the second via; depositing metal material in the second via to form the second metal interconnect via 132.

[0105] In some embodiments, step S505 may include: forming a first metal interconnect via 131 connecting the second drain structure 1222 and the first gate structure 114 before forming the second drain metal 1252, and forming a second metal interconnect via 132 connecting the second gate structure 124 and the first drain structure 1122 after forming the second gate structure 124.

[0106] It is understood that the first metal interconnect via 131 can be formed before the second drain metal 1252 is formed. The formation process of the first metal interconnect via 131 can be referred to the description in the above embodiments, and will not be repeated here.

[0107] Understandably, the second metal interconnect via 132 can be formed after the second gate structure 124 is formed. The process of forming the second metal interconnect via 132 includes: etching the second gate structure 124, the first isolation structure 23 located between the first transistor 11 and the second transistor, and the first interlayer dielectric layer 113 encapsulating the first drain structure 1122 until the first source metal 1151 is exposed to form the third via; and depositing metal material in the third via to form the second metal interconnect via 132.

[0108] In some embodiments, step S505 may include: after forming the second drain metal 1252, forming a first metal interconnect via 131 that connects the second drain structure 1222 and the first gate structure 114, and before forming the second gate structure 124, forming a second metal interconnect via 132 that connects the second gate structure 124 and the first drain structure 1122.

[0109] Understandably, the first metal interconnect via 131 can be formed after the second drain metal 1252 is formed. The process of forming the first metal interconnect via 131 includes: etching the second drain metal 1252, the second interlayer dielectric layer 123 encapsulating the second drain structure 1222, and the first isolation structure 23 until the first gate structure 114 is exposed, thereby forming the fourth via; the fourth via penetrates the second drain metal 1252, and metal material is deposited in the fourth via to form the first metal interconnect via 131.

[0110] It is understood that the second metal interconnect via 132 can be formed before the second gate structure 124 is formed. The formation process of the second metal interconnect via 132 can be referred to the description in the above embodiments, and will not be repeated here.

[0111] In this embodiment, by utilizing both the front and back sides of a wafer to fabricate two layers of transistors, the integration density of the transistors is increased, further improving their integration performance. Furthermore, the staggered arrangement of the two layers allows for electrical connections between different structures within the transistors to be achieved simply by forming metal interconnect vias. Compared to related technologies that employ complex interconnect lines, this embodiment not only more easily meets the needs of different logic circuits and effectively reduces fabrication difficulty, but also does not increase the size of transistor units, thus contributing to further improvements in circuit integration.

[0112] Secondly, embodiments of this application provide a stacked transistor. See also... Figure 21As shown, the stacked transistor 10 may include at least one first transistor 11 and at least one second transistor 12, wherein the first transistor 11 and the second transistor 12 are stacked along a first direction; wherein the first transistor 11 includes a first drain structure 1122, a first gate structure 114 and a first source structure 1121 arranged sequentially along a second direction; the second direction is perpendicular to the first direction; the second transistor 12 includes a second drain structure 1222, a second gate structure 124 and a second source structure 1221 arranged sequentially along the second direction. The second drain structure 1222 and the first gate structure 114 are stacked along the first direction, and a first metal interconnect via 131 is provided between the second drain structure 1222 and the first gate structure 114; the second gate structure 124 and the first drain structure 1122 are stacked along the first direction, and a second metal interconnect via 132 is provided between the second gate structure 124 and the first drain structure 1122; the first metal interconnect via 131 is used to connect the second drain structure 1222 and the first gate structure 114, and the second metal interconnect via 132 is used to connect the second gate structure 124 and the first drain structure 1122.

[0113] In some embodiments, the stacked transistor 10 further includes: a first monodiffusion isolation structure 24 stacked with the second source structure 1221 along a first direction, and a second monodiffusion isolation structure 27 stacked with the first source structure 1121 along a first direction; wherein the first monodiffusion isolation structure 24 is used to electrically isolate two adjacent first transistors 11; and the second monodiffusion isolation structure 27 is used to electrically isolate two adjacent second transistors 12.

[0114] In some embodiments, when at least one first transistor 11 is a plurality of first transistors 11, two adjacent first transistors 11 share a first source structure 1121, and / or when at least one second transistor 12 is a plurality of second transistors 12, two adjacent second transistors 12 share a second source structure 1221.

[0115] Understandable, see Figure 4 As can be seen from the map shown, Figure 4The system includes a first coupling capacitor Decap1 and a second coupling capacitor Decap2. The first coupling capacitor Decap1 includes a pair of stacked transistors (consisting of a first transistor 11 and a second transistor 12), and the second coupling capacitor Decap1 also includes a pair of stacked transistors (consisting of a first transistor 11 and a second transistor 12), resulting in a total of two first transistors 11 and two second transistors 12. Adjacent second transistors 12 can be isolated by a second single-diffusion isolation structure 27, and adjacent first transistors 11 can share the structure shown in the DD' direction cross-sectional view, which is the first source structure 1121. Similarly, in some embodiments, adjacent first transistors 11 in the first coupling capacitor Decap1 and the second coupling capacitor Decap2 can be isolated by a first single-diffusion isolation structure 24, and adjacent second transistors 12 can share a second source structure 1221.

[0116] Furthermore, assuming in Figure 4 Adding another pair of stacked transistors (consisting of a first transistor 11 and a second transistor 12) to the structure shown allows the first transistor 11 in the second coupling capacitor Decap2 to be isolated from the newly added first transistor 11 by the first single-diffusion isolation structure 24. The second transistor 12 in the second coupling capacitor Decap2 and the newly added second transistor can share a second source structure 1221. Based on this, the embodiments of this application can achieve an area occupied by stacked transistors of 3N+1 contact pitches (CPP) when the number of transistor pairs is N.

[0117] In this embodiment, the interconnects within the coupling capacitors do not require a metal interconnect layer or a large aspect ratio (via), and are compatible with existing process flows, reducing dependence on the manufacturing process. Furthermore, when multiple coupling capacitors are connected in parallel, each coupling capacitor unit does not require additional space; the layout area of ​​multiple coupling capacitors only increases by one contact pitch compared to related technologies, thereby improving transistor integration performance.

[0118] In one or more of the above embodiments for fabricating stacked transistors, the stacked transistors also possess self-alignment. On the one hand, this solves the long-standing problems of complex processes and alignment difficulties in existing mainstream stacked transistor technologies, thus promoting the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active and gate structures, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through stacked transistors. This greatly frees up metal wiring resources without changing the ultra-miniaturized 4T track cell design.

[0119] Finally, the flip-chip method for realizing top and bottom transistors is compatible with existing mainstream device architectures, enabling the stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs) on both sides without requiring special process development for specific device architectures. This offers high flexibility and strong scalability from the perspective of semiconductor process node iteration. Flip-chip transistors are conceptually very advanced, possess significant industrial value, and are highly practical with broad expansion prospects.

[0120] Thirdly, embodiments of this application provide a semiconductor device, including: a stacked transistor as described in the above embodiments. Specific limitations of the stacked transistor can be found at least in the above description. Figure 21 The stacked transistors shown will not be described in detail here.

[0121] Fourthly, embodiments of this application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the stacked transistors described above. Specific limitations of the stacked transistors can be found at least in the above description. Figure 21 The structure shown is not elaborated here.

[0122] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0123] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating stacked transistors, characterized in that, include: A fin structure is formed on a semiconductor substrate, wherein the fin structure includes a first portion and a second portion stacked along a first direction, the first portion being closer to the semiconductor substrate than the second portion; Based on the first part, at least one first transistor is formed, wherein the first transistor includes: a first drain structure, a first gate structure, and a first source structure arranged sequentially along a second direction; the second direction is perpendicular to the first direction; The semiconductor substrate is then poured and removed. Based on the second part, at least one second transistor is formed, wherein the second transistor includes: a second source structure, a second gate structure, and a second drain structure arranged sequentially along a second direction; the second gate structure and the first drain structure are stacked along a first direction, and the second drain structure and the first gate structure are stacked along a first direction. A first metal interconnect via is formed to connect the second drain structure and the first gate structure, and a second metal interconnect via is formed to connect the second gate structure and the first drain structure; The step of forming at least one second transistor based on the second portion includes: forming a second source structure and a second drain structure alternately arranged along a second direction based on the second portion; forming a second gate structure and a second single-diffusion isolation structure between the second source structure and the second drain structure based on the second portion, such that the second source structure, the second gate structure, the second drain structure, and the second single-diffusion isolation structure are arranged in sequence; wherein the second single-diffusion isolation structure is stacked with the first source structure along a first direction; the second source structure is stacked with the first single-diffusion isolation structure in the first transistor along a first direction; one second gate structure and an adjacent second source structure and second drain structure form one second transistor; the second single-diffusion isolation structure is used to electrically isolate two adjacent second transistors.

2. The preparation method according to claim 1, characterized in that, Based on the second portion, forming the second gate structure and the second single-diffusion isolation structure between the second source structure and the second drain structure includes: Based on the second part, a second gate structure is formed on the first source structure and the first drain structure; The second gate structure located above the first source structure is removed, and an insulating material is deposited at the location where the second gate structure is removed to form the second single-diffusion isolation structure.

3. The preparation method according to claim 1, characterized in that, The second part, forming a second source structure and a second drain structure arranged alternately along a second direction, includes: Based on the second part, a second drain structure is formed on top of the first gate structure; Based on the second part, the second source structure is formed on both sides of the second drain structure, so that the second source structure and the second drain structure are arranged alternately along the second direction.

4. The preparation method according to claim 1, characterized in that, The formation of at least one first transistor based on the first portion includes: Based on the first part, the first drain structure and the first source structure are formed in sequence and alternately arranged along the second direction; Based on the first part, a first gate structure and a first single-diffusion isolation structure are formed between the first drain structure and the first source structure, such that the first single-diffusion isolation structure, the first drain structure, the first gate structure and the first source structure are arranged in sequence; the first single-diffusion isolation structure is used to electrically isolate two adjacent first transistors.

5. The preparation method according to claim 1, characterized in that, The second transistor includes a second drain metal; The formation of a first metal interconnect via connecting the second drain structure and the first gate structure, and the formation of a second metal interconnect via connecting the second gate structure and the first drain structure, include any one of the following: Before forming the second drain metal, a first metal interconnect via is formed to connect the second drain structure and the first gate structure; and before forming the second gate structure, a second metal interconnect via is formed to connect the second gate structure and the first drain structure. Before forming the second drain metal, a first metal interconnect via is formed to connect the second drain structure and the first gate structure; and after forming the second gate structure, a second metal interconnect via is formed to connect the second gate structure and the first drain structure. After the second drain metal is formed, a first metal interconnect via is formed to connect the second drain structure and the first gate structure. Before the second gate structure, a second metal interconnect via is formed to connect the second gate structure and the first drain structure.

6. A stacked transistor, characterized in that, The transistor is fabricated using any one of the fabrication methods of claims 1 to 5, comprising: at least one first transistor and at least one second transistor, wherein the first transistor and the second transistor are stacked along a first direction; The first transistor includes: a first drain structure, a first gate structure, and a first source structure arranged sequentially along a second direction; the second direction is perpendicular to the first direction; the second transistor includes: a second source structure, a second gate structure, and a second drain structure arranged sequentially along the second direction. The second drain structure and the first gate structure are stacked along a first direction, and a first metal interconnect via is provided between the second drain structure and the first gate structure; the second gate structure and the first drain structure are stacked along a first direction, and a second metal interconnect via is provided between the second gate structure and the first drain structure. The first metal interconnect via is used to connect the second drain structure and the first gate structure, and the second metal interconnect via structure is used to connect the second gate structure and the first drain structure.

7. The stacked transistor according to claim 6, characterized in that, The stacked transistor further includes: a first single-diffusion isolation structure stacked with the second source structure along a first direction, and a second single-diffusion isolation structure stacked with the first source structure along a first direction; Wherein, the first single-diffusion isolation structure is used to electrically isolate two adjacent first transistors; the second single-diffusion isolation structure is used to electrically isolate two adjacent second transistors.

8. The stacked transistor according to claim 6, characterized in that, In the at least one first transistor being a plurality of first transistors, two adjacent first transistors sharing a first source structure, and / or, When the at least one second transistor is a plurality of second transistors, two adjacent second transistors share a second source structure.

9. A semiconductor device, characterized in that, include: The stacked transistor as described in any one of claims 6 to 8.

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