N-type semiconductor device, semiconductor device and manufacturing method thereof, chip, and electronic device

Abstract

The present disclosure relates to the technical field of semiconductor manufacturing, in particular to an N-type semiconductor device, a semiconductor device and a manufacturing method thereof, a chip and an electronic device, the manufacturing method of the N-type semiconductor device comprising: providing a substrate formed with a gate structure; performing multiple pre-amorphous implantations on the substrate on both sides of the gate structure; wherein, except for the last pre-amorphous implantation, a low-temperature annealing treatment is performed after each pre-amorphous implantation; and performing source-drain implantation on the substrate on both sides of the gate structure after the last pre-amorphous implantation to form a source electrode and a drain electrode. The above technical solution utilizes multiple pre-amorphous implantations on the substrate on both sides of the gate structure, and in the subsequent annealing process, the volume expansion of the source-drain region substrate when changing from an amorphous state to a crystalline state generates a stress effect on the channel, thereby improving the tensile stress of the channel, and further improving the electron mobility.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to an N-type semiconductor device, a semiconductor device and a manufacturing method thereof, a chip and an electronic device. BACKGROUND

[0002] In the past, the semiconductor industry has continuously reduced the size of MOS devices in proportion to improve the performance of the devices and reduce the cost of the devices. However, when the traditional silicon devices approach their physical limits, especially below 65 nm, serious short channel effects, large tunneling current of the device gate oxide layer, and large polysilicon gate resistance occur. Therefore, further reducing the feature size to improve device performance will be limited by cost and technology.

[0003] Stress memorization technique (SMT) is a process method mainly for improving the channel carrier mobility of a device to improve the performance of the device. SMT technology mainly uses silicon nitride with tensile stress to act on an N-type semiconductor device to transfer stress to the channel region of the semiconductor device, so that the channel region forms a stress structure that is beneficial to the increase of electron mobility, i.e., a tensile stress structure. This stress structure of the channel region has a memory effect, i.e., the stress remains after the silicon nitride is removed. However, this process is relatively complex, and existing SMT technology mainly considers the tensile stress improvement of the polysilicon gate on the channel, and rarely considers the stress improvement of the source / drain region on the channel. SUMMARY

[0004] To solve the problems in the related art, the present disclosure provides an N-type semiconductor device, a semiconductor device and a manufacturing method thereof, a chip and an electronic device.

[0005] In a first aspect, the present disclosure provides a manufacturing method of an N-type semiconductor device, comprising:

[0006] providing a substrate formed with a gate structure;

[0007] performing multiple pre-amorphous implantation (PAI) implantations on the substrate on both sides of the gate structure; wherein, in addition to the last pre-amorphous implantation, a low-temperature annealing process is performed after each pre-amorphous implantation;

[0008] performing source / drain implantation on the substrate on both sides of the gate structure after the last pre-amorphous implantation to form a source and a drain;

[0009] wherein the depth of the last pre-amorphous implantation is greater than the depth of the previous pre-amorphous implantation; and the depth of the source / drain implantation is not greater than the depth of the last pre-amorphous implantation.

[0010] In one embodiment of the present disclosure, the pre-amorphization implantation ions are germanium ions, silicon ions or indium ions.

[0011] In one embodiment of the present disclosure, the process parameters of the low-temperature annealing treatment include an annealing temperature of 500-650℃ and an annealing time of 10-30min.

[0012] In one embodiment of the present disclosure, the method further comprises:

[0013] performing a lightly doped drain implantation on the substrate on both sides of the gate structure;

[0014] The lightly doped drain implantation is performed before the first low-temperature annealing treatment after the first pre-amorphization implantation.

[0015] In one embodiment of the present disclosure, the doping ions of the lightly doped drain implantation include one or both of BF2 and phosphorus.

[0016] In one embodiment of the present disclosure, the depth of the lightly doped drain implantation is not greater than the depth of the first pre-amorphization implantation.

[0017] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an NMOS region and a PMOS region formed on the substrate; the NMOS region and the PMOS region are respectively formed with a gate structure, a source and a drain; wherein the source and the drain of the NMOS region are obtained by using the manufacturing method of any one of the above.

[0018] The manufacturing method further comprises:

[0019] forming a stress memory layer on the surface of the NMOS region and the PMOS region;

[0020] performing ion doping on the stress memory layer corresponding to the PMOS region, and then performing a spike annealing treatment on the substrate.

[0021] In one embodiment of the present disclosure, the doping ions of the ion doping include germanium ions, silicon ions, indium ions or arsenic ions.

[0022] In a third aspect, the present disclosure provides an N-type semiconductor device manufactured by using the manufacturing method of any one of the first aspect.

[0023] In a fourth aspect, the present disclosure provides a semiconductor device manufactured by using the manufacturing method of any one of the second aspect.

[0024] In a fifth aspect, the chip provided in the embodiments of the present disclosure includes the N-type semiconductor device provided in the third aspect or the semiconductor device provided in the fourth aspect.

[0025] In a sixth aspect, the electronic device provided in the embodiments of the present disclosure includes the N-type semiconductor device provided in the third aspect or the semiconductor device provided in the fourth aspect.

[0026] The technical effects provided by the embodiments of the present disclosure can include the following beneficial effects:

[0027] According to the technical scheme provided in the embodiments of the present disclosure, the manufacturing method of the N-type semiconductor device includes: providing a substrate formed with a gate structure; performing multiple pre-amorphization implantations on the substrate on both sides of the gate structure; wherein, after each pre-amorphization implantation, a low-temperature annealing process is performed once, except for the last pre-amorphization implantation; performing source-drain implantation on the substrate on both sides of the gate structure after the last pre-amorphization implantation to form a source electrode and a drain electrode; wherein, the depth of the last pre-amorphization implantation is greater than the depth of the previous pre-amorphization implantation; and the depth of the source-drain implantation is not greater than the depth of the last pre-amorphization implantation. The above technical scheme utilizes multiple pre-amorphization implantations on the substrate on both sides of the gate structure, and in the subsequent annealing process, when the substrate of the source-drain region changes from an amorphous state to a crystalline state, the volume expansion generates stress on the channel, thereby improving the tensile stress of the channel, and further improving the electron mobility.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0029] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of the non-limiting embodiments, taken in conjunction with the accompanying drawings. The following is a description of the drawings.

[0030] Figure 1 A flowchart of a manufacturing method of an N-type semiconductor device according to an embodiment of the present disclosure is shown.

[0031] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 A step schematic diagram of manufacturing an N-type semiconductor device according to an embodiment of the present disclosure is shown.

[0032] Figure 8 A structural schematic diagram of a semiconductor device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so as to be easily carried out by one of ordinary skill in the art. Also, portions unrelated to the description of the exemplary embodiments are omitted in the drawings so as to make the present disclosure clear.

[0034] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate that there are features, numbers, steps, actions, parts, or combinations thereof disclosed in the specification, and do not exclude the possibility that one or more other features, numbers, steps, actions, parts, or combinations thereof exist or are added.

[0035] It should also be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] As mentioned above, the existing SMT technology mainly considers the tensile stress improvement of the polysilicon gate on the channel, and rarely considers the stress improvement of the source and drain position on the channel.

[0037] In view of the above defects, the manufacturing method of the N-type semiconductor device provided by the present disclosure includes: providing a substrate formed with a gate structure; performing multiple pre-amorphous implantations on the substrate on both sides of the gate structure; wherein, in addition to the last pre-amorphous implantation, a low-temperature annealing process is performed after each pre-amorphous implantation; after the last pre-amorphous implantation, source and drain implantation is performed on the substrate on both sides of the gate structure to form a source and a drain. The above technical solution utilizes multiple pre-amorphous implantations on the substrate on both sides of the gate structure, and in the subsequent annealing process, the stress is retained when the substrate of the source and drain region is converted from amorphous to crystalline, thereby improving the tensile stress of the source and drain region on the channel and improving the electron mobility.

[0038] Figure 1 A flowchart of the manufacturing method of the N-type semiconductor device according to the embodiments of the present disclosure is shown.

[0039] As Figure 1As shown, the manufacturing method of the N-type semiconductor device comprises steps S1 to S5. Step S1 is to provide a substrate formed with a gate structure; steps S2 to S4 are to perform multiple PAI injections (i.e. pre-amorphization injections), and a low-temperature annealing process is performed after each PAI injection except the last one; in the present disclosure, PAI injections are performed on the substrate on both sides of the gate structure; after step S4 of the last PAI injection, step S5 of S / D injection (i.e. source-drain injection) is performed; in the present disclosure, source-drain injection is performed on the substrate on both sides of the gate structure to form a source and a drain. The present disclosure only takes three PAI injections as an example for illustrative purposes, and it can be understood that, according to needs, a third PAI injection or more PAI injections can be performed before the last PAI injection, and the present disclosure does not limit this. In addition, the same or different process parameters can be used for each PAI injection, and those skilled in the art can adjust them flexibly.

[0040] As shown in Figure 1 and Figure 2 Step S1 is first performed to provide a substrate formed with a gate structure. In the present disclosure, an insulating structure 101, such as a shallow trench isolation (STI) structure, is formed in the substrate 100 to provide an electrical isolation function. The material of the substrate 100 can include a semiconductor material such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, or gallium arsenide. The material of the insulating structure 101 can be a dielectric material such as silicon dioxide. The gate structure is formed on the substrate 100, and the gate structure includes a gate layer 102 which comprises, from bottom to top, a gate dielectric layer 102a, a gate material layer 102b, and a hard mask 102c. The gate dielectric layer 102a can include silicon dioxide, silicon nitride, or a high-dielectric constant (high-k) material. The gate material layer 102b can include a conductive material such as polycrystalline silicon, a metal material, or a metal silicide. The gate layer 102 can be manufactured by forming a gate stack on the substrate 100, which comprises, from bottom to top, a gate dielectric layer, a gate material layer, and a hard mask, and then patterning the gate stack to obtain the gate layer 102.

[0041] The gate structure may further include a gate spacer 103, which is disposed around the sidewalls of the gate layer 102 to protect the gate layer 102 during the subsequent PAI implantation process. The material of the gate spacer 103 may include an oxide and / or a nitride, such as silicon dioxide, silicon nitride, silicon oxyammonium, or silicon carbide nitride. The gate spacer 103 may have a single-layer structure, such as a single layer of silicon oxide or silicon nitride, or a stacked structure, such as a silicon oxide layer formed on the sidewalls of the gate layer 102, and then a silicon nitride layer formed on the sidewalls of the silicon oxide layer.

[0042] Proceed to step S2, as Figure 1 and Figure 3 As shown, the insulating structure 101 in the substrate 100 is omitted in the figure. The first PAI implantation 310 is performed on the substrate on both sides of the gate structure, and the implantation depth is recorded as d1 to form the first implantation region 210. The dotted line portion in the figure indicates that the implanted ions may diffuse laterally in the substrate. The implanted ions can be germanium ions, silicon ions or indium ions. The ion implantation dose range can be 3E14-5E14, the energy can be 10-25k, the tilt angle is 0°, the rotation angle is 0° and the number of rotations is 0. Then, a first low-temperature annealing treatment is performed. During the annealing process, the volume expansion of the substrate in the first implantation region 210 when it transforms from an amorphous state to a crystalline state generates stress on the channel, thereby increasing the tensile stress of the channel and thereby improving the electron mobility. The process parameters of the first low-temperature annealing treatment include an annealing temperature of 500-650°C and an annealing time of 10-30 minutes.

[0043] like Figure 4 As shown, after the first PAI injection 310 and before the first low-temperature annealing treatment, LDD injection 311 can be performed on the substrate on both sides of the gate structure to form an LDD region 211. The first PAI injection 310 before the LDD injection 311 can avoid the punch-through effect caused by subsequent ion injection. The doping ions of the LDD injection 311 include one or both of BF2 and phosphorus. The injection depth of the LDD injection 311 is recorded as d2, and d2 is not greater than the depth d1 of the first PAI injection 310. That is, the LDD injection 311 is performed inside the first injection region 210 to avoid the range end defect problem caused by subsequent annealing.

[0044] Next, a sidewall 104 can be formed around the sidewall of the gate sidewall 103 to precisely position the subsequent source / drain implantation. The material of the sidewall 104 can include oxide and / or nitride, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbon nitride. The sidewall 104 can be formed after step S2, or after step S3. In some cases, if the thickness of the gate sidewall 103 is sufficient to prevent leakage current, the sidewall 104 can be omitted, and the present disclosure does not limit this. In the present disclosure, the subsequent steps S3 to S5 are illustratively described by taking the formation of the sidewall 104 as an example.

[0045] In step S3, the present disclosure takes the LDD implantation as an example, and as shown in Figure 1 and Figure 5 , a second PAI implantation 320 is performed on the substrate on both sides of the gate structure, and the implantation depth is denoted as d3, to form a second implantation region 220. In the present disclosure, the process parameters of the second PAI implantation 320 are the same as those of the first PAI implantation 310, that is, the implanted ions, ion implantation dose, energy, tilt angle, rotation angle, and rotation number are the same, and the implantation depth d3 is also the same as d1. Then, a second low-temperature annealing process is performed. In the annealing process, when the substrate of the second implantation region 220 changes from amorphous state to crystalline state, the volume expansion of the substrate generates stress on the channel, thereby increasing the tensile stress of the channel and further improving the electron mobility. The process parameters of the second low-temperature annealing process include an annealing temperature of 500-650°C and an annealing time of 10-30 min.

[0046] In step S4, as shown in Figure 1 , Figure 6 , a last PAI implantation 330 is performed on the substrate on both sides of the gate structure, and the implantation depth is denoted as d4, to form a third implantation region 230. The implantation depth d4 of the last PAI implantation 330 is greater than the implantation depth d1 of the first PAI implantation 310 and the implantation depth d3 of the second PAI implantation 320, and the purpose is to form a heavily doped source / drain region to reduce the contact resistance of this region and to control the threshold voltage of the device.

[0047] In step S5, as shown in Figure 1 , Figure 6 and Figure 7 , a source / drain implantation 300 is performed on the substrate on both sides of the gate structure to form a source and a drain 200. Specifically, N-type impurities, such as arsenic, phosphorus, etc., can be implanted in the third implantation region 230 to form the source and the drain. The last PAI implantation 330 can be performed before the source / drain implantation 300 to avoid the punch-through effect caused by subsequent ion implantation. The implantation depth of the source / drain implantation is not greater than the depth d4 of the last PAI implantation 330, that is, the source / drain implantation 300 is performed inside the third implantation region 230, which is to avoid the range-end defect problem caused by subsequent annealing.

[0048] Figure 8 A schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure is shown.

[0049] like Figure 8 As shown, the semiconductor device includes a substrate 100, and an NMOS region and a PMOS region formed on the substrate 100. A P-well 112a is formed in the NMOS region, and an N-well 112b is formed in the PMOS region. An insulating structure 101 is also formed on the substrate 100, defining active regions. Gate layers 102 are formed in the NMOS and PMOS regions, respectively. Gate spacers 103 are formed on the sides of the gate layers 102. After the gate spacers 103 are formed, LDD implantation is performed to form LDD regions. The NMOS LDD region is an N-type LDD region 211a, and the PMOS LDD region is a P-type LDD region 211b. After the spacers 104 are formed, source and drain implantation is performed to form source and drain electrodes. Figure 8 In the embodiment, the source and drain are symmetrically arranged. The source and drain of the NMOS region are respectively composed of the N+ region 200a located on both sides of the gate structure. The source and drain of the PMOS region are respectively composed of the P+ region 200b located on both sides of the gate structure.

[0050] In the present disclosure, embodiments provide Figure 8 The method for manufacturing a semiconductor device shown in FIG, wherein the source and drain of the NMOS region are formed by Figure 1 The manufacturing method of the LDD region, source and drain of the PMOS region is obtained by the manufacturing method described above, which is referred to the prior art and will not be described in detail here. It should be noted that before the PAI implantation, a mask layer is formed on the substrate of the POMS region to avoid damage to the PMOS region.

[0051] Furthermore, the manufacturing method further comprises:

[0052] forming a stress memory layer on the surfaces of the NMOS region and the PMOS region;

[0053] Ion doping is performed on the stress memory layer corresponding to the PMOS region, and then a spike annealing process is performed on the substrate.

[0054] In the disclosed method, the doping ions include germanium ions, silicon ions, indium ions, or arsenic ions. In one embodiment, the doping particles are germanium ions, the ion implantation dose range is 4E14-6E14, the energy is 20-35k, the tilt angle is 0°, the rotation angle is 0°, and the number of rotations is 0 times.

[0055] By ion doping the stress memory layer of the PMOS region after the stress memory layer is formed, the stress memory layer will transfer tensile stress to the channel region of the NMOS after peak annealing to improve the electron mobility of the NMOS; meanwhile, the tensile stress of the stress memory layer of the PMOS region is eliminated, so that the tensile stress in the channel region of the PMOS is reduced or even has no tensile stress, so that the hole mobility of the PMOS is not affected.

[0056] Further, a photoresist layer can be formed on the substrate 100, and a metal silicide forming region is exposed by a mask plate, exposure, etc. After the metal silicide is formed, the photoresist layer is removed, and then an etching stop layer is formed on the surface of the NMOS region and the PMOS region.

[0057] Based on the same or similar inventive concept, the embodiments of the present disclosure further provide an N-type semiconductor device, which adopts the manufacturing method of the N-type semiconductor device. Figure 1 The N-type semiconductor device is manufactured by the manufacturing method of the N-type semiconductor device.

[0058] As another aspect, the embodiments of the present disclosure further provide a chip, which includes the N-type semiconductor device or the semiconductor device described in the above embodiments.

[0059] As another aspect, the embodiments of the present disclosure further provide an electronic device, which includes the N-type semiconductor device or the semiconductor device described in the above embodiments.

[0060] The above description is merely preferred embodiments of the present disclosure and a description of the principles of the applied technology. It should be understood by those skilled in the art that the inventive scope of the present disclosure is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combinations of the above technical features or equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features disclosed in the present disclosure (but not limited to) having similar functions to form technical solutions.

Claims

1. A method for manufacturing an N-type semiconductor device, characterized in that: include: providing a substrate having a gate structure formed thereon; Performing multiple pre-amorphization implantations on the substrate on both sides of the gate structure; wherein, except for the last pre-amorphization implantation, each pre-amorphization implantation is followed by a low-temperature annealing treatment; the process parameters of the low-temperature annealing treatment include an annealing temperature of 500-650° C. and an annealing time of 10-30 minutes; After the last pre-amorphization implantation, source and drain implantation is performed on the substrate on both sides of the gate structure to form a source and a drain; The depth of the last pre-amorphization implantation is greater than the depth of the previous pre-amorphization implantation; and the depth of the source / drain implantation is not greater than the depth of the last pre-amorphization implantation.

2. The method for manufacturing an N-type semiconductor device according to claim 1, wherein: The ions implanted for pre-amorphization are germanium ions, silicon ions or indium ions.

3. The method for manufacturing an N-type semiconductor device according to claim 1, wherein: Also includes: Performing lightly doped drain implantation on the substrate on both sides of the gate structure; The lightly doped drain implantation is performed after the first pre-amorphization implantation and before the first low-temperature annealing treatment.

4. The method for manufacturing an N-type semiconductor device according to claim 3, wherein: The doping ions of the lightly doped drain implantation include one or both of BF2 and phosphorus.

5. The method for manufacturing an N-type semiconductor device according to claim 3, wherein: The depth of the lightly doped drain implantation is no greater than the depth of the first pre-amorphization implantation.

6. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device includes a substrate, and an NMOS region and a PMOS region formed on the substrate; the NMOS region and the PMOS region are respectively formed with a gate structure, a source, and a drain; wherein the source and drain of the NMOS region are obtained by the manufacturing method according to any one of claims 1 to 5; The manufacturing method further comprises: forming a stress memory layer on the surfaces of the NMOS region and the PMOS region; Ion doping is performed on the stress memory layer corresponding to the PMOS region, and then a spike annealing process is performed on the substrate.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The doping ions of the ion doping include germanium ions, silicon ions, indium ions or arsenic ions. 8 . An N-type semiconductor device manufactured by the method for manufacturing an N-type semiconductor device according to claim 1 .

9. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 6 to 7.

10. A chip, characterized in that: The method comprises the N-type semiconductor device according to claim 8 or the semiconductor device according to claim 9.

11. An electronic device, characterized in that: The method comprises the N-type semiconductor device according to claim 8 or the semiconductor device according to claim 9.

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