GaN-based complementary logic device based on p-BN and preparation method thereof

Abstract

The invention discloses a gallium nitride-based complementary logic device based on p-BN and a preparation method thereof. The preparation method comprises the following steps: dividing an undoped GaN layer into a first region and a second region by a strip-shaped groove in the undoped GaN layer; the first polarization layer, the first barrier layer and the first p-BN layer are sequentially arranged on the upper surface of the first region of the undoped GaN layer in a stacked mode, a first source electrode, a dielectric layer and a first drain electrode are arranged on the upper surface of the first p-BN layer at intervals, and a first grid electrode is arranged on the upper surface of the dielectric layer; the second polarization layer, the second barrier layer and the second p-BN layer are sequentially arranged on the upper surface of the second area of the non-doped GaN layer in a stacked mode, the second p-BN layer is located in the middle area of the upper surface of the second barrier layer, a second source electrode and a second drain electrode are arranged on the two side areas of the upper surface of the second barrier layer respectively, and a second grid electrode is arranged on the upper surface of the second p-BN layer; the first drain electrode is electrically connected with the second drain electrode, and the first grid electrode is electrically connected with the second grid electrode. The performance of the complementary logic device can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a p-BN-based gallium nitride-based complementary logic device and a preparation method thereof. Background Art

[0002] Compared with traditional silicon-based semiconductors, gallium nitride shows significant advantages in the high-temperature field. GaN has higher breakdown field strength, higher electron mobility and greater electron density, which enables it to work stably in extremely harsh environments. Under high temperature conditions, GaN shows excellent stability and can withstand higher junction temperatures while maintaining excellent switching efficiency and low power consumption. In high-temperature applications, GaN materials have strong thermal stability and low intrinsic carrier concentration due to their wide bandgap characteristics (3.42eV), which can significantly reduce the concentration of leakage current at high temperatures, thereby improving the heat resistance and reliability of the device.

[0003] Compared with traditional silicon devices, GaN devices have less performance degradation in high temperature environments and can achieve high-frequency switching operations with higher efficiency and lower energy loss. This high-temperature advantage makes the application of GaN in aerospace, electric vehicle power electronics and other harsh environments particularly important. However, the current development of GaN-based complementary logic devices is slow and the device performance is poor. The main reason is that the hole mobility of p-type materials is much lower than the electron mobility in n-type materials. The electron mobility in the common AlGaN / GaN heterojunction can easily reach 2000cm 2 / V·s, while the hole mobility of most p-type devices is only 10cm 2 / V·s. The current of GaN-based p-type devices is much smaller than that of n-type GaN devices. They cannot match with n-type devices in complementary logic integrated circuits. They have weak driving capabilities and poor switching characteristics, which severely limits the efficiency and performance of the overall complementary logic circuit.

[0004] Conventional complementary logic devices using GaN / AlGaN / GaN heterojunctions have very low hole mobility and surface density levels. The hole mobility of the best device in the world can only reach 30cm 2 / V·s, and the device has poor ohmic contact characteristics and poor switching characteristics. The main reason is that p-GaN material is used as the p-type layer and conductive channel, the hole mobility is extremely low, and the device is difficult to make ohmic contact, which makes the device have poor switching characteristics and power characteristics when working. Therefore, it is urgent to provide a gallium nitride-based complementary logic device to improve the defects in the prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a p-BN-based gallium nitride-based complementary logic device and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a p-BN-based gallium nitride-based complementary logic device, comprising:

[0007] An undoped GaN layer, wherein a strip-shaped groove is provided in the undoped GaN layer, and the strip-shaped groove divides the undoped GaN layer into a first region and a second region;

[0008] A first polarization layer, a first barrier layer and a first p-BN layer are sequentially stacked on the upper surface of the first region of the undoped GaN layer, a first source electrode, a dielectric layer and a first drain electrode are arranged on the upper surface of the first p-BN layer, and a first gate electrode is arranged on the upper surface of the dielectric layer;

[0009] A second polarization layer, a second barrier layer, and a second p-BN layer are sequentially stacked on the upper surface of the second region of the undoped GaN layer, the second p-BN layer is located in the middle region of the upper surface of the second barrier layer, a second source electrode and a second drain electrode are respectively disposed in the two side regions of the upper surface of the second barrier layer, and a second gate electrode is disposed on the upper surface of the second p-BN layer;

[0010] The first drain is electrically connected to the second drain, and the first gate is electrically connected to the second gate.

[0011] In a second aspect, the present invention further provides a method for preparing a p-BN-based gallium nitride-based complementary logic device, which is used to prepare the p-BN-based gallium nitride-based complementary logic device provided above, comprising:

[0012] Providing an undoped GaN layer;

[0013] Growing a polarization layer on the upper surface of the undoped GaN layer;

[0014] growing a barrier layer on the upper surface of the polarization layer;

[0015] Growing a p-BN layer on the upper surface of the barrier layer;

[0016] The p-BN layer, the barrier layer, the polarization layer and part of the undoped GaN layer are etched by an etching process, and strip-shaped openings are formed in the p-BN layer, the barrier layer and the polarization layer, and strip-shaped grooves are formed in the undoped GaN layer; the strip-shaped openings separate the p-BN layer into a first p-BN layer and a second p-BN layer, separate the barrier layer into a first barrier layer and a second barrier layer, separate the polarization layer into a first polarization layer and a second polarization layer, and the strip-shaped grooves separate the undoped GaN layer into a first region and a second region;

[0017] The second p-BN layer is etched by an etching process to etch away both sides of the second p-BN layer, exposing the upper surfaces of the two side regions of the second barrier layer, depositing metal on the upper surfaces of the two side regions of the exposed second barrier layer to form a second source electrode and a second drain electrode respectively, and depositing metal on the upper surface of the second p-BN layer that has not been etched to form a second gate electrode;

[0018] Depositing metal on the upper surface of the two side regions of the first p-BN layer to form a first source and a first drain respectively, depositing a dielectric layer on the upper surface of the middle region of the first p-BN layer, and depositing metal on the upper surface of the dielectric layer to form a first gate;

[0019] The first drain electrode is electrically connected to the second drain electrode, and the first gate electrode is electrically connected to the first gate electrode by means of evaporation interconnection line.

[0020] Beneficial effects of the present invention:

[0021] The present invention provides a p-BN-based gallium nitride-based complementary logic device and a preparation method thereof, wherein the first p-BN layer is used as a hole supply layer for a p-type device, and the second p-BN layer is used as a cap layer for an n-type device; considering that the p-BN material has a natural p-type advantage, it shows significant application potential in GaN-based devices. On the one hand, p-BN has a higher hole concentration and mobility, and can be more effectively used as a hole supply layer for a p-type device compared to traditional p-GaN materials, significantly improving the carrier transport capacity and output current of the device; on the other hand, p-BN can also be used as a p-cap layer for an n-type device, and an enhanced device is realized by optimizing the electric field distribution under the gate, simplifying the process flow while improving the device performance. In addition, p-BN and GaN have good matching in lattice constant and thermal expansion coefficient, which can reduce the interface defect density and further improve the stability and reliability of the device. By introducing p-BN into a GaN-based complementary logic device, the matching of the performance of the p-type device and the n-type device is greatly improved, thereby effectively improving the driving capability, power consumption efficiency and operating speed of the circuit.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a p-BN-based gallium nitride-based complementary logic device provided by an embodiment of the present invention;

[0024] Figure 2 It is a flow chart of a method for preparing a p-BN-based gallium nitride-based complementary logic device provided by an embodiment of the present invention;

[0025] Figures 3a to 3nIt is a flow chart of a method for preparing a p-BN-based gallium nitride-based complementary logic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0027] Existing complementary logic devices, on the one hand, have poor performance of p-GaN materials, with hole density and mobility much lower than electron density and electron mobility of n-type materials, resulting in mismatch between p-type devices and n-type devices, which severely limits the performance of complementary logic devices. On the other hand, GaN-based p-type devices are difficult to dope, have poor ohmic contact characteristics, and the top p-GaN layer has low hole density and poor material quality.

[0028] In view of this, the present invention provides a p-BN-based gallium nitride-based complementary logic device, which uses p-BN material as a hole supply layer for p-type devices and a p-cap layer for n-type devices to simultaneously realize n-type enhancement devices, which can effectively improve the hole density and mobility of p-type devices and improve the performance of GaN-based complementary logic devices.

[0029] See also Figure 1 , Figure 1 1 is a schematic diagram of a p-BN-based GaN-based complementary logic device provided by an embodiment of the present invention. The p-BN-based GaN-based complementary logic device provided by the present invention includes:

[0030] An undoped GaN layer 10, wherein a strip-shaped groove 20 is provided in the undoped GaN layer 10, and the strip-shaped groove 20 divides the undoped GaN layer 10 into a first region 11 and a second region 12;

[0031] A first polarization layer 31, a first barrier layer 41 and a first p-BN layer 51 are sequentially stacked on the upper surface of the first region 11 of the undoped GaN layer 10, a first source 61, a dielectric layer 62 and a first drain 63 are arranged on the upper surface of the first p-BN layer 51, and a first gate 64 is arranged on the upper surface of the dielectric layer 62;

[0032] A second polarization layer 32, a second barrier layer 42, and a second p-BN layer 52 are sequentially stacked on the upper surface of the second region 12 of the undoped GaN layer 10, the second p-BN layer 52 is located in the middle region of the upper surface of the second barrier layer 42, a second source 65 and a second drain 66 are respectively disposed on the two side regions of the upper surface of the second barrier layer 42, and a second gate 67 is disposed on the upper surface of the second p-BN layer 52;

[0033] The first drain electrode 63 is electrically connected to the second drain electrode 66 , and the first gate electrode 64 is electrically connected to the second gate electrode 67 .

[0034] For more details, please see Figure 1 The p-BN-based gallium nitride-based complementary logic device provided in this embodiment includes an undoped GaN layer 10, and the undoped GaN layer 10 is divided into a first region 11 and a second region 12 by a strip groove 20 arranged thereon, and a first polarization layer 31, a first barrier layer 41 and a first p-BN layer 51 are stacked on the first region 11, and a first source 61, a dielectric layer 62 and a first drain 63 are arranged on the upper surface of the first p-BN layer 51, and the dielectric layer 62 is located between the first source 61 and the first drain 63, and a first gate 64 is arranged on the upper surface of the dielectric layer 62, and a second polarization layer 31, a first barrier layer 41 and a first p-BN layer 51 are stacked on the first region 11. 32. The second barrier layer 42 and the second p-BN layer 52, the second p-BN layer 52 is located in the middle area of ​​the upper surface of the second barrier layer 42, and it can also be understood that along the direction D1 perpendicular to the substrate, the orthographic projection of the second p-BN layer 52 is located within the range of the orthographic projection of the second barrier layer 42, the second source 65 and the second drain 66 are located on both side areas of the upper surface of the second barrier layer 42, and the second p-BN layer 52 is located between the second source 65 and the second drain 66, and arranged at intervals; wherein the first drain 63 and the second drain 66 are electrically connected through interconnection lines, and the first gate 64 and the second gate 67 are electrically connected through interconnection lines. In this embodiment, p-BN material is used as the hole supply layer of the p-type device and the p-cap layer of the n-type device, so that n-type enhancement-type devices can be realized at the same time. Due to the natural p-type advantage of BN material, the hole concentration and mobility in the device can be effectively increased, which can significantly improve the output current of the p-type logic device and achieve matching with the n-type GaN device, thereby realizing the improvement of the performance of GaN-based complementary logic devices.

[0035] It is understandable that p-BN materials show significant application potential in GaN-based devices due to their natural p-type advantages. On the one hand, p-BN has a higher hole concentration and mobility. Compared with traditional p-GaN materials, it can be more effectively used as a hole supply layer for p-type devices, significantly improving the carrier transport capacity and output current of the device; on the other hand, p-BN can also be used as a p-cap layer for n-type devices, and an enhanced device can be realized by optimizing the electric field distribution under the gate, simplifying the process flow and improving device performance. In addition, p-BN and GaN have good matching in lattice constant and thermal expansion coefficient, which can reduce the interface defect density and further improve the stability and reliability of the device. By introducing p-BN in GaN-based complementary logic devices, the matching of the performance of p-type devices and n-type devices can be greatly improved, thereby effectively improving the driving capability, power efficiency and operating speed of the circuit.

[0036] The present invention uses p-BN material as the hole supply layer and p-cap layer to greatly improve the concentration and mobility of holes in the device. Compared with the activation energy of 170mV of Mg ions and the extremely low hole mobility in p-type GaN material, the performance of p-BN / AlGaN / GaN structure devices is significantly improved.

[0037] In an optional embodiment of the present invention, the present invention further comprises: a substrate 70 and a buffer layer 80 which are stacked, wherein the buffer layer 80 is located on a side of the undoped GaN layer 10 away from the strip-shaped groove 20, and along a direction D1 perpendicular to the substrate, the orthographic projections of the substrate 70 and the buffer layer 80 overlap with the orthographic projection of the undoped GaN layer 10;

[0038] The substrate 70 , the buffer layer 80 , the undoped GaN layer 10 , the first polarization layer 31 , the first barrier layer 41 , the first p-BN layer 51 , the dielectric layer 62 , the first source 61 , the first drain 63 and the first gate 64 constitute a p-type device.

[0039] In an optional embodiment of the present invention, the channel region of the p-type device is located on a side of the first barrier layer 41 close to the first p-BN layer 51 .

[0040] In an optional embodiment of the present invention, the present invention further comprises: a substrate 70 and a buffer layer 80 which are stacked, wherein the buffer layer 80 is located on a side of the undoped GaN layer 10 away from the strip-shaped groove 20, and along a direction D1 perpendicular to the substrate, the orthographic projections of the substrate 70 and the buffer layer 80 overlap with the orthographic projection of the undoped GaN layer 10;

[0041] The substrate 70 , the buffer layer 80 , the undoped GaN layer 10 , the second polarization layer 32 , the second barrier layer 42 , the second p-BN layer 52 , the second source 65 , the second drain 66 and the second gate 67 constitute an n-type device.

[0042] In an optional embodiment of the present invention, the channel region of the n-type device is located on a side of the undoped GaN layer 10 close to the second polarization layer 32 .

[0043] Based on the same inventive concept, see Figure 2 , Figure 2 1 is a flow chart of a method for preparing a p-BN-based gallium nitride-based complementary logic device provided in an embodiment of the present invention. The present invention also provides a method for preparing a p-BN-based gallium nitride-based complementary logic device, which is used to prepare the p-BN-based gallium nitride-based complementary logic device provided in the above embodiment of the present invention. The embodiments of the device are referred to above and will not be described in detail here. The preparation method comprises:

[0044] S101 , providing an undoped GaN layer 10 .

[0045] S102 , growing a polarization layer 30 on the upper surface of the undoped GaN layer 10 . Optionally, the polarization layer 30 has a thickness of 1 to 3 nm.

[0046] S103 , growing a barrier layer 40 on the upper surface of the polarization layer 30 , wherein the barrier layer 40 may be an AlGaN barrier layer, wherein the Al component is 10-30%, and the thickness of the barrier layer 40 is 15-35 nm.

[0047] S104 , growing a p-BN layer 50 on the upper surface of the barrier layer 40 . Optionally, the thickness of the p-BN layer 50 is 30-60 nm.

[0048] S105. The p-BN layer 50, the barrier layer 40, the polarization layer 30 and part of the undoped GaN layer 10 are etched by an etching process to form strip-shaped openings in the p-BN layer 50, the barrier layer 40 and the polarization layer 30, and strip-shaped grooves 20 are formed in the undoped GaN layer 10; the strip-shaped openings separate the p-BN layer 50 into a first p-BN layer 51 and a second p-BN layer 52, separate the barrier layer 40 into a first barrier layer 41 and a second barrier layer 42, separate the polarization layer 30 into a first polarization layer 31 and a second polarization layer 32, and the strip-shaped grooves 20 separate the undoped GaN layer 10 into a first region 11 and a second region 12.

[0049] S106. The second p-BN layer 52 is etched by an etching process to etch away the two sides of the second p-BN layer 52 to expose the upper surfaces of the two side regions of the second barrier layer 42, and metal is deposited on the upper surfaces of the two side regions of the exposed second barrier layer 42 to form a second source 65 and a second drain 66, respectively. Metal is deposited on the upper surface of the second p-BN layer 52 that has not been etched to form a second gate 67.

[0050] S107 , depositing metal on the upper surface of the two side regions of the first p-BN layer 51 to form a first source 61 and a first drain 63 respectively, depositing a dielectric layer 62 on the upper surface of the middle region of the first p-BN layer 51 , and depositing metal on the upper surface of the dielectric layer 62 to form a first gate 64 .

[0051] S108 , electrically connecting the first drain electrode 63 to the second drain electrode 66 , and electrically connecting the first gate electrode 64 to the first gate electrode 64 by means of evaporation interconnection lines.

[0052] In an optional embodiment of the present invention, it also includes:

[0053] Providing a substrate 70;

[0054] Depositing a buffer layer 80 on the upper surface of the substrate 70; Optionally, the thickness of the buffer layer 80 is 2-3 μm;

[0055] An undoped GaN layer 10 is deposited on the upper surface of the buffer layer 80 . Optionally, the thickness of the undoped GaN layer 10 is 300-400 nm.

[0056] In an optional embodiment of the present invention, metal is deposited on the upper surface of the exposed two side regions of the second barrier layer 42 to form a second source 65 and a second drain 66, respectively, and metal is deposited on the upper surface of the unetched second p-BN layer 52 to form a second gate 67, including:

[0057] Using electron beam evaporation process, Ti / Al / Ni / Au metal is deposited on the upper surface of the exposed two side regions of the second barrier layer 42, and rapidly annealed at 850-950°C in N2 atmosphere to form ohmic contacts of the second source 65 and the second drain 66;

[0058] Ni / Au metal is deposited on the upper surface of the second p-BN layer 52 by electron beam evaporation process, and thermal annealing is performed at 550-650° C. in an O 2 atmosphere to form an ohmic contact of the second gate 67 .

[0059] In an optional embodiment of the present invention, a dielectric layer 62 is deposited on the upper surface of the middle region of the first p-BN layer 51, a metal is deposited on the upper surface of the regions on both sides of the first p-BN layer 51 to form a first source 61 and a first drain 63 respectively, and a metal is deposited on the upper surface of the dielectric layer 62 to form a first gate 64, including:

[0060] Using electron beam evaporation process, Ti / Al / Ni / Au metal is deposited on the upper surface of the two side regions of the first p-BN layer 51, and rapidly annealed at 850-950°C in N2 atmosphere to form ohmic contacts of the first source 61 and the first drain 63;

[0061] A dielectric layer 62 is deposited on the upper surface of the middle region of the first p-BN layer 51 , and Ti / Pt / Au metal is deposited on the upper surface of the dielectric layer 62 using electron beam evaporation technology. In an O2 atmosphere, thermal annealing is performed at 550-650°C to form an ohmic contact of the second gate 67 .

[0062] In an optional embodiment of the present invention, growing a p-BN layer on the upper surface of the barrier layer comprises:

[0063] At 950-1050° C., a nitrogen source with a flow rate of 1950-2050 sccm, a boron source with a flow rate of 35-45 sccm, and a magnesium source with a flow rate of 15-25 sccm are introduced to grow p-BN with a thickness of 45-55 nm.

[0064] In an optional embodiment of the present invention, the preparation of a p-BN-based GaN-based complementary logic device is achieved by the following process, specifically:

[0065] S1. Provide a substrate 70, such as Figure 3a shown.

[0066] Specifically, the substrate 70 is ultrasonically cleaned with acetone, and then the acetone is washed off with anhydrous ethanol and blown dry, and then placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and the reaction chamber is evacuated to reduce the vacuum degree to 3×10 -2 Torr, the temperature in the reaction chamber was maintained at 1000°C.

[0067] S2, preparing a buffer layer 80, such as Figure 3b shown.

[0068] Specifically, the temperature of the reaction chamber is maintained at 950°C, and under the condition of maintaining the pressure at 20 Torr, trimethylgallium Ga(CH3)3 is introduced at a flow rate of 25 sccm, and then the temperature is raised to 1000°C, NH3 is introduced at a flow rate of 1500 sccm, and a GaN buffer layer 80 with a thickness of 2 μm is grown on the substrate 70 using the MOCVD process.

[0069] S3, preparing an undoped GaN layer 10, such as Figure 3c shown.

[0070] Specifically, the reaction chamber temperature is maintained at 1000° C., the pressure is maintained at 20 Torr, a nitrogen source with a flow rate of 2000 sccm and a gallium source with a flow rate of 25 sccm are continuously introduced, and a 350 nm undoped GaN layer 10 is grown on the buffer layer 80 using a MOCVD growth process.

[0071] S4, preparing a polarization layer 30, such as Figure 3d shown.

[0072] Specifically, the temperature of the reaction chamber was maintained at 1000° C., and a nitrogen source with a flow rate of 2000 sccm and an aluminum source with a flow rate of 40 sccm were introduced at the same time, and a 1.5 nm AlN was grown using a MOCVD growth process as an AlN polarization enhancement layer.

[0073] S5, preparing a barrier layer 40, such as Figure 3e shown.

[0074] Specifically, the reaction chamber temperature was maintained at 1000°C, a nitrogen source with a flow rate of 2000sccm, a gallium source with a flow rate of 50sccm, and an aluminum source with a flow rate of 20sccm were introduced, and an Al2O3 film with an Al component of 0.25 and a thickness of 25nm was grown using a MOCVD growth process. 0.25 Ga 0.75 N barrier layer.

[0075] S6, preparing a p-BN layer 50, such as Figure 3f shown.

[0076] Specifically, the temperature of the reaction chamber is maintained at 1000° C., a nitrogen source with a flow rate of 2000 sccm, a boron source with a flow rate of 40 sccm, and a magnesium source with a flow rate of 20 sccm are introduced, and a p-BN layer 50 with a thickness of 50 nm is grown by using an MOCVD growth process.

[0077] S7, dry etching to achieve device separation, such as Figure 3g shown.

[0078] Specifically, a photolithography mask is used to define the p-type region and the n-type region of the device, and the device is selectively etched by dry etching using Cl2 / BCl3 plasma with an etching depth of 150 nm to achieve separation of the p-type device and the n-type device.

[0079] S8, dry etching to form an electrode contact layer, such as Figure 3h shown.

[0080] Specifically, a photolithography mask is used to selectively etch the device in the n-type region by dry etching using Cl2 / BCl3 plasma, and the etching stops at the barrier layer.

[0081] S9, make metal electrodes for n-type devices, such as Figure 3i shown.

[0082] Specifically, Ti / Al / Ni / Au metal (15nm / 85nm / 30nm / 40nm) is deposited on the upper surface of the barrier layer exposed in the n-type device by electron beam evaporation process, and then rapid thermal annealing is performed at 900°C in a N2 environment to form source and drain contact electrodes of the n-type device.

[0083] S10, making a gate metal electrode of an n-type device, such as Figure 3j shown.

[0084] Specifically, Ni / Au metal (30nm / 100nm) is deposited on the p-BN layer of the n-type device by electron beam evaporation process, and thermal annealing is performed at 600° C. in an O 2 environment to form a gate contact electrode.

[0085] S11, making source and drain electrodes of p-type devices, such as Figure 3k shown.

[0086] Specifically, Ti / Al / Ni / Au metals (15nm / 85nm / 30nm / 40nm) are deposited on the p-BN layer of the p-type device by electron beam evaporation process, and then rapid thermal annealing is performed at 900°C in a N2 environment to form source and drain contact electrodes of the p-type device.

[0087] S12, depositing a dielectric layer 62 of a p-type device, such as Figure 3l shown.

[0088] Specifically, on the left p-type device, a dielectric layer 62 with a thickness of 20 nm is deposited by using an atomic layer deposition process.

[0089] S13, making a gate metal electrode of a p-type device, such as Figure 3m shown.

[0090] Specifically, Ti / Pt / Au metal (10 nm / 20 nm / 60 nm) is deposited on the dielectric layer 62 by electron beam evaporation process to form a gate contact electrode.

[0091] S14, cascade of n-type devices and p-type devices, such as Figure 3n shown.

[0092] Specifically, Ti / Au metal is deposited by electron beam evaporation process to achieve connection between n-type devices and p-type devices.

[0093] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0095] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A p-BN-based GaN-based complementary logic device, characterized in that: include: An undoped GaN layer, wherein a strip-shaped groove is provided in the undoped GaN layer, and the strip-shaped groove divides the undoped GaN layer into a first region and a second region; A first polarization layer, a first barrier layer and a first p-BN layer are sequentially stacked on the upper surface of the first region of the undoped GaN layer, a first source electrode, a dielectric layer and a first drain electrode are arranged on the upper surface of the first p-BN layer, and a first gate electrode is arranged on the upper surface of the dielectric layer; A second polarization layer, a second barrier layer and a second p-BN layer are sequentially stacked on the upper surface of the second region of the undoped GaN layer, the second p-BN layer is located in the middle region of the upper surface of the second barrier layer, a second source and a second drain are respectively disposed in the two side regions of the upper surface of the second barrier layer, and a second gate is disposed on the upper surface of the second p-BN layer; The first drain is electrically connected to the second drain, and the first gate is electrically connected to the second gate.

2. The p-BN-based GaN-based complementary logic device according to claim 1, characterized in that: Also includes: A substrate and a buffer layer are stacked, wherein the buffer layer is located on a side of the undoped GaN layer away from the strip-shaped groove, and along a direction perpendicular to the substrate, the orthographic projections of the substrate and the buffer layer overlap with the orthographic projection of the undoped GaN layer; The substrate, the buffer layer, the undoped GaN layer, the first polarization layer, the first barrier layer, the first p-BN layer, the dielectric layer, the first source, the first drain and the first gate constitute a p-type device.

3. The p-BN-based GaN-based complementary logic device according to claim 2, characterized in that: The channel region of the p-type device is located on a side of the first barrier layer close to the first p-BN layer.

4. The p-BN-based GaN-based complementary logic device according to claim 1, characterized in that: Also includes: A substrate and a buffer layer are stacked, wherein the buffer layer is located on a side of the undoped GaN layer away from the strip-shaped groove, and along a direction perpendicular to the substrate, the orthographic projections of the substrate and the buffer layer overlap with the orthographic projection of the undoped GaN layer; The substrate, the buffer layer, the undoped GaN layer, the second polarization layer, the second barrier layer, the second p-BN layer, the second source, the second drain and the second gate constitute an n-type device.

5. The p-BN-based GaN-based complementary logic device according to claim 4, characterized in that: The channel region of the n-type device is located on a side of the undoped GaN layer close to the second polarization layer.

6. A method for preparing a p-BN-based gallium nitride-based complementary logic device, for preparing the p-BN-based gallium nitride-based complementary logic device as claimed in any one of claims 1 to 5, characterized in that: include: Providing an undoped GaN layer; Growing a polarization layer on the upper surface of the undoped GaN layer; growing a barrier layer on the upper surface of the polarization layer; growing a p-BN layer on the upper surface of the barrier layer; The p-BN layer, the barrier layer, the polarization layer and part of the undoped GaN layer are etched by an etching process to form strip-shaped openings in the p-BN layer, the barrier layer and the polarization layer, and to form strip-shaped grooves in the undoped GaN layer; The strip-shaped opening separates the p-BN layer into a first p-BN layer and a second p-BN layer, separates the barrier layer into a first barrier layer and a second barrier layer, separates the polarization layer into a first polarization layer and a second polarization layer, and the strip-shaped groove separates the undoped GaN layer into a first region and a second region; The second p-BN layer is etched by an etching process to etch away both sides of the second p-BN layer, exposing the upper surfaces of the two side regions of the second barrier layer, depositing metal on the upper surfaces of the two side regions of the exposed second barrier layer to form a second source and a second drain, respectively, and depositing metal on the upper surface of the second p-BN layer that has not been etched to form a second gate; Depositing metal on the upper surface of the two side regions of the first p-BN layer to form a first source and a first drain respectively, depositing a dielectric layer on the upper surface of the middle region of the first p-BN layer, and depositing metal on the upper surface of the dielectric layer to form a first gate; The first drain electrode is electrically connected to the second drain electrode, and the first gate electrode is electrically connected to the first gate electrode by means of evaporation interconnection line.

7. The method for preparing a p-BN-based GaN-based complementary logic device according to claim 6, characterized in that: Also includes: providing a substrate; depositing a buffer layer on the upper surface of the substrate; An undoped GaN layer is deposited on the upper surface of the buffer layer.

8. The method for preparing a p-BN-based gallium nitride-based complementary logic device according to claim 6, characterized in that: Depositing metal on the upper surface of the exposed two side regions of the second barrier layer to form a second source and a second drain respectively, and depositing metal on the upper surface of the second p-BN layer that has not been etched to form a second gate, including: Using electron beam evaporation process, Ti / Al / Ni / Au metal is deposited on the upper surface of the exposed two side regions of the second barrier layer, and rapidly annealed at 850-950° C. in N2 atmosphere to form ohmic contacts of the second source and the second drain; Ni / Au metal is deposited on the upper surface of the second p-BN layer by electron beam evaporation process, and thermal annealing is performed at 550-650° C. in an O2 atmosphere to form an ohmic contact of the second gate.

9. The method for preparing a p-BN-based GaN-based complementary logic device according to claim 6, characterized in that: A dielectric layer is deposited on the upper surface of the middle region of the first p-BN layer, a metal is deposited on the upper surfaces of the regions on both sides of the first p-BN layer to form a first source and a first drain respectively, and a metal is deposited on the upper surface of the dielectric layer to form a first gate, including: Using electron beam evaporation process, Ti / Al / Ni / Au metal is deposited on the upper surface of the two side regions of the first p-BN layer, and rapidly annealed at 850-950° C. in N2 atmosphere to form ohmic contacts of the first source and the first drain; A dielectric layer is deposited on the upper surface of the middle region of the first p-BN layer, Ti / Pt / Au metal is deposited on the upper surface of the dielectric layer using electron beam evaporation technology, and thermal annealing is performed at 550-650° C. in an O2 atmosphere to form an ohmic contact of the second gate.

10. The method for preparing a p-BN-based gallium nitride-based complementary logic device according to claim 6, characterized in that: Growing a p-BN layer on the upper surface of the barrier layer comprises: At 950-1050° C., a nitrogen source with a flow rate of 1950-2050 sccm, a boron source with a flow rate of 35-45 sccm, and a magnesium source with a flow rate of 15-25 sccm are introduced to grow p-BN with a thickness of 45-55 nm.

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