Array substrate preparation method, array substrate and display device

Abstract

The invention provides an array substrate preparation method, an array substrate and a display device, and the preparation method comprises the steps: providing a light shielding layer which is provided with a first surface and a second surface which are oppositely arranged; arranging a low-temperature polycrystalline silicon layer on the first surface; forming a lightly doped channel and a heavily doped channel at the same time by adopting one process; low-temperature polycrystalline silicon light doping is carried out on the light doping channel, and low-temperature polycrystalline silicon heavy doping is carried out on the heavy doping channel; depositing an insulating layer on one side, far away from the shading layer, of the low-temperature polycrystalline silicon layer; and forming a gate layer on one side, far away from the low-temperature polycrystalline silicon layer, of the deposited insulating layer. The thickness distribution of the photoresist is accurately controlled, so that the ion implantation depth and concentration are accurately regulated and controlled, and the light doping uniformity of the low-temperature polycrystalline silicon is improved. Meanwhile, the method simplifies the technological process, reduces the dependence on the thickness uniformity of the insulating layer, and improves the stability and controllability of the whole manufacturing process.

Description

Technical Field

[0001] The present application relates to the technical field of array substrates, and in particular to an array substrate preparation method, an array substrate and a display device. Background Art

[0002] LTPS is the abbreviation of Low-Temperature Polycrystalline Silicon, which is a high-performance thin-film transistor technology widely used in display technologies such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). LTPS technology has the advantages of fast response, low power consumption, high resolution, bright colors and reduced eye fatigue.

[0003] At present, the non-uniformity problem of LTPS-LCD products is quite serious. Analysis shows that it is strongly related to the uniformity of the characteristics of transistor devices. In view of the fact that the uniformity of the thickness of the insulating layer is difficult to control in actual production, and the gate line is dry-etched after the insulating layer is vapor-deposited, the remaining thickness of the insulating layer is not easy to control, which affects the uniformity of the lightly doped injection amount of low-temperature polysilicon, thereby affecting the uniformity of the characteristics of the LTPS device. Therefore, controlling the uniformity of the lightly doped ion injection of low-temperature polysilicon has a great influence on the characteristics of the transistor device.

[0004] Therefore, providing an array substrate preparation method, an array substrate and a display device that improve the uniformity of light doping of low-temperature polysilicon has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] Embodiments of the present application provide an array substrate manufacturing method, an array substrate, and a display device.

[0006] An embodiment of the present application provides a method for preparing an array substrate, including: providing a light-shielding layer, the light-shielding layer having a first surface and a second surface arranged opposite to each other; arranging a low-temperature polysilicon layer on the first surface; simultaneously forming a lightly doped channel and a heavily doped channel using one process; lightly doping the lightly doped channel with low-temperature polysilicon, and heavily doping the heavily doped channel with low-temperature polysilicon; depositing an insulating layer on a side of the low-temperature polysilicon layer away from the light-shielding layer; and forming a gate layer on a side of the deposited insulating layer away from the low-temperature polysilicon layer.

[0007] In some embodiments, the process of simultaneously forming a lightly doped channel and a heavily doped channel in one process includes: forming a photoresist on the low-temperature polysilicon layer; exposing and developing the photoresist using a half-tone mask; removing the photoresist; and simultaneously forming a lightly doped channel and a heavily doped channel.

[0008] In some embodiments, after forming a photoresist on the low temperature polysilicon layer, the method further includes: controlling the thickness of the photoresist to form a lightly doped region and a heavily doped region.

[0009] In some embodiments, controlling the thickness of the photoresist to form lightly doped regions and heavily doped regions includes: forming the photoresist into a first sub-photoresist and a second sub-photoresist, the first sub-photoresist corresponds to the gate layer, and the second sub-photoresist is located on both sides of the first sub-photoresist; controlling the thickness of the first sub-photoresist to be greater than the second sub-photoresist.

[0010] In some embodiments, lightly doping the lightly doped channel low-temperature polysilicon and heavily doping the heavily doped channel low-temperature polysilicon are performed simultaneously.

[0011] In some embodiments, LDD ions are implanted into the lightly doped channel, and ND ions are implanted into the heavily doped channel.

[0012] In some embodiments, the thickness of the photoresist is 1 micrometer to 3 micrometers.

[0013] In some embodiments, the heavily doped channel is located outside the lightly doped channel.

[0014] Another embodiment of the present application further provides an array substrate, which is manufactured using the array substrate manufacturing method described in the above embodiment.

[0015] Another embodiment of the present application further provides a display device, comprising the array substrate described in the above embodiment.

[0016] The embodiment of the present application provides a method for preparing an array substrate, including: providing a light shielding layer, the light shielding layer having a first surface and a second surface arranged opposite to each other; arranging a low-temperature polysilicon layer on the first surface; forming a lightly doped channel and a heavily doped channel simultaneously by a process; lightly doping the lightly doped channel with low-temperature polysilicon, and heavily doping the heavily doped channel with low-temperature polysilicon; depositing an insulating layer on a side of the low-temperature polysilicon layer away from the light shielding layer; and forming a gate layer on a side of the deposited insulating layer away from the low-temperature polysilicon layer. This method not only solves the problem of complex process and many process steps in forming lightly doped and heavily doped channels of low-temperature polysilicon, but also provides a more efficient and accurate technical path for the manufacture of LTPS devices. By optimizing the doping distribution, the uniformity problem of LTPS-LCD products can be further improved, and the display quality and performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the process of preparing an array substrate provided in an embodiment of the present application.

[0019] Figure 2 Another schematic diagram of the process of preparing an array substrate provided in an embodiment of the present application.

[0020] Figure 3 A schematic diagram of the structure of an array substrate provided in an embodiment of the present application.

[0021] Figure 4 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0023] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0024] Embodiments of the present application provide an array substrate manufacturing method, an array substrate, and a display device.

[0025] See also Figure 1 to Figure 2 , an embodiment of the present application provides a method for preparing an array substrate, comprising: S10 provides a light shielding layer, wherein the light shielding layer has a first surface and a second surface that are oppositely disposed.

[0026] It should be noted that the first surface is the upper surface of the shading layer, and the second surface is the lower surface of the shading layer. Of course, the positions of the first surface and the second surface can be exchanged as needed. Unless otherwise specified in the embodiments of the present application, the first surface is assumed to be the upper surface of the shading layer.

[0027] The function of the light shielding layer is to block light, prevent unnecessary reflection and scattering of light inside the display panel, and improve display contrast and image quality. The light shielding layer material usually selects metals or metal oxides with good light shielding properties, such as metals such as chromium, molybdenum and their alloys, or oxides such as indium tin oxide. The preparation process can form a uniform light shielding layer on the substrate by methods such as physical vapor deposition and chemical vapor deposition.

[0028] S20: providing a low temperature polysilicon layer on the first surface.

[0029] Among them, low-temperature polysilicon has high carrier mobility and good electrical properties, which can improve the switching speed and current driving capability of thin-film transistors, thereby improving the display performance of display panels. A low-temperature polysilicon layer can be grown on the first surface of the light-shielding layer by chemical vapor deposition and other methods, and parameters such as deposition temperature, gas flow rate and reaction time can be controlled to obtain a high-quality low-temperature polysilicon film.

[0030] S30 uses one process to simultaneously form a lightly doped channel and a heavily doped channel.

[0031] It should be noted that a halftone mask process or similar technology is used to simultaneously form a lightly doped channel and a heavily doped channel. This process controls the exposure degree of the photoresist by adjusting the transmittance of the mask, thereby achieving precise control of the channel doping area.

[0032] S40: lightly doping the lightly doped channel with low-temperature polysilicon, and heavily doping the heavily doped channel with low-temperature polysilicon.

[0033] Among them, light doping can adjust the electrical properties of the channel, such as threshold voltage, carrier mobility, etc., so that the thin film transistor has suitable switching characteristics under different working conditions. Heavy doping is mainly used to reduce the resistance of the source, drain and other regions and improve the current transmission efficiency. The doping process usually uses ion implantation or chemical vapor doping to introduce corresponding impurity atoms, such as boron and phosphorus, into the lightly doped channel and the heavily doped channel under specific process conditions.

[0034] S50 deposits an insulating layer on a side of the low-temperature polysilicon layer away from the light shielding layer.

[0035] It should be noted that the role of the insulating layer is to isolate different conductive layers and prevent short circuits between electrodes. It can also serve as a gate insulating layer, affecting the electrical properties of thin film transistors. Commonly used insulating layer materials include silicon dioxide, silicon nitride, etc. A uniform insulating layer can be deposited on the low-temperature polysilicon layer by chemical vapor deposition, atomic layer deposition, etc., and the deposition parameters can be controlled to obtain appropriate insulating properties and film thickness.

[0036] S60 forms a gate layer on a side of the deposited insulating layer away from the low-temperature polysilicon layer.

[0037] It should be noted that the gate layer is used to control the conduction and cutoff of the thin film transistor, and its performance directly affects the switching speed and power consumption of the display panel. The gate layer material is usually selected from metals or metal alloys, such as aluminum, copper, molybdenum, etc., and a patterned gate layer can be formed on the insulating layer by physical vapor deposition, photolithography, etching and other processes. The size and shape of the gate can be precisely controlled by photolithography technology to optimize the performance of the thin film transistor.

[0038] Specifically, this problem is particularly prominent on a typical LTPS-LCD panel production line. For example, in the production process of a 5.5-inch high-resolution LTPS-LCD panel, the thickness of the insulating layer may vary by ±10% in different areas of the panel, resulting in significant differences in the depth and concentration distribution of low-temperature polysilicon lightly doped ion implantation. Specifically, the insulating layer in the center area of ​​the panel may be 5-8nm thinner than that in the edge area. This difference directly leads to an increase in the depth of lightly doped ion implantation in the center area, while the concentration distribution becomes more diffuse. Among them, this non-uniformity can cause the brightness of pixels at different locations on the panel to differ by up to 5-8%, and the color saturation to vary by more than 3%. In some extreme cases, it may even cause the response time of local areas to increase by 15-20%. Changes in these parameters directly affect the overall performance and user experience of the display panel.

[0039] If this technical problem cannot be effectively solved, it will have a serious impact on the market competitiveness of LTPS-LCD products. First, the non-uniformity of the panel will lead to a decrease in product yield and increase production costs. Secondly, the decline in display quality will directly affect the user experience and may damage the brand reputation. For example, in application scenarios such as high-end smartphones or tablets that have extremely high requirements for display quality, even a 5% brightness difference may be noticed by users, thereby affecting the market acceptance of the product. In addition, the non-uniformity problem may also lead to a shortened product life, because the performance differences of devices in different regions will cause inconsistent local aging rates. In the long run, if this problem cannot be solved, LTPS technology may lose its advantage in future display technology competition. Therefore, the development of a new array substrate preparation method that can improve the uniformity of low-temperature polysilicon light doping has become a key research direction in the field of display technology.

[0040] In view of the non-uniformity problem existing in LTPS-LCD products, this application deeply analyzes its root cause and proposes an innovative solution.

[0041] In the process of exploring solutions, the possibility of optimizing the insulating layer deposition process was first considered. By improving the vapor deposition equipment or adjusting the deposition parameters, the uniformity of the insulating layer thickness may be improved. However, although this method is direct, it is difficult to achieve the desired effect on large-area panels and may increase production costs.

[0042] Next, we considered performing precise chemical mechanical polishing (CMP) after the deposition of the insulating layer. This method can theoretically achieve precise control of the thickness of the insulating layer, but in practice it may introduce new non-uniformities and significantly increase process complexity and cost.

[0043] After further consideration, the present application turned to the direction of controlling the low-temperature polysilicon light doping process from the source. Specifically, an innovative process method is proposed, that is, a process is used to form a lightly doped channel and a heavily doped channel at the same time. The core of this method is to achieve precise control of the ion implantation depth and concentration by precisely controlling the thickness and distribution of the photoresist.

[0044] To achieve this goal, the present application proposes the following specific steps: First, a low-temperature polysilicon layer is provided on the light-shielding layer. Then, a lightly doped channel and a heavily doped channel are formed simultaneously using one process. The key to this step is to use a half-tone mask to expose and develop the photoresist, so as to achieve precise control of the thickness of the photoresist in different regions in a single process. Next, the lightly doped channel is lightly doped with low-temperature polysilicon, and the heavily doped channel is heavily doped with low-temperature polysilicon. Finally, an insulating layer is deposited on the low-temperature polysilicon layer, and a gate layer is formed thereon.

[0045] The advantage of this method is that by precisely controlling the thickness of the photoresist, the lightly doped and heavily doped regions can be precisely defined in a single process, thereby greatly improving the uniformity of the lightly doped low-temperature polysilicon. At the same time, this method also simplifies the process flow and reduces the reliance on the uniformity of the thickness of the insulating layer, thereby improving the stability and controllability of the overall process.

[0046] The core innovation of this application is to form lightly doped channels and heavily doped channels simultaneously in one process. This method achieves precise control of ion implantation depth and concentration by precisely controlling the thickness distribution of the photoresist, thereby improving the uniformity of lightly doped low-temperature polysilicon. At the same time, this method simplifies the process flow, reduces the dependence on the uniformity of the thickness of the insulating layer, and improves the stability and controllability of the overall process.

[0047] The working principle of this application can be described in detail as follows: First, a light shielding layer having a first surface and a second surface is provided. The light shielding layer is usually made of a metal material or a black resin material, and is used to block light from penetrating to prevent the light from interfering with the subsequent thin film transistor structure.

[0048] Next, a low-temperature polysilicon layer is disposed on the first surface of the light shielding layer. The low-temperature polysilicon layer is a polysilicon thin film prepared by a low-temperature process (usually below 600° C.) and has high carrier mobility and good uniformity.

[0049] Then, a lightly doped channel and a heavily doped channel are formed simultaneously in one process. This step is the core innovation of the present application. Specifically, a photoresist is first formed on the low-temperature polysilicon layer, and then the photoresist is exposed and developed using a half-tone mask. By controlling the thickness of the photoresist, regions with different doping concentrations can be formed in the same process step.

[0050] After that, the lightly doped channel is lightly doped with low-temperature polysilicon, and the heavily doped channel is heavily doped with low-temperature polysilicon. This step is achieved through ion implantation technology. The different thicknesses of photoresist will lead to differences in ion implantation depth and concentration, thus forming lightly doped and heavily doped areas.

[0051] Finally, an insulating layer is deposited on the side of the low-temperature polysilicon layer away from the light shielding layer, and a gate layer is formed on the side of the deposited insulating layer away from the low-temperature polysilicon layer. The insulating layer is usually made of materials such as silicon oxide or silicon nitride for electrical isolation. The gate layer is usually made of metal materials or polysilicon materials to control the conduction state of the transistor.

[0052] The reason for choosing this process method is that by forming lightly doped and heavily doped channels simultaneously through one process, doping uniformity can be significantly improved, process steps can be reduced, and costs can be reduced. At the same time, since the dependence on the uniformity of the thickness of the insulating layer is reduced, the stability and controllability of the overall process are improved.

[0053] As a preferred implementation, the specific embodiments of the present application can be described as follows: First, a molybdenum-chromium alloy light shielding layer with a size of 200 mm×200 mm and a thickness of 0.5 μm is provided. The light shielding layer has a first surface and a second surface arranged opposite to each other, wherein the first surface faces the thin film transistor structure to be formed subsequently.

[0054] Next, a low-temperature polysilicon layer with a thickness of 50 nm is deposited on the first surface of the light shielding layer at a temperature of 420° C. using a low-pressure chemical vapor deposition (LPCVD) method.

[0055] Then, a layer of positive photoresist with a thickness of 1.5 μm was spin-coated on the low-temperature polysilicon layer. The photoresist was exposed using a half-tone mask with an exposure energy of 200 mJ / cm 2 After development, two photoresist regions with different thicknesses of 1.5 μm and 0.8 μm are formed, corresponding to the lightly doped channel and the heavily doped channel.

[0056] After that, ion implantation equipment is used for doping. For lightly doped channels, phosphorus ions are implanted with an energy of 60keV and a dose of 1×10^15cm^2. For heavily doped channels, phosphorus ions are implanted with an energy of 80keV and a dose of 5×10^15cm^2. In this way, light doping and heavy doping are completed in the same process step.

[0057] Finally, a 200 nm thick silicon oxide is deposited on the low temperature polysilicon layer by plasma enhanced chemical vapor deposition (PECVD) as an insulating layer, and then a 300 nm thick aluminum is deposited on the insulating layer by magnetron sputtering as a gate layer.

[0058] Through this method, lightly doped and heavily doped channels can be formed simultaneously in one process step, which significantly improves the uniformity of light doping of low-temperature polysilicon, simplifies the process flow, and improves the stability and controllability of the overall process.

[0059] In some of the above embodiments, during the implementation of the present application, there are still problems such as the complex process and many process steps for forming the lightly doped and heavily doped channels of low-temperature polysilicon. In response to this, the present application further proposes a method for simultaneously forming the lightly doped channel and the heavily doped channel using one process. Specifically, the method includes forming a photoresist on the low-temperature polysilicon layer; exposing and developing the photoresist using a half-tone mask; removing the photoresist; and simultaneously forming the lightly doped channel and the heavily doped channel.

[0060] This method uses a combination of a half-tone mask and a photoresist to form a lightly doped channel and a heavily doped channel in one process. The half-tone mask can produce different degrees of exposure in the same exposure process, thereby forming areas of different thicknesses on the photoresist. These areas of different thicknesses will produce different doping concentrations in the subsequent ion implantation process, thereby forming lightly doped and heavily doped areas. Specifically, the half-tone mask usually contains completely transparent, completely opaque, and semi-transparent areas. The completely transparent area corresponds to the position where the heavily doped channel is to be formed, the completely opaque area corresponds to the position where doping is not required, and the semi-transparent area corresponds to the position where the lightly doped channel is to be formed. By controlling the transmittance of the semi-transparent area, the formation of the lightly doped area can be precisely controlled.

[0061] After the photoresist is exposed and developed, photoresist areas of different thicknesses will be formed. For example, a photoresist with a thickness of 1 micron to 3 microns can be formed. Among them, the photoresist corresponding to the heavily doped area is thinner or completely removed, the photoresist corresponding to the lightly doped area has a moderate thickness, and the thicker photoresist is retained in the area that does not require doping. In the subsequent ion implantation process, photoresists of different thicknesses will have different degrees of blocking effects on the penetration of ions. Thin or no photoresist areas allow more ions to penetrate, forming heavily doped areas; medium-thick photoresist areas only allow part of the ions to penetrate, forming lightly doped areas; and thick photoresist areas completely block ions and maintain the original undoped state.

[0062] An important advantage of this method is that lightly doped and heavily doped regions can be formed simultaneously in one photolithography and ion implantation process, which greatly simplifies the process flow, reduces alignment errors, and improves production efficiency. In addition, since the lightly doped and heavily doped regions are formed simultaneously, the positional relationship between them is more precise, which is conducive to improving the performance and consistency of the device. As a preferred embodiment, the thickness of the photoresist can be further controlled to form more precise lightly doped regions and heavily doped regions. For example, the photoresist can be formed into a first sub-photoresist and a second sub-photoresist, the first sub-photoresist corresponds to the gate layer, and the second sub-photoresist is located on both sides of the first sub-photoresist. By controlling the thickness of the first sub-photoresist to be greater than the second sub-photoresist, a more precise doping distribution can be formed in the subsequent ion implantation process. Specific embodiments are as follows: First, a layer of positive photoresist with a thickness of 2 microns is spin-coated on the low-temperature polysilicon layer. Then, a special half-tone mask is used for exposure. The mask has a transmittance of 80% at the position corresponding to the heavily doped area to be formed, a transmittance of 40% at the position corresponding to the lightly doped area to be formed, and is completely opaque in other areas. After exposure, development is performed to obtain a photoresist pattern with different thickness distributions. Among them, the photoresist thickness of the heavily doped area is about 0.4 microns, the photoresist thickness of the lightly doped area is about 1.2 microns, and the other areas maintain the original 2 microns thickness.

[0063] Next, ion implantation is performed, for example, phosphorus ions with a concentration of 1×10^15 cm^-2 are implanted. Due to the different thickness of the photoresist, the heavily doped area will receive most of the ions, forming a heavily doped area with a concentration of about 5×10^19 cm^-3; due to the thicker photoresist in the lightly doped area, only part of the ions can penetrate, forming a lightly doped area with a concentration of about 1×10^18 cm^-3; and other areas are basically not penetrated by ions because the photoresist is the thickest. Finally, the remaining photoresist is removed to complete the simultaneous formation of the lightly doped channel and the heavily doped channel. Compared with the traditional multiple photolithography and ion implantation method, the method of the present application has the following advantages: 1. The process steps are greatly simplified, from the original multiple photolithography and ion implantation to one time, which significantly improves the production efficiency. 2. The cumulative error caused by multiple alignments is reduced, and the position accuracy between the lightly doped area and the heavily doped area is improved. 3. Since light doping and heavy doping are carried out simultaneously, the doping concentration gradient between the two areas can be better controlled, which is conducive to optimizing device performance. 4. Reduced production costs, reduced material consumption and equipment usage time. 5. Improve the yield rate of products, because reducing the process steps also reduces the defects that may be introduced in each step.

[0064] This method not only solves the problem of complex and multi-step process of forming channels of low-temperature polysilicon lightly doped and heavily doped, but also provides a more efficient and accurate technical path for the manufacture of LTPS devices. By optimizing the doping distribution, the uniformity of LTPS-LCD products can be further improved, and the display quality and performance can be improved.

[0065] In some of the above-mentioned embodiments, during the implementation of the present application, there is still a problem that the inaccurate control of the photoresist thickness leads to undesirable formation of lightly doped and heavily doped regions.

[0066] In this regard, the present application further proposes to control the thickness of the photoresist after forming the photoresist on the low-temperature polysilicon layer to form lightly doped regions and heavily doped regions. By controlling the thickness of the photoresist, the lightly doped regions and heavily doped regions can be formed more accurately, thereby improving the uniformity of the light doping of the low-temperature polysilicon. This method can better control the formation of lightly doped and heavily doped regions, thereby improving the uniformity of the characteristics of the LTPS device.

[0067] Specifically, the method of controlling the thickness of the photoresist can be achieved in a variety of ways. For example, the thickness can be controlled by adjusting the rotation speed and time during the photoresist coating process. Another method is to use precision coating equipment, such as spraying equipment or drop coating equipment, which can more accurately control the amount and distribution of the photoresist.

[0068] Furthermore, the control of photoresist thickness can be combined with the use of half-tone masks. By precisely controlling the photoresist thickness, the characteristics of the half-tone mask can be better utilized to form photoresist areas of different thicknesses in a single exposure process, thereby achieving precise definition of lightly doped and heavily doped areas.

[0069] Thus, the step of controlling the thickness of the photoresist and the method of forming both the lightly doped channel and the heavily doped channel in one process have a synergistic effect. This synergy not only simplifies the process, but also improves the accuracy of the doped region formation, thereby improving the performance and uniformity of the LTPS device.

[0070] As a preferred embodiment, the thickness of the photoresist can be controlled between 1 micron and 3 microns. This range can ensure that the photoresist has enough thickness difference in the subsequent halftone exposure process to form clear lightly doped and heavily doped regions. In practical applications, the thickness of the photoresist can be further optimized according to specific device design and process requirements. For example, for devices that require more precise control, the thickness of the photoresist can be controlled between 1.5 microns and 2.5 microns. This precise control can further improve the boundary clarity of the lightly doped and heavily doped regions, thereby improving device performance.

[0071] By implementing the method of the present application, the performance uniformity of LTPS devices can be significantly improved. Compared with the traditional method, the method of the present application can form lightly doped and heavily doped regions simultaneously in a single exposure process by accurately controlling the thickness of the photoresist and combining the half-tone mask technology, which greatly simplifies the process steps. This not only improves production efficiency, but also reduces the errors that may be caused by multiple exposures and etching, thereby improving the consistency and reliability of the device. In addition, the method of the present application also has good adaptability and controllability. By adjusting the design of the photoresist thickness and the half-tone mask, it can flexibly adapt to different types of LTPS device requirements and achieve more sophisticated doping control. This flexibility makes the present method have a wide range of application prospects in different display technology applications.

[0072] In some of the above-mentioned embodiments, the present application still has the problem of inaccurate control of the thickness of the photoresist during the implementation process. In this regard, the present application further proposes to form the photoresist into a first sub-photoresist and a second sub-photoresist, wherein the first sub-photoresist corresponds to the gate layer, and the second sub-photoresist is located on both sides of the first sub-photoresist; and the thickness of the first sub-photoresist is controlled to be greater than that of the second sub-photoresist. This scheme can better realize the formation of lightly doped regions and heavily doped regions by accurately controlling the thickness distribution of the photoresist, thereby improving the uniformity of lightly doped low-temperature polysilicon. Specifically, the present application can realize more refined doping control by dividing the photoresist into two parts and controlling their thickness difference. The first sub-photoresist corresponds to the gate layer, and its thickness is relatively large, which can better protect the gate region from heavy doping. The second sub-photoresist is located on both sides of the first sub-photoresist, and its thickness is relatively small, allowing moderate ion implantation to form a lightly doped region.

[0073] The advantages of this design are: 1. Precise control: By controlling the thickness of the photoresist in the two regions separately, the depth and concentration of ion implantation can be adjusted more accurately. 2. Structural optimization: The first sub-photoresist corresponds to the gate layer, which can better protect the gate region and reduce the influence of parasitic capacitance. 3. Process simplification: Two photoresists of different thicknesses can be formed using the same photolithography process, which simplifies the manufacturing process. 4. Improved uniformity: By accurately controlling the lightly doped and heavily doped regions, the uniformity of the characteristics of the LTPS device can be significantly improved. In practical applications, the following steps can be used to achieve this photoresist thickness control: First, apply photoresist on the low-temperature polysilicon layer. Then, use a grayscale mask for exposure, which has a higher transmittance in the region corresponding to the gate and a lower transmittance in the regions on both sides. After exposure, development is performed to obtain the first sub-photoresist and the second sub-photoresist of different thicknesses. For example, the thickness of the first sub-photoresist can be controlled to be 2.5 microns, and the thickness of the second sub-photoresist can be controlled to be 1.5 microns. This thickness difference can effectively distinguish lightly doped areas from heavily doped areas while ensuring a sufficient process window. With this method, lightly doped areas and heavily doped areas can be formed simultaneously in one photolithography process, greatly simplifying the manufacturing process and improving production efficiency. At the same time, due to the precise control of the photoresist thickness, the depth and concentration of ion implantation can be better adjusted, thereby improving the performance and uniformity of LTPS devices.

[0074] Compared with traditional technologies, the solution of the present application has the following advantages: 1. Improved uniformity of light doping: By precisely controlling the thickness of the photoresist, the depth and concentration of ion implantation can be better controlled, thereby improving the uniformity of the LTPS device. 2. Simplified manufacturing process: Traditional methods may require multiple photolithography and doping steps, while the solution of the present application can be completed in one photolithography process, greatly simplifying the manufacturing process. 3. Improved device performance: By optimizing the distribution of lightly doped and heavily doped areas, parasitic capacitance can be reduced and the switching speed and driving capability of the device can be improved. 4. Enhanced process controllability: Compared with single-thickness photoresist, the double-thickness photoresist solution of the present application provides a larger process adjustment space, which can more flexibly adapt to different device design requirements.

[0075] In some of the above-mentioned embodiments, during the implementation of the present application, there is still a problem of uniformity control of light doping and heavy doping of low-temperature polysilicon. In this regard, the present application further proposes a technical solution for lightly doping the lightly doped channel low-temperature polysilicon and heavily doping the heavily doped channel low-temperature polysilicon at the same time. The present application provides a method for preparing an array substrate, including providing a light shielding layer, arranging a low-temperature polysilicon layer on the first surface of the light shielding layer, using a process to simultaneously form a lightly doped channel and a heavily doped channel, lightly doping the lightly doped channel with low-temperature polysilicon, and heavily doping the heavily doped channel with low-temperature polysilicon, depositing an insulating layer on the side of the low-temperature polysilicon layer away from the light shielding layer, and forming a gate layer on the side of the deposited insulating layer away from the low-temperature polysilicon layer. Among them, light doping of the lightly doped channel low-temperature polysilicon and heavy doping of the heavily doped channel low-temperature polysilicon are carried out simultaneously. The technical solution of the present application can effectively improve the uniformity and efficiency of the doping process by performing light doping and heavy doping at the same time. Specifically, this simultaneous doping method can reduce process steps and manufacturing costs, and since the two dopings are carried out simultaneously, the non-uniformity problem caused by time difference can be reduced. In actual operation, ion implantation technology can be used to achieve simultaneous doping. For example, ion implantation equipment with dual energy or multi-energy can be used to simultaneously implant different concentrations of ions into lightly doped channels and heavily doped channels. Lightly doped channels can be implanted with lower concentrations of ions, such as 1E15 to 1E16 atoms / cm², while heavily doped channels can be implanted with higher concentrations of ions, such as 1E18 to 1E20 atoms / cm². This simultaneous doping method can also be used in combination with the aforementioned half-tone mask technology. Photoresists of different thicknesses formed by half-tone masks can be used to distinguish lightly doped and heavily doped areas in the same ion implantation process. Thicker photoresist areas correspond to lightly doped areas, and thinner photoresist areas correspond to heavily doped areas.

[0076] Furthermore, simultaneous doping can also achieve more precise control by adjusting the energy and dose of ion implantation. For example, low energy and high dose implantation can be performed first, and then high energy and low dose implantation can be performed, so that doping regions with different depths can be formed in one process. As a preferred embodiment, phosphorus ions can be used as n-type dopants and boron ions can be used as p-type dopants. For lightly doped areas, 5-15 keV energy and 1E15-5E15 atoms / cm² doses can be used; for heavily doped areas, 20-40 keV energy and 1E18-5E19 atoms / cm² doses can be used. This parameter setting can minimize the damage to the lattice structure of the low-temperature polysilicon layer by ion implantation while ensuring the effects of light and heavy doping. By adopting the method of simultaneous doping, the present application can effectively solve the problem of non-uniformity caused by step-by-step doping in the traditional LTPS preparation process. This method not only simplifies the process flow, but also improves production efficiency. Since light doping and heavy doping are carried out simultaneously, surface contamination and oxidation problems caused by process intervals can be reduced, thereby improving the performance and reliability of the device. Compared with the prior art, the simultaneous doping method of the present application has the following advantages: first, it reduces the process steps and reduces the production cost; second, by completing light doping and heavy doping at one time, the uniformity of doping is improved; third, the damage to the low-temperature polysilicon layer caused by multiple doping is reduced, and the electrical performance of the device is improved; finally, the combination of this method with half-tone mask technology makes it possible to achieve more complex doping distributions, thereby enhancing the flexibility and adaptability of the process.

[0077] In some of the above embodiments, during the implementation of the present application, there is still the problem of uneven ion implantation of lightly doped and heavily doped low-temperature polysilicon. In this regard, the present application further proposes a technical solution of injecting LDD ions into lightly doped channels and injecting ND ions into heavily doped channels. The present application provides a method for preparing an array substrate, including providing a light shielding layer, arranging a low-temperature polysilicon layer on the first surface of the light shielding layer, forming a lightly doped channel and a heavily doped channel simultaneously by a process, lightly doping the lightly doped channel with low-temperature polysilicon, heavily doping the heavily doped channel with low-temperature polysilicon, depositing an insulating layer on the side of the low-temperature polysilicon layer away from the light shielding layer, and forming a gate layer on the side of the deposited insulating layer away from the low-temperature polysilicon layer. Further, LDD ions are injected into the lightly doped channel, and ND ions are injected into the heavily doped channel. The present application can achieve precise control of light doping and heavy doping of low-temperature polysilicon by injecting LDD ions into the lightly doped channel and ND ions into the heavily doped channel. LDD (Lightly Doped Drain) ions are lightly doped ions suitable for the formation of lightly doped channels. ND (N-type Doped) ions are heavily doped ions suitable for the formation of heavily doped channels. Specifically, LDD ion implantation can be performed in a low-energy, low-dose manner, such as using phosphorus ions or arsenic ions, with an implantation energy in the range of 10-30keV and a dose in the range of 1E13-5E13 atoms / cm². This low-energy, low-dose implantation method ensures that the lightly doped channel has an appropriate doping concentration, thereby achieving good electrical properties. For heavily doped channels, ND ion implantation can be performed in a high-energy, high-dose manner, such as using phosphorus ions or arsenic ions, with an implantation energy in the range of 30-80keV and a dose in the range of 1E15-5E15 atoms / cm². This high-energy, high-dose implantation method ensures that the heavily doped channel has a sufficiently high doping concentration, thereby achieving low resistance characteristics.

[0078] By injecting different types and doses of ions into the lightly doped channel and the heavily doped channel respectively, the doping concentration distribution of the two channels can be accurately controlled. This precise control helps to optimize the electrical properties of the device, such as reducing leakage current, improving the switching ratio, improving subthreshold swing, etc. At the same time, since the implantation of LDD ions and ND ions can be carried out continuously on the same device, the process can be simplified and production efficiency can be improved. As a preferred embodiment, the implantation of LDD ions and ND ions can be carried out using ion implantation equipment. During the implantation process, the implantation depth and distribution of ions can be accurately controlled by adjusting the parameters of the ion implantation equipment, such as acceleration voltage, beam current, injection angle, etc. For example, the injection angle of LDD ions can be set to 7°-10°, and the injection angle of ND ions can be set to 0°-3° to achieve different injection depths and lateral diffusion effects.

[0079] In practical applications, the injection parameters of LDD ions and ND ions can be optimized according to specific device design requirements and process conditions. For example, the width and concentration gradient of the lightly doped area and the heavily doped area can be controlled by adjusting the injection energy and dosage, thereby achieving better device performance. By adopting the technical solution of the present application, the problem of uneven characteristics of transistor devices in LTPS-LCD products can be effectively solved. Compared with the traditional single doping process, the present application can more accurately control the doping concentration distribution by injecting different types of ions into the lightly doped channel and the heavily doped channel respectively, thereby improving the uniformity of device characteristics. This improvement can significantly improve the display quality of LTPS-LCD products, reduce problems such as uneven brightness and color deviation, and ultimately improve the market competitiveness of the product.

[0080] In some of the above-mentioned embodiments, during the implementation of the present application, there is still a problem that improper control of photoresist thickness may affect the light doping and heavy doping effects.

[0081] In this regard, the present application further proposes that the thickness of the photoresist is 1 micron to 3 microns. In this technical solution, the thickness of the photoresist is 1 micron to 3 microns. The selection of this thickness range is based on a comprehensive consideration of the effects of light doping and heavy doping. When the thickness of the photoresist is within this range, the depth and concentration of light doping and heavy doping can be effectively controlled, thereby achieving uniformity control of light doping of low-temperature polysilicon. Specifically, the control of the thickness of the photoresist is crucial for forming lightly doped areas and heavily doped areas. When the thickness of the photoresist is 1 micron to 3 microns, appropriate lightly doped areas and heavily doped areas can be formed during exposure and development. This thickness range allows light to properly penetrate the photoresist during the exposure process of the half-tone mask, forming exposure areas of different degrees, thereby forming photoresist areas of different thicknesses after development, corresponding to lightly doped areas and heavily doped areas. For example, the photoresist can be formed into a first sub-photoresist and a second sub-photoresist, the first sub-photoresist corresponds to the gate layer, and the second sub-photoresist is located on both sides of the first sub-photoresist. By controlling the thickness of the first sub-photoresist to be greater than that of the second sub-photoresist, precise control of the lightly doped region and the heavily doped rod region can be achieved. In this process, the photoresist thickness range of 1 micron to 3 microns provides sufficient operating space, so that the thickness difference of the two sub-photoresists can be accurately controlled. In addition, this thickness range is also beneficial to the subsequent ion implantation process. When LDD ions are injected into the lightly doped channel and ND ions are injected into the heavily doped channel, the photoresist thickness of 1 micron to 3 microns can provide appropriate masking effect to ensure the accuracy and uniformity of ion implantation. This thickness range will neither be too thin to cause insufficient masking effect, nor too thick to affect the penetration ability of ions. By controlling the photoresist thickness within the range of 1 micron to 3 microns, the present application can effectively improve the uniformity of low-temperature polysilicon light doping. The improvement of this uniformity directly affects the characteristics of LTPS devices and helps to solve the problem of non-uniformity of LTPS-LCD products. Thus, the performance of the display can be improved, including improving response speed, reducing power consumption, improving resolution and color performance, etc.

[0082] As a specific embodiment, the following steps can be used to control the thickness of the photoresist: First, spin-coat the photoresist on the low-temperature polysilicon layer, and the spin-coating speed and time can be adjusted according to the required thickness. For example, the spin-coating speed can be set to 3000rpm and the time can be set to 30 seconds. Then, pre-bake the coated photoresist, and the temperature can be set to 100°C and the time can be set to 90 seconds. This step can remove the solvent in the photoresist and solidify the photoresist. Next, expose the photoresist using a half-tone mask. The exposure energy can be set to 150mJ / cm², and the exposure time can be adjusted according to the intensity of the light source. After exposure, develop the photoresist. A 2.38% TMAH (tetramethylammonium hydroxide) solution can be used as a developer, and the development time is 60 seconds. Finally, hard bake is performed, and the temperature can be set to 120°C and the time can be set to 120 seconds. This step can further solidify the photoresist and improve its corrosion resistance.

[0083] Through these precisely controlled steps, the photoresist thickness can be precisely controlled within the range of 1 micron to 3 microns, thereby providing a good foundation for subsequent light doping and heavy doping processes. Compared with the prior art, the present application achieves an effective improvement in the uniformity of light doping of low-temperature polysilicon by precisely controlling the thickness of the photoresist. This method avoids the problem of uneven light doping injection amount caused by uneven thickness of the insulating layer in traditional technology. At the same time, the method of the present application is simple and easy to implement, does not require additional complex process steps, can be well integrated into the existing LTPS manufacturing process, and has good practicality and economy.

[0084] In some of the above-mentioned embodiments, during the implementation of the present application, there is still a problem that the position of the heavily doped channel is not accurate enough.

[0085] In this regard, the present application further proposes a technical solution in which a heavily doped channel is located outside a lightly doped channel. This layout arrangement can better control the position of the heavily doped channel and improve the performance and reliability of the array substrate. By arranging the heavily doped channel outside the lightly doped channel, the leakage current can be effectively reduced, the switching ratio of the device can be improved, and the parasitic capacitance can be reduced at the same time, thereby improving the response speed of the array substrate. Specifically, the design in which the heavily doped channel is located outside the lightly doped channel can be achieved in the following manner: first, a photoresist is formed on a low-temperature polysilicon layer. The thickness of the photoresist can be controlled between 1 micron and 3 microns, and this thickness range can ensure that the subsequent doping process can be carried out effectively. Then, the photoresist is exposed and developed using a half-tone mask. The design of the half-tone mask can make the photoresist form different thicknesses in the lightly doped area and the heavily doped area. For example, the photoresist can be formed into a first sub-photoresist and a second sub-photoresist, wherein the first sub-photoresist corresponds to the gate layer, and the second sub-photoresist is located on both sides of the first sub-photoresist. By controlling the thickness of the first sub-photoresist to be greater than that of the second sub-photoresist, different doping concentrations can be formed in the subsequent doping process. Then, the photoresist is removed to form a lightly doped channel and a heavily doped channel at the same time. This step can be completed simultaneously through a process, thereby improving manufacturing efficiency. Finally, the lightly doped channel is lightly doped with low-temperature polysilicon, and the heavily doped channel is heavily doped with low-temperature polysilicon. These two doping processes can be performed simultaneously, further improving manufacturing efficiency.

[0086] Specifically, LDD ions can be injected into the lightly doped channel, and ND ions can be injected into the heavily doped channel. In this way, the heavily doped channel is precisely positioned outside the lightly doped channel. This layout can effectively control the flow path of the current, reduce leakage current, and improve the switching ratio of the device. At the same time, since the heavily doped area is located on the outside, the overlapping area between the gate and the source and drain can be reduced, thereby reducing parasitic capacitance and improving the response speed of the device.

[0087] As a preferred embodiment, the width of the heavily doped channel can be controlled between 0.5 microns and 1.5 microns, while the width of the lightly doped channel can be controlled between 0.3 microns and 1 micron. This size design can minimize the size of the device and improve the integration while ensuring the performance of the device. In addition, the doping concentration of the heavily doped channel can be set between 1×10^20 cm^-3 and 5×10^20 cm^-3, while the doping concentration of the lightly doped channel can be set between 1×10^17 cm^-3 and 5×10^18 cm^-3. This doping concentration design can minimize the short channel effect and hot carrier effect while ensuring the performance of the device.

[0088] Compared with the prior art, the technical solution of the present application solves the problem of inaccurate position of the heavily doped channel in the traditional LTPS preparation method by setting the heavily doped channel outside the lightly doped channel. This design not only improves the performance and reliability of the device, but also simplifies the manufacturing process and improves production efficiency. Compared with the traditional multiple doping process, the method of forming a lightly doped channel and a heavily doped channel in one process of the present application greatly reduces the manufacturing steps and reduces the production cost. In addition, the technical solution of the present application can also better control the distribution of the doping concentration, thereby achieving better device performance. See also Figure 3 Another embodiment of the present application further provides an array substrate 100, which is manufactured by the array substrate manufacturing method described in the above embodiment. Since the array substrate manufacturing method has been described in detail in the above embodiment, the array substrate manufacturing method in the above embodiment will not be described in detail in the present application embodiment. See also Figure 4 Another embodiment of the present application further provides a display device 1000, comprising the array substrate 100 described in the above embodiment. Since the array substrate 100 has been described in detail in the above embodiment, the array substrate 100 in the above embodiment will not be described in detail in the present application embodiment.

[0089] The above is a detailed introduction to the method for preparing the array substrate, the array substrate and the display device provided by the embodiments of the present application. The principles and implementation methods of the present application are described in detail using specific examples herein. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A method for preparing an array substrate, characterized in that: include: Providing a light shielding layer, wherein the light shielding layer has a first surface and a second surface arranged opposite to each other; Disposing a low temperature polysilicon layer on the first surface; A lightly doped channel and a heavily doped channel are formed simultaneously using one process; Lightly doping the lightly doped channel with low-temperature polysilicon, and heavily doping the heavily doped channel with low-temperature polysilicon; Depositing an insulating layer on a side of the low-temperature polysilicon layer away from the light shielding layer; A gate layer is formed on a side of the deposited insulating layer away from the low-temperature polysilicon layer.

2. The method for preparing an array substrate according to claim 1, characterized in that: The method of simultaneously forming the lightly doped channel and the heavily doped channel by one process comprises: forming a photoresist on the low temperature polysilicon layer; Using a half-tone mask to expose and develop the photoresist; removing the photoresist; A lightly doped channel and a heavily doped channel are formed simultaneously.

3. The method for preparing an array substrate according to claim 2, characterized in that: After forming a photoresist on the low temperature polysilicon layer, the method comprises: The thickness of the photoresist is controlled to form lightly doped regions and heavily doped regions.

4. The method for preparing an array substrate according to claim 2, characterized in that: The step of controlling the thickness of the photoresist to form a lightly doped region and a heavily doped region comprises: The photoresist is formed into a first sub-photoresist and a second sub-photoresist, wherein the first sub-photoresist and the Corresponding to the gate layer, the second sub-photoresist is located on both sides of the first sub-photoresist; The thickness of the first sub-photoresist is controlled to be greater than that of the second sub-photoresist.

5. The method for preparing an array substrate according to claim 4, characterized in that: The lightly doped channel low-temperature polysilicon is lightly doped, and the heavily doped channel low-temperature polysilicon is heavily doped simultaneously.

6. The method for preparing an array substrate according to claim 1, characterized in that: LDD ions are implanted into the lightly doped channel, and ND ions are implanted into the heavily doped channel.

7. The method for preparing an array substrate according to claim 1, characterized in that: The thickness of the photoresist is 1 micron to 3 microns.

8. The method for preparing an array substrate according to claim 1, wherein: The heavily doped channel is located outside the lightly doped channel.

9. An array substrate, characterized in that: The array substrate is manufactured by the method for manufacturing the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the array substrate as claimed in claim 9.

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