Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device may include a first inorganic insulating layer disposed between the first semiconductor layer and the first gate electrode, a second inorganic insulating layer disposed between the first gate electrode and the capacitor electrode, a third inorganic insulating layer disposed on the capacitor electrode, a fourth inorganic insulating layer disposed between the second semiconductor layer and the second gate electrode, and a third inorganic insulating layer disposed on the third inorganic insulating layer. A fifth inorganic insulating layer disposed on the second gate electrode; a first-1 connection electrode disposed over the fifth inorganic insulating layer and electrically connected to the first semiconductor layer through a first-1 contact hole passing through the first to fifth inorganic insulating layers; and a (1-1)-th bridge contact layer on an inner surface of the (1-1)-th contact hole and a portion of the first semiconductor layer corresponding to the (1-1)-th contact hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0132463 filed in the Korean Intellectual Property Office on October 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device, and more particularly, to a display device having a reduced possibility of occurrence of defects during a manufacturing process and a method of manufacturing the display device. Background Art

[0004] The display device includes a display element and a pixel circuit. The pixel circuit is electrically connected to the display element. The pixel circuit includes at least one thin film transistor. The thin film transistor includes a semiconductor layer, a gate electrode, a source electrode and a drain electrode. The source electrode and / or the drain electrode are arranged above the semiconductor layer and are electrically connected to the semiconductor layer through a contact hole.

[0005] However, defects may occur during the manufacture of the display device. For example, in a display device according to the related art, the contact hole may have a long shape in the thickness direction, and the source electrode and / or the drain electrode may be disconnected inside the contact hole. Therefore, the source electrode and / or the drain electrode are not electrically connected to the semiconductor layer. Summary of the invention

[0006] One or more embodiments include a display device having a reduced possibility of occurrence of defects during a manufacturing process and a method of manufacturing the display device. However, such technical purpose is only an example, and the embodiments of the present disclosure are not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to an embodiment of the present disclosure, a display device includes a substrate and a first semiconductor layer disposed on the substrate. A first gate electrode is disposed above the first semiconductor layer. A first inorganic insulating layer is disposed between the first semiconductor layer and the first gate electrode. A capacitor electrode is disposed above the first gate electrode to overlap with the first gate electrode. A second inorganic insulating layer is disposed between the first gate electrode and the capacitor electrode. A third inorganic insulating layer is disposed on the capacitor electrode. The second semiconductor layer is disposed on the third inorganic insulating layer. The second gate electrode is disposed above the second semiconductor layer. A fourth inorganic insulating layer is disposed between the second semiconductor layer and the second gate electrode. A fifth inorganic insulating layer is disposed on the second gate electrode. A 1-1 connecting electrode is disposed above the fifth inorganic insulating layer. The 1-1 connecting electrode is electrically connected to the first semiconductor layer through a 1-1 contact hole that passes through the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer, and the fifth inorganic insulating layer. The 1-1 bridging contact layer covers a portion of the fifth inorganic insulating layer, an inner surface of the 1-1 contact hole, and a portion of the first semiconductor layer corresponding to the 1-1 contact hole.

[0009] In an embodiment, the 1-1 th bridge contact layer may directly contact a portion of the first semiconductor layer corresponding to the 1-1 th contact hole.

[0010] In an embodiment, the 1-1th connection electrode may directly contact the 1-1th bridge contact layer.

[0011] In an embodiment, the 1-1 th bridge contact layer conformally covers the 1-1 th connection electrode.

[0012] In an embodiment, the 1-1 th bridge contact layer may have a shape corresponding to a lower surface of the 1-1 th connection electrode.

[0013] In an implementation, the first semiconductor layer may include a silicon semiconductor.

[0014] In an embodiment, the second semiconductor layer may include an oxide semiconductor.

[0015] In an implementation, the 1-1 th bridge contact layer may include amorphous silicon doped with N-type impurities or P-type impurities.

[0016] In an embodiment, the 1-1 th bridge contact layer may include tungsten or titanium nitride.

[0017] In an embodiment, the display device may further include a 2-1st connecting electrode disposed above the fifth inorganic insulating layer. The 2-1st connecting electrode is electrically connected to the second semiconductor layer through a 2-1st contact hole passing through the fourth inorganic insulating layer and the fifth inorganic insulating layer. The 2-1st bridging contact layer covers a portion of the fifth inorganic insulating layer. The 2-1st bridging contact layer is spaced apart from the second semiconductor layer.

[0018] In an embodiment, the 2-1 th connection electrode may directly contact the second semiconductor layer.

[0019] In an embodiment, the 2-1st bridge contact layer may not directly contact an inner surface of the 2-1st contact hole and a portion of the second semiconductor layer corresponding to the 2-1st contact hole.

[0020] In an embodiment, the 2-1th bridging contact layer may include the same material as that of the 1-1th bridging contact layer.

[0021] According to an embodiment of the present disclosure, a method for manufacturing a display device includes providing a substrate, forming a first inorganic insulating layer, a second inorganic insulating layer, a third inorganic insulating layer, a fourth inorganic insulating layer and a fifth inorganic insulating layer over the substrate, forming a 1-1 contact hole passing through the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer and the fifth inorganic insulating layer, forming a first preliminary bridging contact layer on the fifth inorganic insulating layer, forming a second preliminary bridging contact layer by forming a 2-1 contact hole passing through the fourth inorganic insulating layer and the fifth inorganic insulating layer and removing a portion of the first preliminary bridging contact layer corresponding to the 2-1 contact hole, forming a preliminary connecting electrode layer on the second preliminary bridging contact layer, and forming a 1-1 connecting electrode, a 2-1 connecting electrode, a 1-1 bridging contact layer and a 2-1 bridging contact layer by patterning the preliminary connecting electrode layer and the second preliminary bridging contact layer.

[0022] In an implementation, forming the first preliminary bridging contact layer may include forming the first preliminary bridging contact layer using a chemical vapor deposition method.

[0023] In an implementation, the first preliminary bridging contact layer may include amorphous silicon doped with N-type impurities or P-type impurities.

[0024] In an implementation, the first preliminary bridging contact layer may include tungsten or titanium nitride.

[0025] In an embodiment, forming the first preliminary bridging contact layer may include covering an inner surface of the 1-1th contact hole with the first preliminary bridging contact layer.

[0026] In an embodiment, forming a first inorganic insulating layer, a second inorganic insulating layer, a third inorganic insulating layer, a fourth inorganic insulating layer, and a fifth inorganic insulating layer over a substrate may include forming the first inorganic insulating layer to be disposed between the first semiconductor layer and the first gate electrode, forming the second inorganic insulating layer to be disposed between the first gate electrode and the capacitor electrode, forming the third inorganic insulating layer on the capacitor electrode, forming the fourth inorganic insulating layer to be disposed between the second semiconductor layer and the second gate electrode, and forming the fifth inorganic insulating layer on the second gate electrode.

[0027] In an embodiment, the 1-1th connection electrode may be electrically connected to the first semiconductor layer through the 1-1th contact hole, and the 2-1th connection electrode may be electrically connected to the second semiconductor layer through the 2-1th contact hole.

[0028] These and / or other aspects will become more apparent and more readily understood from the following detailed description of the embodiments, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 is an equivalent circuit diagram of a pixel of a display device according to an embodiment;

[0032] Figure 3 According to the implementation method Figure 1 The line I-I' intercepts Figure 1 A schematic cross-sectional view of a display device; and

[0033] Figures 4 to 9 The present invention is a method for manufacturing an Figure 3 Schematic cross-sectional views of some of the processes of a display device. DETAILED DESCRIPTION

[0034] The embodiments shown in the accompanying drawings will now be referred to in detail, in which the same reference numerals always refer to the same elements. In this respect, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Accordingly, the embodiments are described below only by reference to the figures to explain the various aspects of this description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0035] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in the written description. The effects and features of the present disclosure and methods for achieving them will become clear by referring to the embodiments described in detail below with reference to the drawings. However, the embodiments of the present disclosure are not limited to the embodiments described below and can be implemented in various forms.

[0036] Although such terms as "first" and "second" may be used to describe various components, such components should not be limited by the above terms. The above terms are used to distinguish one component from another component.

[0037] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] It should be understood that the terms “comprise”, “comprising”, “include” and / or “including” as used herein specify the presence of stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0039] In the present specification, "A and / or B" means A or B, or A and B. In the present specification, "at least one of A and B" means A or B, or A and B.

[0040] In this specification, when various elements (such as layers, regions, plates, and the like) are disposed “on” another element, these elements may be disposed “directly” on the other element, or intervening elements may be disposed therebetween. When various elements (such as layers, regions, plates, and the like) are disposed “directly” on another element, no intervening elements may be disposed therebetween.

[0041] It should be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, it may be "directly connected" to the other layer, region, or component, or it may be "indirectly connected" to the other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it should be understood that when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or component, it may be "directly electrically connected" to the other layer, region, or component, or it may be "indirectly electrically connected" to the other layer, region, or component with other layers, regions, or components interposed therebetween. When a layer, region, or component is referred to as being "directly connected" to another layer, region, or component, there may be no intervening elements.

[0042] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0043] In the case where a particular embodiment can be implemented in different ways, the specific process sequence can be performed in a different order than the described order. As an example, two consecutively described processes can be performed substantially simultaneously or in a reverse order.

[0044] In this specification, “in a plan view” means when an object portion is viewed from above. For example, in this specification, “in a plan view” means when viewed in a direction perpendicular to the substrate 100 .

[0045] In this specification, the “upper surface” means a surface in the +z direction, and the “lower surface” means a surface in the −z direction.

[0046] In this specification, "conductive property" means electrical conductivity, "conductive material" means a material having conductivity, and "for a conductive material or layer" means that the material or layer is conductive.

[0047] Hereinafter, the embodiments will be described with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements, and their repeated description may be omitted. For the convenience of explanation, the size of the elements in the accompanying drawings may be exaggerated or reduced. As an example, for the convenience of description, the size and thickness of each element shown in the accompanying drawings are arbitrarily represented, and therefore the present disclosure is not necessarily limited thereto.

[0048] Figure 1 1 is a schematic plan view of a display device 1 according to an embodiment. Figure 1 As shown in , the display device 1 may include a display area DA and a peripheral area PA. A plurality of pixels P are arranged in the display area DA. The peripheral area PA is located outside the display area DA (e.g., in the x-axis and y-axis directions). For example, the peripheral area PA may completely surround the display area DA (e.g., in the x-axis and y-axis directions).

[0049] Each pixel P of the display device 1 is a region configured to emit light of a preset color. The display device 1 may be configured to display an image using light emitted from the pixel P. As an example, in an embodiment, each pixel P may be configured to emit red light, green light, or blue light. However, embodiments of the present disclosure are not necessarily limited thereto.

[0050] like Figure 1 As shown in , the display area DA may have a polygonal shape including a quadrilateral shape. As an example, in an embodiment, the display area DA may have a rectangular shape in which its horizontal length is less than its vertical length, a rectangular shape in which its horizontal length is greater than its vertical length, or a square shape. Alternatively, the display area DA may have various shapes, such as an elliptical shape or a circular shape.

[0051] The peripheral area PA may be a non-display area in which no pixels are arranged. A driver and the like configured to provide an electrical signal or power to the pixel P may be arranged in the peripheral area PA. In an embodiment, a plurality of pads may be arranged in the peripheral area PA. The plurality of pads are areas to which electronic components or printed circuit boards may be electrically connected. The plurality of pads may be spaced apart from each other in the peripheral area PA and may be electrically connected to a printed circuit board or an integrated circuit element.

[0052] Hereinafter, although an organic light-emitting display device is described as an example of the display device 1 according to an embodiment, the display device is not necessarily limited thereto. For example, in an embodiment, the display device 1 may be an inorganic light-emitting display device or a quantum dot light-emitting display device. As an example, the emission layer of the display element of the display device 1 may include an organic material or an inorganic material. In addition, the display device 1 may include an emission layer and a quantum dot layer disposed on a path of light emitted from the emission layer.

[0053] Figure 2 is an equivalent circuit diagram of a pixel P of the display device 1 according to the embodiment. Figure 2 As shown in , the pixel P may correspond to a display element, and the display element may be electrically connected to the pixel circuit PC. Figure 2 An organic light emitting diode OLED is shown as a display element. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0054] like Figure 2 As shown in, in an embodiment, the pixel circuit PC may include a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 and a storage capacitor Cst. The plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 and the storage capacitor Cst may be connected to a plurality of signal lines (e.g., SL1, SL2, SLp, SLn, EL and DL), a first initialization voltage line VL1, a second initialization voltage line VL2 and a driving voltage line PL. At least one of these lines, for example, the driving voltage line PL may be shared by a plurality of adjacent pixels P.

[0055] In an embodiment, the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6 and a second initialization transistor T7 (hereinafter, for the convenience of explanation, the thin film transistor T1 and the driving transistor T1, the thin film transistor T2 and the switching transistor T2, the thin film transistor T3 and the compensation transistor T3, the thin film transistor T4 and the first initialization transistor T4, the thin film transistor T5 and the operation control transistor T5, the thin film transistor T6 and the emission control transistor T6, the thin film transistor T7 and the second initialization transistor T7, respectively indicate the same features and are not particularly distinguished in the description).

[0056] The organic light emitting diode OLED may include a first electrode (e.g., a pixel electrode) and a second electrode (e.g., an opposing electrode). The first electrode of the organic light emitting diode OLED may be connected to the driving transistor T1 through the emission control transistor T6 to receive a driving current, and the second electrode may receive a common voltage ELVSS. The organic light emitting diode OLED may be configured to generate light of a brightness corresponding to the driving current.

[0057] In an embodiment, some of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be N-channel metal oxide semiconductor (NMOS) field effect transistors (N-channel MOSFETs), and the remaining portion of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be P-channel metal oxide semiconductor (PMOS) field effect transistors (P-channel MOSFETs). As an example, in an embodiment, among the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, the compensation transistor T3 and the first initialization transistor T4 may be N-channel MOSFETs (NMOS), and the remaining portion of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be P-channel MOSFETs (PMOS). Alternatively, among the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, the compensation transistor T3, the first initialization transistor T4 and the second initialization transistor T7 may be N-channel MOSFET (NMOS), and the remaining portion of the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be P-channel MOSFET (PMOS). Alternatively, all of the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be NMOS or PMOS. In an embodiment, the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 may each include amorphous silicon or polycrystalline silicon. In some embodiments, the thin film transistor as NMOS may include an oxide semiconductor. Hereinafter, for the convenience of description, an embodiment is described in which the compensation transistor T3 and the first initialization transistor T4 are NMOS including an oxide semiconductor, and the remaining portion of the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7 is PMOS.

[0058] In an embodiment, the plurality of signal lines may include a first scan line SL1, a second scan line SL2, a previous scan line SLp, a next scan line SLn, an emission control line EL, and a data line DL. The first scan line SL1 is configured to transmit a first scan signal Sn, the second scan line SL2 is configured to transmit a second scan signal Sn', the previous scan line SLp is configured to transmit a previous scan signal Sn-1 to a first initialization transistor T4, the next scan line SLn is configured to transmit a next scan signal Sn+1 to a second initialization transistor T7, the emission control line EL is configured to transmit an emission control signal En to an operation control transistor T5 and an emission control transistor T6, and the data line DL crosses the first scan line SL1 and is configured to transmit a data signal Dm.

[0059] The driving voltage line PL may be configured to transmit the driving voltage ELVDD to the driving transistor T1, the first initialization voltage line VL1 may be configured to transmit the first initialization voltage Vint1 to initialize the driving transistor T1, and the second initialization voltage line VL2 may be configured to transmit the second initialization voltage Vint2 to initialize the first electrode of the organic light emitting diode OLED.

[0060] The driving gate electrode of the driving transistor T1 may be connected to the storage capacitor Cst through the second node N2. One of the source region and the drain region of the driving transistor T1 may be connected to the driving voltage line PL through the operation control transistor T5 via the first node N1. The other of the source region and the drain region of the driving transistor T1 may be connected to the first electrode (e.g., pixel electrode) of the organic light emitting diode OLED through the emission control transistor T6 via the third node N3. The driving transistor T1 may be configured to receive the data signal Dm and supply the driving current to the organic light emitting diode OLED according to the switching operation of the switching transistor T2. For example, the driving transistor T1 may be configured to control the amount of current flowing from the first node N1 to the organic light emitting diode OLED in response to a voltage applied to the second node N2 and changed by the data signal Dm. The first node N1 is electrically connected to the driving voltage line PL.

[0061] The switching gate electrode of the switching transistor T2 may be connected to a first scan line SL1 configured to transmit a first scan signal Sn. One of the source region and the drain region of the switching transistor T2 may be connected to the data line DL, and the other of the source region and the drain region of the switching transistor T2 may be connected to the driving transistor T1 through the first node N1, and connected to the driving voltage line PL through the operation control transistor T5. The switching transistor T2 may be configured to transmit the data signal Dm from the data line DL to the first node N1 in response to a voltage applied to the first scan line SL1. For example, the switching transistor T2 may perform a switching operation of being turned on according to the first scan signal Sn transmitted through the first scan line SL1 and transmitting the data signal Dm to the driving transistor T1 through the first node N1. The data signal Dm is transmitted through the data line DL.

[0062] The compensation gate electrode of the compensation transistor T3 is connected to the second scan line SL2. One of the source region and the drain region of the compensation transistor T3 may be connected to the first electrode of the organic light emitting diode OLED through the emission control transistor T6 via the third node N3. The other of the source region and the drain region of the compensation transistor T3 may be connected to the first capacitor electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 through the second node N2. The compensation transistor T3 may diode-connect the driving transistor T1 by being turned on according to the second scan signal Sn' received through the second scan line SL2.

[0063] The first initialization gate electrode of the first initialization transistor T4 may be connected to the previous scan line SLp. One of the source region and the drain region of the first initialization transistor T4 may be connected to the first initialization voltage line VL1. The other of the source region and the drain region of the first initialization transistor T4 may be connected to the first capacitor electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 through the second node N2. The first initialization transistor T4 may be configured to apply the first initialization voltage Vint1 from the first initialization voltage line VL1 to the second node N2 according to the voltage applied to the previous scan line SLp. For example, the first initialization transistor T4 may be turned on according to the previous scan signal Sn-1 received through the previous scan line SLp, and may perform an initialization operation of initializing the voltage of the driving gate electrode of the driving transistor T1 by transmitting the first initialization voltage Vint1 to the driving gate electrode of the driving transistor T1.

[0064] The operation control gate electrode of the operation control transistor T5 may be connected to the emission control line EL. One of the source region and the drain region of the operation control transistor T5 may be connected to the driving voltage line PL. The other of the source region and the drain region of the operation control transistor T5 may be connected to the driving transistor T1 and the switching transistor T2 through the first node N1.

[0065] The emission control gate electrode of the emission control transistor T6 may be connected to the emission control line EL. One of the source region and the drain region of the emission control transistor T6 may be connected to the driving transistor T1 and the compensation transistor T3 through the third node N3. The other of the source region and the drain region of the emission control transistor T6 may be electrically connected to a first electrode (e.g., a pixel electrode) of the organic light emitting diode OLED.

[0066] In an embodiment, the operation control transistor T5 and the emission control transistor T6 may be synchronously turned on according to the emission control signal En transmitted through the emission control line EL. When the operation control transistor T5 and the emission control transistor T6 are turned on (e.g., synchronously turned on), the driving voltage ELVDD is transmitted to the organic light emitting diode OLED, and the driving current flows through the organic light emitting diode OLED.

[0067] The second initialization gate electrode of the second initialization transistor T7 may be connected to the next scan line SLn. One of the source region and the drain region of the second initialization transistor T7 may be connected to the first electrode (e.g., the pixel electrode) of the organic light emitting diode OLED. The other of the source region and the drain region of the second initialization transistor T7 may be electrically connected to the second initialization voltage line VL2 to receive the second initialization voltage Vint2. The second initialization transistor T7 is turned on according to the next scan signal Sn+1 transmitted through the next scan line SLn, and initializes the first electrode (e.g., the pixel electrode) of the organic light emitting diode OLED. In an embodiment, the next scan line SLn may be the same as the first scan line SL1. In the present embodiment, the relevant scan lines may be configured to transmit the same electrical signal with a time difference, and thus may be used as the first scan line SL1 and the next scan line SLn. For example, in an embodiment, the next scan line SLn may be a pixel (which is the same as the first scan line SL1). Figure 2 The pixel P shown in FIG. 1 is adjacent to the pixel P shown in FIG. 1 and is electrically connected to the data line DL.

[0068] like Figure 2 As shown in , the second initialization transistor T7 may be connected to the next scan line SLn. However, embodiments of the present disclosure are not necessarily limited thereto, and in some embodiments, the second initialization transistor T7 may be connected to the emission control line EL and driven according to the emission control signal En.

[0069] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving transistor T1 through the second node N2, and the second capacitor electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. In an embodiment, the storage capacitor Cst may be configured to store charges corresponding to a voltage difference between a voltage of the driving gate electrode of the driving transistor T1 and the driving voltage ELVDD.

[0070] A detailed operation of each pixel P according to the embodiment is described below.

[0071] In an embodiment, when a previous scan signal Sn-1 is supplied through the previous scan line SLp during the initialization period, the first initialization transistor T4 is turned on according to the previous scan signal Sn-1, and the driving transistor T1 is initialized by the first initialization voltage Vint1 supplied from the first initialization voltage line VL1.

[0072] In an embodiment, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2 respectively during the data programming period, the switching transistor T2 and the compensation transistor T3 are turned on according to the first scan signal Sn and the second scan signal Sn', respectively. In the present embodiment, the driving transistor T1 is diode-connected and forward biased by the turned-on compensation transistor T3. In an embodiment, the compensation voltage Dm+Vth (Vth has a (-) value) is then applied to the driving gate electrode of the driving transistor T1. The compensation voltage Dm+Vth is a voltage obtained by subtracting the threshold voltage Vth of the driving transistor T1 from the data signal Dm supplied by the data line DL. The driving voltage ELVDD and the compensation voltage Dm+Vth are respectively applied to two opposite ends of the storage capacitor Cst. The charge corresponding to the difference between the voltages at the opposite ends is stored in the storage capacitor Cst.

[0073] During the emission period, the operation control transistor T5 and the emission control transistor T6 are turned on (e.g., turned on synchronously) according to the emission control signal En supplied from the emission control line EL. A driving current corresponding to the voltage difference between the voltage of the driving gate electrode of the driving transistor T1 and the driving voltage ELVDD occurs. The driving current is then supplied to the organic light emitting diode OLED through the emission control transistor T6.

[0074] As described above, some (eg, a first portion) of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may include an oxide semiconductor. As an example, in an embodiment, the compensation transistor T3 and the first initialization transistor T4 may include an oxide semiconductor.

[0075] Since polysilicon has high reliability, it is possible to accurately control the flow of desired current. Accordingly, the driving transistor T1 that directly affects the brightness of the display device can be configured to include a semiconductor layer including polysilicon with high reliability, and therefore, a high-resolution display device can be realized by this configuration. Since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not large even when the driving time is long. For example, in oxide semiconductors, since the color change of the image according to the voltage drop is relatively small even when the display device is driven at a low frequency, the display device can be driven at a low frequency. Accordingly, by allowing the compensation transistor T3 and the first initialization transistor T4 to include an oxide semiconductor, a display device in which the occurrence of leakage current is prevented and at the same time with reduced power consumption can be realized.

[0076] Since the oxide semiconductor is sensitive to light, a change in the amount of current may occur due to external light. Accordingly, a metal layer may be provided under the oxide semiconductor to absorb or reflect external light. Figure 2As shown in , the gate electrodes of the compensation transistor T3 and the first initialization transistor T4 may be disposed on and below the oxide semiconductor layer, respectively. For example, when viewed in the z-axis direction, the metal layer disposed below the oxide semiconductor may overlap the oxide semiconductor.

[0077] Figure 3 According to the implementation method Figure 1 The line I-I' intercepts Figure 1 Schematic cross-sectional view of a display device 1.

[0078] like Figure 3 As shown in , the display device 1 includes a substrate 100. In an embodiment, the substrate 100 may include glass, metal, or a polymer resin. The substrate 100 may be flexible or bendable. In an embodiment in which the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. However, embodiments of the present disclosure are not necessarily limited thereto. In an embodiment, the substrate 100 may have a multilayer structure including two layers each including a polymer resin and an inorganic material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y However, the embodiments of the present disclosure are not necessarily limited thereto.

[0079] A display element DPE and a pixel circuit PC may be disposed on the substrate 100. The pixel circuit PC is electrically connected to the display element DPE. In an embodiment, the pixel circuit PC may include at least one silicon thin film transistor S-TFT, at least one oxide thin film transistor O-TFT, and a storage capacitor Cst. Figure 3 2 shows that an organic light emitting diode as a display element DPE is positioned over the substrate 100. When the display element DPE is electrically connected to the pixel circuit PC, the pixel electrode 210 of the display element DPE may be electrically connected to the thin film transistor of the pixel circuit PC.

[0080] As described above, although the pixel circuit PC may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7, for the convenience of description, Figure 3Only some of the driving transistor T1, the switching transistor T2, the compensating transistor T3, the first initialization transistor T4, the operation control transistor T5, the emission control transistor T6 and the second initialization transistor T7 are shown. As an example, in an embodiment, Figure 3 The silicon thin film transistor S-TFT shown in FIG. 1 may be a driving transistor T1, and Figure 3 The oxide thin film transistor O-TFT shown in FIG. 4 may be the compensation transistor T3 .

[0081] The silicon thin film transistor S-TFT may be disposed on the substrate 100. Figure 3 As shown in , the silicon thin film transistor S-TFT may include a first semiconductor layer A1, a first gate electrode G1, a 1-1 connection electrode S1, and a 1-2 connection electrode D1. As an example, in an embodiment, the 1-1 connection electrode S1 may be a source electrode, and the 1-2 connection electrode D1 may be a drain electrode. Alternatively, according to the polarity of the silicon thin film transistor S-TFT, the 1-1 connection electrode S1 may be a drain electrode, and the 1-2 connection electrode D1 may be a source electrode.

[0082] In an embodiment, the first semiconductor layer A1 may be disposed on the substrate 100 (e.g., directly disposed thereon in the z-axis direction). The first semiconductor layer A1 may include a silicon semiconductor. In an embodiment, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. As an example, the first semiconductor layer A1 may include low temperature polycrystalline silicon (LTPS). The first semiconductor layer A1 may include a first channel region, a first source region, and a first drain region. The first source region and the first drain region may be disposed on opposite sides of the first channel region (e.g., in the x-axis direction), respectively. The first source region and the first drain region may be doped with impurities. The impurities may include N-type impurities or P-type impurities. In an embodiment, the first channel region may overlap with the first gate electrode G1 (e.g., in the z-axis direction), and may not be doped with impurities or may include a very small amount of impurities. The first source region may be electrically connected to the 1-1 connection electrode S1, and the first drain region may be electrically connected to the 1-2 connection electrode D1.

[0083] In an embodiment, the first inorganic insulating layer 111 may be disposed on the first semiconductor layer A1 (e.g., directly thereon in the z-axis direction). The first inorganic insulating layer 111 may include an inorganic material. As an example, in an embodiment, the first inorganic insulating layer 111 may include an inorganic insulating material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y )), and may have a single-layer or multi-layer structure including the above materials.

[0084] The first gate electrode G1 may be disposed on the first inorganic insulating layer 111. For example, the first gate electrode G1 may be disposed above the first semiconductor layer A1 (for example, in the z-axis direction), and the first inorganic insulating layer 111 may be disposed between the first semiconductor layer A1 and the first gate electrode G1 (for example, in the z-axis direction). The first gate electrode G1 may at least partially overlap the first semiconductor layer A1 (for example, in the z-axis direction). As an example, the first gate electrode G1 may overlap the first channel region of the first semiconductor layer A1 (for example, in the z-axis direction). In an embodiment, the first gate electrode G1 of the silicon thin film transistor S-TFT may include a low-resistance conductive material (such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti)), and have a single-layer structure or a multilayer structure including the above materials. As an example, the first gate electrode G1 may include a single Mo layer or a multilayer structure of Mo / Al / Mo. However, embodiments of the present disclosure are not necessarily limited thereto.

[0085] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. In an embodiment, the storage capacitor Cst may be formed to overlap with the silicon thin film transistor S-TFT (for example, in the z-axis direction). In the present embodiment, the first gate electrode G1 may not only be used as the gate electrode of the silicon thin film transistor S-TFT, but may also be used synchronously as the first capacitor electrode CE1. For example, in an embodiment, the first gate electrode G1 may be provided integrally with the first capacitor electrode CE1. In an embodiment, the first capacitor electrode CE1 may be formed as an island-shaped electrode. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the storage capacitor Cst may be provided separately and may not overlap with the silicon thin film transistor S-TFT (for example, in the z-axis direction).

[0086] The second inorganic insulating layer 112 may be disposed on the first gate electrode G1 (eg, directly thereon). The second inorganic insulating layer 112 may include an inorganic material. As an example, in an embodiment, the second inorganic insulating layer 112 may include an inorganic insulating material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y )), and may have a single-layer or multi-layer structure including the above materials. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0087] The second capacitor electrode CE2 may be disposed on the second inorganic insulating layer 112 (e.g., directly thereon in the z-axis direction). For example, the second capacitor electrode CE2 may be disposed on the second inorganic insulating layer 112 to overlap with the first capacitor electrode CE1 (e.g., in the z-axis direction). For example, the second capacitor electrode CE2 may be disposed above the first capacitor electrode CE1 to overlap with the first capacitor electrode CE1 (e.g., in the z-axis direction), and the second inorganic insulating layer 112 may be disposed between the first capacitor electrode CE1 and the second capacitor electrode CE2 (e.g., in the z-axis direction). The second inorganic insulating layer 112 may serve as a dielectric layer of the storage capacitor Cst.

[0088] The second capacitor electrode CE2 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like. In an embodiment, the second capacitor electrode CE2 may include, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) At least one, and includes a single layer or multilayer structure containing the above materials. However, embodiments of the present disclosure are not necessarily limited thereto.

[0089] The third inorganic insulating layer 113 may be disposed on the second capacitor electrode CE2 (eg, directly thereon in the z-axis direction). The third inorganic insulating layer 113 may include an inorganic material. As an example, in an embodiment, the third inorganic insulating layer 113 may include an inorganic insulating material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y )), and may have a single-layer or multi-layer structure including the above materials. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0090] The oxide thin film transistor O-TFT may be disposed on the third inorganic insulating layer 113 (eg, directly thereon in the z-axis direction). Figure 3 As shown in , in an embodiment, the oxide thin film transistor O-TFT may include a second semiconductor layer A2, a second gate electrode G2, a 2-1st connection electrode S2, and a 2-2nd connection electrode D2. As an example, in an embodiment, the 2-1st connection electrode S2 may be a source electrode, and the 2-2nd connection electrode D2 may be a drain electrode. Alternatively, depending on the polarity of the oxide thin film transistor O-TFT, the 2-1st connection electrode S2 may be a drain electrode, and the 2-2nd connection electrode D2 may be a source electrode.

[0091] In an embodiment, the second semiconductor layer A2 may be disposed on the third inorganic insulating layer 113 (e.g., directly disposed thereon in the z-axis direction). The second semiconductor layer A2 may include a material different from the first semiconductor layer A1. As an example, the second semiconductor layer A2 may include an oxide semiconductor. In an embodiment, the oxide semiconductor is a Zn oxide-based material and may include Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. In an embodiment, the oxide semiconductor may include an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor containing metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO. However, embodiments of the present disclosure are not necessarily limited thereto. In an embodiment, the second semiconductor layer A2 may include a second channel region, a second source region, and a second drain region. The second source region and the second drain region are disposed on opposite sides of the second channel region (e.g., in the x-axis direction). In an implementation, the second source region may be electrically connected to the 2-1th connection electrode S2, and the second drain region may be electrically connected to the 2-2nd connection electrode D2.

[0092] In an embodiment, the fourth inorganic insulating layer 114 may be disposed on the second semiconductor layer A2 (e.g., directly thereon in the z-axis direction). The fourth inorganic insulating layer 114 may include an inorganic material. As an example, in an embodiment, the fourth inorganic insulating layer 114 may include an inorganic insulating material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y )), and may have a single-layer or multi-layer structure including the above materials.

[0093] The second gate electrode G2 may be disposed on the fourth inorganic insulating layer 114 (e.g., directly disposed thereon in the z-axis direction). For example, the second gate electrode G2 may be disposed above the second semiconductor layer A2, and the fourth inorganic insulating layer 114 may be disposed between the second semiconductor layer A2 and the second gate electrode G2 (e.g., in the z-axis direction). The second gate electrode G2 may at least partially overlap the second semiconductor layer A2 (e.g., in the z-axis direction). As an example, the second gate electrode G2 may overlap the second channel region of the second semiconductor layer A2 (e.g., in the z-axis direction). In an embodiment, the second gate electrode G2 of the oxide thin film transistor O-TFT may include a low-resistance conductive material (such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti)), and have a single-layer structure or a multilayer structure including the above materials. As an example, the second gate electrode G2 may include a single Mo layer or a multilayer structure of Mo / Al / Mo. However, embodiments of the present disclosure are not necessarily limited thereto.

[0094] In an embodiment, the fifth inorganic insulating layer 115 may be disposed on the second gate electrode G2 (e.g., directly thereon). The fifth inorganic insulating layer 115 may cover the oxide thin film transistor O-TFT. The fifth inorganic insulating layer 115 may include an inorganic material. As an example, in an embodiment, the fifth inorganic insulating layer 115 may include an inorganic insulating material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y )), and may have a single-layer or multi-layer structure including the above materials. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0095] The 1-1 connection electrode S1, the 1-2 connection electrode D1, the 2-1 connection electrode S2, and the 2-2 connection electrode D2 may be disposed above the fifth inorganic insulating layer 115 (e.g., directly above it). Each of the 1-1 connection electrode S1, the 1-2 connection electrode D1, the 2-1 connection electrode S2, and the 2-2 connection electrode D2 may include a conductive material. As an example, in an embodiment, each of the 1-1 connection electrode S1, the 1-2 connection electrode D1, the 2-1 connection electrode S2, and the 2-2 connection electrode D2 may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer or multilayer structure including the above materials. As an example, each of the 1-1 connection electrode S1, the 1-2 connection electrode D1, the 2-1 connection electrode S2, and the 2-2 connection electrode D2 may have a multilayer structure of Ti / Al / Ti. However, embodiments of the present disclosure are not necessarily limited thereto.

[0096] The connection electrode may be electrically connected to the semiconductor layer through a contact hole formed in the inorganic insulating layer. For example, in an embodiment, a 1-1 contact hole CNTS1 and a 1-2 contact hole CNTD1 may be formed in the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115. For example, the 1-1 contact hole CNTS1 may pass through the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115 (for example, in the z-axis direction). The 1-1 connection electrode S1 may be electrically connected to the first semiconductor layer A1 through the 1-1 contact hole CNTS1. The 1-2 contact hole CNTD1 may pass through the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115 (for example, in the z-axis direction). The 1-2 connection electrode D1 may be electrically connected to the first semiconductor layer A1 through the 1-2 contact hole CNTD1. For example, the 1-1 connection electrode S1 may be electrically connected to the source region of the first semiconductor layer A1 through the 1-1 contact hole CNTS1, and the 1-2 connection electrode D1 may be electrically connected to the drain region of the first semiconductor layer A1 through the 1-2 contact hole CNTD1.

[0097] In addition, a 2-1 contact hole CNTS2 and a 2-2 contact hole CNTD2 may be formed in the fourth inorganic insulating layer 114 and the fifth inorganic insulating layer 115. For example, the 2-1 contact hole CNTS2 may pass through the fourth inorganic insulating layer 114 and the fifth inorganic insulating layer 115 (for example, in the z-axis direction). The 2-1 connection electrode S2 may be electrically connected to the second semiconductor layer A2 through the 2-1 contact hole CNTS2. The 2-2 contact hole CNTD2 may pass through the fourth inorganic insulating layer 114 and the fifth inorganic insulating layer 115 (for example, in the z-axis direction). The 2-2 connection electrode D2 may be electrically connected to the second semiconductor layer A2 through the 2-2 contact hole CNTD2. For example, the 2-1 connection electrode S2 may be electrically connected to the source region of the second semiconductor layer A2 through the 2-1 contact hole CNTS2, and the 2-2 connection electrode D2 may be electrically connected to the drain region of the second semiconductor layer A2 through the 2-2 contact hole CNTD2.

[0098] However, the embodiments of the present disclosure are not necessarily limited thereto. As an example, the silicon thin film transistor S-TFT may include only one of the 1-1 connection electrode S1 and the 1-2 connection electrode D1, or may not include both. As an example, in an embodiment, the silicon thin film transistor S-TFT may not include the 1-2 connection electrode D1, another silicon thin film transistor S-TFT connected to this silicon thin film transistor S-TFT may not include the 1-1 connection electrode S1, and the first semiconductor layers A1 of these two silicon thin film transistors S-TFT may be connected to each other. This connection structure may have the same effect that one of the silicon thin film transistors S-TFT has the 1-2 connection electrode D1, the other silicon thin film transistor S-TFT has the 1-1 connection electrode S1, and the 1-2 connection electrode D1 of the one silicon thin film transistor S-TFT is connected to the 1-1 connection electrode S1 of the other silicon thin film transistor S-TFT.

[0099] Similarly, in an embodiment, the oxide thin film transistor O-TFT may include only one of the 2-1 connection electrode S2 and the 2-2 connection electrode D2, or may not include both. As an example, the oxide thin film transistor O-TFT may not include the 2-2 connection electrode D2, another oxide thin film transistor O-TFT connected to this oxide thin film transistor O-TFT may not include the 2-1 connection electrode S2, and the second semiconductor layers A2 of the two oxide thin film transistors O-TFT may be connected to each other. This connection structure may have the same effect that one oxide thin film transistor O-TFT has the 2-2 connection electrode D2, the other oxide thin film transistor O-TFT has the 2-1 connection electrode S2, and the 2-2 connection electrode D2 of the one oxide thin film transistor O-TFT is connected to the 2-1 connection electrode S2 of the other oxide thin film transistor O-TFT.

[0100] A bridge contact layer may be disposed between the fifth inorganic insulating layer 115, the 1-1th connection electrode S1, the 1-2th connection electrode D1, the 2-1th connection electrode S2, and the 2-2nd connection electrode D2. The bridge contact layer will be described in detail below.

[0101] In an embodiment, the silicon thin film transistor S-TFT and the oxide thin film transistor O-TFT may be covered by (e.g., directly covered by) the organic insulating layer 116. As an example, the organic insulating layer 116 may cover (e.g., directly cover) the 1-1st connection electrode S1, the 1-2nd connection electrode D1, the 2-1st connection electrode S2, and the 2-2nd connection electrode D2. For example, the organic insulating layer 116 may be disposed on the 1-1st connection electrode S1, the 1-2nd connection electrode D1, the 2-1st connection electrode S2, and the 2-2nd connection electrode D2. The display element DPE may be disposed on the organic insulating layer 116.

[0102] The organic insulating layer 116 is a planarized insulating layer and may include a substantially flat upper surface. Accordingly, the organic insulating layer 116 may provide a flat upper surface so that the pixel electrode 210 of the display element DPE is formed to be flat. The organic insulating layer 116 may include an organic insulating material. As an example, in an embodiment, the organic insulating layer 116 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative with a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer and a blend thereof. However, embodiments of the present disclosure are not necessarily limited thereto. The organic insulating layer 116 may include a single layer or multilayer structure containing the above materials.

[0103] As described above, the display element DPE may be disposed on the organic insulating layer 116 (e.g., directly thereon in the z-axis direction). In an embodiment, the display element DPE may be an organic light emitting diode including a pixel electrode 210, an opposing electrode 230, and an intermediate layer 220. The intermediate layer 220 is disposed between the pixel electrode 210 and the opposing electrode 230 (e.g., in the z-axis direction) and includes an emission layer. As described above, the display element DPE may be electrically connected to the pixel circuit PC. When the display element DPE is electrically connected to the pixel circuit PC, the pixel electrode 210 of the display element DPE is electrically connected to the pixel circuit PC. For example, in an embodiment, the pixel electrode 210 may be electrically connected to the silicon thin film transistor S-TFT by directly contacting one of the 1-1 connection electrode S1 and the 1-2 connection electrode D1 through a contact hole formed in the organic insulating layer 116. Although in Figure 3 2 shows that the pixel electrode 210 contacts the 1-1 connection electrode S1 through a contact hole formed in the organic insulating layer 116, but the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the pixel electrode 210 may directly contact the 1-2 connection electrode D1 through a contact hole formed in the organic insulating layer 116.

[0104] In an implementation, the pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the pixel electrode 210 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an embodiment, the pixel electrode 210 may also include a layer above / below the reflective layer, the layer including ITO, IZO, ZnO or In 2 O 3 As an example, the pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO. However, embodiments of the present disclosure are not necessarily limited thereto.

[0105] The pixel defining layer 120 may be disposed on the organic insulating layer 116 (e.g., directly thereon in the z-axis direction). In an embodiment, the pixel defining layer 120 may cover the edge (e.g., the lateral edge) of the pixel electrode 210, and may expose the central portion of the pixel electrode 210. The pixel defining layer 120 may include a pixel opening 120OP, and the pixel opening 120OP may overlap with the pixel electrode 210 (e.g., in the z-axis direction) (such as the central portion of the pixel electrode 210). The pixel opening 120OP may define an emission area EA of light emitted from the display element DPE. The pixel defining layer 120 may include an organic insulating material and / or an inorganic insulating material. In an embodiment, the pixel defining layer 120 may include a light blocking material.

[0106] The intermediate layer 220 may be disposed on the pixel electrode 210 and the pixel defining layer 120 (e.g., in the z-axis direction). The intermediate layer 220 may include an emission layer 220b. In an embodiment, the emission layer 220b may include an organic material including a fluorescent or phosphor material configured to emit red light, green light, or blue light. The emission layer 220b may include a low molecular weight organic material or a polymer organic material. The first functional layer 220a and the second functional layer 220c may be selectively further arranged (e.g., in the z-axis direction) below the emission layer 220b and on the emission layer 220b. The first functional layer 220a includes a hole transport layer (HTL) and a hole injection layer (HIL). The second functional layer 220c includes an electron transport layer (ETL) and an electron injection layer (EIL). In an embodiment, the intermediate layer 220 may be formed by a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI) method, or a similar method. However, the intermediate layer 220 is not necessarily limited thereto, but may have various structures. The intermediate layer 220 may include a layer that is integrated throughout the plurality of pixel electrodes 210 (eg, commonly disposed), or include a layer that is patterned to correspond to each of the plurality of pixel electrodes 210 .

[0107] The counter electrode 230 may be disposed on the intermediate layer 220 (eg, in the z-axis direction). In an embodiment, the counter electrode 230 may be formed as a whole (eg, commonly disposed) throughout a plurality of organic light emitting diodes to correspond to a plurality of pixel electrodes 210. In an embodiment, the counter electrode 230 may include a layer including ITO, In 2 O 3 The light-transmitting conductive layer may be a light-transmitting conductive layer of IZO or IZO, and may include a semi-transmitting layer including a metal such as aluminum (Al) or silver (Ag). As an example, the opposing electrode 230 may be a semi-transmitting layer including magnesium (Mg) and silver (Ag). However, the embodiments of the present disclosure are not necessarily limited thereto.

[0108] Since the display element DPE may be easily damaged by external moisture, oxygen, or the like, the encapsulation layer 300 may protect the display element DPE by covering the display element DPE. Figure 3 As shown in , in an embodiment, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 .

[0109] In an implementation, the first inorganic encapsulating layer 310 may cover the opposite electrode 230 and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y In some embodiments, other layers including a capping layer may be disposed (eg, in the z-axis direction) between the first inorganic encapsulation layer 310 and the opposing electrode 230. Since the first inorganic encapsulation layer 310 is formed along the structure below it, the upper surface of the first inorganic encapsulation layer 310 may be as shown in FIG. Figure 3 310, and the upper surface of the organic encapsulation layer 320 may be substantially flat. In an embodiment, the organic encapsulation layer 320 may include at least one of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, embodiments of the present disclosure are not necessarily limited thereto. In an embodiment, the second inorganic encapsulation layer 330 may cover the organic encapsulation layer 320 and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y ). However, the embodiments of the present disclosure are not necessarily limited thereto.

[0110] Since the encapsulation layer 300 includes the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330, even when cracks occur inside the encapsulation layer 300, the cracks may not be connected through the above multilayer structure between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. Through this configuration, the formation of a path for external moisture or oxygen to penetrate the inside of the display panel may be prevented or reduced.

[0111] As described above, the 1-1st connection electrode S1, the 1-2nd connection electrode D1, the 2-1st connection electrode S2, and the 2-2nd connection electrode D2 may be disposed above (e.g., directly above) the fifth inorganic insulating layer 115. In an embodiment, a bridging contact layer may be disposed between the fifth inorganic insulating layer 115 and each of the 1-1st connection electrode S1, the 1-2nd connection electrode D1, the 2-1st connection electrode S2, and the 2-2nd connection electrode D2. For example, each of the 1-1st connection electrode S1, the 1-2nd connection electrode D1, the 2-1st connection electrode S2, and the 2-2nd connection electrode D2 may be disposed on (e.g., directly above) the bridging contact layer.

[0112] In an embodiment, the 1-1 connection electrode S1 may be disposed on (e.g., directly on) the 1-1 bridging contact layer BCLS1. The 1-1 bridging contact layer BCLS1 may cover a portion of the fifth inorganic insulating layer 115, the inner surface of the 1-1 contact hole CNTS1, and a portion of the first semiconductor layer A1 corresponding to (e.g., exposed by) the 1-1 contact hole CNTS1. For example, the 1-1 bridging contact layer BCLS1 may be disposed on (e.g., directly on) a portion of the fifth inorganic insulating layer 115, the inner surface of the 1-1 contact hole CNTS1, and a portion of the first semiconductor layer A1. The 1-1 bridging contact layer BCLS1 may cover a portion of the upper surface of the fifth inorganic insulating layer 115, the inner surface of the 1-1 contact hole CNTS1, and a portion of the upper surface of the first semiconductor layer A1 corresponding to (e.g., exposed by) the 1-1 contact hole CNTS1. Accordingly, the 1-1th bridge contact layer BCLS1 may be disposed between a portion of the 1-1th connection electrode S1 and a portion of the fifth inorganic insulation layer 115 .

[0113] In an embodiment, the inner surface of the 1-1 contact hole CNTS1 may be covered by the 1-1 bridge contact layer BCLS1, and a portion of the first semiconductor layer A1 corresponding to (e.g., exposed by) the 1-1 contact hole CNTS1 may also be covered by the 1-1 bridge contact layer BCLS1. A portion of the 1-1 connection electrode S1 may fill the 1-1 contact hole CNTS1. Accordingly, the 1-1 connection electrode S1 may be disposed on (e.g., directly on) the 1-1 bridge contact layer BCLS1.

[0114] As described above, the 1-1st connection electrode S1 may be connected to the first semiconductor layer A1 through the 1-1st contact hole CNTS1 formed in the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115. The 1-1st connection electrode S1 may be in surface contact with the 1-1st bridge contact layer BCLS1. For example, the 1-1st bridge contact layer BCLS1 disposed below the 1-1st connection electrode S1 may have a shape corresponding to the lower surface of the 1-1st connection electrode S1. The 1-1st bridge contact layer BCLS1 may conformally cover the side surface and the lower surface of the 1-1st connection electrode S1. For example, the 1-1st bridge contact layer BCLS1 may be in direct contact with the first semiconductor layer A1, and the 1-1st connection electrode S1 may be in direct contact with the 1-1st bridge contact layer BCLS1. Accordingly, the 1-1st connection electrode S1 may be electrically connected to the first semiconductor layer A1. The above description about the positional relationship between the 1-1st connection electrode S1 and the 1-1st bridge contact layer BCLS1 also applies to the positional relationship between the 1-2nd bridge contact layer BCLD1 and the 1-2nd contact hole CNTD1. Accordingly, regarding this point, for the sake of economy of description, repeated description is omitted.

[0115] In an embodiment, the 1-2nd connection electrode D1 may be disposed on (e.g., directly on) the 1-2nd bridging contact layer BCLD1. The 1-2nd bridging contact layer BCLD1 may cover a portion of the fifth inorganic insulating layer 115, the inner surface of the 1-2nd contact hole CNTD1, and a portion of the first semiconductor layer A1 corresponding to (e.g., exposed by) the 1-2nd contact hole CNTD1. For example, the inner surface of the 1-2nd contact hole CNTD1 may be covered by the 1-2nd bridging contact layer BCLD1, and a portion of the first semiconductor layer A1 corresponding to (e.g., exposed by) the 1-2nd contact hole CNTD1 may also be covered by the 1-2nd bridging contact layer BCLD1. A portion of the 1-2nd connection electrode D1 may fill the 1-2nd contact hole CNTD1. Accordingly, the 1-2nd connection electrode D1 may be disposed on (e.g., directly on) the 1-2nd bridging contact layer BCLD1. For example, the 1-2 th bridge contact layer BCLD1 may be in direct contact with the first semiconductor layer A1 , and the 1-2 th connection electrode D1 may be in direct contact with the 1-2 th bridge contact layer BCLD1 .

[0116] In an embodiment, the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may include amorphous silicon doped with impurities, and the impurities may include N-type impurities or P-type impurities. As an example, in an embodiment, the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may include P-type amorphous silicon doped with impurities such as boron (B), aluminum (Al), or indium (In). Alternatively, the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may include N-type amorphous silicon doped with impurities such as phosphorus (P), arsenic (As), or antimony (Sb). However, embodiments of the present disclosure are not necessarily limited thereto.

[0117] In an embodiment, the 1-1st bridge contact layer BCLS1 and the 1-2nd bridge contact layer BCLD1 may include a metal material. As an example, the 1-1st bridge contact layer BCLS1 and the 1-2nd bridge contact layer BCLD1 may include tungsten (W). In an embodiment, the 1-1st bridge contact layer BCLS1 and the 1-2nd bridge contact layer BCLD1 may include a conductive metal nitride. As an example, the 1-1st bridge contact layer BCLS1 and the 1-2nd bridge contact layer BCLD1 may include titanium nitride (TiN). Accordingly, the 1-1st bridge contact layer BCLS1 and the 1-2nd bridge contact layer BCLD1 may have conductivity.

[0118] As described below, in an embodiment, the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may be formed by a chemical vapor deposition (CVD) method. Accordingly, the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may have excellent step coverage. Accordingly, the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may cover the entire inner surface of the 1-1 contact hole CNTS1 and the entire inner surface of the 1-2 contact hole CNTD1, respectively. Each of the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may cover a portion of the upper surface of the first semiconductor layer A1. Accordingly, inside each of the 1-1 contact hole CNTS1 and the 1-2 contact hole CNTD1, each of the 1-1 bridging contact layer BCLS1 and the 1-2 bridging contact layer BCLD1 may be continuously connected.

[0119] Typically, a layer including a metal material is formed using a sputtering method. The sputtering method has a higher anisotropy than a chemical vapor deposition (CVD) method. Accordingly, in the case of filling a contact hole having a long shape in a thickness direction (e.g., +z direction or -z direction) with a layer including a metal material using a sputtering method, a portion of the inner surface of the contact hole may not be covered by the layer including the metal material. For example, the layer including the metal material may be disconnected inside the contact hole. For example, since the connecting electrode includes a metal material, a portion of the inner surface of the contact hole having a long shape in a thickness direction (e.g., +z direction or -z direction) may not be covered by the connecting electrode. Accordingly, the connecting electrode may be disconnected. Therefore, the connecting electrode may not be electrically connected to the semiconductor layer.

[0120] However, even in the present embodiment, the 1-1 contact hole CNTS1 and the 1-2 contact hole CNTD1 may have a long shape in the thickness direction (e.g., +z direction or -z direction). For example, the distance of the 1-1 contact hole CNTS1 in the thickness direction (e.g., +z direction or -z direction) may be greater than the width of the 1-1 contact hole CNTS1 when viewed in the xy plane. The distance of the 1-2 contact hole CNTD1 in the thickness direction (e.g., +z direction or -z direction) may be greater than the width of the 1-2 contact hole CNTD1 when viewed in the xy plane. The 1-1 bridge contact layer BCLS1 and the 1-2 bridge contact layer BCLD1, each having conductivity and excellent step coverage, may be respectively disposed below (e.g., directly below) the 1-1 connection electrode S1 and the 1-2 connection electrode D1. Accordingly, each of the 1-1 connection electrode S1 and the 1-2 connection electrode D1 may be electrically connected to the first semiconductor layer A1.

[0121] The 2-1st connection electrode S2 may be disposed on (e.g., directly on) the 2-1st bridging contact layer BCLS2. For example, the 2-1st connection electrode S2 may be disposed on the 2-1st bridging contact layer BCLS2. The 2-1st bridging contact layer BCLS2 may cover a portion of the fifth inorganic insulating layer 115. For example, the 2-1st bridging contact layer BCLS2 may be disposed on (e.g., directly on) a portion of the fifth inorganic insulating layer 115. Therefore, the 2-1st bridging contact layer BCLS2 may cover a portion of the upper surface of the fifth inorganic insulating layer 115. Accordingly, the 2-1st bridging contact layer BCLS2 may be disposed between a portion of the 2-1st connection electrode S2 and a portion of the fifth inorganic insulating layer 115.

[0122] However, the inner surface of the 2-1st contact hole CNTS2 may not be covered by the 2-1st bridge contact layer BCLS2, and the portion of the second semiconductor layer A2 corresponding to the 2-1st contact hole CNTS2 may not be covered by the 2-1st bridge contact layer BCLS2. A portion of the 2-1st connection electrode S2 may fill the 2-1st contact hole CNTS2. Accordingly, another portion of the 2-1st connection electrode S2 may not be disposed on the 2-1st bridge contact layer BCLS2.

[0123] As described above, the 2-1st connection electrode S2 may be connected to the second semiconductor layer A2 through the 2-1st contact hole CNTS2 formed in the fourth inorganic insulating layer 114 and the fifth inorganic insulating layer 115. For example, the 2-1st connection electrode S2 may be in direct contact with the second semiconductor layer A2. Accordingly, the 2-1st connection electrode S2 may be electrically connected to the second semiconductor layer A2. The 2-1st bridging contact layer BCLS2 may not be in direct contact with the second semiconductor layer A2. For example, the 2-1st bridging contact layer BCLS2 may be spaced apart from the second semiconductor layer A2 (e.g., in the z-axis direction). The above description of the positional relationship between the 2-1st connection electrode S2 and the 2-1st bridging contact layer BCLS2 also applies to the positional relationship between the 2-2nd bridging contact layer BCLD2 and the 2-2nd contact hole CNTD2. Accordingly, with regard to this point, for the sake of economy of description, repeated description is omitted.

[0124] In an embodiment, the 2-2nd connection electrode D2 may be disposed on (e.g., directly on) the 2-2nd bridging contact layer BCLD2. The 2-2nd bridging contact layer BCLD2 may cover a portion of the fifth inorganic insulating layer 115. The inner surface of the 2-2nd contact hole CNTD2 may not be covered by the 2-2nd bridging contact layer BCLD2, and the portion of the second semiconductor layer A2 corresponding to the 2-2nd contact hole CNTD2 may also not be covered by the 2-2nd bridging contact layer BCLD2. A portion of the 2-2nd connection electrode D2 may fill the 2-2nd contact hole CNTD2. Accordingly, another portion of the 2-2nd connection electrode D2 may not be disposed on the 2-2nd bridging contact layer BCLD2. The 2-2nd connection electrode D2 may be in direct contact with the second semiconductor layer A2.

[0125] In an embodiment, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include the same material as that of the 1-1st bridge contact layer BCLS1 and the 1-2nd bridge contact layer BCLD1. As an example, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include P-type amorphous silicon doped with impurities such as boron (B), aluminum (Al), or indium (In). Alternatively, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include N-type amorphous silicon doped with impurities such as phosphorus (P), arsenic (As), or antimony (Sb). Alternatively, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include a metal material. As an example, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include tungsten (W). Alternatively, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include a conductive metal nitride. As an example, the 2-1st bridge contact layer BCLS2 and the 2-2nd bridge contact layer BCLD2 may include titanium nitride (TiN). However, embodiments of the present disclosure are not necessarily limited thereto.

[0126] As described below, in an embodiment, when forming the 1-1 bridge contact layer BCLS1 and the 1-2 bridge contact layer BCLD1, the 2-1 bridge contact layer BCLS2 and the 2-2 bridge contact layer BCLD2 may be simultaneously formed using the same material. However, unlike the 1-1 bridge contact layer BCLS1 and the 1-2 bridge contact layer BCLD1, each of the 2-1 bridge contact layer BCLS2 and the 2-2 bridge contact layer BCLD2 is not in direct contact with the second semiconductor layer A2. Accordingly, in the impurity-doped amorphous silicon of the 2-1 bridge contact layer BCLS2 and the 2-2 bridge contact layer BCLD2, the performance degradation of the second semiconductor layer A2 due to the diffusion of impurities into the second semiconductor layer A2 can be prevented.

[0127] Although the display device 1 has been described so far, the embodiments of the present disclosure are not necessarily limited thereto. A method of manufacturing the display device 1 also falls within the scope of the present disclosure. Hereinafter, the method of manufacturing the display device 1 is described.

[0128] Figures 4 to 9 The present invention is a method for manufacturing an Figure 3 Schematic cross-sectional views of some of the processes of the display device 1. Specifically, Figures 4 to 9 Is manufacturing Figure 3A schematic cross-sectional view of the process of forming the 1-1st connecting electrode S1, the 1-2nd connecting electrode D1, the 2-1st connecting electrode S2, the 2-2nd connecting electrode D2, the 1-1st bridging contact layer BCLS1, the 1-2nd bridging contact layer BCLD1, the 2-1st bridging contact layer BCLS2 and the 2-2nd bridging contact layer BCLD2 of the display device 1. For the convenience of description, Figures 4 to 9 A method of manufacturing a display device based on a cross section of the display device 1 taken along line II' of the display device 1 is described. Figures 4 to 9 When describing the method for manufacturing a display device according to an embodiment, Figures 1 to 3 The same reference numerals as in the figures denote the same components, and thus their repeated description may be omitted for the sake of economy of description.

[0129] like Figure 4 As shown in , in an embodiment, a first inorganic insulating layer 111, a second inorganic insulating layer 112, a third inorganic insulating layer 113, a fourth inorganic insulating layer 114, and a fifth inorganic insulating layer 115 may be formed over the substrate 100. The first inorganic insulating layer 111 is formed to be disposed between the first semiconductor layer A1 and the first gate electrode G1, and the second inorganic insulating layer 112 may be formed to be disposed (for example, in the z-axis direction) between the first gate electrode G1 and the second capacitor electrode CE2. The third inorganic insulating layer 113 is formed on the second capacitor electrode CE2 (for example, directly formed thereon), and the fourth inorganic insulating layer 114 is formed to be disposed between the second semiconductor layer A2 and the second gate electrode G2. The fifth inorganic insulating layer 115 may be formed on the second gate electrode G2 (for example, directly formed thereon).

[0130] A first semiconductor layer A1 and a first gate electrode G1 of a silicon thin film transistor S-TFT, a storage capacitor Cst, and a second semiconductor layer A2 and a second gate electrode G2 of an oxide thin film transistor O-TFT may be provided on a substrate 100. For example, a first semiconductor layer A1 may be formed on the substrate 100, a first inorganic insulating layer 111 may be formed on the first semiconductor layer A1, and a first gate electrode G1 may be formed on the first inorganic insulating layer 111. In an embodiment, the first gate electrode G1 may serve as a first capacitor electrode CE1 of the storage capacitor Cst. In an embodiment, a second inorganic insulating layer 112 may then be formed on the first gate electrode G1, a second capacitor electrode CE2 may be formed on the second inorganic insulating layer 112, and a third inorganic insulating layer 113 may be formed on the second capacitor electrode CE2. In an embodiment, a second semiconductor layer A2 may then be formed on the third inorganic insulating layer 113, a fourth inorganic insulating layer 114 may be formed on the second semiconductor layer A2, and a second gate electrode G2 may be formed on the fourth inorganic insulating layer 114. In an embodiment, a fifth inorganic insulating layer 115 may be formed on the second gate electrode G2 . For example, first, second, third, fourth, and fifth inorganic insulating layers 111 , 112 , 113 , 114 , and 115 may be formed over the substrate 100 .

[0131] Therefore, the above reference Figure 3 A portion of the pixel circuit PC described is formed on a substrate 100. For example, a first semiconductor layer A1 and a first gate electrode G1 of a silicon thin film transistor S-TFT are formed on the substrate 100, a first capacitor electrode CE1 and a second capacitor electrode CE2 of a storage capacitor Cst are formed on the substrate 100, and a second semiconductor layer A2 and a second gate electrode G2 of an oxide thin film transistor O-TFT are formed on the substrate 100. A first inorganic insulating layer 111 is formed to be disposed between the first semiconductor layer A1 and the first gate electrode G1, and a second inorganic insulating layer 112 may be formed to be disposed between the first gate electrode G1 and the second capacitor electrode CE2. A third inorganic insulating layer 113 is formed on the second capacitor electrode CE2, and a fourth inorganic insulating layer 114 is formed to be disposed between the second semiconductor layer A2 and the second gate electrode G2. A fifth inorganic insulating layer 115 may be formed on the second gate electrode G2.

[0132] In an embodiment, the fifth inorganic insulating layer 115 may be formed on the second gate electrode G2 and completely formed over the substrate 100. Accordingly, Figure 4As shown in , the fifth inorganic insulating layer 115 may cover the first semiconductor layer A1 of the silicon thin film transistor S-TFT and the second semiconductor layer A2 of the oxide thin film transistor O-TFT. For example, the fifth inorganic insulating layer 115 may be disposed on the first semiconductor layer A1 of the silicon thin film transistor S-TFT and the second semiconductor layer A2 of the oxide thin film transistor O-TFT. As described above, in an embodiment, each of the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115 may include an inorganic material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiO x N y In an embodiment, the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115, each including an inorganic material, may be formed using a CVD method or an atomic layer deposition (ALD) method.

[0133] In an embodiment, if Figure 5 As shown in , a 1-1 contact hole CNTS1 and a 1-2 contact hole CNTD1 may then be formed (e.g., in the z-axis direction) through the first inorganic insulating layer 111, the second inorganic insulating layer 112, the third inorganic insulating layer 113, the fourth inorganic insulating layer 114, and the fifth inorganic insulating layer 115. For example, a portion of the fifth inorganic insulating layer 115 may be completely removed from an upper surface of the fifth inorganic insulating layer 115 in a thickness direction (e.g., +z direction or -z direction), and a portion of the fourth inorganic insulating layer 114 may be completely removed from an upper surface of the fourth inorganic insulating layer 114 in a thickness direction (e.g., +z direction or -z direction). Together, a portion of the third inorganic insulating layer 113 may be completely removed from the upper surface of the third inorganic insulating layer 113 in the thickness direction (e.g., +z direction or -z direction), a portion of the second inorganic insulating layer 112 may be completely removed from the upper surface of the second inorganic insulating layer 112 in the thickness direction (e.g., +z direction or -z direction), and a portion of the first inorganic insulating layer 111 may be completely removed from the upper surface of the first inorganic insulating layer 111 in the thickness direction (e.g., +z direction or -z direction). In an embodiment, a photolithography process using a mask and an etching process may be used to form the contact hole. However, embodiments of the present disclosure are not necessarily limited thereto, and any process commonly used to form a contact hole in an inorganic insulating layer can be used.

[0134] In an embodiment, if Figure 6As shown in , a first preliminary bridging contact layer PBCL may then be formed on the fifth inorganic insulating layer 115. For example, the first preliminary bridging contact layer PBCL may be formed on (e.g., directly on) the fifth inorganic insulating layer 115 to correspond to (e.g., overlap in the z-axis direction) the entire surface of the substrate 100. As an example, in an embodiment, the first preliminary bridging contact layer PBCL may be formed on the entire surface of the substrate 100 using a CVD method inside a chamber. Accordingly, the first preliminary bridging contact layer PBCL may cover the inner surface of the 1-1 contact hole CNTS1 and the inner surface of the 1-2 contact hole CNTD1. The first preliminary bridging contact layer PBCL may cover a portion of the upper surface of the first semiconductor layer A1 corresponding to the 1-1 contact hole CNTS1 and a portion of the upper surface of the first semiconductor layer A1 corresponding to the 1-2 contact hole CNTD1.

[0135] In an embodiment, the first preliminary bridging contact layer PBCL may include amorphous silicon doped with impurities, and the impurities may include N-type impurities or P-type impurities. As an example, the first preliminary bridging contact layer PBCL may include P-type amorphous silicon doped with impurities such as boron (B), aluminum (Al), or indium (In). Alternatively, the first preliminary bridging contact layer PBCL may include N-type amorphous silicon doped with impurities such as phosphorus (P), arsenic (As), or antimony (Sb). In an embodiment, the first preliminary bridging contact layer PBCL may include a metal material. As an example, the first preliminary bridging contact layer PBCL may include tungsten (W). In another embodiment, the first preliminary bridging contact layer PBCL may include a conductive metal nitride. As an example, the first preliminary bridging contact layer PBCL may include titanium nitride (TiN). However, embodiments of the present disclosure are not necessarily limited thereto.

[0136] As in the embodiment in which the first preliminary bridging contact layer PBCL includes amorphous silicon doped with impurities, the first preliminary bridging contact layer PBCL including tungsten (W) or titanium nitride (TiN) may also be formed using a CVD method. Since the method using CVD is common in the formation of a layer including tungsten (W) or titanium nitride (TiN), a detailed description is omitted for the sake of economy of description.

[0137] As described above, the sputtering method has higher anisotropy than the CVD method. Accordingly, in the case of filling a contact hole having a relatively long shape in the thickness direction (e.g., +z direction or -z direction) with a layer including a conductive material using the sputtering method, a portion of the inner surface of the contact hole may not be covered by the layer including the conductive material. The 1-1 contact hole CNTS1 and the 1-2 contact hole CNTD1 have a relatively long shape in the thickness direction (e.g., +z direction or -z direction). However, in an embodiment of the present disclosure, the first preliminary bridging contact layer PBCL is formed using the CVD method. Accordingly, since the first preliminary bridging contact layer PBCL has excellent step coverage, the first preliminary bridging contact layer PBCL can cover the entire inner surface of the 1-2 contact hole CNTD1 and the entire inner surface of the 1-1 contact hole CNTS1.

[0138] In an embodiment, if Figure 7 As shown in , the 2-1st contact hole CNTS2 and the 2-2nd contact hole CNTD2 passing through the fourth inorganic insulating layer 114 and the fifth inorganic insulating layer 115 may then be formed. Thus, the second preliminary bridging contact layer PBCL' may be formed. For example, a portion of the fifth inorganic insulating layer 115 may be completely removed from the upper surface of the fifth inorganic insulating layer 115 in the thickness direction (e.g., the +z direction or the -z direction), and a portion of the fourth inorganic insulating layer 114 may be completely removed from the upper surface of the fourth inorganic insulating layer 114 in the thickness direction (e.g., the +z direction or the -z direction). Together, a portion of the first preliminary bridging contact layer PBCL corresponding to a portion of the fifth inorganic insulating layer 115 may also be removed. For example, a portion of the first preliminary bridging contact layer PBCL disposed on a portion of the fifth inorganic insulating layer 115 may also be removed together. For example, the second preliminary bridging contact layer PBCL' may be the first preliminary bridging contact layer PBCL from which portions corresponding to the 2-1st contact hole CNTS2 and the 2-2nd contact hole CNTD2 have been removed. In an embodiment, the contact hole may be formed using a photolithography process and an etching process. However, the embodiments of the present disclosure are not necessarily limited thereto, and any process generally used to form a contact hole in an inorganic insulating layer can be used.

[0139] In an embodiment, if Figure 8As shown in , a preliminary connection electrode layer PSDL may then be formed on the second preliminary bridging contact layer PBCL'. For example, the preliminary connection electrode layer PSDL may be formed on the second preliminary bridging contact layer PBCL' to correspond to the entire surface of the substrate 100. As an example, the preliminary connection electrode layer PSDL may be formed on the entire surface of the substrate 100 using a sputtering method inside a chamber. Accordingly, the preliminary connection electrode layer PSDL may cover the inner surface of the 2-1st contact hole CNTS2 and the inner surface of the 2-2nd contact hole CNTD2. The preliminary connection electrode layer PSDL may also cover a portion of the second semiconductor layer A2 corresponding to the 2-1st contact hole CNTS2 and a portion of the second semiconductor layer A2 corresponding to the 2-2nd contact hole CNTD2. In addition, the preliminary connection electrode layer PSDL may also cover a portion of the second preliminary bridging contact layer PBCL' covering the inner surface of the 1-1st contact hole CNTS1 and a portion of the second preliminary bridging contact layer PBCL' covering the inner surface of the 1-2nd contact hole CNTD1. The preliminary connection electrode layer PSDL may also cover a portion of the second preliminary bridging contact layer PBCL' that covers a portion of the first semiconductor layer A1. In an embodiment, the preliminary connection electrode layer PSDL may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. However, embodiments of the present disclosure are not necessarily limited thereto.

[0140] In an embodiment, if Fig. 9 As shown in , by patterning the preliminary connection electrode layer PSDL and the second preliminary bridging contact layer PBCL', a 1-1st connection electrode S1, a 1-2nd connection electrode D1, a 2-1st connection electrode S2, a 2-2nd connection electrode D2, a 1-1st bridging contact layer BCLS1, a 1-2nd bridging contact layer BCLD1, a 2-1st bridging contact layer BCLS2, and a 2-2nd bridging contact layer BCLD2 can be formed. In an embodiment, a photolithography process using a mask and an etching process can be used for patterning. However, the embodiments of the present disclosure are not necessarily limited thereto, and any process commonly used for patterning can be used.

[0141] According to the embodiment, a display device having a reduced possibility of occurrence of defects during a manufacturing process can be realized. However, the scope of the embodiments of the present disclosure is not necessarily limited to this effect.

[0142] It should be understood that the embodiments described herein should be considered in a descriptive sense only, and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: substrate; a first semiconductor layer, wherein the first semiconductor layer is disposed on the substrate; a first gate electrode, the first gate electrode being disposed above the first semiconductor layer; a first inorganic insulating layer, the first inorganic insulating layer being disposed between the first semiconductor layer and the first gate electrode; a capacitor electrode disposed above the first gate electrode to overlap the first gate electrode; a second inorganic insulating layer, the second inorganic insulating layer being disposed between the first gate electrode and the capacitor electrode; a third inorganic insulating layer, the third inorganic insulating layer being disposed on the capacitor electrode; a second semiconductor layer, wherein the second semiconductor layer is disposed on the third inorganic insulating layer; a second gate electrode, the second gate electrode being disposed above the second semiconductor layer; a fourth inorganic insulating layer, the fourth inorganic insulating layer being disposed between the second semiconductor layer and the second gate electrode; a fifth inorganic insulating layer, the fifth inorganic insulating layer being disposed on the second gate electrode; a 1-1 connection electrode, the 1-1 connection electrode being disposed above the fifth inorganic insulating layer, the 1-1 connection electrode being electrically connected to the first semiconductor layer through a 1-1 contact hole passing through the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer, and the fifth inorganic insulating layer; as well as A 1-1 bridge contact layer, wherein the 1-1 bridge contact layer covers a portion of the fifth inorganic insulating layer, an inner surface of the 1-1 contact hole, and a portion of the first semiconductor layer corresponding to the 1-1 contact hole.

2. The display device according to claim 1, wherein: The 1-1 bridge contact layer directly contacts the portion of the first semiconductor layer corresponding to the 1-1 contact hole.

3. The display device according to claim 2, wherein: The 1-1th connecting electrode directly contacts the 1-1th bridging contact layer.

4. The display device according to claim 3, wherein: The 1-1 th bridging contact layer conformally covers the 1-1 th connecting electrode.

5. The display device according to claim 3, wherein: The 1-1 th bridge contact layer has a shape corresponding to a lower surface of the 1-1 th connection electrode.

6. The display device according to any one of claims 1 to 5, wherein: The first semiconductor layer includes a silicon semiconductor.

7. The display device according to any one of claims 1 to 5, wherein: The second semiconductor layer includes an oxide semiconductor.

8. The display device according to any one of claims 1 to 5, wherein: The 1-1 th bridge contact layer includes amorphous silicon doped with N-type impurities or P-type impurities.

9. The display device according to any one of claims 1 to 5, wherein: The 1-1 th bridge contact layer includes tungsten or titanium nitride.

10. The display device according to claim 1, further comprising: a 2-1 connection electrode, the 2-1 connection electrode being disposed above the fifth inorganic insulating layer, the 2-1 connection electrode being electrically connected to the second semiconductor layer through a 2-1 contact hole penetrating through the fourth inorganic insulating layer and the fifth inorganic insulating layer; as well as The 2-1st bridge contact layer covers a portion of the fifth inorganic insulating layer, and the 2-1st bridge contact layer is spaced apart from the second semiconductor layer.

11. The display device according to claim 10, wherein: The 2-1st connecting electrode directly contacts the second semiconductor layer.

12. The display device according to any one of claims 10 and 11, wherein: The 2-1st bridge contact layer does not directly contact the inner surface of the 2-1st contact hole and a portion of the second semiconductor layer corresponding to the 2-1st contact hole.

13. The display device according to any one of claims 10 and 11, wherein: The 2-1st bridge contact layer includes the same material as that of the 1-1st bridge contact layer.

14. A method for manufacturing a display device, the method comprising: providing a substrate; forming a first inorganic insulating layer, a second inorganic insulating layer, a third inorganic insulating layer, a fourth inorganic insulating layer and a fifth inorganic insulating layer over the substrate; forming a 1-1 contact hole passing through the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer, and the fifth inorganic insulating layer; forming a first preliminary bridging contact layer on the fifth inorganic insulating layer; forming a second preliminary bridge contact layer by forming a 2-1 contact hole passing through the fourth inorganic insulating layer and the fifth inorganic insulating layer and removing a portion of the first preliminary bridge contact layer corresponding to the 2-1 contact hole; forming a preliminary connection electrode layer on the second preliminary bridging contact layer; as well as A 1-1th connection electrode, a 2-1th connection electrode, a 1-1th bridge contact layer, and a 2-1th bridge contact layer are formed by patterning the preliminary connection electrode layer and the second preliminary bridge contact layer.

15. The method for manufacturing a display device according to claim 14, wherein: Forming the first preliminary bridging contact layer includes forming the first preliminary bridging contact layer using a chemical vapor deposition method.

16. The method for manufacturing a display device according to claim 14, wherein: The first preliminary bridging contact layer includes amorphous silicon doped with N-type impurities or P-type impurities.

17. The method for manufacturing a display device according to claim 14, wherein: The first preliminary bridging contact layer includes tungsten or titanium nitride.

18. The method for manufacturing a display device according to claim 14, wherein: Forming the first preliminary bridge contact layer includes covering an inner surface of the 1-1th contact hole with the first preliminary bridge contact layer.

19. The method for manufacturing a display device according to claim 14, wherein: Forming the first inorganic insulating layer, the second inorganic insulating layer, the third inorganic insulating layer, the fourth inorganic insulating layer, and the fifth inorganic insulating layer over the substrate includes: forming the first inorganic insulating layer to be disposed between the first semiconductor layer and the first gate electrode; forming the second inorganic insulating layer to be disposed between the first gate electrode and the capacitor electrode; forming the third inorganic insulating layer on the capacitor electrode; forming the fourth inorganic insulating layer to be disposed between the second semiconductor layer and the second gate electrode; and The fifth inorganic insulating layer is formed on the second gate electrode.

20. The method for manufacturing a display device according to claim 19, wherein: The 1-1 connection electrode is electrically connected to the first semiconductor layer through the 1-1 contact hole; and The 2-1st connecting electrode is electrically connected to the second semiconductor layer through the 2-1st contact hole.

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