Array substrate and manufacturing method thereof, and display panel

Abstract

The present invention relates to an array substrate, a method for manufacturing the same, and a display panel. In the display panel of the present invention, the projection of the first interlayer insulating layer on the first substrate is tangent to or separated from the projection of the opening area on the first substrate, so that the surface of the second interlayer insulating layer in the opening area close to the first substrate is adhered to the surface of the gate insulating layer away from the first substrate. The gate insulating layer and the second interlayer insulating layer are made of the same material, thereby reducing the reflectivity of light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area, thereby reducing the reflectivity of the display panel, reducing the reflection of ambient light by the display panel, improving the contrast of the display panel, and enhancing the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the increasing popularity of electronic products, their innovation and replacement speed is very fast, and the functional requirements are becoming more and more stringent. Among them, the pursuit of lower reflectivity of display panels has become a future market development trend. Lower reflectivity can bring users a more comfortable visual experience, especially in environments with strong external ambient light.

[0003] After natural light enters the display panel, there are three main paths: transmission, absorption and reflection. Ideally, we hope that the light can be completely transmitted or absorbed, but in reality, it is not possible to achieve complete transmission or absorption. This is mainly because there are many film layers in the display panel, and the refractive indices of these film layers are different. Therefore, the angle of light will change when entering different film layers, that is, there will be reflected light, and the reflected light at different interfaces will also produce interference effects. The reflectivity formula of light when entering different film layers is as follows: Reflectivity (R) = (n1-n2)2 / (n1+n2)2 (n1, n2 are the real refractive indices of the two media respectively). According to the above formula (R) = (n1-n2)2 / (n1+n2)2, it can be seen that the closer the refractive index n value of adjacent film layers is, the lower the reflectivity at the junction of the two film layers.

[0004] Current low-temperature polysilicon (LTPS) display panels have multiple insulating layers, resulting in numerous contact surfaces with significantly different refractive index n values. This results in a high reflectivity of the display panel, which, when exposed to sunlight or other ambient light, causes strong reflections, reducing the contrast of the display panel and significantly affecting the display quality. Summary of the Invention

[0005] The present invention provides an array substrate and a preparation method thereof, and a display panel, which can solve the problems of existing display panels having many contact surfaces with large differences in refractive index, resulting in high reflectivity of the display panel, reduced contrast of the display panel, and ultimately reduced display effect of the display panel.

[0006] In order to solve the above problems, the present invention provides an array substrate, which includes an opening area and a non-opening area: a first substrate; a gate insulation layer, arranged on the first substrate, and located in the opening area and the non-opening area; a first interlayer insulation layer, arranged on the side of the gate insulation layer away from the first substrate, and located in the non-opening area; and a second interlayer insulation layer, arranged on the side of the first interlayer insulation layer away from the first substrate, and located in the opening area and the non-opening area; wherein, the projection of the first interlayer insulation layer on the first substrate is tangent to or separated from the projection of the opening area on the first substrate.

[0007] Furthermore, a surface of the second interlayer insulating layer located in the opening region on a side close to the first substrate is attached to a surface of the gate insulating layer located in the opening region on a side away from the first substrate.

[0008] Furthermore, the gate insulating layer and the second interlayer insulating layer are made of the same material.

[0009] Furthermore, the reflectivity of the light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area is lower than the reflectivity of the light at the contact surface between the second interlayer insulating layer and the first interlayer insulating layer in the non-opening area.

[0010] Furthermore, the reflectivity of the light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area is lower than the reflectivity of the light at the contact surface between the first interlayer insulating layer and the gate insulating layer in the non-opening area.

[0011] Furthermore, the array substrate also includes: an active layer, arranged between the first substrate and the gate insulating layer, and located in the non-opening area; a gate layer, arranged between the gate insulating layer and the first interlayer insulating layer, and located in the non-opening area; and a source and drain layer, arranged on the side of the second interlayer insulating layer away from the first substrate, located in the non-opening area, and electrically connected to the active layer; wherein the material of the active layer is low-temperature polycrystalline silicon.

[0012] In order to solve the above problems, the present invention provides a method for preparing an array substrate, which includes the following steps: defining an opening area and a non-opening area on a first substrate; preparing a gate insulating layer on the first substrate in the opening area and the non-opening area; preparing a first interlayer insulating layer on the side of the gate insulating layer in the non-opening area away from the first substrate; the projection of the first interlayer insulating layer on the first substrate is tangent to or separated from the projection of the opening area on the first substrate; and preparing a second interlayer insulating layer on the side of the first interlayer insulating layer in the non-opening area away from the first substrate, the second interlayer insulating layer also extending to cover the gate insulating layer in the opening area.

[0013] Furthermore, the step of preparing a first interlayer insulating layer on the side of the gate insulating layer in the non-opening area away from the first substrate includes: preparing a first interlayer insulating layer on the side of the gate insulating layer in the opening area and the non-opening area away from the first substrate; and removing the first interlayer insulating layer located in the opening area and retaining the first interlayer insulating layer located in the non-opening area.

[0014] In order to solve the above problems, the present invention provides a display panel, which includes the array substrate of the present invention, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate.

[0015] Furthermore, the color film substrate includes: a second substrate; and a plurality of black matrix units, which are spaced apart and arranged on a side of the second substrate close to the first substrate; the projection of the black matrix unit on the first substrate coincides with the projection of the non-opening area on the first substrate.

[0016] The advantages of the present invention are: the projection of the first interlayer insulating layer of the display panel of the present invention on the first substrate is tangent to or separated from the projection of the opening area on the first substrate, so that the surface of the second interlayer insulating layer in the opening area close to the first substrate is adhered to the surface of the gate insulating layer away from the first substrate, and the gate insulating layer and the second interlayer insulating layer are prepared using the same material, thereby reducing the reflectivity of the light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area, thereby reducing the reflectivity of the display panel, reducing the reflection of the display panel to ambient light, improving the contrast of the display panel, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic structural diagram of a display panel of the present invention;

[0019] Figure 2 Schematic diagram of light reflection at the interface between the second interlayer insulating layer and the first interlayer insulating layer and at the interface between the first interlayer insulating layer and the gate insulating layer in the non-opening area;

[0020] Figure 3Schematic diagram of light reflection at the interface between the second interlayer insulating layer and the gate insulating layer in the opening area;

[0021] Figure 4 This is a schematic diagram of Example 1 of the present invention after preparing an array substrate, a first electrode, and a pixel barrier layer on a substrate.

[0022] Description of reference numerals:

[0023] 100, display panel; 1100, opening area;

[0024] 1200, non-opening area;

[0025] 1. Array substrate; 2. Color filter substrate;

[0026] 3. Liquid crystal layer;

[0027] 101. First substrate; 102. Active layer;

[0028] 103. Gate insulating layer; 104. Gate layer;

[0029] 105. First interlayer insulating layer; 106. Second interlayer insulating layer;

[0030] 107. Source and drain layer; 108. Planarization layer;

[0031] 109. Common electrode layer; 110. Passivation layer;

[0032] 111. pixel electrode layer;

[0033] 201, second substrate; 202, color resist unit;

[0034] 203. Black matrix unit. DETAILED DESCRIPTION

[0035] The following describes in detail preferred embodiments of the present invention in conjunction with the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the scope of the present invention.

[0036] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate the present invention, and are not used to limit the scope of protection of the present invention.

[0037] In the accompanying drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0038] like Figure 1 As shown, this embodiment provides a display panel 100. The display panel 100 includes an array substrate 1, a color filter substrate 2, and a liquid crystal layer 3.

[0039] The array substrate 1 includes an opening area 1100 and a non-opening area 1200. The array substrate 1 includes: a first substrate 101, an active layer 102, a gate insulating layer 103, a gate layer 104, a first interlayer insulating layer 105, a second interlayer insulating layer 106, a source and drain electrode layer 107, a planarization layer 108, a common electrode layer 109, a passivation layer 110, and a pixel electrode layer 111.

[0040] The first substrate 101 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the first substrate 101 has good impact resistance and can effectively protect the display device 100. In this embodiment, the first substrate 101 is made of glass.

[0041] The active layer 102 is disposed on a side of the first substrate 101 close to the color filter substrate 2. The active layer 102 is located in the non-opening area 1200. In this embodiment, the active layer 102 is made of low-temperature polysilicon.

[0042] The gate insulating layer 103 covers the side of the active layer 102 away from the first substrate 101 and extends over the first substrate 101. The gate insulating layer 103 is located in the opening area 1100 and the non-opening area 1200. The gate insulating layer 103 is primarily used to prevent short circuits between the active layer 102 and the gate layer 104. The gate insulating layer 103 can be made of SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx. In this embodiment, the gate insulating layer 103 is made of SiOx.

[0043] The gate layer 104 is disposed on a side of the gate insulating layer 103 away from the first substrate 101 and located in the non-opening area 1200. The gate layer 104 may be made of Mo, a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu, and IZO, a combination of IZO, Cu, and IZO, a combination of Mo, Cu, and ITO, a combination of Ni, Cu, and Ni, NiCr, a combination of Cu and NiCr, or CuNb, etc.

[0044] The first interlayer insulating layer 105 covers the side of the gate layer 104 away from the first substrate 101, extends over the surface of the gate insulating layer 103 away from the first substrate 101, and is located in the non-opening area 1200. Because grain boundaries exist between polysilicon grains and interface states exist between polysilicon and the oxide layer, they affect the electrical properties of the transistor. Therefore, hydrogenation is generally performed to improve electrical properties such as mobility and threshold voltage uniformity.

[0045] In this embodiment, the material of the first interlayer insulating layer 105 is SiNx. The SiNx film is used as a hydrogenation source and baked at a specific temperature to diffuse hydrogen atoms into the polycrystalline and oxide layers.

[0046] The projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from the projection of the opening area 1100 on the first substrate 101. In other words, the first interlayer insulating layer 105 is only disposed in the non-opening area 1200 and not in the opening area 1100.

[0047] The second interlayer insulating layer 106 covers the side of the first interlayer insulating layer 105 away from the first substrate 101 and is located in the opening area 1100 and the non-opening area 1200. The gate insulating layer 103 and the second interlayer insulating layer 106 are made of the same material. That is, in this embodiment, the second interlayer insulating layer 106 is made of SiOx.

[0048] The surface of the second interlayer insulating layer 106 located in the opening area 1100 close to the first substrate 101 is attached to the surface of the gate insulating layer 103 located in the opening area 1100 away from the first substrate 101 .

[0049] The source / drain electrode layer 107 is disposed on a side of the second interlayer insulating layer 106 away from the first substrate 101, is located in the non-opening area 1200, and is electrically connected to the active layer 102. The material of the source / drain electrode layer 107 can be Mo, a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu, and IZO, a combination of IZO, Cu, and IZO, a combination of Mo, Cu, and ITO, a combination of Ni, Cu, and Ni, NiCr, a combination of Cu and NiCr, or CuNb, etc.

[0050] The planarization layer 108 covers the side of the source / drain layer 107 away from the first substrate 101, extends over the surface of the second interlayer insulating layer 106 away from the first substrate 101, and is located in the opening area 1100 and the non-opening area 1200. The material of the planarization layer 108 can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx. In this embodiment, the material of the planarization layer 108 is SiOx.

[0051] The common electrode layer 109 is disposed on the surface of the planar layer 108 at a side away from the first substrate 101. In this embodiment, the common electrode layer 109 is made of indium tin oxide (ITO).

[0052] The passivation layer 110 is disposed on the surface of the common electrode layer 109 on a side away from the first substrate 101. The passivation layer 110 is primarily used to prevent contact between the common electrode layer 109 and the pixel electrode layer 111. The passivation layer 110 can be made of SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx. In this embodiment, the passivation layer 110 is made of SiNx.

[0053] The pixel electrode layer 111 is disposed on a surface of the passivation layer 110 that is away from the first substrate 101. In this embodiment, the pixel electrode layer 111 is made of indium tin oxide.

[0054] In this embodiment, the second interlayer insulating layer 106 is made of SiOx, the first interlayer insulating layer is made of SiNx, and the gate insulating layer 103 is made of SiOx. In actual measurements, the refractive index of the second interlayer insulating layer 106 is 1.47, the refractive index of the first interlayer insulating layer is 1.87, and the refractive index of the gate insulating layer 103 is 1.45.

[0055] like Figure 2 As shown, R1 = (1.47-1.87)2 / (1.47+1.87)2 = 1.43%;

[0056] And, R2=(1.87-1.45)2 / (1.87+1.45)2=1.6%.

[0057] like Figure 3 As shown, R3 = (1.47-1.45)2 / (1.47+1.45)2 = 0.005%.

[0058] From the above, it can be seen that R3 is less than R1+R2. This proves that the projection of the first interlayer insulating layer 105 of the display panel 100 of this embodiment on the first substrate 101 is tangent to or separated from the projection of the opening area 1100 on the first substrate 101, so that the surface of the second interlayer insulating layer 106 of the opening area 1100 close to the first substrate 101 is attached to the surface of the gate insulating layer 103 away from the first substrate 101. The gate insulating layer 103 and the second interlayer insulating layer 106 are made of the same material. This can reduce the reflectivity of light at the contact surface between the second interlayer insulating layer 106 and the gate insulating layer 103 in the opening area 1100 without affecting the thin film transistor characteristics of the array substrate 1. The reflectivity of light at the contact surface between the second interlayer insulating layer 106 and the gate insulating layer 103 in the opening area 1100 is smaller than the reflectivity of light at the contact surface between the second interlayer insulating layer 106 and the first interlayer insulating layer 105 in the non-opening area 1200; the reflectivity of light at the contact surface between the second interlayer insulating layer 106 and the gate insulating layer 103 in the opening area 1100 is smaller than the reflectivity of light at the contact surface between the first interlayer insulating layer 105 and the gate insulating layer 103 in the non-opening area 1200; thereby reducing the reflectivity of the display panel 100, weakening the reflection of ambient light by the display panel 100, improving the contrast of the display panel 100, and improving the display effect of the display panel 100.

[0059] The color filter substrate 2 is disposed opposite to the array substrate 1 , and includes a second substrate 201 , a plurality of color resist units 202 , and a plurality of black matrix units 203 .

[0060] The second substrate 201 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the second substrate 201 has good impact resistance and can effectively protect the display device 100. In this embodiment, the second substrate 201 is made of glass.

[0061] The black matrix units 203 are arranged at intervals on the surface of the second substrate 201 on the side close to the first substrate 101. The black matrix units 203 are used to prevent cross-color phenomenon. The projection of the black matrix unit 203 on the first substrate 101 coincides with the projection of the non-opening area 1200 on the first substrate 101. The color resist unit 202 is arranged on the surface of the black matrix unit 203 on the side close to the first substrate 101 and extends to cover the surface of the second substrate 201 on the side close to the first substrate 101. The color resist unit 202 includes a red color resist unit, a green color resist unit, and a blue color resist unit. The projection of the color resist unit 202 on the first substrate 101 coincides with the projection of the opening area 1100 on the first substrate 101.

[0062] The liquid crystal layer 3 is disposed between the array substrate 1 and the color filter substrate 2 .

[0063] like Figure 4 As shown, this embodiment also provides a method for preparing an array substrate, which includes the following steps: S1, defining an opening area 1100 and a non-opening area 1200 on a first substrate 101; preparing a gate insulating layer 103 on the first substrate 101 in the opening area 1100 and the non-opening area 1200; S2, preparing a first interlayer insulating layer 105 on the side of the gate insulating layer 103 in the non-opening area 1200 away from the first substrate 101; the projection of the first interlayer insulating layer 105 on the first substrate 101 is tangent to or separated from the projection of the opening area 1100 on the first substrate 101; and S3, preparing a second interlayer insulating layer 106 on the side of the first interlayer insulating layer 105 in the non-opening area 1200 away from the first substrate 101, and the second interlayer insulating layer 106 also extends to cover the gate insulating layer 103 in the opening area 1100.

[0064] S2 includes: preparing a first interlayer insulating layer 105 on the side of the gate insulating layer 103 in the opening area 1100 and the non-opening area 1200 away from the first substrate 101; and removing the first interlayer insulating layer 105 located in the opening area 1100, and retaining the first interlayer insulating layer 105 located in the non-opening area 1200.

[0065] Furthermore, the above provides a detailed introduction to an array substrate, a preparation method thereof, and a display panel provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes an opening area and a non-opening area; wherein the array substrate includes: a first substrate; a gate insulating layer, disposed on the first substrate and located in the opening area and the non-opening area; a first interlayer insulating layer, disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area; and a second interlayer insulating layer, disposed on a side of the first interlayer insulating layer away from the first substrate, and located in the opening area and the non-opening area; The reflectivity of the light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area is lower than the reflectivity of the light at the contact surface between the second interlayer insulating layer and the first interlayer insulating layer in the non-opening area.

2. The array substrate according to claim 1, wherein: The reflectivity of the light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area is lower than the reflectivity of the light at the contact surface between the first interlayer insulating layer and the gate insulating layer in the non-opening area.

3. The array substrate according to claim 2, wherein: The refractive index of the second interlayer insulating layer is smaller than that of the first interlayer insulating layer, and the refractive index of the second interlayer insulating layer is smaller than that of the gate insulating layer.

4. The array substrate according to any one of claims 1 to 3, wherein: A projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening region on the first substrate.

5. The array substrate according to any one of claims 1 to 3, characterized in that: A surface of the second interlayer insulating layer located in the opening region and close to the first substrate is adhered to a surface of the gate insulating layer located in the opening region and away from the first substrate.

6. The array substrate according to any one of claims 1 to 3, characterized in that: The gate insulating layer and the second interlayer insulating layer are made of the same material.

7. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate further includes: an active layer, disposed between the first substrate and the gate insulating layer and located in the non-opening area; a gate layer, disposed between the gate insulating layer and the first interlayer insulating layer and located in the non-opening area; and The source-drain electrode layer is disposed on a side of the second interlayer insulating layer away from the first substrate, is located in the non-opening area, and is electrically connected to the active layer.

8. A method for preparing an array substrate, characterized in that: include: defining an opening area and a non-opening area on a first substrate; forming a gate insulating layer on the first substrate in the opening area and the non-opening area; forming a first interlayer insulating layer on a side of the gate insulating layer in the non-opening area away from the first substrate; forming a second interlayer insulating layer on a side of the first interlayer insulating layer in the non-opening area away from the first substrate, wherein the second interlayer insulating layer further extends and covers the gate insulating layer in the opening area; The reflectivity of the light at the contact surface between the second interlayer insulating layer and the gate insulating layer in the opening area is lower than the reflectivity of the light at the contact surface between the second interlayer insulating layer and the first interlayer insulating layer in the non-opening area.

9. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate.

10. The display panel according to claim 9, wherein: The color film substrate comprises: a second substrate; and a plurality of black matrix units, spaced apart from each other and arranged on a side of the second substrate close to the first substrate; The projection of the black matrix unit on the first substrate and the projection of the non-opening area on the first substrate overlap with each other.

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