Array substrate, display panel, display device and vehicle-mounted terminal

Abstract

The invention discloses an array substrate, a display panel, a display device and a vehicle-mounted terminal. The array substrate comprises a display area and a non-display area on the periphery of the display area. The display area comprises a plurality of pixel circuits, and the non-display area comprises more than two signal generating circuits; the signal generation circuit is used for providing required signals for pixel circuits in the display area; any stage of connecting line between two adjacent signal generating circuits comprises more than two connecting sections which are connected with each other; and the more than two mutually connected connecting sections are positioned on different metal layers of the array substrate. By adopting the scheme, the yield of the array substrate can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel, a display device and a vehicle-mounted terminal. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The display panel is an important component of electronic devices to realize the display function, and the array substrate is an important component of the display panel. During the production process of the array substrate, a cutter wheel is needed to cut the front or back of the array substrate to separate different array substrates on the same substrate.

[0004] However, when using a cutter wheel to cut the front or back side of the array substrate, static electricity from the environment and the machine is easily introduced into the substrate through the cutter wheel, causing damage to the devices in the array substrate and affecting the yield of the array substrate. Summary of the invention

[0005] The problem to be solved by the present invention is: how to improve the yield rate of the array substrate.

[0006] To solve the above problems, an embodiment of the present invention provides an array substrate, the array substrate comprising: a display area and a non-display area outside the display area; the display area comprises a plurality of pixel circuits, and the non-display area comprises more than two signal generating circuits; the signal generating circuit is used to provide required signals for the pixel circuits in the display area;

[0007] Wherein, any one-level interconnection line between two adjacent signal generating circuits comprises: more than two interconnected connecting segments; and the more than two interconnected connecting segments are located in different metal layers of the array substrate.

[0008] An embodiment of the present invention further provides a display panel, which includes: any one of the above array substrates.

[0009] An embodiment of the present invention further provides a display device, which includes the above-mentioned display panel.

[0010] An embodiment of the present invention further provides a vehicle-mounted terminal, which includes the above-mentioned display device.

[0011] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0012] By applying the solution of the present invention, any cascade line between two adjacent signal generating circuits may include more than two interconnected connecting segments, and the two or more interconnected connecting segments are located in different metal layers of the array substrate. This can reduce the static electricity accumulation of the cascade line in the same metal layer, and further reduce the density of the electrostatic charge in the array substrate, avoiding single-point electrostatic discharge from damaging the device, thereby reducing the dark line rate of the array substrate and improving the yield of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a structural schematic diagram of an array substrate;

[0014] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure of the non-display area NAA along the L1L2 direction;

[0015] Figure 3 It is a schematic diagram of an enlarged structure of a cascade line and a non-bonding region device of a second signal generating circuit;

[0016] Figure 4 It is an enlarged structural schematic diagram of the cascade line and the bonding area device of the second signal generating circuit;

[0017] Figure 5 It is a schematic diagram of the change in threshold voltage of a device damaged by static electricity;

[0018] Figure 6 is a schematic structural diagram of an array substrate in an embodiment of the present invention;

[0019] Figure 7 is a schematic diagram of a cross-sectional structure of an array substrate along a cutting direction in an embodiment of the present invention;

[0020] Figure 8 is a top view of each connecting segment located in the same metal layer in an embodiment of the present invention;

[0021] Fig. 9 is a top view of a connecting section with a tip portion in an embodiment of the present invention;

[0022] Fig.10 is a schematic diagram of a cross-sectional structure of another array substrate along a cutting direction in an embodiment of the present invention;

[0023] Fig.11 is a schematic diagram of connection between two adjacent signal generating circuits in an embodiment of the present invention;

[0024] Fig.12 is another schematic diagram of connection between two adjacent signal generating circuits in an embodiment of the present invention;

[0025] Fig.13It is a schematic diagram of a circuit structure of an LED pixel circuit;

[0026] Fig.14 The figure is a schematic diagram of the structure of an LCD pixel circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be fully described below in combination with the drawings in the embodiments of the present invention through specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work fall within the protection scope of the present invention.

[0028] During the manufacturing process of the array substrate, a cutter wheel is required to cut the front or back side of a substrate (such as glass) of the array substrate to separate different array substrates on the same substrate.

[0029] Figure 1 FIG. 1 is a schematic diagram of the structure of an array substrate in the prior art. Figure 1 , the array substrate may include a display area AA and a non-display area NAA outside the display area AA. A plurality of pixel circuits are arranged in the display area AA. More than two signal generating circuits may be arranged in the non-display area NAA. The signal generating circuit in the non-display area NAA may generate a required signal and be connected to the pixel circuit in the display area AA through a signal line, thereby providing a signal to the pixel circuit in the display area AA to drive the pixel circuit.

[0030] For example, refer to Figure 1 , the non-display area NAA may be provided with a first signal generating circuit 11 and a second signal generating circuit 12. The first signal generating circuit 11 may provide required signals to some pixel circuits in the display area AA through the first signal line 13. The second signal generating circuit 12 may provide required signals to the remaining pixel circuits in the display area AA through the second signal line 14. The first signal line 13 and the second signal line respectively include a plurality of signal lines, the first signal generating circuit 11 may provide all signals required by the connected pixel circuits, and the second signal generating circuit 12 may provide all signals required by the connected pixel circuits. The first signal line 13 and the second signal line 14 are both metal lines.

[0031] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the non-display area NAA along the L1L2 direction. Figure 2, some devices 111 in the pixel circuit connected to the first signal generating circuit 11 are distributed between the input terminal input and the output terminal output of the first signal generating circuit 11, and some devices 112 in the pixel circuit connected to the second signal generating circuit 12 are distributed between the input terminal input and the output terminal output of the second signal generating circuit 12, and the first signal generating circuit 11 and the second signal generating circuit 12 are connected through a cascade line 15. The first signal generating circuit 11 is connected to the control circuit board through a flexible circuit board, so that it can provide corresponding signals for the connected pixel circuits under the control instructions sent by the control circuit board.

[0032] When using a cutter wheel to cut along the cutting line L3L4 (such as Figure 1 When cutting, it is easy to introduce static electricity from the environment and the machine into the substrate through the cutter wheel, and the static electricity is concentrated on the cascade line 15 (as shown in FIG. Figure 2 As the metal wires on the display area AA are close to the cutting lines L3L4, after the static electricity is introduced and reaches a certain intensity at the end of the cascade line 15, the end of the cascade line 15 will move toward the devices in the bonding area (such as Figure 2 The discharge may cause the devices in the bonding area to be damaged, or the signal lines or the devices connected to the signal lines may be damaged after being transmitted through the signal lines.

[0033] Figure 3 It is a schematic diagram of the enlarged structure of the cascade line 15 and the non-bonding area device of the second signal generating circuit 12. Figure 4 FIG. 1 is a schematic diagram of the enlarged structure of the bonding area device of the cascade line 15 and the second signal generating circuit 12. Figure 3 It can be seen that the device has not been significantly damaged in the non-bonding area. Figure 4 It can be seen that there is an obvious electrostatic damage area 41 in the bonding area.

[0034] Figure 5 This is a schematic diagram of the change in threshold voltage of a device damaged by static electricity. Figure 5 The inventors have found that the threshold voltage of a device damaged by static electricity obviously drifts to the right relative to the threshold voltage of a device not damaged by static electricity, which may cause insufficient charging and form dark lines.

[0035] In current vehicle-mounted terminals, some devices in the step area at the junction of the display area and the non-display area of ​​the array substrate will be damaged by static electricity due to static discharge at the end of the cascade line 15, resulting in a dark line rate of up to 8.7% on the array substrate, which greatly affects the yield of the array substrate.

[0036] To address this problem, the present invention provides an array substrate, wherein in a non-display area of ​​the array substrate, any cascading line between two adjacent signal generating circuits may include more than two interconnected connecting segments, and the two or more interconnected connecting segments are located in different metal layers of the array substrate. This can reduce electrostatic accumulation of the cascading line in the same metal layer, thereby improving the yield of the array substrate.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Reference Figure 6 An embodiment of the present invention provides an array substrate 60, which may include: a display area AA and a non-display area NAA outside the display area AA; the display area AA may include a plurality of pixel circuits (not shown), and the non-display area NAA includes more than two signal generating circuits; the signal generating circuit is used to provide the required signals for the pixel circuits in the display area AA.

[0039] In a specific implementation, the non-display area NAA may be provided with only two signal generating circuits, or may be provided with multiple signal generating circuits, for example, three or four signal generating circuits. The signal generating circuit is integrated in a chip, and the chip is then fixed on the array substrate 60. The signal generating circuit may also be a device fixed on the array substrate 60 and capable of providing the signals required by the pixel circuit.

[0040] Regardless of the form in which the signal generating circuit is presented, each signal generating circuit of the non-display area NAA can be arranged along the direction of the cutting line HH', and any adjacent signal generating circuits are connected by cascade lines. Each signal generating circuit can provide all the required signals for the connected pixel circuit. The same cascade line is used to input the same control signal to the two connected signal generating circuits. The number of control signals input to the signal generating circuit is equal to the number of cascade lines between the two adjacent signal generating circuits.

[0041] In an embodiment of the present invention, for any two adjacent signal generating circuits, any cascade line connecting the two adjacent signal generating circuits may include: two or more interconnected connecting segments. The two or more interconnected connecting segments are located on different metal layers of the array substrate. This is equivalent to cutting the long line of the existing cascade line into multiple short lines. The length of each short line may be the same or different.

[0042] Among them, two or more interconnected connection segments are located in different metal layers of the array substrate, which means that the connection segments of the same cascade line are distributed in different metal layers of the array substrate. That is, multiple short traces of the same cascade line are distributed in more than two metal layers, and two adjacent connection segments can be located in the same metal layer or in different metal layers.

[0043] For example, some connection segments of the same cascade line are distributed on the first metal layer of the array substrate, another part of the connection segments are distributed on the second metal layer of the array substrate, and another part of the connection segments are distributed on the third metal layer of the array substrate.

[0044] Since the connection segments of the same cascade line are not distributed in the same metal layer of the array substrate, the static electricity accumulation in the same metal layer can be reduced, thereby achieving the purpose of reducing the density of static electricity charge in the same metal layer, thereby avoiding single-point static electricity discharge from damaging devices.

[0045] In one embodiment of the present invention, in the two or more interconnected connecting segments, two adjacent connecting segments are located in different metal layers. In other words, any two adjacent connecting segments of the same cascade line are distributed in different metal layers. In this way, adjacent connecting segments can be connected by punching holes to form cascade lines distributed in different metal layers.

[0046] For example, a cascade line may include: a first connecting segment, a second connecting segment, a third connecting segment, a fourth connecting segment and a fifth connecting segment. The first connecting segment may be located at the first metal layer, the second connecting segment may be located at the second metal layer, the third connecting segment may be located at the third metal layer, the fourth connecting segment may be located at the second metal layer, and the fifth connecting segment may be located at the third metal layer.

[0047] In one embodiment of the present invention, the cascade line includes: more than two first connecting segments and a second connecting segment; the more than two first connecting segments are located in the same metal layer, and the second connecting segment is used to connect two adjacent first connecting segments; the metal layer where the second connecting segment is located is different from the metal layer where the first connecting segment is located.

[0048] Specifically, the cascade line may include more than two first connection segments, two adjacent first connection segments are located in the same metal layer, the second connection segment is located in a non-first metal layer, and the two adjacent first connection segments are connected by the second connection segment. The number of the second connection segments is at least one. When the number of the second connection segments is more than two, each second connection segment may be located in the same metal layer or in a different metal layer, as long as it is different from the metal layer where the first connection segment is located. Specifically, the first connection segment may be connected to the second connection segment by punching.

[0049] For example, when the first connecting segment is located in the first metal layer, part of the second connecting segment may be located in the second metal layer, and the remaining part of the second connecting segment may be located in the third metal layer.

[0050] Since the second connection section and the first connection section are located in different metal layers, the electrostatic charge density in the metal layer where the first connection section is located can be reduced, thereby avoiding the occurrence of concentrated static discharge at a single point to damage the inner film layer of the glass maintain.

[0051] In one embodiment of the present invention, the array substrate includes a first metal layer and a second metal layer which are stacked; the first connecting section is located in the first metal layer, and the second connecting section is located in the second metal layer.

[0052] At this time, each connection segment of the same cascade line is distributed either in the first metal layer or in the second metal layer. Of any two adjacent connection segments, one connection segment is distributed in the first metal layer and the other connection segment is distributed in the second metal layer. The connection segments of the cascade line are alternately distributed in the first metal layer and the second metal layer, so that the adjacent two connection segments can be connected by periodically punching the cascade line, which can effectively improve the manufacturing efficiency of the array substrate while reducing the electrostatic charge density in the same metal layer and avoiding the occurrence of concentrated electrostatic release at a single point to damage the inner film layer of the glass maintain.

[0053] Figure 7 is a schematic diagram of the cross-sectional structure of the array substrate along the cutting direction. Figure 7 In one embodiment of the present invention, the array substrate may include: a barrier layer 71, a buffer layer 72, a first metal layer 73, an interlayer insulating layer 74, and a second metal layer 75. The barrier layer 71 may be made of glass, the buffer layer 72 may be made of silicon oxide (SiOx) or silicon nitride (SiNx), the first metal layer 73 may be made of molybdenum (Mo), the interlayer insulating layer 74 may be made of silicon oxide (SiOx) or silicon nitride (SiNx), and the second metal layer 75 may be made of titanium (Ti) or aluminum (Al).

[0054] At this time, for the same cascade line, the first connection segment can be set in the first metal layer 73, and the second connection segment can be set in the second metal layer 75, and the first connection segment and the second connection segment are connected by punching. In this way, the top view of each connection segment located in the same metal layer is as shown in FIG. Figure 8 shown.

[0055] Assumptions Figure 8 , which is a top view of the first connecting segment 81 in the first metal layer, adjacent first connecting segments 81 are spaced apart in the first metal layer, and each first connecting segment 81 is connected to an adjacent second connecting segment in the second metal layer. Figure 8, which is a top view of the second connecting segment 82 in the second metal layer, adjacent second connecting segments 82 are spaced apart in the second metal layer, and each second connecting segment 82 is connected to an adjacent first connecting segment in the first metal layer. Figure 8 The 80 in the figure indicates the original routing direction of the cascade line where the connection segment is located.

[0056] In a specific implementation, there may be a variety of configurations for the shape of the connecting segment, which may be a regular shape or an irregular shape.

[0057] In one embodiment of the present invention, referring to Figure 7 The shape of the connection segment can be linear. Each linear connection segment can be connected in sequence to form a cascade line. The use of a linear connection segment facilitates punching connection, which can effectively reduce the difficulty of implementation and improve the reliability of the connection.

[0058] In another embodiment of the present invention, referring to Figure 6 , along the distribution direction X of the display area and the non-display area, the connection segment located in the bottom metal layer of the array substrate has a pointed end at one end close to the cutting line.

[0059] Correspondingly, the array substrate further comprises: a redundant structure located in the semiconductor layer below the bottom metal layer and around the tip portion; the redundant structure is used to receive the charge released by the tip portion.

[0060] Fig. 9 FIG. 1 is a top view of a connecting section with a tip portion in one embodiment of the present invention. Fig. 9 , the cascade line L0 extends along the direction 91. The cascade line L0 may include a plurality of connection segments L01, and each connection segment L01 is distributed along the direction 91. Each connection segment L01 has a tip portion L01a at one end close to the cutting line.

[0061] The tip portion L01a has a sharp corner, and the shape of the sharp corner includes but is not limited to a triangle, and can be a sawtooth or other angular shapes. The charge accumulated on the connecting section L01 can be discharged through the tip portion L01a.

[0062] On the array substrate, a redundant structure 92 can be provided in the semiconductor layer below the metal layer where the cascade line L0 is located. The redundant structure 92 is not connected to any signal line, so that the connection segment L01 can release the accumulated charge without damaging other lines or effective devices.

[0063] Fig.10 FIG. 2 is another schematic cross-sectional structure diagram of an array substrate along a cutting direction in an embodiment of the present invention. Fig.10 ,and Figure 8 The difference between the array substrate structure and Fig.10In the embodiment, the array substrate may further include an active layer 76. The active layer 76 is located on the surface of the buffer layer 72 and below the first metal layer 73. A redundant structure is disposed in the active layer 76.

[0064] In a specific implementation, the redundant structure can be a redundant resistor or other structure capable of absorbing electrostatic charge. The redundant structure is located around the tip of the connecting section, and the specific location is not limited as long as it can receive the charge released by the tip.

[0065] In a specific implementation, the same redundant structure can be located below at least one tip portion L01a, for example, the same redundant structure can be located below the tip portions L01a of two adjacent connecting segments, or can be located below the tip portions L01a of three adjacent connecting segments. When the redundant structure is located below the tip portions L01a of multiple connecting segments, it can receive the charges released by the multiple tip portions L01a.

[0066] In one embodiment of the present invention, for the same cascade line, a corresponding redundant structure may be provided for the tip of each connection segment, that is, the redundant structure and the tip are provided in a one-to-one correspondence. Fig. 9 , a corresponding redundant structure 72 may be provided for the tip portion L01a of each connection segment L01. When the connection segments of the same cascade line are distributed on more than two metal layers, a corresponding semiconductor layer may be provided below the two or more metal layers to form a redundant structure 72. This allows the charge released by the tip portion to be more completely received.

[0067] In one embodiment of the present invention, in order to allow the charge released by the connecting segment to be more completely absorbed by the redundant structure, a redundant structure may be provided to surround the corresponding tip portion. Fig. 9 As shown, the redundant structure can form an opening toward the tip portion, and the tip portion is aligned with the inside of the opening, which can be more conducive to electrostatic discharge.

[0068] In a specific implementation, two adjacent signal generating circuits may be connected via two or more cascade lines, and each cascade line is used to input the same control signal to the connected signal generating circuit. Each cascade line may include multiple connecting segments. The connecting segments of each cascade line may be distributed along the original direction of the cascade line. The lengths of the connecting segments of each cascade line may be the same or different. The connecting segments of the same cascade line may be distributed in different metal layers, and the specific implementation may refer to the above description of the setting of the connecting segments in the same cascade line, which will not be repeated here.

[0069] For example, each cascade line may include a first connection segment and a second connection segment, the first connection segments of all cascade lines are located in the first metal layer, and the second connection segments of all cascade lines are located in the second metal layer. Two adjacent first connection segments of the same cascade line are connected through the second connection segment of the cascade line.

[0070] In one embodiment of the present invention, in order to reduce electrostatic conduction of the same metal layer between adjacent traces, the connection segments of two adjacent cascade lines in the same metal layer of the array substrate may be arranged to be staggered in the metal layer.

[0071] For example, refer to Fig.11 , two adjacent signal generating circuits are connected by four cascade lines, namely the first cascade line L1, the second cascade line L2, the third cascade line L3 and the fourth cascade line L4, and these four cascade lines are arranged in sequence along the direction Y perpendicular to the cutting line HH'. Among them, 111 represents the original routing direction of the first cascade line L1, 112 represents the original routing direction of the second cascade line L2, 113 represents the original routing direction of the third cascade line L3, and 114 represents the original routing direction of the fourth cascade line L4. The first cascade line L1 has a first connection segment L11 distributed in the first metal layer, the second cascade line L2 has a first connection segment L21 distributed in the first metal layer, the third cascade line L3 has a first connection segment L31 distributed in the first metal layer, and the fourth cascade line L4 has a first connection segment L41 distributed in the first metal layer.

[0072] The first connecting segment L11, the first connecting segment L21, the first connecting segment L31 and the first connecting segment L41 are staggered and distributed in the first metal layer, that is, the first connecting segment L21 corresponds to the interval between adjacent first connecting segments L11, the first connecting segment L31 corresponds to the interval between adjacent first connecting segments L21, and the first connecting segment L41 corresponds to the interval between adjacent first connecting segments L31.

[0073] The other connection segments of each level of the connection line may be located in the second metal layer or in the third metal layer, which is not limited here.

[0074] In one embodiment of the present invention, the array substrate includes a first metal layer and a second metal layer which are stacked. In this case, the connection segments of two adjacent cascade lines in the first metal layer may be arranged to be staggered in the first metal layer, and the connection segments of two adjacent cascade lines in the second metal layer may be arranged to be staggered in the second metal layer.

[0075] Specifically, each cascade line may include a first connection segment and a second connection segment, the first connection segment of each level of cascade line is located in the first metal layer, and the second connection segment of each level of cascade line is located in the second metal layer. Fig. 9The second connecting segment located in the second metal layer can be as shown in FIG. Fig. 9 As shown, staggered distribution.

[0076] At this time, the array substrate only has two metal layers, which can not only reduce the electrostatic charge density in each metal layer, but also reduce the electrostatic conduction between adjacent traces in the same metal layer, thereby further reducing the impact of static electricity on signal lines or devices connected to the signal lines, and further improving the yield of the array substrate.

[0077] The inventors have found through research that the closer the cascade line is to the cutting line, the higher the static charge accumulated, and the more likely it is that the device will be damaged due to the concentrated release of static electricity at a single point.

[0078] To this end, in an embodiment of the present invention, the number of connection segments in each cascade line may be set according to the distance from the cascade line to the cutting line.

[0079] Specifically, in each level of the connection line of two adjacent signal generating circuits, it can be set that as the distance from the cascade line to the cutting line increases, the number of connection segments in the cascade line gradually decreases. That is to say, in the same metal layer, the farther the cascade line is from the cutting line, the fewer the number of connection segments, and the closer the cascade line is to the cutting line, the more the number of connection segments. The connection segments of each level of the connection line are not limited to being distributed only in the first metal layer and the second metal layer, and can also include the third metal layer or the fourth metal layer, etc. For any metal layer, the number of connection segments of each level of the connection line in the metal layer can be set according to the distance from the cutting line.

[0080] For example, refer to Fig.12 , in the first metal layer, the number of connection segments L11 belonging to the first cascade line L1 can be n, the number of connection segments L21 belonging to the second cascade line L2 can be na, the number of connection segments L31 belonging to the third cascade line L3 can be nb, and the number of connection segments L41 belonging to the fourth cascade line L4 can be nc. At this time, n>na>nb>nc can be set, where n, a, b, and c are all positive integers.

[0081] By setting the number of connection segments of the cascade lines close to the cutting line to be greater than the number of connection segments of the cascade lines far from the cutting line, the number of connection segments can be flexibly adjusted according to the degree of electrostatic charge concentration, thereby reducing the complexity of the cascade line implementation while increasing the electrostatic charge density in the array substrate.

[0082] From the above content, it can be known that the array substrate in the embodiment of the present invention can effectively reduce static electricity accumulation and reduce the electrostatic charge density in the array substrate by dividing the long traces between the signal generating circuits into multiple short traces, thereby avoiding single-point electrostatic damage. In addition, by designing the shape of the short traces to be a sharp-cornered shape and providing a redundant structure under the sharp corners, the charge can be released without damaging the useful circuits.

[0083] An embodiment of the present invention further provides a display panel, which includes any one of the above array substrates.

[0084] In a specific implementation, the display panel may further include a plurality of light-emitting elements. At least some of the electronic components in the array substrate constitute a plurality of pixel drive circuits arranged in an array. Each pixel drive circuit is connected to each light-emitting element. The light-emitting element includes but is not limited to light-emitting diodes (LEDs) and other light-emitting devices.

[0085] In some embodiments, the light-emitting element includes a mini LED or a micro LED. Mini LED has a smaller size, so that the display panel can accommodate a larger number of light-emitting elements while maintaining the same area, so as to improve the display brightness and display effect of the display panel. Micro LED introduces electron excitation in semiconductor materials to generate photoluminescence, thereby achieving a display effect. This technology can achieve extremely high pixel density and resolution, and has the characteristics of high brightness, high contrast and fast response, so as to improve the display effect of the display panel.

[0086] In some embodiments, the pixel driving circuit may include active electronic components and / or passive electronic components. The active electronic components include transistors, etc., and the passive electronic components include resistors, capacitors, inductors, etc. The pixel driving circuit can drive the light-emitting elements to display light.

[0087] Specifically, the pixel driving circuit can provide an electrical signal to the light emitting device, and can control the color and brightness of the light emitted by the light emitting device by controlling the signal applied to the light emitting device, so as to drive the light emitting device to display light. The electrical signal provided to the light emitting device can be a voltage or a current.

[0088] Fig.13 Schematic diagram of a circuit structure of a pixel circuit. Fig.13, the pixel circuit includes a pixel driving circuit and a light emitting device. The pixel driving circuit may include: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8. One end of the first transistor M1 is connected to the first power signal PVDD, and one end of the second transistor M2 is connected to the data signal Vdata. The other ends of the first transistor M1 and the second transistor M2 are connected to the third transistor M3. The gate of the third transistor M3 is connected to one end of the fifth transistor M5, the other end of the fifth transistor M5 is connected to the reset signal Vref, and the gate of the fifth transistor M5 is connected to the first scanning signal S1. The other end of the third transistor M3 is connected to one end of the fourth transistor M4 and the sixth transistor M6. The gate of the fourth transistor M4 and the gate of the second transistor M2 are both connected to the second scanning signal S2. The gate of the sixth transistor M6 is connected to the light emitting control signal Emit. The other end of the sixth transistor M6 is connected to the light emitting device and one end of the seventh transistor M7. The other end of the seventh transistor M7 is connected to the reset signal Vref. The gate of the seventh transistor M7 is connected to the first scanning signal S1. The other end of the light emitting device is connected to the second power signal PVEE.

[0089] The reset signal Vref is used to reset the node N1, and the first power signal PVDD and the second power signal PVEE are used to provide corresponding power supply voltages. The first scan signal S1 and the second scan signal S2 are used to control the connected transistor to be turned on or off to achieve the writing of the data signal Vdata. The light emitting control signal Emit is used to control the light emitting device to emit light.

[0090] The signals required by the pixel circuit include: a first power signal PVDD, a data signal Vdata, a reset signal Vref, a first scan signal S1, a second scan signal S2, a light emitting control signal Emit and a second power signal PVEE. These signals can be provided by the signal generating circuit in the embodiment of the present invention.

[0091] In some other embodiments, the display panel may be a liquid crystal display (LCD), in which case the light emitting element includes but is not limited to a thin film field effect transistor (TFT).

[0092] In a specific implementation, the pixel driving structure of the thin film field effect transistor generally includes: a data line (Data Line, also called Source Line) and a scan line (Gate Line, also called Gate Line).

[0093] Specifically, Fig.14As shown, the pixel unit array of the liquid crystal display screen includes a plurality of data lines and a plurality of scan lines. The data lines are arranged in a vertical direction and are parallel to each other. Figure 1 The data lines D1, D2, D3, ..., D M-2 , data line D M-1 , data line D M , where M is a positive integer. The scanning lines are arranged in the transverse direction and are parallel to each other, such as Figure 1 The scanning lines G1, G2, G3, ..., G N-2 , Scan line G N-1 , Scan line G N , wherein N is a positive integer. The plurality of data lines and the plurality of scan lines intersect to define a plurality of sub-pixels, and the plurality of sub-pixels are arranged in a matrix.

[0094] Each sub-pixel can be one of the three sub-pixels of red (abbreviated as R), green (abbreviated as G), and blue (abbreviated as B). At the same time, in the sub-pixel matrix structure, the three sub-pixels R, G, and B are arranged cyclically along the direction of the scan line, and the three adjacent sub-pixels R, G, and B can form a pixel circuit. The three sub-pixels in the same pixel circuit share a data line and are respectively connected to the three scan lines. For example, the three sub-pixels R, G, and B connected to the data line D1 are respectively connected to different scan lines G1, G2, and G3.

[0095] The signals required by the pixel circuit include: input signals of each data line and input signals of each scanning line. These signals can be provided by the signal generating circuit in the embodiment of the present invention.

[0096] Since the cascade lines between the signal generating circuits in the embodiment of the present invention are divided into multiple connecting segments, static electricity accumulation can be reduced, thereby preventing the pixel circuit and the signal lines connecting the signal generating circuit and the pixel circuit from being damaged by static electricity, thereby improving the display stability.

[0097] An embodiment of the present invention further provides a display device, which includes the display panel in the above embodiment.

[0098] In a specific implementation, the display device includes but is not limited to any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0099] An embodiment of the present invention further provides a vehicle-mounted terminal, which includes the display device in the above embodiment.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An array substrate, characterized in that: include: A display area and a non-display area outside the display area; the display area includes a plurality of pixel circuits, and the non-display area includes more than two signal generating circuits; the signal generating circuit is used to provide required signals for the pixel circuits in the display area; Wherein, any one-level interconnection line between two adjacent signal generating circuits comprises: more than two interconnected connecting segments; the more than two interconnected connecting segments are located in different metal layers of the array substrate.

2. The array substrate according to claim 1, characterized in that: In the two or more interconnected connecting segments, two adjacent connecting segments are located in different metal layers.

3. The array substrate according to claim 1 or 2, characterized in that: The cascade line includes: more than two first connecting segments and second connecting segments; the more than two first connecting segments are located in the same metal layer, and the second connecting segment is used to connect two adjacent first connecting segments; the metal layer where the second connecting segment is located is different from the metal layer where the first connecting segment is located.

4. The array substrate according to claim 3, characterized in that: The array substrate includes a first metal layer and a second metal layer which are stacked; the first connecting section is located in the first metal layer, and the second connecting section is located in the second metal layer.

5. The array substrate according to claim 1, wherein: Two adjacent signal generating circuits are connected via two or more cascade lines, wherein the connection sections of two adjacent cascade lines located in the same metal layer of the array substrate are staggeredly distributed in the metal layer.

6. The array substrate according to claim 5, characterized in that: The array substrate includes a first metal layer and a second metal layer which are stacked; the connection segments of two adjacent cascade lines in the first metal layer are staggered in the first metal layer; the connection segments of two adjacent cascade lines in the second metal layer are staggered in the second metal layer.

7. The array substrate according to claim 1, wherein: The connecting section is in a straight line shape.

8. The array substrate according to claim 1, 2 or 4, characterized in that: Along the distribution direction of the display area and the non-display area, the connection segment located in the bottom metal layer of the array substrate has a tip portion at one end close to the cutting line; The array substrate further comprises: a redundant structure located in the semiconductor layer below the bottom metal layer and around the tip portion; the redundant structure is used to receive the charge released by the tip portion.

9. The array substrate according to claim 8, characterized in that: The redundant structure is a redundant resistor.

10. The array substrate according to claim 9, characterized in that: The redundant structure is located around the tip portion and surrounds the tip portion.

11. The array substrate according to claim 8, characterized in that: The redundant structures are arranged in one-to-one correspondence with the tip portions.

12. The array substrate according to claim 1, 2 or 4, characterized in that: The number of connection segments in the cascade line is related to the distance from the cascade line to the cutting line.

13. The array substrate according to claim 12, characterized in that: In each level of the cascade lines of two adjacent signal generating circuits, as the distance between the cascade line and the cutting line increases, the number of connection segments in the cascade line gradually decreases.

14. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 13.

15. A display device, characterized in that: Comprising the display panel as claimed in claim 14.

16. A vehicle-mounted terminal, characterized in that: Includes the display device as claimed in claim 15.

Images