High-efficiency perovskite-crystalline silicon two-end laminated battery assembly and preparation method thereof

Abstract

The invention relates to the technical field of laminated cells, in particular to a high-efficiency perovskite-crystalline silicon two-end laminated cell assembly and a preparation method thereof, and the high-efficiency perovskite-crystalline silicon two-end laminated cell assembly comprises a top cell and a bottom cell; the top cell sequentially comprises a top electrode, an anti-reflection layer, a first conductive layer, a buffer layer, a dual-electron transport layer, a perovskite absorption layer, a hole transport layer and a second conductive layer; the bottom cell sequentially comprises an n-type doped layer, a first silicon oxide layer, a suede silicon substrate, a second silicon oxide layer, a p-type doped layer and a bottom electrode. The broadband gap perovskite absorption layer is improved through the synergistic effect of the lead thiocyanate and the dimethyl sulfoxide, the lead thiocyanate is introduced into the perovskite precursor solution, the crystallization rate of perovskite can be slowed down, grain growth is promoted, the grain size is increased, the number of grain boundaries is reduced, the surface of the perovskite thin film is reconstructed in the curing process, and the performance of the perovskite thin film is improved. The generation of excessive lead iodide caused by SCN-volatilization is inhibited, and the performance of the perovskite absorption layer can be improved through the synergistic effect of the two, so that the quality of the laminated cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of laminated batteries, and in particular to a high-efficiency perovskite-crystalline silicon two-terminal laminated battery assembly and a preparation method thereof. Background Art

[0002] With the continuous growth of global energy demand and the increasing concern about the environmental problems caused by traditional fossil energy, solar energy has received widespread attention as a clean and renewable energy source. Photovoltaic technology is the key technology for converting solar energy into electrical energy. Improving the efficiency of photovoltaic cells and reducing costs are the main goals of its development. Crystalline silicon solar cells are currently the most widely used photovoltaic technology. They have the advantages of high efficiency and good stability. However, the theoretical efficiency limit of single-crystal silicon cells limits the room for further improvement. At present, the laboratory efficiency of single-crystal silicon cells is close to its theoretical limit, and the efficiency of industrially produced single-crystal silicon cells is difficult to be significantly improved.

[0003] As an emerging material in the photovoltaic field, perovskite material has excellent optical and electrical properties. For example, it has a high absorption coefficient and can absorb most of the sunlight at a very thin thickness, which makes perovskite material have great advantages in solar cell applications. The current perovskite / crystalline silicon tandem cell combines the characteristics of perovskite material's strong absorption ability for short-wavelength light and crystalline silicon material's strong absorption ability for long-wavelength light, but due to the limitations of the perovskite material itself and the tandem structure, the improvement of photoelectric conversion efficiency is limited. Based on this, a high-efficiency perovskite-crystalline silicon two-terminal tandem cell assembly and its preparation method are proposed. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a high-efficiency perovskite-crystalline silicon two-terminal laminated battery assembly and a preparation method thereof, which improves the quality of the laminated battery by improving the layer structure, thereby making it have a higher conversion efficiency.

[0005] To achieve the above-mentioned object, the present invention provides the following technical solutions: a high-efficiency perovskite-crystalline silicon two-terminal stacked cell assembly, comprising a top cell and a bottom cell;

[0006] The top cell includes, in sequence, a top electrode, an anti-reflection layer, a first conductive layer, a buffer layer, a double electron transport layer, a perovskite absorption layer, a hole transport layer, and a second conductive layer;

[0007] The bottom cell comprises an n-type doping layer, a first silicon oxide layer, a textured silicon substrate, a second silicon oxide layer, a p-type doping layer and a bottom electrode in sequence.

[0008] Preferably, the anti-reflection layer is a magnesium fluoride layer; the top electrode and the bottom electrode are both silver electrodes; the buffer layer is a titanium dioxide layer or an ion chelating polymer layer; the first conductive layer and the second conductive layer are both indium zinc oxide layers; and the hole transport layer is a nickel oxide layer.

[0009] Preferably, the preparation method of the perovskite absorption layer is as follows: add lead thiocyanate (Pb(SCN)2) to the perovskite precursor solution, spin-coat it onto the surface of the hole transport layer, then add chlorobenzene for extraction, and ripen it in a dimethyl sulfoxide atmosphere to obtain the perovskite absorption layer; the lead thiocyanate accounts for 1.5% of the mass of the perovskite precursor solution; the mass ratio of chlorobenzene to the perovskite precursor solution is 1.2:1.

[0010] Preferably, the double electron transport layer consists of a zinc oxide layer and a tin oxide layer.

[0011] Preferably, the preparation method of the ion chelating polymer layer is as follows: cobalt acetate tetrahydrate is placed in a 0.1wt% polyethoxyethyleneimine solution, the resulting mixed solution is spin-coated on the surface of the double electron transport layer, and after drying, the ion chelating polymer layer is obtained; the material-liquid ratio of the cobalt acetate tetrahydrate to the polyethoxyethyleneimine solution is 1:10 mg / mL.

[0012] Preferably, the preparation method of the velvet silicon substrate is as follows: immersing the silicon substrate in a mixed solution composed of copper nitrate, hydrofluoric acid and hydrogen peroxide, etching at 40°C for 3 minutes, and treating with nitric acid and sodium hydroxide in sequence after the etching is completed to obtain a velvet silicon substrate with an inverted pyramid structure; the concentration of the copper nitrate is 0.001 mol / L, the concentration of the hydrofluoric acid is 2 mol / L, and the concentration of the hydrogen peroxide is 2 mol / L.

[0013] Preferably, in the top battery, the thickness of the antireflection layer is 50-60nm, the thickness of the first conductive layer is 100-200nm, the thickness of the buffer layer is 20-30nm, the thickness of the double electron transport layer is 50-100nm, the thickness of the perovskite absorption layer is 1-2μm, the thickness of the hole transport layer is 50-80nm, and the thickness of the second conductive layer is 50-100nm; in the bottom battery, the thickness of the n-type doped layer is 80-120nm, the thickness of the first silicon oxide layer is 1-2nm, the thickness of the velvet silicon substrate is 200-250μm, the thickness of the second silicon oxide layer is 1-2nm, and the thickness of the p-type doped layer is 80-120nm.

[0014] Preferably, in the double electron transport layer, the thickness of the zinc oxide layer is 30-50 nm, and the thickness of the tin oxide layer is 20-50 nm.

[0015] The present invention also provides a method for preparing a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly, which is specifically: depositing an aluminum oxide film layer on the surface of a top battery; stacking a backplane layer, a second organic silica gel layer, a top battery with an aluminum oxide film layer-a bottom battery, a first organic silica gel layer and a glass layer in sequence from bottom to top, and then performing heating and lamination treatment to obtain a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly.

[0016] The present invention provides a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly and a preparation method thereof, which has the following beneficial effects compared with the prior art:

[0017] The present invention improves the wide bandgap perovskite absorption layer through the synergistic effect of lead thiocyanate and dimethyl sulfoxide, wherein the introduction of lead thiocyanate into the perovskite precursor solution can slow down the perovskite crystallization rate, promote grain growth, increase the grain size, reduce the number of grain boundaries, and reconstruct the surface of the perovskite film during the ripening process, thereby inhibiting the SCN - The excess lead iodide generated due to volatilization can improve the performance of the perovskite absorption layer through the synergistic effect of the two, thereby improving the quality of the stacked battery.

[0018] The present invention adopts a double electron transport layer composed of a zinc oxide layer and a tin oxide layer, which integrates the high conductivity of zinc oxide and the high electron extraction ability of tin oxide, and helps to further improve the quality of the stacked battery.

[0019] The present invention adopts a mixed solution of copper nitrate, hydrofluoric acid and hydrogen peroxide to etch a silicon substrate, thereby forming an inverted pyramid velvet surface thereon, which is convenient for subsequent spin coating of a perovskite solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 This is a schematic diagram of the top cell-bottom cell structure of the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly of the present invention;

[0023] Figure 3 It is a schematic diagram of the inverted pyramid pile surface and the upright pyramid of the present invention. DETAILED DESCRIPTION

[0024] The following examples are used to explain the implementation methods of the present application in detail, so that the implementation process of how the present application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0025] Example 1

[0026] The preparation method of the perovskite absorption layer is as follows: lead thiocyanate is added to the perovskite precursor solution, spin-coated onto the surface of the hole transport layer, then chlorobenzene is added dropwise for extraction, and ripened in a dimethyl sulfoxide atmosphere to obtain the perovskite absorption layer; lead thiocyanate accounts for 1.5% of the mass of the perovskite precursor solution; the mass ratio of chlorobenzene to the perovskite precursor solution is 1.2:1.

[0027] The above-mentioned perovskite precursor solution is prepared as follows: 15 parts of potassium iodide amidine, 3 parts of methylamine bromide, 5 parts of cesium iodide, 50 parts of lead iodide and 10 parts of lead bromide are weighed in parts by weight; the above-mentioned raw materials are poured into a mixed solvent (N,N-dimethylformamide and N-methylpyrrolidone in a volume ratio of 4:1) at a solid-liquid ratio of 4:5 g / mL, stirred to fully dissolve, and a perovskite precursor solution is obtained.

[0028] Example 2

[0029] The preparation method of the ion chelating polymer layer is as follows: cobalt acetate tetrahydrate is placed in a 0.1wt% polyethoxyethyleneimine solution, the resulting mixed solution is spin-coated on the surface of the double electron transport layer, and after drying, the ion chelating polymer layer is obtained; the material-liquid ratio of cobalt acetate tetrahydrate to polyethoxyethyleneimine solution is 1:10 mg / mL.

[0030] Example 3

[0031] The preparation method of the velvet silicon substrate is as follows: immersing the silicon substrate in a mixed solution composed of copper nitrate, hydrofluoric acid and hydrogen peroxide, etching at 40°C for 3 minutes, and treating with nitric acid and sodium hydroxide in sequence after the etching is completed, wherein the nitric acid treatment removes residual metal ions, and the sodium hydroxide treatment reconstructs the surface to remove surface defects, thereby obtaining a velvet silicon substrate with an inverted pyramid structure; the concentration of copper nitrate is 0.001 mol / L, the concentration of hydrofluoric acid is 2 mol / L, and the concentration of hydrogen peroxide is 2 mol / L.

[0032] Example 4

[0033] High-efficiency perovskite-crystalline silicon two-terminal stacked cell module, including top cell and bottom cell;

[0034] The top cell sequentially comprises a top electrode (silver electrode), an antireflection layer (magnesium fluoride layer), a first conductive layer (indium zinc oxide layer), a buffer layer (titanium dioxide layer), a double electron transport layer (zinc oxide layer and tin oxide layer), a perovskite absorption layer (obtained in Example 1), a hole transport layer (nickel oxide layer) and a second conductive layer (indium zinc oxide layer); the bottom cell sequentially comprises an n-type doped layer, a first silicon oxide layer, a velvet silicon substrate (obtained in Example 3), a second silicon oxide layer, a p-type doped layer and a bottom electrode (silver electrode).

[0035] The preparation method of the above-mentioned high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly is specifically as follows: an aluminum oxide film layer is deposited on the surface of the top battery; a backplane layer, a second organic silicone layer, a top battery with an aluminum oxide film layer-a bottom battery, a first organic silicone layer and a glass layer are stacked in sequence from bottom to top, and then a heating and lamination process is performed to obtain a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly.

[0036] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery component prepared in this embodiment has an anti-reflection layer with a thickness of 60nm, a first conductive layer with a thickness of 100nm, a buffer layer with a thickness of 30nm, a double electron transport layer (a zinc oxide layer with a thickness of 30nm, a tin oxide layer with a thickness of 20nm), a perovskite absorption layer with a thickness of 1μm, a hole transport layer with a thickness of 80nm, and a second conductive layer with a thickness of 100nm; the thickness of the n-type doped layer is 80nm, the thickness of the first silicon oxide layer is 2nm, the thickness of the velvet silicon substrate is 200μm, the thickness of the second silicon oxide layer is 2nm, and the thickness of the p-type doped layer is 80nm.

[0037] Example 5

[0038] High-efficiency perovskite-crystalline silicon two-terminal stacked cell module, including top cell and bottom cell;

[0039] The top cell sequentially comprises a top electrode (silver electrode), an antireflection layer (magnesium fluoride layer), a first conductive layer (indium zinc oxide layer), a buffer layer (the ion chelating polymer layer obtained in Example 2), a double electron transport layer (zinc oxide layer and tin oxide layer), a perovskite absorption layer (obtained in Example 1), a hole transport layer (nickel oxide layer) and a second conductive layer (indium zinc oxide layer); the bottom cell sequentially comprises an n-type doped layer, a first silicon oxide layer, a velvet silicon substrate (obtained in Example 3), a second silicon oxide layer, a p-type doped layer and a bottom electrode (silver electrode).

[0040] The preparation method of the above-mentioned high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly is specifically as follows: an aluminum oxide film layer is deposited on the surface of the top battery; a backplane layer, a second organic silicone layer, a top battery with an aluminum oxide film layer-a bottom battery, a first organic silicone layer and a glass layer are stacked in sequence from bottom to top, and then a heating and lamination process is performed to obtain a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly.

[0041] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery component prepared in this embodiment has an anti-reflection layer with a thickness of 50nm, a first conductive layer with a thickness of 200nm, a buffer layer with a thickness of 20nm, a double electron transport layer (a zinc oxide layer with a thickness of 50nm, a tin oxide layer with a thickness of 50nm), a perovskite absorption layer with a thickness of 2μm, a hole transport layer with a thickness of 50nm, and a second conductive layer with a thickness of 50nm; the thickness of the n-type doped layer is 120nm, the thickness of the first silicon oxide layer is 1nm, the thickness of the velvet silicon substrate is 250μm, the thickness of the second silicon oxide layer is 1nm, and the thickness of the p-type doped layer is 120nm.

[0042] Example 6

[0043] High-efficiency perovskite-crystalline silicon two-terminal stacked cell module, including top cell and bottom cell;

[0044] The top cell sequentially comprises a top electrode (silver electrode), an antireflection layer (magnesium fluoride layer), a first conductive layer (indium zinc oxide layer), a buffer layer (the ion chelating polymer layer obtained in Example 2), a double electron transport layer (zinc oxide layer and tin oxide layer), a perovskite absorption layer (obtained in Example 1), a hole transport layer (nickel oxide layer) and a second conductive layer (indium zinc oxide layer); the bottom cell sequentially comprises an n-type doped layer, a first silicon oxide layer, a velvet silicon substrate (obtained in Example 3), a second silicon oxide layer, a p-type doped layer and a bottom electrode (silver electrode).

[0045] The preparation method of the above-mentioned high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly is specifically as follows: an aluminum oxide film layer is deposited on the surface of the top battery; a backplane layer, a second organic silicone layer, a top battery with an aluminum oxide film layer-a bottom battery, a first organic silicone layer and a glass layer are stacked in sequence from bottom to top, and then a heating and lamination process is performed to obtain a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly.

[0046] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery component prepared in this embodiment has an anti-reflection layer with a thickness of 55nm, a first conductive layer with a thickness of 120nm, a buffer layer with a thickness of 25nm, a double electron transport layer (a zinc oxide layer with a thickness of 30nm, a tin oxide layer with a thickness of 20nm), a perovskite absorption layer with a thickness of 1.5μm, a hole transport layer with a thickness of 70nm, and a second conductive layer with a thickness of 80nm; the thickness of the n-type doped layer is 100nm, the thickness of the first silicon oxide layer is 1.5nm, the thickness of the velvet silicon substrate is 220μm, the thickness of the second silicon oxide layer is 2nm, and the thickness of the p-type doped layer is 100nm.

[0047] Comparative Example 1

[0048] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly is basically the same as Example 6, except that the perovskite precursor solution is directly spin-coated onto the surface of the hole transport layer, and after drying, the perovskite absorption layer is obtained.

[0049] Wherein, the preparation method of the perovskite precursor solution is the same as that in Example 1.

[0050] Comparative Example 2

[0051] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly is basically the same as Example 6, except that the buffer layer is set to a titanium dioxide layer.

[0052] Comparative Example 3

[0053] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery component is basically the same as Example 6, except that the double electron transport layer is set to a 50nm thick zinc oxide layer.

[0054] Comparative Example 4

[0055] The high-efficiency perovskite-crystalline silicon two-terminal stacked battery component is basically the same as Example 6, except that the double electron transport layer is set to a 50nm thick tin oxide layer.

[0056] Performance Testing

[0057] 1. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery components in Examples 4-6 and Comparative Examples 1-4 were used as test objects, and the battery performance was tested using the halm test sorting equipment. The halm machine is a device that simulates sunlight, and is equipped with electronic loads, data acquisition and computers to test the electrical performance of the stacked battery. The specific results are shown in the following table.

[0058] Table 1 Battery performance

[0059]

[0060]

[0061] From the above table, we can see that:

[0062] (1) Compared with Example 6, the perovskite absorption layer in Comparative Example 1 was not improved, resulting in a significant decrease in its conversion efficiency.

[0063] (2) Compared with Example 6, the buffer layer in Comparative Example 2 is a titanium dioxide layer, which results in a relatively low conversion efficiency, indicating that the ion chelating polymer layer helps to improve the performance of the laminated battery assembly.

[0064] (3) The conversion efficiency of the battery components in Comparative Examples 3 and 4 is slightly lower than that in Example 6, indicating that compared with the single electron transport layer, the double electron transport layer can improve the performance of the stacked battery to a certain extent.

[0065] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. High-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly, characterized by: Includes top cell and bottom cell; The top cell includes, in sequence, a top electrode, an anti-reflection layer, a first conductive layer, a buffer layer, a double electron transport layer, a perovskite absorption layer, a hole transport layer, and a second conductive layer; The bottom cell comprises an n-type doping layer, a first silicon oxide layer, a textured silicon substrate, a second silicon oxide layer, a p-type doping layer and a bottom electrode in sequence.

2. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 1 is characterized in that: The anti-reflection layer is a magnesium fluoride layer; the top electrode and the bottom electrode are both silver electrodes; the buffer layer is a titanium dioxide layer or an ion chelating polymer layer; the first conductive layer and the second conductive layer are both indium zinc oxide layers; and the hole transport layer is a nickel oxide layer.

3. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 2, characterized in that: The preparation method of the perovskite absorption layer is as follows: adding lead thiocyanate to the perovskite precursor solution, spin coating it onto the surface of the hole transport layer, then dripping chlorobenzene for extraction, and ripening in a dimethyl sulfoxide atmosphere to obtain the perovskite absorption layer; The lead thiocyanate accounts for 1.5% of the mass of the perovskite precursor solution; the mass ratio of chlorobenzene to the perovskite precursor solution is 1.2:

1.

4. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 1, characterized in that: The double electron transport layer consists of a zinc oxide layer and a tin oxide layer.

5. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 2, characterized in that: The preparation method of the ion chelating polymer layer is as follows: cobalt acetate tetrahydrate is placed in a 0.1wt% polyethoxyethyleneimine solution, the resulting mixed solution is spin-coated on the surface of the double electron transport layer, and after drying, the ion chelating polymer layer is obtained; The solid-liquid ratio of the cobalt acetate tetrahydrate to the polyethoxyethyleneimine solution is 1:10 mg / mL.

6. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 1, characterized in that: The preparation method of the suede silicon substrate is as follows: immersing the silicon substrate in a mixed solution of copper nitrate, hydrofluoric acid and hydrogen peroxide, etching at 40° C. for 3 minutes, and treating with nitric acid and sodium hydroxide in sequence after the etching is completed to obtain a suede silicon substrate with an inverted pyramid structure; The concentration of the copper nitrate is 0.001 mol / L, the concentration of the hydrofluoric acid is 2 mol / L, and the concentration of the hydrogen peroxide is 2 mol / L.

7. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 4, characterized in that: In the top cell, the thickness of the antireflection layer is 50-60nm, the thickness of the first conductive layer is 100-200nm, the thickness of the buffer layer is 20-30nm, the thickness of the double electron transport layer is 50-100nm, the thickness of the perovskite absorption layer is 1-2μm, the thickness of the hole transport layer is 50-80nm, and the thickness of the second conductive layer is 50-100nm; In the bottom cell, the thickness of the n-type doped layer is 80-120nm, the thickness of the first silicon oxide layer is 1-2nm, the thickness of the textured silicon substrate is 200-250μm, the thickness of the second silicon oxide layer is 1-2nm, and the thickness of the p-type doped layer is 80-120nm.

8. The high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to claim 7, characterized in that: In the double electron transport layer, the thickness of the zinc oxide layer is 30-50 nm, and the thickness of the tin oxide layer is 20-50 nm.

9. The method for preparing a high-efficiency perovskite-crystalline silicon two-terminal stacked battery assembly according to any one of claims 1 to 8, characterized in that: Specifically, an aluminum oxide film layer is deposited on the surface of the top battery; a backplane layer, a second organic silicone layer, a top battery with an aluminum oxide film layer-a bottom battery, a first organic silicone layer and a glass layer are stacked from bottom to top, and then heated and laminated to obtain a high-efficiency perovskite-crystalline silicon two-terminal stacked battery component.

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