Calibrating signal current in radio frequency signal generator

Abstract

Techniques are provided for calibrating a signal current in a radio frequency signal generator system, such as an arbitrary waveform generator system. An apparatus includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of the radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during a calibration process. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

Description

Background Art

[0001] The present disclosure relates generally to radio frequency (RF) signal generators, and techniques for calibrating RF signal generators, such as arbitrary waveform generator (AWG) systems. For various applications, the RF signal generator includes an orthogonal architecture in which a baseband signal is up-converted to an RF signal using a single sideband (SSB) modulation system that modulates a quadrature local oscillator (LO) signal using a quadrature baseband signal. For SSB modulation, generating a high-fidelity RF signal with no LO leakage or sideband image spurs (or significantly suppressed spurs) requires precise amplitude and phase balance between in-phase (I) and quadrature-phase (Q) signal components. More specifically, amplitude and phase imbalances between quadrature I / Q signal components may result in degraded image rejection performance, which results in the presence of unwanted sideband spurs. In addition, positive and negative components in the same phase (e.g., I + and I - ) can cause LO leakage spurs. Measuring and calibrating I / Q imbalance is especially important when the signal paths for the I and Q channels are implemented using single-ended baseband filter structures. Single-ended filter components can have inherent amplitude imbalances that can impair RF performance due to component mismatch.

[0002] Conventional techniques for detecting and calibrating amplitude and phase imbalances of I / Q signals in RF signal generators typically utilize on-chip or off-chip calibration instruments that are configured to perform RF measurements to analyze the RF output signal generated by the RF signal generator. For example, a conventional on-chip calibration instrument implements an RF down-conversion receiver that is disposed in a feedback path of a transmitter and configured to extract a baseband signal component from the RF output signal. The on-chip calibration instrument compensates for the imbalance detected in the extracted baseband signal component. In addition, conventional on-chip and off-chip calibration instruments may be implemented using complex spectrum analyzer systems and circuits. Conventional calibration systems that perform RF measurements are significantly expensive in terms of hardware complexity, resource usage, and area overhead required for on-chip implementation. In addition, conventional calibration systems that perform RF measurements consume a large amount of power, which is prohibited at cryogenic temperatures. Summary of the invention

[0003] Exemplary embodiments of the present disclosure include techniques for calibrating signal currents in an RF signal generator system, such as an AWG system.

[0004] In an exemplary embodiment, a device includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of a radio frequency signal generator during a calibration process and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

[0005] Advantageously, compared to conventional calibration techniques that perform RF measurements to analyze an RF output signal generated by an RF signal generator, calibration techniques according to exemplary embodiments of the present disclosure implement current measurement circuitry to measure a signal current (e.g., a DC baseband current) generated in a signal path of an RF signal generator during a calibration process, wherein such baseband signal current measurements are significantly less costly in terms of hardware complexity and computational resources required for calibration than calibration systems that analyze an RF output signal generated by an RF signal generator. In addition, the current measurement circuitry can operate at very low power (e.g., on the order of milliwatts or less) and have a relatively low footprint (occupying a small chip area), which is advantageous for on-chip implementation and cryogenic control electronics for quantum computing applications.

[0006] Another advantage is that for quadrature RF signal generator architectures utilizing I / Q signals, the same current measurement circuit can be used to measure all components of the I / Q baseband signal (e.g., I + ,I - , Q + , Q - ). In this regard, the current measurement is insensitive to the inherent offset of the current measurement circuitry, and thus inaccuracies in the current measurement circuitry will not adversely affect the accuracy of the measurement because any inherent offset in the current measurement circuitry will be applied to all signal current measurements, which effectively cancels out such inherent errors when determining the difference between the measured currents.

[0007] Another exemplary embodiment includes a system comprising a radio frequency signal generator and a calibration system. The radio frequency signal generator is configured to convert a baseband signal into a radio frequency signal. The radio frequency signal generator includes a first signal path for processing a first signal component of the baseband signal and a second signal path for processing a second signal component of the baseband signal. The calibration system is configured to perform a calibration process to calibrate the radio frequency signal generator. The calibration system includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of the radio frequency signal generator during the calibration process and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

[0008] Another exemplary embodiment includes a system including a quantum processor, an arbitrary waveform generator system, and a calibration system. The quantum processor includes at least one superconducting qubit. The arbitrary waveform generator system includes at least one arbitrary waveform generator channel configured to convert a baseband signal into a radio frequency control pulse that controls at least one superconducting qubit. At least one arbitrary waveform generator channel includes a first signal path for processing a first signal component of the baseband signal and a second signal path for processing a second signal component of the baseband signal. The calibration system is configured to perform a calibration process to calibrate at least one arbitrary waveform generator channel. The calibration system includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of at least one arbitrary waveform generator channel during the calibration process, and to measure a second current in a second signal path of at least one arbitrary waveform generator channel. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the at least one arbitrary waveform generator channel to correct an imbalance between the measured first current and the measured second current.

[0009] Another exemplary embodiment as may be combined with the previous paragraphs includes a control circuit configured to determine a difference between a measured first current and a measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to a current imbalance correction circuit. In response to the control signal, the current imbalance correction circuit is configured to inject a current into at least one of the first signal path and the second signal path of the radio frequency signal generator to compensate for the determined difference between the measured first current and the measured second current.

[0010] In another exemplary embodiment, as may be combined with the preceding paragraphs, the current measurement circuit includes a current mode digital-to-analog converter circuit and a current comparator circuit. The current mode digital-to-analog converter circuit is configured to generate a reference current. The current comparator circuit is configured to receive one of a first current and a second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal. The current mode digital-to-analog converter circuit is configured to increase or decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

[0011] In another exemplary embodiment, as can be combined with the preceding paragraph, a current comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a voltage comparator. The first transistor includes a drain terminal coupled to an input node of the comparator circuit, a source terminal coupled to a power supply node, and a gate terminal coupled to the first node. The first switch is coupled between the input node and the first node. The second switch is coupled between the first node and the power supply node. The second transistor includes a gate terminal coupled to the first node, a source terminal coupled to the power supply node, and a drain terminal coupled to the second node. The voltage comparator includes a first input terminal coupled to a threshold voltage node and a second input terminal coupled to the second node. The output of the current mode digital-to-analog converter circuit is coupled to the second node. During a calibration process, the first switch is activated to configure the first transistor as a diode-connected transistor by coupling the gate terminal and the drain terminal of the first transistor, and the second switch is deactivated to enable the input current to flow into the current measurement circuit.

[0012] In another exemplary embodiment, as may be combined with the preceding paragraph, the current comparator circuit further comprises a low pass filter circuit configured to enable the current comparator circuit to measure a direct current (DC) offset component of an alternating current (AC) input current. The low pass filter circuit is one of: (i) coupled between the first node and a gate terminal of the second transistor, and (ii) coupled to a second input terminal of the voltage comparator.

[0013] Another exemplary embodiment includes a computer program product for performing a calibration process to calibrate a radio frequency signal generator. The computer program product includes one or more computer-readable storage media, and program instructions stored together on the one or more computer-readable storage media. The program instructions include program instructions for configuring a current measurement circuit to measure a first current in a first signal path of the radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during the calibration process; and program instructions for configuring a current imbalance correction circuit to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

[0014] Another exemplary embodiment includes a method comprising: measuring a first current in a first signal path of a radio frequency signal generator; measuring a second current in a second signal path of the radio frequency signal generator; and adjusting a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

[0015] Other embodiments will be described in the following detailed description of exemplary embodiments, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A radio frequency signal generator system and a calibration system according to an exemplary embodiment of the present disclosure are schematically shown. The calibration system is configured to calibrate a baseband signal in the radio frequency signal generator system.

[0017] Figure 2 A radio frequency signal generator system and a calibration system according to another exemplary embodiment of the present disclosure are schematically shown. The calibration system is configured to calibrate a baseband signal in the radio frequency signal generator system.

[0018] Figure 3 A current measurement circuit implemented by a calibration system to measure a baseband current according to an exemplary embodiment of the present disclosure is schematically illustrated.

[0019] Figure 4A , 4B 4C schematically shows an exemplary embodiment of the present disclosure that can be Figure 3 A current mode digital-to-analog converter circuit is implemented in a current measurement circuit.

[0020] Figure 5 A local oscillator signal output configuration circuit according to an exemplary embodiment of the present disclosure is schematically shown.

[0021] Figure 6 A setup table for configuring a radio frequency signal generator system and a calibration system in a calibration mode to measure various baseband currents according to an exemplary embodiment of the present disclosure is shown.

[0022] Fig. 7A and 7B A process for calibrating baseband current in a radio frequency signal generator system according to an exemplary embodiment of the present disclosure is shown.

[0023] Figure 8 A current measurement circuit according to an exemplary embodiment of the present disclosure is schematically shown, which is implemented by a calibration system to measure a DC component of an up-converted radio frequency current signal.

[0024] Fig. 9 A current measurement circuit according to another exemplary embodiment of the present disclosure is schematically shown, and the current measurement circuit is implemented by a calibration system to measure a DC component of an up-converted radio frequency current signal.

[0025] Fig.10 A quantum computing system implementing an arbitrary waveform generator system and a calibration circuit according to an exemplary embodiment of the present disclosure is schematically illustrated.

[0026] Fig.11 A quantum computing system according to another exemplary embodiment of the present disclosure is schematically shown.

[0027] Fig.12 An exemplary computing environment configured to execute program instructions for controlling a calibration process of a calibration system according to an exemplary embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with respect to systems and methods for calibrating signal currents in RF signal generator systems (such as AWG systems). It should be understood that the various features shown in the accompanying drawings are schematic diagrams that are not drawn to scale. In addition, the same or similar reference numerals are used throughout the accompanying drawings to represent the same or similar features, elements, or structures, and therefore, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each drawing. In addition, the term "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not be construed as being preferred or advantageous over other embodiments or designs.

[0029] In addition, it should be understood that the phrase "configured to" used in conjunction with circuits, structures, elements, components, etc. that perform one or more functions or otherwise provide some functions is intended to cover embodiments in which the circuits, structures, elements, components, etc. are implemented in hardware, software, and / or a combination thereof, as well as implementations including hardware, where the hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) chips, field programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), one or more integrated circuits, and / or a combination thereof. Therefore, by way of example only, when a circuit, structure, element, component, etc. is configured to implement the present invention, it may be configured to implement the present invention. For example, although defined as being configured to provide a specific function, it is intended to cover but not be limited to embodiments in which the circuits, structures, elements, components, etc. A circuit, structure, element, component, etc., when in a non-operating state (e.g., not connected or otherwise deployed in a system, not powered, not receiving input and / or not generating output) or in a partially operational state, includes elements, processing devices and / or integrated circuits that enable it to perform specific functions.

[0030] Figure 1 The RF signal generator system and the calibration system according to an exemplary embodiment of the present disclosure are schematically shown, and the calibration system is configured to calibrate the baseband current in the signal path of the RF signal generator system. Specifically, Figure 1 Schematically illustrated is an RF signal generator system 100, which includes a baseband I / Q signal generator 110, a digital-to-analog converter stage 120 (or DAC stage 120), a baseband filter stage 130, a mixer stage 140, an amplifier stage 150, an impedance matching network 160, a local oscillator (LO) signal generator circuit 170, and an LO signal output configuration circuit 180, the functions of which will be explained in further detail below. A calibration system 190 includes a current measurement circuit 192, a current imbalance correction circuit 194, and a calibration control circuit 196, the functions of which will be explained in further detail below.

[0031] like Figure 1, the DAC stage 120 includes an input coupled to the output of the baseband I / Q signal generator 110. The baseband filter stage 130 includes an input coupled to the output of the DAC stage 120. The mixer stage 140 includes an input coupled to the output of the baseband filter stage 130. The amplifier stage 150 includes an input coupled to the output of the mixer stage 140, and an output coupled to the input of the impedance matching network 160, and the output of the impedance matching network 160 is coupled to the output node (RF_OUT) of the RF signal generator system 100. The LO signal generator circuit 170 is configured to generate an LO signal (e.g., a quadrature LO signal) that is used by the mixer stage 140 to perform amplitude modulation of the in-phase LO signal (LO_I) and the quadrature-phase LO signal (LO_Q). The LO signal output configuration circuit 180 is configured to control the input of the LO signal to the mixer stage 140 for different operating modes (eg, real-time operating mode and calibration mode) of the RF signal generator system 100, as will be discussed in further detail below.

[0032] It should be understood that the RF signal generator system 100 can be implemented for various applications. For example, in some embodiments, the RF signal generator system 100 includes an RF transmitter for wireless applications, wherein the output of the RF signal generator system 100 is coupled to an antenna system, which is configured to transmit the RF output signal generated by the RF signal generator system 100. In other embodiments, the RF signal generator system 100 includes a waveform generator (e.g., an arbitrary waveform generator (AWG) or a function generator), wherein the output of the RF signal generator system 100 is coupled to the input of a sensor device, wherein the RF output signal generated by the RF signal generator system 100 is configured to excite the sensor device. In other embodiments, the RF signal generator system 100 includes an AWG system implemented for quantum computing applications, wherein the RF signal generator system 100 is configured to generate RF control pulses for controlling the operation of, for example, a superconducting quantum bit (qubit), an active superconducting coupler circuit coupling two superconducting quantum bits, or other superconducting quantum devices.

[0033] In the context of the exemplary embodiments discussed herein, the RF signal includes a signal having a frequency ranging from, for example, about 20 kHz to about 300 GHz. In some embodiments, the RF signal generator system 100 includes an analog quadrature system configured to generate quadrature (I / Q) signals (e.g., baseband I / Q signals and LO I / Q signals) and perform quadrature modulation (or I / Q signal modulation) to generate an RF signal for a given application. As is known in the art, a quadrature signal includes an in-phase (I) signal component and a quadrature phase (Q) signal component. A pair of orthogonal signals have the same frequency but differ in phase by 90 degrees. For example, by convention, the I signal is a cosine waveform and the Q signal is a sine waveform. For illustrative purposes, exemplary embodiments of the present disclosure will be described in the context of an orthogonal RF signal generator system, but the exemplary signal processing circuits and methods discussed herein may be implemented with other types of RF signal generator systems and modulation techniques.

[0034] exist Figure 1 In an exemplary embodiment of the present invention, the baseband I / Q signal generator 110 is configured to generate digital orthogonal signals I and Q, which represent input baseband data for a given application. For example, for quantum computing applications, the baseband I / Q signal generator 110 is configured to implement pulse shaping techniques to generate RF control pulses with a desired envelope shape (e.g., Gaussian pulses, cosine pulses (e.g., the sum of half cosines), hyperbolic secant pulses, etc.), which are applied to superconducting qubits or active qubit coupler circuits to perform single qubit gate operations, entangled gate operations, etc. In some embodiments, the baseband I / Q signal generator 110 implements digital signal processing techniques based on a combination of hardware and software to generate digital orthogonal baseband signals I and Q.

[0035] The DAC stage 120 is configured to convert the digital quadrature signals I and Q into analog baseband signals I'(t) and Q'(t) having a target baseband frequency. Specifically, the DAC stage 120 includes a multi-bit DAC circuit, which includes a first DAC circuit 121 and a second DAC circuit 122. The first DAC circuit 121 is configured to convert the digital baseband component I into an analog baseband component I'(t) having a baseband frequency, and the second DAC circuit 122 is configured to convert the digital baseband component Q into an analog baseband component Q'(t) having the same baseband frequency, but with a phase shift of 90 degrees relative to I'(t). The DAC stage 120 is configured to convert the digital baseband component I into an analog baseband component Q'(t) having the same baseband frequency, but with a phase shift of 90 degrees relative to I'(t). The DAC stage 120 is configured to convert the digital baseband component Q into an analog baseband component Q'(t) having the same baseband frequency, but with a phase shift of 90 degrees relative to I'(t). The DAC stage 120 is configured to convert the digital baseband component I into an analog baseband component Q'(t) having a target baseband frequency. S) or sampling frequency, for example, the baseband frequency is in the range of about 100 kHz to about 1 GHz, depending on the given application. In some embodiments, the first DAC circuit 121 and the second DAC circuit 122 implement a configurable hardware framework, in which various operating parameters of the DAC stage 120 can be adjusted by digital control signals input to the DAC stage 120. For example, in some embodiments, digital control can be used to adjust DAC operating parameters, including but not limited to sampling rate, analog output gain, etc.

[0036] Based on the Nyquist sampling theorem, with a sampling frequency f S The maximum fundamental output frequency that the DAC can generate is f O The signal is equal to half the sampling rate or f S / 2 (called the first Nyquist zone). In the frequency domain, when the generated frequency f O When the sine wave is O will be expressed as f O , and there will be an additional higher frequency component generated at the output of the DAC stage 120, which is called the “image” and is f S and f O For example, the higher frequency component is determined as |(n×f S )±f O |, where n=1, 2, 3, ... The images have the same information content as the fundamental spectral components, but at higher frequencies and smaller amplitudes. The unwanted images are suppressed / rejected using, for example, a baseband filter stage 130 .

[0037] The baseband filter stage 130 is configured to filter the analog baseband signals I'(t) and Q'(t) output from the DAC stage 120 and thereby generate filtered analog baseband signals I(t) and Q(t). The baseband filter stage 130 includes a first filter circuit 131 and a second filter circuit 132. The first filter circuit 131 is configured to filter the in-phase analog signal I'(t) output from the first DAC circuit 121, and the second filter circuit 132 is configured to filter the quadrature-phase analog signal Q'(t) output from the second DAC circuit 122. In some embodiments, the first filter circuit 131 and the second filter circuit 132 include low-pass filters configured to pass fundamental spectral components of the respective analog signals I'(t) and Q'(t) while suppressing image components of the respective analog signals I'(t) and Q'(t). In other embodiments, the first filter circuit 131 and the second filter circuit 132 can be configured as bandpass filters to pass a desired band of higher frequency image components of the corresponding analog signals I'(t) and Q'(t) while suppressing the fundamental spectral components and other image components of the corresponding analog signals I'(t) and Q'(t). In other embodiments, the first filter circuit 131 and the second filter circuit 132 can be configured as high pass filters, as may be desired for a given application.

[0038] In some embodiments, the baseband filter stage 130 includes a configurable filter circuit, wherein, for example, the cutoff frequencies of the first filter circuit 131 and the second filter circuit 132 can be adjusted, or wherein the first filter circuit 131 and the second filter circuit 132 can be configured to have different filter types (e.g., low pass, band pass, etc.) as required by a given application. For example, in some embodiments, a band pass filter can be configured using two low pass filters using known signal filtering techniques and architectures. In some embodiments, the filter configuration is digitally controlled by a digital control signal input to the baseband filter stage 130.

[0039] For example, a higher DAC sampling frequency may be utilized as needed to transmit baseband data and / or relax the filter response of the downstream filter of the baseband filter stage 130. In fact, an increase in the DAC sampling frequency results in the possibility of accommodating higher baseband transmission frequencies (i.e., analog signals I'(t) and Q'(t) have higher baseband frequencies). In addition, an increase in the DAC sampling frequency results in an increase in the center frequency f of the baseband component. O and the center frequency of the higher frequency image n×f S ±f OThe spacing between increases, which relaxes the required sharpness of the filter cutoff at the filter's corner frequency. However, higher DAC sampling rates result in increased power consumption. Therefore, the tradeoff of power consumption versus DAC sampling frequency and the sharpness of the filter cutoff at the filter's corner frequency is a factor that should be considered.

[0040] In some embodiments, the mixer stage 140 is configured to perform analog I / Q signal modulation, e.g., single sideband (SSB) modulation, by mixing the filtered analog signals I(t) and Q(t) output from the baseband filter stage 130 with quadrature LO signals (e.g., in-phase LO signal (LO_I) and quadrature phase LO signal (LO_Q)) to generate and output an analog RF signal (e.g., a single sideband modulated RF output signal). The local oscillator signals LO_I and LO_Q each have the same LO frequency, but the LO_Q signal is phase shifted by 90 degrees relative to the LO_I signal. For amplitude modulation, the filtered analog signals I(t) and Q(t) amplitude modulate the LO_I and LO_Q signals. It is desirable to ensure that the amplitude modulation level applied to the LO_I signal is well matched to the amplitude modulation level applied to the LO_Q signal. Otherwise, the in-phase (I) and quadrature-phase (Q) signal components of the RF output generated by the RF signal generator system 100 will be unbalanced, resulting in degraded image rejection performance and the presence of unwanted sideband spurs.

[0041] More specifically, the mixer stage 140 includes a first mixer circuit 141 (e.g., an I mixer circuit), a second mixer circuit 142 (e.g., a Q mixer circuit), and a signal combiner circuit 143. The first mixer circuit 141 is configured to mix the filtered analog signal I(t) with the LO_I signal and generate a first RF signal output. The second mixer circuit 142 is configured to mix the filtered analog signal Q(t) with the LO_Q signal and generate a second RF signal output. The first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142 are input to the signal combiner circuit 143 and combined (e.g., added) to generate a single-sideband RF signal output.

[0042] In some embodiments, a quadrature phase shifter circuit is implemented to generate quadrature LO signals LO_I and LO_Q signals. For example, the quadrature phase shifter circuit is configured to receive an LO signal as an input and output quadrature LO signals LO_I and LO_Q based on the LO input signal. In this configuration, the LO_I signal includes the same frequency and phase as the input LO signal, and the LO_Q signal includes the same frequency as the input LO signal, but with a 90 degree phase shift. The quadrature phase shifter circuit can be implemented using one of a variety of quadrature phase shifting techniques known to those of ordinary skill in the art.

[0043] The mixer stage 140 performs an up-conversion mixing process configured to generate an RF analog signal having a center frequency greater than the baseband frequency of the baseband signal output from the DAC stage 120. In some embodiments, the LO frequency of the mixer stage 140 is in the range of 100 MHz to about 10 GHz, depending on the application. More specifically, as will be appreciated by those of ordinary skill in the art, as a result of the mixing operation of the first mixer circuit 141 and the second mixer circuit 142, the first RF signal and the second RF signal output from the corresponding first mixer circuit 141 and the second mixer circuit 142 each include a double-sideband RF signal. The double-sideband signal includes an upper sideband (USB) and a lower sideband (LSB), which are arranged at equal distances above and below the LO frequency. The upper sideband includes a spectral band of frequencies higher than the LO frequency, and the lower sideband includes a spectral band of frequencies lower than the LO frequency. The upper sideband and the lower sideband each carry the same information content of the IQ signal. For example, assume that the filtered analog signals I(t) and Q(t) (ie, the modulating signals) have a center frequency f M (IF), and the LO signal has a frequency f LO The first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142 will each have (i) an upper sideband of a spectral component, which is represented by (f LO +f M ) and (ii) the lower sideband of the spectral components, which is centered at the frequency of (f LO -f M ) frequency as the center.

[0044] In some embodiments, the signal combiner circuit 143 is configured to add the first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142, in which case the signal combiner circuit 143 will output the "real" lower sideband signal as a single sideband modulated RF signal (with a suppressed carrier frequency) having a center frequency that is derived from the frequencies f of the modulating signals I(t) and Q(t). M Up-converted to the center frequency of the lower sideband (f LO -f M ). In other embodiments, the signal combiner circuit 143 is configured to subtract the first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142, in which case the signal combiner circuit 143 will output a "real" upper sideband signal as a single sideband modulated RF signal (with a suppressed carrier) having a center frequency that is 1 / 200 from the frequency f of the modulated signals I(t) and Q(t). M Up-converted to the center frequency of the upper sideband (f LO +f M). In other embodiments, the mixer stage 140 is configured as a double sideband modulator (with a suppressed carrier frequency). More specifically, the mixer stage 140 can be configured to provide double sideband modulation by maintaining the LO_Q input to the second mixer 142 at a constant zero voltage level (i.e., LO_Q=0). In this case, the second mixer circuit 142 will have a zero output (i.e., no RF signal is output from the second mixer circuit 142), and the output of the signal combiner circuit 143 will be the double sideband RF signal output from the first mixer circuit 141.

[0045] The amplifier stage 150 is configured to receive the modulated RF signal output from the mixer stage 140, and amplify or attenuate the modulated RF signal to a desired power level, and drive the output of the RF signal generator system 100 (e.g., drive an antenna, sensor device, qubit, etc. coupled to the output of the RF signal generator system 100). In some embodiments, the amplifier stage 150 includes a programmable gain, where the gain can be expressed as the difference between the input power level (at the input of the amplifier stage 150) and the output power level (at the output of the amplifier stage 150), or more specifically, as the ratio of the output power to the input power. In some embodiments, the amplifier stage 150 is used to increase the power level of the RF output signal to a level sufficient to transmit the modulated RF signal at a given power level and over a desired transmission distance (wirelessly or wired). In other embodiments, the amplifier stage 150 includes a programmable gain attenuation stage. The programmable gain attenuation stage includes a programmable amplifier configured to amplify the modulated RF signal with a gain factor of 1 or less than 1. In this manner, the programmable gain attenuation stage may attenuate the power level of the modulated RF signal output from mixer stage 140 as desired for a given application.

[0046] The impedance matching network 160 is configured to match the source impedance or load impedance of the output of the amplifier stage 150 to the characteristic impedance of the output load (e.g., antenna input, duplexer, etc.) of the RF signal generator system 100. In some embodiments, the impedance matching network 160 includes a balanced-unbalanced converter to convert the differential / balanced output of the amplifier stage 150 to a single-ended / unbalanced output. In some embodiments, the resonant parameters (e.g., impedance and bandwidth) of the impedance matching network 160 remain substantially unchanged, wherein the impedance matching network 160 is designed to have a center frequency corresponding to the desired operating frequency of the load. In other embodiments, the impedance matching network 160 is configured with multiple injection points to provide different impedance matching and filtering characteristics. Different injection points can be selected by a digital control signal applied to the impedance matching network 160. The impedance matching network 160 can have high-pass and low-pass characteristics, wherein different injection points can be selected to provide different impedance matching and response characteristics. In some embodiments, the impedance matching network 160 is designed to have a high Q factor, wherein the center frequency of the impedance matching network 160 can be adjusted to provide adequate impedance matching for different transmission frequencies, which are generated by, for example, changing the sampling frequency of the DAC stage 120 and / or changing the LO frequency of the mixer stage 140, depending on a given application.

[0047] In some embodiments, the LO signal generator circuit 170 is configured to generate quadrature LO signals LO_I and LO_Q having target center frequencies, which are utilized by the mixer stage 140 to perform I / Q modulation and up-conversion. In some embodiments, for a differential signal framework, the LO signal generator circuit 170 is configured to generate complementary quadrature LO signals, which include complementary in-phase LO signals LO_I and LO_Q. and the complementary quadrature phase LO signal LO_Q and Ideally, the complementary orthogonal LO signals LO_I, LO_Q, and They have the same amplitude and center frequency, but different phases of 0°, 90°, 180°, and 270° respectively.

[0048] The LO signal generator circuit 170 is implemented using known circuit architectures and LO signal generation techniques. For example, in some embodiments, the LO signal generator circuit 170 includes a phase-locked loop (PLL) system configured to generate an LO signal having a target center frequency, and a phase shifter circuit that converts the LO signal generated by the PLL system into quadrature LO signals LO_I and LO_Q. For differential quadrature LO signals, in some embodiments, the LO signal generator circuit 170 may implement a quadrature phase shifter circuit that is configured to receive a complementary pair of LO signals LO and As input, it generates complementary quadrature LO signals LO_I, LO_Q, and In some embodiments, the quadrature phase shifter circuit may be implemented using a quadrature polyphase phase shifter circuit having a single polyphase filter stage or multiple polyphase filter stages, as known to those of ordinary skill in the art.

[0049] The LO signal output configuration circuit 180 includes an LO signal driver stage configured to drive the LO inputs of the first mixer circuit 141 and the second mixer circuit 142 in the mixer stage 140 with the quadrature LO signals generated and output from the LO signal generator circuit 170. As explained in further detail below, in a normal operating mode of the RF signal generator system 100, the LO signal output configuration circuit 180 is configured to drive the LO inputs of the first mixer circuit 141 and the second mixer circuit 142 with the quadrature LO signals LO_I and LO_Q (or complementary quadrature LO signals) to perform normal I / Q modulation. In the calibration mode of the RF signal generator system 100, the LO signal output configuration circuit 180 is configured to selectively drive the LO inputs of the first mixer circuit 141 and the second mixer circuit 142 with a DC voltage, wherein the DC voltage is configured to selectively activate and deactivate the switching transistors of the first mixer circuit 141 and the second mixer circuit 142 to perform a DC measurement of the baseband current, the details of which will be explained in further detail below. An exemplary embodiment of the LO signal output configuration circuit 180 will be described below in conjunction with Figure 5 Further detailed discussion.

[0050] like Figure 1 As shown, each signal processing stage 110, 120, 130, 140, 150, 160, 170, and 180 of the RF signal generator system 100 includes a control signal input port that receives a digital control signal from a calibration system 190 or some processor or microcontroller configured to control the operation of the RF signal generator system 100. The calibration system 190 can generate a digital control signal to configure the RF signal generator system 100 to operate in a calibration mode, and control the execution of a calibration process performed in the calibration mode to calibrate the I / Q signals of the RF signal generator system 100. In addition, in some embodiments, some or all of the stages 110, 120, 130, 140, 150, 160, 170, and 180 have a configurable hardware framework, wherein various operating parameters of the stages can be adjusted by digital control signals to adjust the normal mode operation of the RF signal generator system 100.

[0051] exist Figure 1In the exemplary I / Q modulation architecture of the RF signal generator system 100 shown, it is desirable to eliminate or otherwise substantially minimize the imbalance between the baseband I and Q signals for the purpose of image rejection. In practice, I / Q imbalance may result in unwanted spectral components at the image frequency. As described above, the SSB mixer is configured to up-convert the intermediate frequency (IF) of the baseband signal to f LO -f IF or IF +f LO This is particularly useful when using low IF frequencies where preselection filtering is difficult. For example, if the desired RF signal is to be transmitted at a frequency f RF =f LO -f IF Generate, then f IF +f LO The sideband signal (image signal) at the image frequency will be suppressed by the sideband suppression provided by the SSB mixer. However, the imbalance in the amplitude of the baseband I and Q signals may result in the presence of relatively high spectral power of unwanted spectral components at the image frequency.

[0052] In addition, for the use of differential analog I signal (I(t), ) and the differential analog Q signal (Q(t), ) differential I / Q solution, the differential analog I signal I(t) and The unbalanced and / or differential analog Q signal Q(t) between An imbalance between the differential analog baseband signal I(t) and The unbalanced and / or differential analog baseband signal Q(t) between The DC offset between the differential baseband signals means that the signals are not completely complementary due to the presence of the DC term. In the mixer stage 140, the DC offset of the complementary baseband signal pair results in a DC term that is multiplied by the LO frequency, causing the output of the mixer stage 140 to include an unwanted LO frequency component that would otherwise be suppressed if the differential signal was properly balanced (e.g., zero offset of the differential signal).

[0053] The calibration system 190 is configured to perform functions such as (i) generating a control signal to configure the RF signal generator system 100 to operate in a calibration mode, (ii) detecting an imbalance between baseband I and Q signals in an I / Q signal path of the RF signal generator system 100 using a DC measurement technique, (iii) generating a DC correction signal in the I / Q signal path to compensate for the detected imbalance between baseband I and Q signals in the I / Q signal path of the RF signal generator system 100, and other functions, as discussed in further detail below.

[0054] In some embodiments, the current measurement circuit 192 is configured to measure the I / Q baseband current in the I / Q signal path of the RF signal generator system 100 and detect the amount of imbalance (if any) in the I / Q baseband current when the RF signal generator system 100 is configured in the calibration operating mode. For example, in some embodiments, the current measurement circuit 192 is configured to measure the I and Q baseband currents and detect any imbalance between the I and Q baseband signals. In addition, in some embodiments, for a differential I / Q system, the current measurement circuit 192 is configured to (i) measure the complementary I(t) and Baseband current to detect the complementary I(t) and and (ii) measure the complementary Q(t) and Baseband current to sense the complementary Q(t) and Any imbalance between baseband signals.

[0055] The current imbalance correction circuit 194 is configured to generate a DC correction signal in the I / Q signal path to compensate for an imbalance detected between baseband I and Q signals in the I / Q baseband signal path of the RF signal generator system 100. In some embodiments, as discussed in further detail below, the current imbalance correction circuit 194 is configured to inject a DC current into the I / Q baseband signal path of the RF signal generator system 100 to compensate for the imbalance between (i) the I and Q baseband currents, (ii) the complementary I(t) and baseband current, and / or (iii) complementary Q(t) and An imbalance is detected between the baseband currents.

[0056] The calibration control circuit 196 is configured to perform various functions of the calibration system 190 for calibrating the baseband I / Q signals of the RF signal generator system 100. For example, the calibration control circuit 196 generates various control signals for configuring the RF signal generator system 100 to operate in a calibration mode to perform a calibration process. In addition, the calibration control circuit 196 generates control signals to control the operation of the current measurement circuit 192 and the current imbalance correction circuit 194. In addition, in some embodiments, the calibration control circuit 196 includes control logic that is configured to, for example, (i) process the I / Q baseband current measurement data generated by and output from the current measurement circuit 192 during the calibration process, and generate digital control signals to control the operation of the current imbalance correction circuit 194, thereby generating a target DC current correction signal based on the results of processing the I / Q baseband current measurement. In some embodiments, the control logic implements a finite state machine to process the current measurement data output from the current measurement circuit 192, and generate digital control signals to control the operation of the current imbalance correction circuit 194.

[0057] Figure 2 Schematically illustrates a radio frequency signal generator system and a calibration system according to another exemplary embodiment of the present disclosure, wherein the calibration system is configured to calibrate a baseband current in a signal path of the radio frequency signal generator system. More specifically, Figure 2 The RF signal generator system 200 is schematically shown and includes a baseband signal input stage 210, a current-commutated mixer stage 220, a signal attenuation stage 230, and a transformer circuit 240 (alternatively, an output transformer stage 240). Figure 2 A calibration system including a current measurement circuit 250 , a control logic circuit 260 , a first DC offset compensation DAC 270 , and a second DC offset compensation DAC 272 is schematically shown.

[0058] In some embodiments, the RF signal generator system 200 schematically illustrates a current mode RF signal generator framework configured to utilize complementary in-phase baseband signals I(t) and The complementary quadrature phase baseband signal Q(t) and and includes complementary in-phase LO signals LO_I and and the complementary quadrature phase LO signal LO_Q and In some embodiments, the baseband signal input stage 210 and the current commutated mixer stage 220 are schematically shown. Figure 1 In addition, in some embodiments, the signal attenuation stage 230 schematically shows Figure 1 In addition, in some embodiments, the output transformer stage 240 represents Figure 1 1 , wherein the output transformer stage 240 includes circuitry for converting a differential output signal to a single-ended output signal. The output transformer stage 240 may be implemented using a variety of techniques and circuit configurations for converting a differential output signal to a single-ended output signal that are suitable for a given application and are known to those of ordinary skill in the art.

[0059] The baseband signal input stage 210 includes a plurality of baseband input transistors 211, 212, 213, and 214. In some embodiments, the baseband input transistors 211, 212, 213, and 214 are p-type metal oxide semiconductor (PMOS) transistors. The transistors 211 and 212 include a first differential transistor pair 210-1, wherein the transistors 211 and 212 have source terminals commonly connected to a positive power supply voltage node VDD (e.g., VDD_RF, wherein VDD_RF is approximately 900 mV or less), and receive complementary in-phase baseband signals I(t) and I(t), respectively. The transistors 213 and 214 comprise a second differential transistor pair 210-2, wherein the transistors 213 and 214 have source terminals commonly connected to a positive power supply voltage node VDD (eg, VDD_RF) and receive complementary quadrature-phase baseband signals Q(t) and Q(t), respectively. The transistors 211 , 212 , 213 and 214 each include a drain terminal connected to a respective differential transistor pair of the plurality of differential transistor pairs in the current commutated mixer stage 220 .

[0060] In some embodiments, transistors 211, 212, 213, and 214 of baseband signal input stage 210 include variable gain elements (as schematically shown by diagonal arrows across the transistors) that can be configured to adjust the baseband signal gain in the I / Q signal path. For example, in some embodiments, each baseband input transistor 211, 212, 213, and 214 includes a variable width transistor that is structurally configured and controlled using known techniques to change the effective gate width of the transistor structure and, therefore, adjust the drain current I flowing through the corresponding transistor 211, 212, 213, and 214 when operating in saturation mode. D_1 ,I D_2 ,I D_3 and I D_4 The maximum amount.

[0061] For example, in some embodiments, each baseband input transistor 211, 212, 213, and 214 can be structurally configured to include multiple transistor segments coupled in parallel, wherein the number of segments that are active / inactive at a given time (via a digital switch control system) can be adjusted to change the effective gate width of a given baseband input transistor. In this regard, the effective width of the transistors 211, 212, 213, and 214 in the baseband signal input stage 210 can be configured to adjust the baseband signal gain in the I / Q signal path over a target gain range (e.g., a 20 dB gain range) using multiple gain step settings within the gain range. For example, in some embodiments, the DC baseband current can be adjusted to one of various target current levels within a given range, wherein the highest baseband current level is approximately 10 times greater than the lowest baseband current level (e.g., a range from about 35 μA to about 350 μA).

[0062] The current commutated mixer stage 220 includes a differential I mixer 220-1 and a differential Q mixer 220-2. The differential I mixer 220-1 includes a plurality of mixing transistors 221, 222, 223, and 224 (alternatively, I mixer switch transistors 221, 222, 223, and 224). The differential Q mixer 220-2 includes mixing transistors 225, 226, 227, and 228 (alternatively, Q mixer switch transistors 225, 226, 227, and 228). In some embodiments, as Figure 2 As shown, the mixer transistors 221, 222, 223, 224, 225, 226, 227 and 228 are PMOS transistors.

[0063] In the differential I mixer 220-1, the mixing transistors 221 and 222 comprise a first differential mixing transistor pair having source terminals commonly connected to the drain terminal of the transistor 211 in the baseband signal input stage 210 and receiving complementary in-phase LO signals LO_I and LO_L, respectively. Mixing transistors 223 and 224 comprise a second differential mixing transistor pair having source terminals commonly connected to the drain terminal of transistor 212 in baseband signal input stage 210 and receiving complementary in-phase LO signals, respectively. and LO_I as the corresponding gate terminals of the inputs.

[0064] In the differential Q mixer 220-2, the mixer transistors 225 and 226 comprise a first differential mixer transistor pair having source terminals commonly connected to the drain terminal of the transistor 213 in the baseband signal input stage 210 and receiving the complementary quadrature phase LO signals LO_Q and LO_Q, respectively. Mixing transistors 227 and 228 comprise a second differential mixing transistor pair having source terminals commonly connected to the drain terminal of transistor 214 in baseband signal input stage 210 and receiving complementary quadrature phase LO signals, respectively. and LO_Q as the corresponding gate terminals of the inputs.

[0065] The current-commutated mixer stage 220 includes two output nodes, denoted as INT_0 and INT_1. Figure 2 , mixing transistors 221, 223, 225, and 227 have drain terminals commonly coupled to an output node INT_1 of the current commutated mixer stage 220, and mixing transistors 222, 224, 226, and 228 have drain terminals commonly coupled to an output node INT_0 of the current commutated mixer stage 220. The differential I mixer 220-1 and the differential Q mixer 220-2 are configured to provide analog I / Q modulation and up-conversion, wherein the connection of the mixing transistors of the differential I mixer 220-1 and the differential Q mixer 220-2 (where the mixing transistors operate in triode mode) allows summing / subtraction of the output currents of the mixing transistors 221, 222, 223, 224, 225, 226, 227, and 228 to achieve SSB I / Q modulation, as understood by one of ordinary skill in the art. As explained in further detail below, in some embodiments, output nodes INT_0 and INT_1 comprise intermediate nodes of baseband I and Q signal paths that are tapped by the calibration system to measure I / Q baseband currents of the RF signal generator system 200 during a calibration process.

[0066] The signal attenuation stage 230 is configured to adjust the signal strength of the RF output signal. Figure 2 In an exemplary embodiment of the present invention, the signal attenuation stage 230 is configured to adjust the amount of differential current flowing from the output nodes INT_0 and INT_1 to the output transformer stage 240. In this regard, the signal attenuation stage 230 is used to adjust the signal level of the signal output from the current-commutated mixer stage 220. The signal attenuation stage 230 includes a plurality of attenuation sections 230-1, ..., 230-s, which are controlled by corresponding differential control signals. Digitally controlled. Figure 2As schematically shown in FIG. 1 , the first attenuation section 230-1 includes a first differential transistor pair 231 and 232 and a second differential transistor pair 233 and 234. In addition, the attenuation section 230-s includes a first differential transistor pair 235 and 236 and a second differential transistor pair 237 and 238. In some embodiments, the transistors 231, 232, 233, 234, 235, 236, 237, and 238 of the signal attenuation stage 230 are PMOS transistors. The number of attenuation sections 230-1, ..., 230-s implemented will depend on the desired resolution of the gain adjustment.

[0067] In the first attenuation section 230-1, the first differential transistor pair 231 and 232 have source terminals commonly connected to the mixer output node INT_1 and receive the differential control signal V ATTN_1 and The transistor 231 has a drain terminal coupled to the output transformer stage 240, and the transistor 232 has a drain terminal coupled to the negative power supply node VSS (e.g., 0V ground voltage). In addition, the second differential transistor pair 233 and 234 have source terminals commonly connected to the mixer output node INT_0, and receive differential control signals respectively. and V ATTN_1 Transistor 233 has a drain terminal coupled to the negative power supply node VSS, and transistor 234 has a drain terminal coupled to the output transformer stage 240 .

[0068] Similarly, in the attenuation section 230-s, the first differential transistor pair 235 and 236 have source terminals commonly connected to the mixer output node INT_1 and receive the differential control signal V ATTN_S and The transistor 235 has a drain terminal coupled to the output transformer stage 240, and the transistor 236 has a drain terminal coupled to the negative power supply node VSS. In addition, the second differential transistor pair 237 and 238 have source terminals commonly connected to the mixer output node INT_0, and receive differential control signals INT_0, INT_1, INT_2, INT_3, INT_4, INT_5, INT_6, INT_7, INT_8, INT_9, INT_10, INT_11, INT_12, INT_13, INT_14, INT_15, INT_16, INT_17, INT_18, INT_19, INT_20, INT_21, INT_22, INT_23, INT_24, INT_25, INT_26, INT_27, INT_28, INT_29, INT_30, and V ATTN_S Transistor 237 has a drain terminal coupled to the negative power supply node VSS, and transistor 238 has a drain terminal coupled to the output transformer stage 240 .

[0069] In operation, the amount of differential current flowing from the output nodes INT_0 and INT_1 to the output transformer stage 240 can be adjusted based on the number of activated attenuation segments 230-1, ..., 230-s. ATTN and When V is a logic "0" and a logic "1", respectively, a given attenuation segment is "deactivated" (and does not contribute to the attenuation of the RF output signal). For example, the first attenuation segment 230-1 will be at V ATTN_1 is logic "0" and is “deactivated” when V is logic “1”, so that transistors 231 and 234 will be in the “on” state, and allow some current to flow from output nodes INT_1 and INT_0 to the output transformer stage 240, while transistors 232 and 233 will be in the “off” state. On the other hand, the first attenuation stage 230-1 will be in the “off” state. ATTN_1 is logic "1" and When the output transformer stage 240 is at logic "0", it is "activated" (and will contribute to the attenuation of the RF output signal), so that the transistors 231 and 234 will be in the "off" state of being disconnected, and the transistors 232 and 233 will be in the "on" state of being turned on, and some current is allowed to flow from the output nodes INT_1 and INT_0 to the negative power supply node VSS (e.g., ground). Since this current flowing from the output nodes INT_1 and INT_0 to the negative power supply node VSS (e.g., ground) does not contribute to the current flowing through the output transformer stage 240, the RF output signal level is reduced.

[0070] In this configuration, the amount of differential current flowing from output nodes INT_0 and INT_1 to output transformer stage 240 can be (i) increased by increasing the number of "deactivated" attenuation segments (thereby increasing the RF output signal level), or (ii) decreased by increasing the number of "activated" attenuation segments (thereby decreasing the RF output signal level). The number of attenuation segments 230-1, ..., 230-s implemented will depend on the desired resolution of the gain adjustment.

[0071] As described above, in the baseband signal input stage 210, the first differential transistor pair 210-1 is configured to receive the complementary in-phase baseband signals I(t) and The second differential transistor pair 210-2 is configured to receive the complementary quadrature-phase baseband signals Q(t) and And in response, the first differential transistor pair 210-1 and the second differential transistor pair 210-2 generate a current mode signal that is applied to the current commutated mixer stage 220. In this regard, in the baseband signal input stage 210, matching between the first differential transistor pair 211 and 212 and between the second differential transistor pair 213 and 214 is critical. In addition, matching between the first differential transistor pair 210-1 and the second differential transistor pair 210-2 is critical. In this regard, mismatching between the baseband input transistors in the baseband signal input stage 210 may cause an imbalance in the I / Q baseband current signal, which may cause LO leakage and insufficient image suppression.

[0072] As mentioned above, the amplitude or phase imbalance between the I and Q signals may lead to a degradation of the image rejection performance, which results in the presence of unwanted spurious sidebands. In addition, the positive component and the negative component (e.g., I phase) in the same phase (I phase) may be + and I - ) causes LO leakage spurs. Figure 2 In the current mode RF signal generator system architecture shown (e.g., AWG system), (i) I and Q baseband currents, (ii) I + and I - Current and / or (iii) Q + and Q - An imbalance between the currents may result in performance degradation with respect to LO leakage and unwanted parasitic sideband signals.

[0073] Figure 2 The exemplary calibration system shown in is configured to correct for imbalances in I / Q baseband currents. As described above, in some embodiments, output nodes INT_0 and INT_1 comprise intermediate nodes of the baseband I and Q signal paths that are tapped by the calibration system to measure I / Q baseband currents in the RF signal generator system 200 during the calibration process. Figure 2 In an exemplary embodiment of the present invention, the current measurement circuit 250 includes first and second inputs that are selectively coupled (via switches) to respective output nodes INT_0 and INT_1 of the current-commutated mixer stage 220. During the calibration process, the current measurement circuit 250 is activated and configured to perform DC measurements to sense respective I-phase and Q-phase current signal components I at the output nodes INT_0 and INT_1. + ,I - , Q + and Q - .

[0074] More specifically, in some embodiments, calibration is performed as follows. The RF signal generator system 200 is configured to operate in a calibration mode. In the calibration mode, the baseband input transistors 211, 212, 213, and 214 of the baseband signal input stage 210 are biased at their normal current levels (i.e., the same as used in the normal operating mode). Upstream circuits (such as Figure 1 The first DAC circuit 121 and the second DAC circuit 122 in the embodiment are configured (programmed) so that a zero differential voltage is applied to the non-inverting input (I(t) and ) and quadrature phase input (Q(t) and ). In addition, the signal attenuation stage 230 is completely turned off by applying a constant DC voltage of an appropriate logic level to the gate terminals of the transistors in each attenuation segment 230-1, ..., 230-s to turn off all transistors in the signal attenuation stage 230. In this regard, completely shutting down the signal attenuation stage 230 causes the DC current generated by the current commutated mixer stage 220 and output to the intermediate nodes INT_0 and INT_1 during the calibration process to be routed to the input of the current measurement circuit 250.

[0075] Furthermore, in the calibration mode, the current-commutated mixer stage 220 may be configured to selectively output a baseband current I of a given baseband phase at one of the nodes INT_0 and INT_1. + ,I - , Q + or Q - , for input to the current measurement circuit 250. Specifically, in order to selectively output the baseband current I at a given time + ,I - , Q + or Q - for measurement, the I and Q mixer switching transistors are configured by applying a DC voltage of logic “1” or a DC voltage of logic “0” to the gate terminals of the I and Q mixer switching transistors as needed to selectively turn on one mixing transistor while turning off the other mixing transistors.

[0076] For example, to output the baseband current I at node INT_1 + , the mixing transistor 221 of the I mixer 220-1 is turned on, while all other mixing transistors 222, 223, 224, 225, 226, 227 and 228 are turned off. In addition, in order to output the baseband current I - , the mixing transistor 223 of the I mixer 220-1 is turned on, while all other mixing transistors 221, 222, 224, 225, 226, 227 and 228 are turned off. In addition, in order to output the baseband current Q at the node INT_1 + , the mixing transistor 225 of the Q mixer 220-2 is turned on, while all other mixing transistors 221, 222, 223, 224, 226, 227 and 228 are turned off. In addition, in order to output the baseband current Q at the node INT_1 -, the mixing transistor 227 of the Q mixer 220-2 is turned on, while all other mixing transistors 221, 222, 223, 224, 225, 226, and 228 are turned off. It should be noted that in other embodiments, by selectively activating only one of the mixing transistors 222, 224, 226, or 228 at a given time, separate I-phase and Q-phase current signal components I can be selectively output on the node INT_0. + ,I - , Q + and Q - .

[0077] In some embodiments, the current measurement circuit 250 is configured to measure / estimate the DC baseband current I + ,I - , Q + and Q - , and the control logic circuit 260 is configured to determine the same phase pair {I + , I -} and {Q + , Q -}, which provides an indication of the DC offset. For example, the measured I + Baseband current and I - The difference between the baseband currents (imbalance) and / or the measured Q + Baseband Current and Q - The difference (imbalance) between the baseband currents represents the DC offset that causes LO leakage. In addition, the control logic circuit 260 is configured to determine the measured I + and Q + The difference (imbalance) between the baseband currents, where I + and Q + The imbalance between the baseband currents may degrade the image rejection, which results in the presence of unwanted sideband spurs.

[0078] The control logic circuit 260 is configured to generate corresponding first and second digital control signals (e.g., n-bit control signals [n-1:0]), which are applied to the first DC offset compensation DAC 270 and the second DC offset compensation DAC 272, respectively. In some embodiments, the first control signal input to the first DC offset compensation DAC 270 provides the measured I + Baseband current and I - The determined difference between the baseband currents and the second control signal input to the second DC offset compensation DAC 272 provides an indication of the measured Q + Baseband Current and Q - An indication of the determined difference between the baseband currents.

[0079] like Figure 2As schematically shown in FIG. 2 , the first DC offset compensation DAC 270 includes a first output terminal coupled to the drain terminal of the baseband input transistor 211, and a second output terminal coupled to the drain terminal of the baseband input transistor 212. The second DC offset compensation DAC 272 includes a first output terminal coupled to the drain terminal of the baseband input transistor 213, and a second output terminal coupled to the drain terminal of the baseband input transistor 214.

[0080] In this exemplary configuration, in response to a control signal received from the control logic circuit 260, the first DC offset compensation DAC 270 is configured to provide an additional current I C_1 and I C_2 Inject into I + and I - In the baseband signal path. Additional current I C_1 and I C_2 is added to the respective drain currents I of the respective baseband input transistors 211 and 212 D_1 and I D_2 , thus balancing I + and I - baseband current, and thus significantly reduces or eliminates the I applied to the input of I mixer 220-1. + and I - Similarly, in response to the control signal received from the control logic circuit 260, the second DC offset compensation DAC 272 is configured to convert the additional current I C_3 and I C_4 Inject Q + and Q - Baseband signal path. Additional current I C_3 and I C_4 is added to the respective drain currents I of the baseband input transistors 213 and 214 D_3 and I D_4 , thus balancing Q + and Q - baseband current, and thus significantly reduces or eliminates the Q applied to the input of Q mixer 220-2. + and Q - DC offset between baseband currents.

[0081] It should be noted that the imbalance between the baseband currents can be Figure 1 The first DC offset compensation DAC 270 and the second DC offset compensation DAC 272 in the embodiment and / or the first DAC circuit 121 and the second DAC circuit 122 are used to adjust. For example, the first DC offset compensation DAC 270 and the second DC offset compensation DAC 272 are used to ensure that the phase corresponding to a given phase (for example, {I + and I-} and {Q + and Q - Any imbalance (offset) between the two baseband currents of the first DAC circuit 121 and the second DAC circuit 122 ( Figure 1 ) is preferably used to correct the baseband current I + and Q + Therefore, the use of the first DC offset compensation DAC 270 and the second DC offset compensation DAC 272 and the first DAC circuit 121 and the second DAC circuit 122 provides the ability to correct the imbalance and ensure that all baseband currents I + ,I - , Q + and Q - The magnitudes are essentially equal.

[0082] Figure 2 The current measurement circuit 250 (and Figure 1 The current measurement circuit 192) can be implemented using the exemplary techniques and circuit architectures described herein. For example, Figure 3 A current measurement circuit 300 implemented by a calibration system to measure a baseband current according to an exemplary embodiment of the present disclosure is schematically shown. The current measurement circuit 300 includes a first current sink circuit 310, a second current sink circuit 320, a transistor 330 (alternatively, a mirror transistor 330), a current DAC circuit 340, a comparator 350, and a switch SW2. The first current sink circuit 310 includes a first transistor 312 and a switch SW0. The second current sink circuit 320 includes a second transistor 322 and a switch SW1. In some embodiments, transistors 312, 322, and 330 are n-type MOS (NMOS) field effect transistors.

[0083] In the first current sink circuit 310, the first transistor 312 has a first current sensing node INT_0 (eg, Figure 2 The switch SW0 is coupled to the drain terminal and the gate terminal of the first transistor 312 and is coupled between the drain terminal and the gate terminal of the first transistor 312. In addition, in the second current sink circuit 320, the second transistor 322 has a second current sensing node INT_1 (for example, Figure 2 The switch SW1 is coupled to the drain terminal and the gate terminal of the second transistor 322 and is coupled between the drain terminal and the gate terminal of the second transistor 322.

[0084] The mirror transistor 330 includes a gate terminal coupled to the first node N1, a drain terminal coupled to the second node N2, and a source terminal coupled to the negative power supply node VSS. The current DAC circuit 340 includes an output terminal coupled to the second node N2. The comparator 350 (e.g., a voltage comparator circuit) includes a non-inverting input terminal (+) coupled to the second node N2, a voltage reference node V REF The inverting input terminal (-) of the Figure 2 Frame 260; Figure 1 The switch SW2 is coupled to the first node N1 and the negative power supply node VSS and is between the first node N1 and the negative power supply node VSS.

[0085] The current DAC circuit 340 includes a high resolution current output DAC configured to output a current having a current that can be used in a calibration control circuit (e.g., Figure 2 Frame 260; Figure 1 The reference current I of the magnitude adjusted under digital control of the block 196 etc. REF In some embodiments, the current DAC circuit 340 includes a segmented DAC framework including an N-bit coarse binary-weighted current output DAC and a P-bit fine thermometer-coded current output DAC. Figure 4A , 4B 4C discuss an exemplary embodiment of the current DAC circuit 340 in further detail.

[0086] It should be noted that the circuit components 310, 320, 330 and 350 of the current measurement circuit system 300 basically include a current comparator circuit that is configured to receive an input baseband current to be measured (from one of the nodes INT_0 or INT_1), compare the input current to a reference current I REF The current DAC circuit 340 is configured to increase or decrease the reference current I REF Until the current comparator circuit generates an indication reference current I REF Until the value of the comparison output signal is substantially equal to the value of the input current.

[0087] More specifically, during the normal operation mode of the RF signal generator system, the current measurement circuit 300 is configured in a deactivated state, wherein the switches SW0 and SW1 are open (deactivated), and the switch SW2 is closed (activated). When the current measurement circuit system 300 is in the deactivated state, the first node N1 is coupled to the negative power supply voltage node VSS (e.g., ground). Since the gate terminals of the transistors 312, 322, and 330 are commonly coupled to the first node N1, the transistors 312, 322, and 330 are in the cut-off mode and are therefore turned off. In addition, when the switches SW0 and SW1 are deactivated, the first node INT_0 and the second node INT_1 are disconnected from the first node N1. In the deactivated state, the current measurement circuit 300 provides a relatively small capacitive load (e.g., a small parasitic capacitance of the first transistor 312 and the second transistor 322 in the cut-off mode) to the first node INT_0 and the second node INT_1 of the current-commutated mixer stage 220 to avoid RF signal attenuation.

[0088] During the calibration mode, the current measurement circuit 300 is configured to measure a DC current (eg, I + ,I - , Q + , Q - ). For example, to measure the baseband current on the first node INT_0, the switch SW0 is activated (closed), the switch SW1 remains deactivated (open), and the switch SW2 is deactivated (open). In this configuration, the first current sink circuit 310 is activated, wherein the first transistor 312 becomes a diode-connected MOSFET, whose drain terminal and gate terminal are coupled together and coupled to the first node N1. In addition, the first transistor 312 (in a diode-connected MOSFET configuration) and the mirror transistor 330 form a current mirror circuit. In some embodiments, the current mirror circuit formed by the first transistor 312 (in a diode-connected configuration) and the mirror transistor 330 is configured to provide a current mirror ratio (or current transfer ratio) of 1:1. In other embodiments, the current mirror circuit is configured to scale the input current by M times, where M<1 or where M>1.

[0089] In the calibration mode, the RF signal generator system is configured so that the signal corresponding to I + ,I - , Q + or Q - A DC current of one of the baseband currents flows from the first node INT_0 into the first current sink circuit 310 and passes through the first transistor 312. The current DAC circuit 340 outputs a reference current I flowing through the mirror transistor 330. REF, and a voltage (denoted as V IN ). In some embodiments, the reference voltage V REF =0.5*VDD is applied to the inverting input (-) terminal of the comparator 350. When the voltage V IN Greater than V REF When the voltage V on the second node N2 is IN Less than V REF When , the output of comparator 350 will be at a logic "0" level. In this exemplary configuration, the high output impedance of node N2 is well suited for performing comparison operations.

[0090] In operation, the DC baseband current being measured flows from the first node INT_0 into the first current sink circuit 310, and the DAC reference current (denoted as I REF ) is output from the current DAC circuit 340. If the DAC reference current is greater than the DC baseband current, the voltage V generated at the second node N2 IN will be greater than V REF , which causes the output of comparator 350 to be at a logic "1" level. In response to the logic "1" output from comparator 350, the calibration control logic will determine that the DC baseband current being measured is less than the DAC reference current, and in response, will generate a control code to cause current DAC circuit 340 to reduce the DAC reference current.

[0091] On the other hand, if the DAC reference current is less than the DC baseband current, the voltage V generated at the second node N2 is IN will be less than V REF , which results in the output of comparator 350 being at a logic "0" level. In response to a logic "0" output from comparator 350, the calibration control logic will determine that the DC baseband current being measured is greater than the DAC reference current, and in response, will generate a control code to cause current DAC circuit 340 to increase the DAC reference current.

[0092] In an exemplary configuration, the comparison result at the output of the comparator 350 is at the DAC reference current I REF is adjusted (increased or decreased) by the calibration control logic. When the output of comparator 350 changes from 0→1 or from 1→0, this provides the latest DAC code corresponding to the DAC reference current I REF Instructions for DAC reference current I REF = is equal to or substantially equal to the DC baseband current being measured. In other words, the current DAC circuit 340 is adjusted to find a DAC code that causes the DAC reference current IREF As close as possible to the DC baseband current being measured, the final code setting of the current DAC circuit 340 will provide an estimate of the magnitude of the DC baseband current.

[0093] In addition, in a similar manner, to measure the baseband current on the second node INT_1, the switch SW1 is activated (closed), the switch SW0 is deactivated (opened), and the switch SW2 is deactivated (opened). In this configuration, the second current sink circuit 320 is activated, wherein the second transistor 322 becomes a diode-connected MOSFET, whose drain and gate terminals are coupled together and coupled to the first node N1. In addition, the second transistor 322 (in a diode-connected MOSFET configuration) and the mirror transistor 330 form a current mirror circuit. In some embodiments, the current mirror circuit formed by the second transistor 322 (in a diode-connected configuration) and the mirror transistor 330 is configured to provide a current mirror ratio of 1:1. In other embodiments, the current mirror circuit is configured to scale the input current M times, where M<1 or where M>1. In some embodiments, the current mirror circuit formed by the second transistor 322 (in a diode-connected configuration) and the mirror transistor 330 is configured to provide the same current mirror ratio as the current mirror circuit formed by the first transistor 312 (in a diode-connected configuration) and the mirror transistor 330.

[0094] In the calibration mode, the RF signal generator system is configured so that the signal corresponding to I + ,I - , Q + or Q - A DC current of one of the baseband currents flows from the second node INT_1 into the second current sink circuit 320 and through the second transistor 322. The current measurement circuit 300 compares the DC baseband current (measured) with different DAC reference currents using the same process as described above to determine the DAC reference current I REF , which is equal to or substantially equal to the DC baseband current being measured. Figure 5 , Figure 6 , Fig. 7A and Figure 7B An exemplary calibration process is discussed in further detail.

[0095] The current DAC circuit 340 may be implemented using any high resolution current output DAC architecture suitable for a given application. The general function of the current DAC circuit 340 is to convert a digital input code (provided from the calibration control logic) into an analog current (e.g., a DAC reference current I REF). As is known in the art, the current mode DAC architecture replicates a reference current source in each branch of the DAC, where the current sources are connected in parallel with each other. In addition, the current sources are connected to the output node via corresponding MOSFET switches, which are controlled by a digital input code. Each branch current is turned off or on based on the digital input code, and the current output from each activated branch of the DAC is summed to generate an analog output current.

[0096] In some embodiments, as described above, the current DAC circuit 340 includes a segmented DAC framework that includes coarse binary weighted DAC segments and fine thermometer coded DAC segments that allow the analog output current of the current DAC circuit 340 to be digitally programmed using coarse bits and fine bits. The coarse binary weighted DAC segments are used to generate an output current close to a target current level (e.g., a measured baseband current), while the fine thermometer coded DAC segments are used for fine-tuning adjustments of the output current to converge closer to the target current level. It should be noted that the current DAC circuit 340 can be designed to have relaxed requirements, for example, the least significant bit (LSB) size of the fine thermometer coded DAC segments does not have to be critically related to the LSB size of the coarse binary weighted DAC segments.

[0097] More specifically, since the current measurement circuit 300 is configured as a current comparator circuit, the current comparator circuit compares the input baseband current to be measured with the DAC reference current I REF Compare and adjust the DAC reference current I REF The amplitude of the DAC reference current I REF is determined to be equal or substantially equal to the magnitude of the input baseband current being measured, so there is no need to correlate / calibrate the LSB size of the coarse DAC segment and the fine DAC segment. The coarse DAC segment is used to convert the DAC reference current I REF The amplitude of the DAC is set within the tuning range of the fine DAC segment, which is used to fine tune the DAC reference current I REF The amplitude of the DAC reference current I is converged as close as possible to the amplitude of the baseband current being measured. As long as the coarse DAC segment can be used to set the DAC reference current I within the tuning range of the fine DAC segment REF The magnitude of the DC baseband current (e.g., I + ,I - , Q + , Q - ) can be compared with each other with high accuracy (resolution) by means of the current measuring circuit 300.

[0098] Furthermore, in some embodiments, the current DAC circuit 340 is configured to have the same Figure 2) of the gain setting range commensurate with the programmable range control. As mentioned above, Figure 2 In an exemplary embodiment of the present invention, the effective widths of transistors 211, 212, 213, and 214 of the baseband signal input stage 210 can be adjusted to increase or decrease the baseband current level in the I / Q signal path within a given range, wherein the highest baseband current level (e.g., 350 μA) is approximately 10 times greater than the lowest baseband current level (e.g., 35 μA). In this regard, the current measurement range of the current measurement circuit 300 can be scaled to match the baseband current level generated by the baseband signal input stage 210.

[0099] For example, in some embodiments, the current DAC circuit 340 is configured to operate over the full range of baseband current levels that can be generated by the baseband signal input stage 210. The current DAC circuit 340 includes a scaling tuning knob (e.g., a pre-scaler adjustment knob) to scale the current DAC circuit 340 to generate an output current level commensurate with the baseband current level in the I / Q signal path, which is generated for a given gain step setting of the baseband signal input stage 210. In some embodiments, the scaling of the current DAC circuit 340 is configured to track the scaling of the baseband signal input stage 210 using a control signal that is "ganged" together, so that when the gain of the baseband signal input stage 210 is adjusted, the DAC current output range of the current DAC circuit 340 is automatically scaled so that the current measurement range of the current measurement circuit 300 is commensurate with the adjusted I / Q baseband current level.

[0100] In some embodiments, the current DAC circuit 340 can be configured to enable scaling of the LSB size of the coarse DAC segment and / or the fine DAC segment. For example, if the baseband current level increases or decreases by a given amount due to a change in the baseband gain setting, the LSB current can be adjusted by the same amount to scale the current output range of the current DAC circuit 340. The LSB size can be scaled using known techniques. For example, in an embodiment where the DAC segment includes an array of current sources biased using a current mirror, the current mirror having a diode-connected transistor coupled to the mirror transistors (current sources) in the various DAC cells, the effective width of the diode-connected transistor can be scaled (increased or decreased) to change the current mirror ratio, and thus change the amount of current generated by the mirror transistor. For example, if the effective width of the diode-connected transistor of the current mirror is increased by 2 times (2X), the amount of current generated by the mirror transistor (current source) is reduced by 2X.

[0101] Figure 4A , Figure 4B and Figure 4C Schematically shows an exemplary embodiment of the present disclosure that can be Figure 3 The current mode DAC 400 implemented in the current measurement circuit 300 is shown in FIG. Figure 4A As shown, the current mode DAC 400 includes a segmented DAC architecture including a prescaler DAC segment 410, a coarse DAC segment 420, a fine DAC segment 430, and a current source 435. The prescaler DAC segment 410 includes a plurality of (e.g., 3) adjustable (i.e., selectable) diode-connected transistors 410-1, 410-2, and 410-3. The coarse DAC segment 420 includes a plurality of (e.g., 7) current sources 420-1, 420-2, 420-3, 420-4, 420-5, 420-6, and 420-7. The fine DAC segment 430 includes a plurality of (e.g., 31) current sources 430-1, ..., 430-31. The current source 435 generates an input current (denoted as I REF_Cal ), which sets the current through the diode-connected transistors 410 - 1 , 410 - 2 , and 410 - 3 of the prescaler DAC segment 410 .

[0102] The prescaler DAC segment 410 operates as a diode-connected transistor that is used to generate a bias voltage for the DAC cell, and its width is programmable to M bits (e.g., M=3) of resolution. The programmable width can be used to prescale the current output level of the current mode DAC 400 based on the gain setting of the baseband signal input stage 210. In some embodiments, the coarse DAC segment 420 includes an N-bit (e.g., N=7) binary weighted current DAC, and the fine DAC segment 430 includes a P-bit (e.g., P=5) thermometer coded current DAC (also known as unary weighted). The output current of the current mode DAC 400 is the sum of the current outputs from the coarse DAC segment 420 and the fine DAC segment 430. For a given baseband gain setting, the setting of the prescaler DAC segment 410 remains fixed, while the current outputs of the coarse DAC segment 420 and the fine DAC segment 430 are dynamically adjusted via digital control to adjust the DAC output current (e.g., reference current I REF , Figure 3 ) to match the amplitude of the baseband current being measured.

[0103] In some embodiments, the DAC segments 410 , 420 , and 430 utilize the same unit current cell to reduce mismatches between the currents of the DAC segments 410 , 420 , and 430 . Figure 4BA unit current cell (1U) 440 is schematically shown according to an exemplary embodiment of the present disclosure, which is used to implement the corresponding unit cells of the DAC segments 410, 420 and 430. The unit current cell 440 includes PMOS transistors 442, 444 and 446. The PMOS transistor 442 includes a gate terminal coupled to a first control node Ctrl, a source terminal coupled to a positive power supply node VDD, and a drain terminal coupled to a gate terminal of the PMOS transistor 446. The PMOS transistor 444 includes a gate terminal coupled to a second control node Ctrlb, a source terminal coupled to a gate terminal of the PMOS transistor 446, and a drain terminal coupled to a node G, which is a gate bias voltage node of the current mode DAC 400. The PMOS transistor 446 includes a source terminal coupled to a positive power supply node VDD and a drain terminal coupled to a current output node D. The control terminals Ctrl and Ctrlb receive complementary controls to enable or disable the unit cell.

[0104] like Figure 4A As shown, the prescaler DAC segment 410 is configured to provide an adjustable reference current mirror circuit, wherein the gate (G) and drain (D) terminals are connected to form a reference current I REF In some embodiments, each of the adjustable diode-connected transistors 410-1, 410-2, and 410-3 of the prescaler DAC segment 410 includes a plurality of diode-connected transistors connected in parallel. Figure 4B For example, in some embodiments, the smallest (e.g., least significant bit, 8X) adjustable diode-connected transistor 410-1 of the prescaler DAC segment 410 includes eight (8) unit current cells 440 connected in parallel, and the remaining adjustable diode-connected transistors 410-2 and 410-3 are weighted by having an increasing number of unit current cells 440. For example, adjustable diode-connected transistor 410-2 (16X) includes 16 unit current cells 440 connected in parallel, and so on.

[0105] In addition, each current source 420-1, 420-2, 420-3, 420-4, 420-5, 420-6, and 420-7 of the coarse DAC segment 420 includes a plurality of Figure 4BFor example, in some embodiments, the smallest (e.g., least significant bit, 1X) current source 420-1 of the coarse DAC segment 420 includes eight (8) unit current cells 440 connected in parallel, and the remaining binary-weighted current sources 420-2, 420-3, 420-4, 420-5, 420-6, and 420-7 have increasing amounts of unit current cells 440. For example, current source 420-2 (2X) includes sixteen (16) unit current cells 440 connected in parallel, and so on.

[0106] Additionally, in some embodiments, each current source 430-1, ..., 430-31 of the fine DAC segment 430 includes a single unit current cell 440 (1U). This configuration provides a 4X overlap (2 bits) between the binary-weighted coarse DAC segment 420 and the thermometer-coded fine DAC segment 430, thereby achieving a 10-bit resolution for the current mode DAC 400, e.g., 7 bits (coarse DAC) + 5 bits (fine DAC) - 2 bits (overlap) = 10 bits. In this exemplary configuration, a 12-bit control signal is applied to the current mode DAC 400 to take advantage of the 4X overlap while achieving 10-bit resolution, and does not rely on matching the LSB size of the coarse DAC segment 420 and the fine DAC segment 430. As shown in FIG. Figure 4C As shown, the 5-bit digital control signal of the fine DAC segment 430 is input to the decoder 450 to generate a 31-bit control signal Ctrl[30:0] and a 31-bit complementary control signal Ctrlb[30:0] to selectively activate the corresponding current sources 430-1, ..., 430-31 of the thermometer coded fine DAC segment 430.

[0107] As described above, the LO signal output configuration circuit 180 ( Figure 1 ) includes an LO signal driver stage configured to drive the LO inputs of the first mixer circuit 141 and the second mixer circuit 142 in the mixer stage 140 with (i) a quadrature LO signal to perform I / Q modulation (in normal mode), or (ii) a DC voltage configured to selectively activate and deactivate the switching transistors of the first mixer circuit 141 and the second mixer circuit 142 to perform DC measurement of the baseband current (in calibration mode). An exemplary embodiment of the LO signal output configuration circuit 180 is Figure 5 Shown in.

[0108] Figure 5 Schematically illustrates an LO signal output configuration circuit 500 according to an exemplary embodiment of the present disclosure. The LO signal output configuration circuit 500 includes a plurality of LO driver stages 501, 502, 503, and 504, which are configured to drive orthogonal LO signals LO_I, LO_Q, and corresponding phases (e.g., corresponding phases 0°, 90°, 180°, and 270°), and generating a voltage equal to (i) a positive power supply node voltage (e.g., VDD_LO, which may be lower than VDD_RF ( Figure 2 )) or (ii) a DC voltage of a negative power supply node VSS voltage (e.g., 0V).

[0109] More specifically, if Figure 5 As shown, the first LO driver stage 501 includes a buffer stage 510 and an output configuration stage 520. The buffer stage 510 includes a CMOS inverter, and the CMOS inverter includes a PMOS transistor 512 and an NMOS transistor 514, and the PMOS transistor 512 and the NMOS transistor 514 are connected in series between a positive power supply voltage node VDD_LO and a negative power supply voltage node VSS. The source terminal of the PMOS transistor 512 is selectively connected to the positive power supply voltage node VDD_LO through a first switch 514-1. The source terminal of the NMOS transistor 514 is selectively connected to the negative power supply voltage node VSS through a second switch 514-2. The PMOS and NMOS transistors 512 and 514 have a commonly connected gate terminal, which is coupled to the input node N10 of the first LO driver stage 501. The PMOS and NMOS transistors 512 and 514 have a commonly connected drain terminal, which is connected to the output node N11 of the CMOS inverter.

[0110] In some embodiments, the first switch 514-1 includes a switch control signal The second switch 514-2 includes an NMOS transistor controlled by a switch control signal S1, which is applied to the gate terminal of the NMOS transistor. In some embodiments, the switch control signal S1 and Complementary digital control signal pairs are included so that the first switch 514-1 and the second switch 514-2 are controlled simultaneously. For example, when S1 is asserted to a logic "1" level, is asserted to a logic "0" level, and both switches 514-1 and 514-2 will be turned on (closed). On the other hand, when S1 is asserted to a logic "0" level, is asserted to a logic "1" level, and both switches 514-1 and 514-2 will be turned off (open).

[0111] In some embodiments, Figure 5As shown, the buffer stage 510 includes a single CMOS inverter stage, wherein the output node N11 of the CMOS inverter is coupled to or includes the output node OUT of the first LO driver stage 501. In other embodiments, the buffer stage 510 is implemented by cascading two CMOS inverters, wherein the output node N11 of the CMOS inverter is connected to the input node of the second CMOS inverter, and wherein the output node of the second CMOS inverter is coupled to or includes the output node OUT of the first LO driver stage 501. As known in the art, the cascaded combination of the two CMOS inverters returns the input LO signal to the original phase.

[0112] The output configuration stage 520 includes a first switch 522-1 and a second switch 522-2. The first switch 522-1 is coupled between a positive power supply node VDD_LO and an output node OUT of the first LO driver stage 501. The second switch 522-2 is coupled between a negative power supply node VSS and an output node OUT of the first LO driver stage 501. In some embodiments, the first switch 522-1 includes a PMOS transistor controlled by a switch control signal PU1 (or a pull-up control signal) applied to its gate terminal, and the second switch 522-2 includes an NMOS transistor controlled by a switch control signal PD1 (or a pull-down control signal) applied to its gate terminal.

[0113] In a normal operating mode, the first LO driver stage 501 is configured to drive one of the phases of the quadrature LO signals LO_I, LO_Q, and Specifically, in normal mode, by asserting the switch control signals S1 and The first LO driver stage 501 activates (closes) the first switch 514-1 and the second switch 514-2 by applying the pull-up control signal PU1 and the pull-down control signal PD1 to deactivate (open) the first switch 522-1 and the second switch 522-2 to maintain the output configuration stage 520 in a deactivated state. In this configuration, the first LO driver stage 501 drives the LO input signal LOIn applied to the input node N10 of the buffer stage 510, and outputs a switching LO signal LO Out (rail-to-rail switching) having a target LO frequency (e.g., 5 GHz).

[0114] On the other hand, in the calibration operation mode, the first LO driver stage 501 is configured to output a DC LO signal at a logic "0" level or a logic "1" level. Specifically, in the calibration mode, by deasserting the switch control signals S1 and The first LO driver stage 501 is configured to deactivate (disconnect) the first switch 514-1 and the second switch 514-2, while activating the output configuration stage 520 by applying the pull-up control signal PU1 and the pull-down control signal PD1 to activate one of the first switch 522-1 and the second switch 522-2. For example, the first LO driver stage 501 can be configured to output a DC voltage at a logic "1" level by activating the first switch 522-1 and pulling the output node up to the positive power rail voltage VDD_LO (e.g., 0.9V), keeping the second switch 522-2 deactivated. Alternatively, the first LO driver stage 501 can be configured to output a DC voltage at a logic "0" level by activating the second switch 522-2 and pulling the output node down to the negative power rail voltage VSS (e.g., 0V), while keeping the first switch 522-1 deactivated.

[0115] It should be understood that, although for ease of explanation, Figure 5 An exemplary circuit configuration of the first LO driver stage 501 is depicted, but the second LO driver stage 502, the third LO driver stage 503, and the fourth LO driver stage 504 have the same circuit configuration as the first LO driver stage 501 and operate in a similar manner, wherein in the exemplary embodiment, the first LO driver stage 501 is configured to drive LO_I and the second LO driver stage 502 is configured to drive The third LO driver stage 503 is configured to drive LO_Q, and the fourth LO driver stage 504 is configured to drive However, no

[0116] The LO driver stages 501, 502, 503 and 504 are controlled by respective control signals S x , As well as PUx, PD x Individual control, where x = 1, 2, 3, 4. Each drive level control signal S x , As well as PUx, PD x This allows the LO driver stages 501 , 502 , 503 , and 504 to be individually controlled as needed to configure the LO signal output configuration circuit 500 for normal and calibration modes of operation.

[0117] For example, Figure 6 Table 600 is shown for configuring an RF signal generator system and a calibration system in a calibration mode to measure various baseband currents according to an exemplary embodiment of the present disclosure. Specifically, Figure 6 FIG. 1 shows an exemplary embodiment according to the present disclosure. Figure 3 The current measurement circuit 300 of the embodiment of the present invention is different from the states of the first switch SW0 and the second switch SW1 and the orthogonal LO signal LO_I, LO_Q and (Its Figure 5 How different DC voltages (generated programmably by the LO signal output configuration circuit 500) can be set to measure the current commutated mixer stage 220 ( Figure 2 ) generated on the first output node INT_0 and the second output node INT_1 + ,I - , Q + and Q - .

[0118] like Figure 2 , Figure 3 and Figure 5 As shown together, in the calibration mode, the LO_I signal having a DC voltage of logic “0” (low) may be applied to the I mixer 220-1 (where LO_Q and ) and activates switch SW1 (where switch SW0 is deactivated) to measure the baseband current I + , or (ii) by placing a DC voltage having a logic “0” on the first output node INT_0 The signal is applied to the I mixer 220-1 (where LO_I, LO_Q and ) and activate switch SW0 (where switch SW1 is deactivated) to measure the baseband current I + In addition, in the calibration mode, the LO_I signal having a DC voltage of logic “0” may be applied to the I mixer 220-1 (where LO_Q and ) and activate switch SW0 (where switch SW1 is deactivated) to measure the baseband current I - , or (ii) by placing a DC voltage having a logic “0” on the second output node INT_1 The signal is applied to the I mixer 220-1 (where LO_I, LO_Q and ) and activate switch SW1 (where switch SW0 is deactivated) to measure the baseband current I - .

[0119] In addition, in the calibration mode, the LO_Q mixer 220-2 (where LO_I, Each of the switches SW1 and SW0 is deactivated to measure the baseband current Q at the second output node INT_1. + , or (ii) by placing a DC voltage with a logic “0” The signal is applied to the Q mixer 220-2 (where LO_I, and LO_Q are each set to a DC voltage of logic "1"), and the switch SW0 is activated (where the switch SW1 is deactivated) to measure the baseband current Q at the first output node INT_0 + In addition, in the calibration mode, the baseband current Q can be measured at the first output node INT_0 by (i) applying an LO_Q signal having a DC voltage of logic “0” to the Q mixer 220-2 (where each of LO_I, LO_I and LO_Q is set to a DC voltage of logic “1”), and activating the switch SW0 (where the switch SW1 is deactivated). - , or (ii) by applying an LO_Q signal having a DC voltage of logic “0” to the Q mixer 220-2 (where each of LO_I, LO_I and LO_Q is set to a DC voltage of logic “1”), and activating switch SW1 (where switch SW0 is deactivated) to measure the baseband current Q at the second output node INT_1 - .

[0120] It should be noted that Figure 6 The exemplary table 600 shown in FIG. 6 shows different switch configurations in the calibration mode for measuring individual DC baseband currents I + ,I - , Q + and Q - In other embodiments, the sum of the two DC baseband currents (eg, I ) may be measured at a given time by simultaneously activating the mixer transistor in the I mixer 220-1 and the mixer transistor in the Q mixer 220-2 at a given time. + +Q + ). It should also be noted that the two output nodes INT_0 and INT_1 coupled to the current-commutated mixer stage 220 are Figure 3 The current measurement circuit 300 provides a balanced load on the two output nodes INT_0 and INT_1 during the normal operation mode of the RF signal generator system (when the calibration circuit is deactivated). In addition, although the same baseband current (e.g., I +), but in some embodiments, the calibration process is configured to measure the same baseband current on both nodes INT_0 and INT_1 separately to obtain better accuracy, for example, measuring the baseband current I on node INT_0 + , measure the baseband current I on node INT_1 + , and calculate the average of the two baseband current measurements.

[0121] Fig. 7A and Figure 7B The present invention illustrates a process for calibrating baseband current in an RF signal generator system according to an exemplary embodiment of the present disclosure. More specifically, Fig. 7A A flow chart of an exemplary signal calibration process is shown, and Figure 7B is a waveform diagram showing an exemplary operating mode of the current measurement circuit. For illustration purposes, Figure 2 and Figure 3 The exemplary embodiments of the RF signal generator and calibration system shown in the FIG. Fig. 7A and Figure 7B . refer to Fig. 7A , a calibration process is initiated by the calibration system (block 700) to calibrate the baseband signals (e.g., I / Q signals) of the RF signal generating system. Depending on a given application of the RF signal generator system, the calibration process may be automatically initiated by the calibration system when the RF signal generator system is powered on. Furthermore, in some embodiments, the calibration process may be automatically or manually performed at any time during an idle operating mode of the RF signal generator system.

[0122] The calibration process includes an initialization phase in which various settings are applied to configure the RF signal generator system and the calibration mode of the calibration system. For example, a digital control signal is applied to the amplifier / attenuation stage at the output of the mixer stage to turn off all transistors in the amplifier / attenuation stage, thereby turning off the amplifier / attenuation stage (step 701). Specifically, in Figure 2 In the exemplary embodiment, as described above, a DC voltage of logic "1" is applied to the gate terminals of all transistors in the signal attenuation stage 230 to turn off all transistors, which results in completely turning off the signal attenuation stage 230, so that the DC baseband current I to be measured + ,I - , Q + and Q - The output from the current commutated mixer stage 220 is routed into the current measurement circuit 250 .

[0123] In addition, the initialization phase includes setting the baseband gain of the baseband input stage to a desired level (block 702). Figure 2In an exemplary embodiment of the invention, the baseband signal input stage 210 includes variable width transistors 211, 212, 213, and 214, which can be configured to adjust the baseband signal gain in the I / Q signal path. For example, as described above, in some embodiments, the DC baseband current can be adjusted to one of various target current levels within a given range, wherein the highest baseband current level is approximately 10 times greater than the lowest baseband current level (e.g., a range from about 35 μA to about 350 μA) to provide a 20 dB gain change. For initial setup and baseband signal measurement, the transistors 211, 212, 213, and 214 of the baseband signal input stage 210 can be set to the lowest gain setting (e.g., the minimum width setting for the lowest baseband current).

[0124] In addition, the initialization phase includes adjusting the current DAC segment of the current measurement circuit 250 based on the current gain setting of the baseband signal input stage 210 and setting the initial code of the current mode DAC to the mid-value level (block 703). As described above, in some embodiments, the current mode DAC (which is implemented in the current measurement circuit) is configured to operate over the full range of current levels of the DC baseband signal to be measured (which depends on the baseband signal gain). In this regard, depending on the gain setting of the baseband signal input stage 210, the current sources of the coarse and fine segments of the current DAC can be scaled (e.g., increased or decreased) according to the baseband gain setting to achieve appropriate and accurate measurement of the DC baseband current.

[0125] Next, the calibration process configures the current measurement circuit to enable the target baseband current to be measured to be input from a given output node of the mixer stage (block 704). Figure 3 In the exemplary embodiment shown in , the current measurement circuit system 300 may be configured to input a baseband current on the output node INT_0 by activating the switch SW0 of the first current sink circuit 310 (while keeping the switch SW1 off) and deactivating the switch SW2 to thereby configure an active current mirror circuit including the transistor 312 (in a diode-connected transistor configuration) and the mirror transistor 330. Alternatively, the current measurement circuit system 300 may be configured to input a baseband current on the output node INT_1 by activating the switch SW1 of the second current sink circuit 320 (while keeping the switch SW0 off) and deactivating the switch SW2 to thereby configure an active current mirror circuit including the transistor 322 (in a diode-connected transistor configuration) and the mirror transistor 330.

[0126] Additionally, the LO signal input applied to the mixer in the mixer stage is configured with an appropriate DC voltage so that the mixer stage outputs a target DC baseband current to be measured at a target output node (block 705). For example, as described above, in some embodiments, the current commutated mixer stage 220 ( Figure 2) are selectively activated / deactivated by applying a DC LO voltage (logic high or logic low) to the gate terminals of the mixing transistors to output a target DC baseband current to be measured at one of the output nodes INT_0 or INT_1 of the current commutated mixer stage 220. For example, Figure 6 As shown in Table 600 of FIG. 6A , by applying a DC LO voltage of logic “0” (low) to the LO_I input of the differential I mixer 220-1 and a DC LO voltage of logic “1” to the LO_I input of the differential I mixer 220-1 and the differential Q mixer 220-2, LO_Q and input, can generate a DC baseband current I + And output it to the node INT_1. When the INT_1 input of the second current sink circuit 320 is enabled, the DC baseband current I + will be measured by the current measurement circuit 300 .

[0127] When the DC baseband current flows into the current measurement circuit system 300, the comparator 350 compares the voltage (V IN ) and the reference voltage V REF (e.g., 1 / 2 VDD), and the control process will determine the initial logic level generated at the output of the comparator 350 (block 706). If the comparator output is determined (in block 706) to be at an initial logic "0" level, this is a result of the DC baseband current being greater than the DAC reference current I output from the current DAC circuit 340. REF In response, the control process will adjust (e.g., increment) the code setting of the current DAC circuit 340 to increase the reference current I generated and output from the current DAC circuit 340. REF In some embodiments, the DAC code is adjusted using a suitable binary search process to select the next code setting for the current DAC circuit 340. After the code setting of the incremental current DAC circuit 340, control will determine whether the comparator output is still at the initial logic "0" level (block 708).

[0128] The code setting of the current DAC circuit 340 is incrementally adjusted while the comparator output remains at the initial logic “0” level (repeating blocks 707 and 708) until the output of the comparator 350 switches from the initial logic “0” level to the logic “1” level. When control determines that the output of the comparator 350 is no longer at the initial logic “0” level (a negative determination in block 708), control determines the reference current I output from the current DAC circuit 340 to be REFis equal to or at least substantially equal to the measured DC baseband current, and control will record (eg, store) the current DAC code setting (block 709), wherein the recorded code setting represents a measurement of the DC baseband current.

[0129] On the other hand, if it is determined that the comparator output is at the initial logic “1” level (in block 706 ), then this is a signal that the DC baseband current is less than the DAC reference current I output from the current DAC circuit 340 . REF In response, the control process will adjust (e.g., decrement) the code setting of the current DAC circuit 340 to reduce the reference current I generated and output from the current DAC circuit 340. REF In some embodiments, the DAC code is adjusted using a suitable binary search process to select the next code setting for the current DAC circuit 340. After decrementing the code setting of the current DAC circuit 340, control will determine whether the comparator output is still at the initial logic "1" level (block 711).

[0130] The code setting of the current DAC circuit 340 is incrementally adjusted while the comparator output remains at the initial logic "1" level (repeating blocks 710 and 711) until the output of the comparator 350 switches from the initial logic "1" level to the logic "0" level. Specifically, when the control process determines that the output of the comparator 350 is no longer at the initial logic "1" level (a negative determination in block 711), the control process determines that the reference current I output from the current DAC circuit 340 is REF is equal to or at least substantially equal to the measured DC baseband current, and control will record (eg, store) the current DAC code setting (block 709), wherein the recorded code setting represents a measurement of the DC baseband current.

[0131] Once the code setting has been recorded for the measured DC baseband current, the control process will determine all the individual I-phase and Q-phase baseband components I for a given baseband gain setting. + ,I - , Q + and Q - If there are one or more additional DC baseband currents to be measured (negative determination in block 712), the calibration process flow returns to block 703, where the current DAC circuit 340, current sink circuits 310 and 320, and the DC LO input to the mixer stage are initialized and configured as needed to measure the next selected DC baseband current using the same measurement process discussed above (blocks 706-711).

[0132] When all individual I-phase and Q-phase baseband components I have been completed for a given baseband gain setting, + ,I - , Q + and Q - When the DC baseband current measurement is determined (affirmative determination in block 712), the control process will determine the DC baseband current measurement (for all individual I-phase and Q-phase baseband components I + ,I - , Q + and Q - ) is complete (block 713). If there are one or more additional baseband gain step settings for the DC baseband current that need to be measured (negative determination in block 713), the calibration process flow returns to block 702, where the baseband gain setting is set to the next gain step setting, and the current DAC circuit 340, current sink circuits 310 and 320, and DC LO inputs to the mixer stage are initialized and configured as needed to measure the DC baseband current for the first selection of the new baseband gain setting using the same measurement process discussed above (blocks 706-711).

[0133] When the DC baseband current is measured (for all individual I and Q phase baseband components I + ,I - , Q + and Q - ) When all baseband gain step settings are complete (affirmative determination in block 713), the calibration database will have the most recently recorded DC baseband current I for each measured baseband gain step setting. + ,I - , Q + and Q - The control process will then continue to adjust the first and second DC offset compensation DACs 270 and 272 as needed ( Figure 2 ) to minimize (i) the DC baseband current I for the selected baseband gain setting + and I - (ii) DC baseband current Q + and Q - and (iii) I + and Q + The offset (imbalance) between the DC baseband currents I and I is determined (block 714), at which point the calibration process terminates (block 715). If the baseband gain setting is subsequently adjusted (increased or decreased), the calibration system can access the calibration database to determine the most recently recorded current DAC code for the measured DC baseband current I + ,I - , Q + and Q- , for the newly adjusted baseband gain setting.

[0134] After the measurement, the four I-phase and Q-phase baseband components (I + ,I - , Q + , Q - ), and the difference between the codes represents the imbalance that contributes to the spurs (e.g., I + and I - The offset between represents the DC offset that causes LO leakage, and I + and Q + The offset between represents an amplitude imbalance that degrades image rejection.) In this way, both image rejection and LO leakage can be improved through calibration to provide an RF signal generator system with excellent spurious performance.

[0135] Figure 7B 720 is a diagram showing an exemplary mode of operation of the current measurement circuit when performing a comparison process to measure the DC baseband current. Figure 3 An exemplary comparison process performed by the current measurement circuit 300 is described in the context of Figure 7B .exist Figure 7B , the Y-axis shows the voltage in millivolts (mV) in the range of 0V (eg, VSS) to 900mV (eg, VDD), and the X-axis shows the digital code of the current DAC used to generate the reference current (eg, ranging from 0 to 100).

[0136] also, Figure 7B Exemplary voltage waveforms 722, 724, and 726 are shown. Exemplary voltage waveform 722 represents a DC reference voltage V applied to the inverting (-) input of comparator 350. REF For example, the reference voltage V REF is shown as 450 mV (1 / 2 VDD). Example voltage waveform 724 represents the input voltage V generated at high impedance node N2 and applied to the non-inverting (+) input terminal of comparator 350. IN In addition, the exemplary voltage waveform 726 represents the voltage waveform generated by the comparator 350 by comparing the input voltage V IN Waveform 724 and DC reference voltage V REF The resulting comparator output voltage.

[0137] Figure 7B The comparison process shows that for a given measured DC baseband current, as the reference current I generated by the current DAC circuit 340 REFThe digital code increases, the measured DC baseband current is compared with the reference current I output from the current DAC circuit 340 REF The difference between them decreases, and the input voltage V IN Waveform 724 increases. When the input voltage V IN Waveform 724 increases to the DC reference voltage V REF 722 crosses the level, the comparator output voltage waveform 726 transitions (switches) from 0V (VSS) to 900mV (VDD), and the measurement ends. The comparator output voltage waveform 726 switches from logic "0" to logic "1" of the reference current I generated by the current DAC circuit 340. REF The digital code represents an estimated measurement of a given DC baseband current. Figure 7B In the exemplary embodiment of FIG. 5 , the digital code value 70 of the current DAC circuit 340 corresponds to an estimated measurement of the DC baseband current.

[0138] It should be noted that the calibration technique described above includes a static current measurement technique configured to compensate for, for example, (i) mismatch between baseband input transistors 211 and 212 for the I phase (compensation I + and I - (ii) the imbalance between the baseband DC currents for the Q phase and the baseband input transistors 213 and 214 (compensating for the Q + and Q - baseband DC currents), and (iii) the imbalance between the differential input transistor pairs 210-1 and 210-2 (compensating I + and Q + The calibration is performed with zero differential voltage applied to the in-phase inputs (I(t) and I(t)) and the quadrature-phase inputs (Q(t) and Q(t)). In this regard, the calibration is performed to provide current compensation to ensure that, for example, the DC baseband current I + and I - The difference between is zero (or substantially zero).

[0139] However, in real-time operation of the RF signal generator system, there may be a duty cycle-induced DC offset caused by the quadrature-phase LO signal that does not have a 50% duty cycle. More specifically, when the LO_I signal and / or the LO_Q signal have a duty cycle less than 50% or greater than 50%, the LO signal may introduce unwanted LO tones in the RF output signal of the RF signal generator system due to a non-zero differential average LO current substantially injected into the I / Q signal path, which may result in LO leakage and / or degraded image rejection.

[0140] In this regard, exemplary embodiments of the present disclosure also include calibration circuits and methods to calibrate the DC offset caused by the duty cycle generated by the quadrature phase LO signal that does not have a 50% duty cycle. Specifically, in some embodiments, the calibration system is configured to apply the switching LO signal to the Figure 2 Dynamic current measurement is performed by applying a static DC voltage of logic "1" to one of the LO inputs of the differential I and Q mixers 220-1 and 220-2 of the current commutation mixer stage 220 to generate an up-converted RF current signal through one mixer transistor driven by the switching LO signal, while applying a static DC voltage of logic "1" to the other LO input of the differential I and Q mixers 220-1 and 220-2 of the current commutation mixer stage 220 to turn off the other mixer transistors. For dynamic measurement, the following combination Figure 8 and Fig. 9 As explained in further detail, the current measurement circuit is configured to receive as input the up-converted RF current signal output from the current-commutated mixer stage 220 and to extract and measure a DC component of the up-converted RF current signal.

[0141] For example, Figure 8 Schematically illustrates a current measurement circuit 800 implemented by a calibration system to measure the DC component of an up-converted RF current signal according to an exemplary embodiment of the present disclosure. Figure 3 The current measurement circuit system 300 of FIG. 800 is shown in FIG. 800 , except that the current measurement circuit system 800 includes a filter circuit 810 configured to remove high frequency components of an up-converted RF current signal output from the mixer stage as a result of applying an AC switching LO input signal (which is being tested for duty cycle error) to the mixer stage in a calibration mode and input to the current measurement circuit system 800 to measure a DC offset of the up-converted RF current signal. The presence of a non-zero DC offset current caused by the switching LO signal is an indication of a duty cycle error of the switching LO signal.

[0142] In some embodiments, Figure 8 As shown, the filter circuit 810 includes a low-pass RC filter circuit including a resistor 812 coupled between nodes N1 and N3, and a capacitor 814 coupled to and between node N3 and a negative power supply node VSS. The gate terminal of the mirror transistor 330 is coupled to the node N3 (which is the output node of the filter circuit 810). In some embodiments, the use Figure 8 The current measurement circuit 800 is implemented Figure 2In such an embodiment, current measurement circuitry 800 operates in the same or similar manner as current measurement circuitry 300 described above, except that current measurement circuitry 800 may be used to measure a DC baseband current or a DC offset of an upconverted RF current signal, depending on a given calibration operating mode.

[0143] It should be noted that dynamic baseband current measurements using a switched LO signal can be performed using the same or similar techniques as discussed above for performing static baseband current measurements. For example, in some embodiments, in addition to applying a switched LO signal (rather than a static LO voltage) to a given input of the mixer transistor to generate an up-converted RF current signal on one of the output nodes INT_0 or INT_1 for input to the current measurement circuit 800, Figure 6 The parameters shown in Table 600 can be used to configure circuit 500 by controlling the LO signal output ( Figure 5 ) and configure the current measurement circuit 800 for use in a calibration mode to perform dynamic current measurements.

[0144] For example, in the calibration mode, the LO_I signal may be applied to the differential I mixer 220-1 (where LO_Q and The up-converted RF current signal (RF_I + ), and the up-converted RF current signal is input to the current measurement circuit 800 by activating switch SW1 (where switch SW0 is deactivated). The signal is applied to the differential I mixer 220-1 (where LO_I, LO_Q and The up-converted RF current signal (RF_I + ), and the up-converted RF current signal is input to the current measurement circuit 800 by activating the switch SW0 (where the switch SW1 is deactivated).

[0145] In this example, the DC voltage output from the filter circuit 810 at the node N3 corresponds to the up-converted RF current signal (RF_I + ) time average current (DC offset current), which provides information about the duty cycle of the switching LO_I signal. The current measurement circuit 800 uses the same current measurement techniques discussed above (e.g., Fig. 7A and 7B ) to determine the up-converted RF current signal (RF_I +) DC offset. Corresponding to the up-converted RF current signal (RF_I + The final digital DAC code of the current DAC circuit 340 with the DC offset measured by the DAC circuit 340 is recorded in the calibration database. In this case, the measured DC offset current will include (i) the DC baseband current (bias current) generated from the baseband signal input stage 210 and (ii) the DC offset current (if any) generated due to the duty cycle error (if any) of the switching LO signal.

[0146] Similar dynamic baseband current measurements may be performed separately to determine other up-converted RF current signals (e.g., RF_I - RF_Q + and RF_Q - ) of the DC offset. The digital code of the current DAC circuit 340 (which represents the corresponding up-converted RF current signal (e.g., RF_I - RF_Q + and RF_Q - ) is recorded in the calibration database. These digital codes can be used to obtain information about the DC offset current generated due to LO duty cycle error. For example, (i) represents the measured DC baseband current I + The digital DAC code and (ii) represent the up-converted RF current signal RF_I + The difference between the digital DAC codes of the measured DC offset currents of LO_I can provide relative information about the amount of LO_I duty cycle error. It should be noted that in some embodiments, the LO_I duty cycle error can be measured by using the first DAC circuit 121 and the second DAC circuit 122 ( Figure 1 ) adjust the basic baseband signal component I + and Q + To correct the imbalance caused by duty cycle.

[0147] Next, Fig. 9 The current measurement circuit 900 is schematically illustrated as being implemented by a calibration system to measure a DC component of an up-converted RF current signal according to another exemplary embodiment of the present disclosure. Figure 8The current measurement circuit system 800 is shown in FIG. 8 , except that the current measurement circuit system 900 includes a filter circuit 910 coupled to the high impedance node N2 to remove high frequency components. In some embodiments, the filter circuit 910 includes a low pass filter including a capacitor 912 coupled to the node N2 and the negative power supply node VSS and between the node N2 and the negative power supply node VSS. The current measurement circuit 900 operates in a manner similar to the current measurement circuits 300 and 800 described above. The implementation of the filter circuit 910 at the high impedance node N2 is used to reduce the swing and enhance the measurement accuracy.

[0148] It should be appreciated that the exemplary calibration systems, circuits, and methods as discussed herein provide significant advantages over conventional techniques commonly used to calibrate RF signal generators and the like. For example, as described above, conventional techniques include RF measurement techniques utilizing on-chip or off-chip instruments that are configured to analyze an RF signal generated by an RF signal generator using, for example, a complex spectrum analyzer or a down-conversion receiver (in a feedback loop) to extract a baseband signal component from the RF signal, and calibrate a DAC to compensate for an imbalance detected in the extracted baseband signal component. Conventional RF measurement techniques are expensive in terms of complexity, resource usage, and area overhead required for on-chip implementation. In addition, such conventional RF techniques consume a large amount of power, which is prohibitive at cryogenic temperatures.

[0149] Compared to conventional calibration techniques that perform RF measurements, the exemplary calibration techniques disclosed herein utilize DC baseband current measurements, which are easier to perform and less time-consuming than RF measurements. Furthermore, compared to using an on-chip spectrum analyzer or loopback receiver to detect signal imbalance, the exemplary DC baseband current measurement techniques discussed herein are significantly less costly in terms of hardware complexity and resources. Furthermore, the DC current measurement hardware and other calibration-related hardware can operate at very low power (e.g., milliwatts), and such hardware has a relatively low footprint (occupying a small chip area), which is advantageous for on-chip implementation.

[0150] Another advantage to note is that the same current measurement hardware (e.g., such as Figure 3 , Figure 8 and Fig. 9 The current measurement circuit shown in the figure is used to measure all I-phase and Q-phase baseband components I + ,I - , Q + , Q - In this regard, the current measurement is insensitive to the inherent offset of the current measuring instrument, and thus inaccuracies in the current measuring hardware will not adversely affect the accuracy of the measurement. For example, since the same current measurement hardware is used to measure all I-phase and Q-phase baseband components I + ,I -, Q + , Q - The DC current is therefore the same as the DC current measured by the circuit, so in the absence of drift, any inherent offset in the circuit (e.g., comparator offset) will be applied to all DC current measurements, which effectively cancels out this inherent error in the DC current measurement. In this regard, the measurement instrument does not need high absolute accuracy to ensure that all baseband currents are equal to each other, because any inherent error in the measurement will not affect the calibration process by equalizing {I + ,I -}, {Q + ,Q -} and {I + ,Q +}'s baseband current to correct the imbalance in the I / Q baseband current.

[0151] Furthermore, the same calibration hardware is used to calibrate both LO leakage and image rejection. Furthermore, since the same hardware is used to measure all I-phase and Q-phase baseband components I + ,I - , Q + , Q - The total area required to calibrate the instrument is significantly reduced because it can measure the DC current and correct the imbalance. For example, with on-chip instrumentation, the same calibration hardware is used to measure all I and Q baseband components I + ,I - , Q + , Q - Allows for reducing the area overhead required for on-chip instrumentation, for example to less than 10%.

[0152] Another advantage to note is the low impedance nodes at the output of the current mode stage of the RF signal generator system (e.g., nodes INT_0 and INT_1, Figure 2 ) is used to minimize the loading effect of the current measurement circuit and therefore minimize any reduction in bandwidth during normal mode operation of the RF signal generator system.

[0153] In addition, further, Figure 2 In an exemplary embodiment of , in which the current measurement circuit is coupled to the output node of the current-commutated mixer stage 220, the voltage headroom across the transistors in the baseband signal input stage 210 and the transistors in the current-commutated mixer stage 220 can be kept substantially the same, thereby ensuring that in the calibration mode, the DC baseband current is measured under conditions that match those in the normal operating mode. In other words, Figure 2 The architecture shown in maintains similar voltage headroom across the baseband transistors and the mixer transistors in both normal mode and calibration mode.

[0154] Another advantage to note is that the current measurement circuit utilizes a wide range, high resolution current mode DAC with a coarse DAC segment and a fine DAC segment for use over a wide range of reference currents I REF Generate a reference current I with the desired resolution REF , performing a current comparison between the measured baseband current and the reference current with high accuracy. In addition, as described above, in order to support wide range scaling, the current mode DAC implements a prescaler DAC segment, which is used to scale the output range of the current mode DAC so that the output reference current I generated by the current mode DAC REF It can be scaled to be commensurate with the amplitude level of the baseband current to be measured, thereby allowing DC measurements to be performed at higher and lower amplitude levels (e.g., varying over a 10X range such as from 35 μA to 350 μA).

[0155] Another advantage to note is that the current imbalance detected by the calibration system is corrected using a current imbalance correction circuit that is configured to inject additional current into the baseband signal path. For example, LO leakage calibration control is provided by adjusting the digital code of the offset control DAC located at the output of the baseband stage. The same offset control DAC can be used to equalize the I current and the Q current. If gain adjustment is required between channels, the reference currents of the IDAC and QDAC can be adjusted.

[0156] Another advantage to note is that the exemplary calibration circuits as described herein are configured to operate at low power (e.g., milliwatt range) and low area overhead, which allows such calibration circuits to be easily implemented as on-chip calibration instruments to calibrate cryogenic electronics for quantum computing applications and other applications or systems operating at cryogenic temperatures. For example, in the context of quantum computing systems implementing superconducting qubits and other components, the exemplary calibration circuits as described herein can be easily implemented on a chip with an AWG system. In such an embodiment, the on-chip calibration instrument is utilized to calibrate the AWG system to generate high-fidelity RF control pulses to control superconducting qubits, thereby achieving high-fidelity qubit gate operations (e.g., single-qubit gate operations, entangled gate operations, etc.). Specifically, the exemplary calibration techniques as discussed herein can be used to generate high-fidelity RF control pulses that are free of or have significantly suppressed LO leakage and sideband image spurs that would otherwise result in lower-fidelity gate operations.

[0157] Fig.10A quantum computing system 1000 implementing an arbitrary waveform generator system and a calibration circuit according to an exemplary embodiment of the present disclosure is schematically shown. The quantum computing system 1000 includes an arbitrary waveform generator system 1002 (or an AWG system 1002) and a quantum processor 1004. The quantum processor 1004 includes a plurality (n) of superconducting qubits 1006-1, ..., 1006-n. The superconducting qubits 1006-1, ..., 1006-n may include superconducting transmon qubits, superconducting fluxonium qubits, superconducting multimode qubits, and other types or combinations of different types of superconducting qubits suitable for a given application. In addition, in some embodiments, the quantum processor 1004 includes a coupler circuit (e.g., a passive coupler circuit and / or an active coupler circuit), wherein a given coupler circuit is configured to couple a pair of superconducting qubits to implement an entangled gate operation (e.g., a two-qubit gate operation).

[0158] Quantum processor 1004 also includes a plurality of control lines (e.g., transmission line resonators), including but not limited to qubit drive lines, flux bias lines, state readout lines, and active coupler drive lines, etc. In some embodiments, the qubit drive lines are coupled (e.g., capacitively coupled) to corresponding superconducting qubits in superconducting qubits 1006-1, ..., 1006-n. The qubit drive lines are configured to apply RF control pulses (generated by AWG system 1002) to corresponding superconducting qubits 1006-1, ..., 1006-n to independently change the state of the corresponding superconducting qubit (e.g., single-qubit gate operation), for example, to change the state of a given superconducting qubit to be in, for example, a ground state |0>, ..., an excited state |1>, ..., or a superposition state. As is known in the art, the qubit drive lines can be coupled (e.g., capacitively coupled) to corresponding superconducting qubits in superconducting qubits 1006-1, ..., 1006-n by applying RF control pulses (generated by AWG system 1002) to corresponding superconducting qubits 1006-1, ..., 1006-n. 01 ) to change the state of the superconducting qubit, where the transition frequency f 01 Corresponds to the energy difference between the ground state |0> and the excited state |1> of the qubit. In some embodiments, superconducting qubits 1006-1, ..., 1006-n are configured to have different operating frequencies (transition frequencies) such that the transition frequencies of adjacent qubits are detuned.

[0159] The state readout line is coupled to a corresponding superconducting qubit in superconducting qubits 1006-1, ..., 1006-n to read the state of the superconducting qubit using known techniques (e.g., dispersion readout). In embodiments where the superconducting qubits include frequency tunable qubits (e.g., flux tunable transmon qubits or fluxonium qubits, etc.), the flux bias control line will be coupled (e.g., inductively coupled) to the corresponding superconducting qubit to apply a flux bias control signal to the tuning structure of the superconducting qubit, thereby tuning the operating frequency of the tunable qubit as required for a given application. In addition, for active coupler circuits, the coupler drive line will be coupled (e.g., capacitively coupled) to a corresponding coupler circuit, where each coupler circuit will have an operating frequency or switching frequency. A given coupler circuit will be driven by an RF control pulse generated by the AWG system 1002 or some other pulse signal generator to achieve exchange coupling between superconducting qubits coupled through a given coupler circuit and achieve dual-qubit gate operation.

[0160] like Fig.10 As shown, AWG system 1002 includes a multi-channel AWG framework including a plurality of AWG channels 1002-1, ..., 1002-c. AWG channels 1002-1, ..., 1002-c are configured to generate RF control pulses that are applied to qubit drive lines to control corresponding superconducting qubits in superconducting qubits 1006-1, ..., 1006-n. Although not shown in FIG. Fig.10 1004, but in some embodiments, the AWG system 1002 will include an AWG channel to generate a control signal that is applied to a coupler drive line to control an active coupler device of the quantum processor 1004.

[0161] AWG channels 1002-1, ..., 1002-c each include a corresponding control pulse envelope generator 1010, a DAC stage 1020, a baseband filter stage 1030, an I / Q mixer stage 1040, an amplifier / attenuator stage 1050, a matching network 1060, an LO signal generator circuit 1070, and an LO signal output configuration circuit 1080. The control pulse envelope generator 1010 is configured to implement a pulse shaping technique to generate an RF control pulse having a desired control pulse envelope shape (e.g., a Gaussian pulse, a cosine pulse (e.g., a sum of half cosines), a hyperbolic secant pulse, etc.), which is applied to a superconducting qubit or an active qubit coupler circuit to perform a single qubit gate operation, an entangled gate operation, etc. The shaped control pulse is calibrated to drive the f of the qubit. 01 transition, while suppressing f 12and higher transitions. Essentially, this pulse shaping technique suppresses / reduces transients associated with turning on and off control pulses. Additionally, pulse shaping techniques include DRAG (Derivative Removal by Adiabatic Heat) correction pulses, which can be used in conjunction with shaped pulses (such as Gaussian, cosine, or hyperbolic secant pulses) to further suppress unwanted state transitions while maintaining the same pulse envelope area (or integral of the pulse envelope).

[0162] In each AWG channel of the AWG system 1002, the digital control pulse envelope signal (digital I and Q components) is converted to an analog control pulse envelope signal (analog baseband I / Q signal), and the I / Q mixer stage 1040 modulates the quadrature LO signal with the baseband I / Q signal by performing, for example, SSB modulation as described above, to generate a modulated signal in the form of an RF control pulse, which is applied, for example, to a qubit driver line to control a given qubit. The functions of the various stages 1020, 1030, 1050, 1060, 1070, and 1080 are similar to Figure 1 , Figure 2 The corresponding stages in the above are the same or similar, and their details will not be repeated.

[0163] like Fig.10 As further shown, in some embodiments, each AWG channel 1002-1, ..., 1002-c of the AWG system 1002 includes a dedicated calibration circuit 1090-1, ..., 1090-c, which is implemented on a chip with the AWG system 1002. The calibration circuit 1090-1, ..., 1090-c is configured to calibrate the I / Q signal current of each AWG channel 1002-1, ..., 1002-c of the AWG system 1002 when the AWG channel 1002-1, ..., 1002-c is configured in a calibration mode, as described above. The calibration circuit 1090-1, ..., 1090-c includes hardware control and logic circuits (e.g., current measurement circuits, current mode DACs, control logic circuits, current imbalance correction circuits, etc.) as described above. In some embodiments, the calibration circuit 1090-1, ..., 1090-c is controlled by software running on a computing platform that controls the quantum computing system 1000.

[0164] For example, Fig.11 A quantum computing system according to another exemplary embodiment of the present disclosure is schematically shown. Specifically, Fig.11A quantum computing system 1100 is schematically shown, comprising a quantum computing platform 1110, a control system 1120, and a quantum processor 1130. In some embodiments, the quantum computing platform 1110 implements a software control program, such as a calibration control process 1112, which performs functions such as configuring the AWG system and calibration circuitry to be in a calibration mode, controlling execution of high-level functions of the calibration process, and the like.

[0165] In addition, the quantum computing platform 1110 performs a calibration process that is periodically performed on a quantum system such as a quantum processor to calibrate various quantum elements such as readout resonators, data qubits, and coupler circuits to achieve high-fidelity gate operations (e.g., single-qubit gate operations and entangled gate operations). For example, various types of in-situ calibration procedures are periodically performed to, for example, determine the resonant frequency of the readout resonator, determine the transition frequency of the qubit, determine the coherence time (T1) of the qubit (where the coherence time T1 of a given qubit represents the time it takes for the qubit state to decay from an excited state to a ground state), determine the transverse relaxation time (T2) (or dephasing time) of the qubit, calibrate the RF control pulses applied to the qubit to perform single-qubit gate operations, calibrate the RF control pulses applied to the active coupler circuit to perform entangled gate operations, etc. The calibration process results in the determination of various control parameters that are maintained in the calibration database and periodically updated on the order of seconds, minutes, hours, days, etc., based on the type of quantum element and the operating characteristics of the quantum computing system, as well as other factors understood by those of ordinary skill in the art.

[0166] In some embodiments, the control system 1120 includes a multi-channel arbitrary waveform generator 1122 and a qubit readout control system 1124 (where Fig.10 An exemplary AWG system 1002 that may be embedded in a control system 1120 is schematically shown.) The quantum processor 1130 includes a solid-state semiconductor chip having an array of superconducting qubits 1132 and a network 1134 of qubit drive lines, coupler drive lines, and qubit state readout lines, as well as other circuit QED components that may be required for a given application or quantum system configuration.

[0167] In some embodiments, the control system 1120 and the quantum processor 1130 are disposed in a dilution refrigeration system 1140, which can generate cryogenic temperatures sufficient to operate components of the control system 1120 for quantum computing applications. For example, the quantum processor 1130 may need to be cooled to near absolute zero, such as 10-15 millikelvin (mK), to allow superconducting qubits to exhibit quantum behavior. In some embodiments, the dilution refrigeration system 1140 includes a multi-stage dilution refrigerator, in which components of the control system 1120 can be maintained at different cryogenic temperatures as needed. For example, while the quantum processor 1130 may need to be cooled to, for example, 10-15 mK, circuit components of the control system 1120 may be operated at cryogenic temperatures greater than 10-15 mK (e.g., cryogenic temperatures in the range of 3K-4K), depending on the configuration of the quantum computing system.

[0168] In some embodiments, the superconducting qubit array 1132 includes a plurality of superconducting transmon qubits and superconducting tunable coupler qubits, wherein each pair of superconducting qubits is connected by a corresponding superconducting qubit coupler using techniques as discussed herein. A network 1134 of qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, etc., is configured to apply microwave control signals to the superconducting qubits and coupler circuits in the superconducting qubit array 1132 to perform various types of gate operations, such as single gate operations, entangled gate operations, etc., and to read the quantum state of the superconducting qubits. The network 1134 of qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, etc., is coupled to the control system 1120 via a suitable hardware input / output (I / O) interface, which couples I / O signals between the control system 1120 and the quantum processor 1130. For example, the hardware I / O interface may include various types of hardware and components, such as RF cables, wiring, RF elements, optical fibers, heat exchangers, filters, amplifiers, isolators, etc.

[0169] The quantum computing platform 1110 includes a software and hardware platform, which includes various software layers configured to perform various functions, including but not limited to generating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into quantum assembly languages, implementing and utilizing a suitable quantum instruction set architecture (ISA), performing calibration operations to calibrate quantum circuit elements and gate operations, etc. In addition, the quantum computing platform 1110 includes a hardware architecture of processors, memories, etc., which is configured to control the execution of quantum applications and interface with the control system 1120 to (i) generate digital control signals, which are converted by the control system 1120 into analog microwave control signals to control the operation of the quantum processor 1130 when executing a given quantum application, and (ii) obtain and process digital signals received from the control system 1120, which digital signals represent processing results generated by the quantum processor 1130 when executing various gate operations of a given quantum application. In some exemplary embodiments, the quantum computing platform 1110 of the quantum computing system 1100 may use any suitable computing system architecture (e.g., such as Fig.12 The computing system architecture is implemented by executing computer-readable program instructions embodied in a computer program product to implement a method of supporting quantum computing operations, the computer program product including a computer-readable storage medium (or multiple media) having such computer-readable program instructions thereon, for causing a processor to execute a control method as discussed herein.

[0170] Various aspects of the present disclosure are described by narrative text, flow charts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flow chart, depending on the technology involved, the operations may be performed in an order different from the order shown in a given flow chart. For example, again depending on the technology involved, two operations shown in successive flow chart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0171] Computer program product embodiments ("CPP embodiments" or "CPP") are terms used in this disclosure to describe any collection of one or more storage media (also referred to as "media") collectively included in a collection of one or more storage devices that collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can retain and store instructions for use by a computer processor. Without limitation, a computer-readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), static random access memories (SRAM), compact disk read-only memories (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / land formed in a major surface of a disk), or any suitable combination of the foregoing. The term computer-readable storage medium as used in this disclosure should not be interpreted as storage in the form of a transitory signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide, a light pulse through a fiber optic cable, an electrical signal transmitted through an electric wire and / or other transmission medium. As will be understood by those skilled in the art, during normal operation of a storage device, such as during access, defragmentation, or garbage collection, data is typically moved at some occasional point in time, but this does not make the storage device transitory because the data is not transitory when it is stored.

[0172] The computing environment 1200 includes an example of an environment for executing at least some of the computer code involved in executing the methods of the present invention, such as calibration process control code 1226 for controlling the calibration process, such as Fig. 7AIn addition to the box 1226, the computing environment 1200 also includes, for example, a computer 1201, a wide area network (WAN) 1202, an end-user device (EUD) 1203, a remote server 1204, a public cloud 1205, and a private cloud 1206. In this embodiment, the computer 1201 includes a processor set 1210 (including a processing circuit 1220 and a cache 1221), a communication structure 1211, a volatile memory 1212, a permanent storage device 1213 (including an operating system 1222 and a block 1226, as identified above), a peripheral device set 1214 (including a user interface (UI), a device set 1223, a storage device 1224, and an Internet of Things (IoT) sensor set 1225) and a network module 1215. The remote server 1204 includes a remote database 1230. The public cloud 1205 includes a gateway 1240 , a cloud orchestration module 1241 , a host physical machine set 1242 , a virtual machine set 1243 , and a container set 1244 .

[0173] Computer 1201 may take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or developed in the future that is capable of running programs, accessing a network, or querying a database (such as remote database 1230). As is well understood in the field of computer technology, and depending on the technology, the execution of the computer-implemented method may be distributed among multiple computers and / or among multiple locations. On the other hand, in this presentation of computing environment 1200, the detailed discussion focuses on a single computer, particularly computer 1201, to keep the presentation as simple as possible. Computer 1201 may be located in the cloud, even if it is not in the cloud. Fig.12 On the other hand, except to any extent that can be indicated with certainty, there is no requirement that computer 1201 be in the cloud.

[0174] Processor set 1210 includes one or more computer processors of any type known now or developed in the future. Processing circuit 1220 can be distributed over multiple packages, for example, multiple coordinated integrated circuit chips. Processing circuit 1220 can implement multiple processor threads and / or multiple processor cores. Cache 1221 is a memory located in (one or more) processor chip packages, and is generally used for data or code that should be available for rapid access by threads or cores running on processor set 1210. Cache memory is generally organized into multiple levels according to relative proximity to the processing circuit. Alternatively, some or all of the caches for the processor set may be located "off-chip". In some computing environments, processor set 1210 may be designed to work with qubits and perform quantum computing.

[0175] Computer readable program instructions are typically loaded onto computer 1201 to cause processor group 1210 of computer 1201 to perform a series of operating steps to implement a computer-implemented method, such that the instructions so executed will instantiate the method specified in the flowchart and / or the narrative description of the computer-implemented method included in this document (collectively referred to as "the method of the present invention"). These computer readable program instructions are stored in various types of computer readable storage media, such as cache 1221 and other storage media discussed below. The program instructions and associated data are accessed by processor group 1210 to control and direct the execution of the method of the present invention. In computing environment 1200, at least some of the instructions for executing the method of the present invention may be stored in permanent storage device 1213 in block 1226.

[0176] Communications fabric 1211 is the signaling pathways that allow the various components of computer 1201 to communicate with each other. Typically, the fabric is made of switches and conductive pathways, such as those that make up a bus, a bridge, physical input / output ports, etc. Other types of signal communication pathways may be used, such as fiber optic communication pathways and / or wireless communication pathways.

[0177] The volatile memory 1212 is any type of volatile memory now known or developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory is characterized by random access, but this is not required unless affirmatively indicated. In the computer 1201, the volatile memory 1212 is located in a single package and is internal to the computer 1201, but alternatively or additionally, the volatile memory can be distributed over multiple packages and / or located externally relative to the computer 1201.

[0178] Permanent storage 1213 is any form of non-volatile storage for computers known now or developed in the future. The non-volatility of the storage means that the stored data is maintained regardless of whether the computer 1201 is powered and / or the permanent storage 1213 is powered directly. Permanent storage 1213 can be a read-only memory (ROM), but usually at least a portion of the permanent storage allows writing data, deleting data, and rewriting data. Some familiar forms of permanent storage include disks and solid-state storage devices. Operating system 1222 can take several forms, such as various known proprietary operating systems or operating systems of open source portable operating system interface types using a kernel. The code included in box 1226 typically includes at least some of the computer code related to the execution of the method of the present invention.

[0179] The peripheral device set 1214 includes a peripheral device set of the computer 1201. The data communication connection between the peripheral device and other components of the computer 1201 can be implemented in various ways, such as a Bluetooth connection, a near field communication (NFC) connection, a connection by a cable (such as a universal serial bus (USB) type cable), a plug-in type connection (e.g., a secure digital (SD) card), a connection through a local area network, and even a connection through a wide area network (such as the Internet). In various embodiments, the UI device set 1223 may include components such as a display screen, a speaker, a microphone, a wearable device (such as goggles and smart watches), a keyboard, a mouse, a printer, a touchpad, a game controller, and a tactile device. The storage device 1224 is an external storage device, such as an external hard drive, or a pluggable storage device, such as an SD card. The storage device 1224 can be permanent and / or volatile. In some embodiments, the storage device 1224 can take the form of a quantum computing storage device for storing data in the form of quantum bits. In embodiments where it is necessary for computer 1201 to have a large amount of storage (e.g., where computer 1201 locally stores and manages a large database), the storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 1225 consists of sensors that can be used in IoT applications. For example, one sensor may be a thermometer, while another sensor may be a motion detector.

[0180] The network module 1215 is a collection of computer software, hardware, and firmware that allows the computer 1201 to communicate with other computers via the WAN 1202. The network module 1215 may include hardware (such as a modem or a Wi-Fi signal transceiver), software for packetizing and / or depacketizing data for transmission over a communication network, and / or web browser software for communicating data over the Internet. In some embodiments, the network control function and the network forwarding function of the network module 1215 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software defined networks (SDN)), the control function and the forwarding function of the network module 1215 are executed on physically separated devices, so that the control function manages several different network hardware devices. Computer-readable program instructions for executing the method of the present invention can typically be downloaded to the computer 1201 from an external computer or an external storage device via a network adapter card or a network interface included in the network module 1215.

[0181] WAN 1202 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any technology now known or developed in the future for transmitting computer data. In some embodiments, the WAN may be replaced and / or supplemented by a local area network (LAN) (such as a Wi-Fi network) designed to transmit data between devices located in a local area. A WAN and / or LAN typically includes computer hardware such as copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.

[0182] End-user device (EUD) 1203 is any computer system used and controlled by an end-user (e.g., a customer of an enterprise operating computer 1201), and may take any of the forms discussed above in connection with computer 1201. EUD 1203 typically receives useful and useful data from the operation of computer 1201. For example, in the hypothetical case where computer 1201 is designed to provide recommendations to an end-user, the recommendations would typically be transmitted from network module 1215 of computer 1201 to EUD 1203 via WAN 1202. In this manner, EUD 1203 may display or otherwise present the recommendations to the end-user. In some embodiments, EUD 1203 may be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, or the like.

[0183] Remote server 1204 is any computer system that provides at least some data and / or functionality to computer 1201. Remote server 1204 may be controlled and used by the same entity that operates computer 1201. Remote server 1204 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 1201. For example, in the hypothetical case where computer 1201 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 1201 from remote database 1230 of remote server 1204.

[0184] The public cloud 1205 is any computer system that can be used by multiple entities, which provides on-demand availability of computer system resources and / or other computer capabilities, especially data storage (cloud storage) and computing capabilities, without the need for direct active management by users. Cloud computing generally uses resource sharing to achieve consistency and economies of scale. The direct and active management of the computing resources of the public cloud 1205 is performed by the computer hardware and / or software of the cloud orchestration module 1241. The computing resources provided by the public cloud 1205 are generally implemented by virtual computing environments running on various computers that constitute the host physical machine set 1242, which is the range of physical computers in the public cloud 1205 and / or available for the public cloud 1205. The virtual computing environment is generally in the form of a virtual machine from a virtual machine set 1243 and / or a container from a container set 1244. It should be understood that these VCEs can be stored as images and can be transmitted between and among various physical machine hosts as images or after instantiation of the VCE. The cloud orchestration module 1241 manages the transfer and storage of images, deploys new instantiations of VCEs and manages active instantiations of VCE deployments. The gateway 1240 is a collection of computer software, hardware and firmware that allows the public cloud 1205 to communicate over the WAN 1202 .

[0185] Some further explanation of virtualized computing environments (VCEs) will now be provided. A VCE can be stored as an "image". A new active instance of a VCE can be instantiated from an image. Two common types of VCEs are virtual machines and containers. Containers are VCEs that use operating system-level virtualization. This refers to an operating system feature in which the kernel allows the existence of multiple isolated user space instances (called containers). From the perspective of the programs running in them, these isolated user space instances typically behave like real computers. Computer programs running on a normal operating system can utilize all of the resources of that computer, such as connected devices, files and folders, network shares, CPU capabilities, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices assigned to the container, a feature known as containerization.

[0186] Private cloud 1206 is similar to public cloud 1205, except that the computing resources are only available to a single enterprise. Although private cloud 1206 is depicted as communicating with WAN 1202, in other embodiments, the private cloud can be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private cloud, community cloud, or public cloud types), typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple constituent clouds. In this embodiment, both public cloud 1205 and private cloud 1206 are part of a larger hybrid cloud.

[0187] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: a current measurement circuit configured to measure a first current in a first signal path of a radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during a calibration process; and A current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the RF signal generator to correct an imbalance between a measured first current and a measured second current.

2. The apparatus of the preceding claim, further comprising a control circuit configured to determine a difference between the measured first current and the measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to the current imbalance correction circuit; Wherein, in response to the control signal, the current imbalance correction circuit is configured to inject current into at least one of the first signal path and the second signal path of the RF signal generator to compensate for the determined difference between the measured first current and the measured second current.

3. The device according to any one of the preceding claims, wherein: The first current and the second current include one of: an in-phase baseband current and a quadrature-phase baseband current, a pair of complementary in-phase baseband currents, and a pair of complementary quadrature-phase baseband currents.

4. The apparatus of any preceding claim, wherein the current measurement circuit comprises: a current mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit configured to receive one of the first current and the second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal; Wherein the current mode digital-to-analog converter circuit is configured to increase or decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

5. The apparatus of any preceding claim, wherein the current measurement circuit comprises: a current mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit comprising a current mirror circuit configured to receive one of the first current and the second current as an input current to be measured and to generate a mirror version of the input current; wherein the current comparator circuit is configured to compare the reference current with the mirrored version of the input current and generate a comparison output signal; Wherein the current mode digital-to-analog converter circuit is configured to increase or decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the mirrored version of the input current.

6. The device according to the preceding claim, wherein the current comparator circuit comprises: a first transistor including a drain terminal coupled to an input node of the current comparator circuit, a source terminal coupled to a power supply node, and a gate terminal coupled to a first node; a first switch coupled between the input node and the first node; a second switch coupled between the first node and the power supply node; a second transistor including a gate terminal coupled to the first node, a source terminal coupled to the power supply node, and a drain terminal coupled to a second node; as well as a voltage comparator comprising a first input terminal coupled to a threshold voltage node and a second input terminal coupled to said second node; wherein an output of the current mode digital-to-analog converter circuit is coupled to the second node; Wherein during the calibration process, the first switch is activated to configure the first transistor as a diode-connected transistor by coupling the gate terminal and the drain terminal of the first transistor, and the second switch is deactivated to enable the input current to flow into the current measurement circuit.

7. Apparatus according to the preceding claim, wherein: The current comparator circuit further includes a low pass filter circuit configured to enable the current comparator circuit to measure a direct current (DC) offset component of an alternating current (AC) input current; and The low pass filter circuit is one of: (i) coupled between the first node and a gate terminal of the second transistor, and (ii) coupled to a second input terminal of the voltage comparator.

8. A system comprising: a radio frequency signal generator configured to convert a baseband signal into a radio frequency signal, the radio frequency signal generator comprising a first signal path to process a first signal component of the baseband signal and comprising a second signal path to process a second signal component of the baseband signal; and A calibration system configured to perform a calibration process to calibrate the radio frequency signal generator, wherein the calibration system comprises: a current measurement circuit configured to measure a first current in the first signal path of the RF signal generator and to measure a second current in the second signal path of the RF signal generator during the calibration process; and A current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the RF signal generator to correct an imbalance between a measured first current and a measured second current.

9. The system according to the preceding claim, wherein the calibration system further comprises a control circuit configured to determine a difference between the measured first current and the measured second current, to generate a control signal based on the determined difference between the measured first current and the measured second current, and to output the control signal to the current imbalance correction circuit; Wherein, in response to the control signal, the current imbalance correction circuit is configured to inject current into at least one of the first signal path and the second signal path of the RF signal generator to compensate for the determined difference between the measured first current and the measured second current.

10. The system according to any of the two preceding claims, wherein the current imbalance correction circuit comprises: a first current mode digital-to-analog converter circuit configured to output a first current in the first signal path; and The second current mode digital-to-analog converter circuit is configured to output a second current in the second signal path.

11. A system according to any of the three preceding claims, wherein: The baseband signal is an orthogonal baseband signal including an in-phase signal component and an orthogonal phase signal component; The first signal path is configured to process the in-phase signal component; and The second signal path is configured to process the quadrature-phase signal component.

12. A system according to any one of the four preceding claims, wherein: The RF signal generator includes a plurality of current mode stages, the plurality of current mode stages including a baseband input stage, a mixer stage coupled to an output node of the baseband input stage, and an attenuation stage coupled to an output node of the mixer stage; the current measurement circuit being coupled to the output node of the mixer stage; and During the calibration process, the baseband input stage is configured to output quiescent baseband currents in the first and second signal paths, and the attenuation stage is turned off to allow the first and second currents to flow from at least one output node of the mixer stage to an input of the current measurement circuit.

13. System according to the preceding claim, wherein: The baseband input stage is configured to include a variable gain that can be adjusted to a target gain setting within a range of gain settings; and The current measurement circuit includes a current measurement range that is scalable to match full-scale current levels of the first current and the second current, the full-scale current levels of the first current and the second current being a function of the target gain setting.

14. System according to any of the two preceding claims, wherein: During the calibration process, the mixer stage is configured to output one of the first current and the second current on the at least one output node of the mixer stage at a given time by applying a static voltage to a local oscillator input of the mixer stage to selectively activate a transistor in the mixer stage at the given time.

15. A system according to any of the three preceding claims, wherein: During the calibration process, the mixer stage is configured to output one of the first current and the second current on the at least one output node of the mixer stage at a given time by applying a switching local oscillator signal to at least one local oscillator input of the mixer stage to selectively activate one transistor in the mixer stage at a given time, and applying a static voltage to other local oscillator inputs to selectively deactivate other transistors in the mixer stage at the given time.

16. A system according to any one of the preceding eight claims, wherein the current measurement circuit comprises: a current mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit configured to receive one of the first current and the second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal; Wherein the current mode digital-to-analog converter circuit is configured to increase or decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

17. A system according to any one of the preceding nine claims, wherein the current measurement circuit comprises: a current mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit comprising a current mirror circuit configured to receive one of the first current and the second current as an input current to be measured and to generate a mirror version of the input current; wherein the current comparator circuit is configured to compare the reference current with the mirrored version of the input current and generate a comparison output signal; Wherein the current mode digital-to-analog converter circuit is configured to increase or decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the mirrored version of the input current.

18. A system comprising: a quantum processor comprising at least one superconducting qubit; an AWG system comprising at least one AWG channel configured to convert a baseband signal into radio frequency control pulses for controlling the at least one superconducting qubit, the at least one AWG channel comprising a first signal path to process a first signal component of the baseband signal and comprising a second signal path to process a second signal component of the baseband signal; as well as a calibration system configured to perform a calibration process to calibrate the at least one arbitrary waveform generator channel, wherein the calibration system comprises: a current measurement circuit configured to measure a first current in the first signal path of the at least one AWG channel and to measure a second current in the second signal path of the at least one AWG channel during the calibration process; and A current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the at least one arbitrary waveform generator channel to correct an imbalance between a measured first current and a measured second current.

19. The system according to the preceding claim, wherein the calibration system further comprises a control circuit configured to determine a difference between the measured first current and the measured second current, generate a control signal based on the determined difference between the measured first current and the measured second current, and output the control signal to the current imbalance correction circuit; Wherein, in response to the control signal, the current imbalance correction circuit is configured to inject current into at least one of the first signal path and the second signal path of the at least one arbitrary waveform generator channel to compensate for the determined difference between the measured first current and the measured second current.

20. The system according to any of the two preceding claims, wherein the current measurement circuit comprises: a current mode digital-to-analog converter circuit configured to generate a reference current; and a current comparator circuit configured to receive one of the first current and the second current as an input current to be measured, compare the reference current with the input current, and generate a comparison output signal; Wherein the current mode digital-to-analog converter circuit is configured to increase or decrease the reference current until the current comparator circuit generates a comparison output signal indicating that the magnitude of the reference current is substantially equal to the magnitude of the input current.

21. A system according to any of the three preceding claims, wherein: The at least one arbitrary waveform generator channel includes a plurality of current mode stages, the plurality of current mode stages including a baseband input stage, a mixer stage coupled to an output node of the baseband input stage, and an attenuation stage coupled to an output node of the mixer stage; the current measurement circuit being coupled to the output node of the mixer stage; and During the calibration process, the baseband input stage is configured to output quiescent baseband currents in the first and second signal paths, and the attenuation stage is turned off to allow the first and second currents to flow from at least one output node of the mixer stage to an input of the current measurement circuit.

22. A computer program product for performing a calibration process to calibrate a radio frequency signal generator, the computer program product comprising: One or more computer-readable storage media, and program instructions stored together on the one or more computer-readable storage media, the program instructions comprising: program instructions for configuring a current measurement circuit to measure a first current in a first signal path of the RF signal generator and to measure a second current in a second signal path of the RF signal generator during the calibration process; and Program instructions for configuring a current imbalance correction circuit to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between a measured first current and a measured second current.

23. The computer program product according to the preceding claim, further comprising program instructions for determining a difference between the measured first current and the measured second current, and generating a control signal based on the determined difference between the measured first current and the measured second current, and outputting the control signal to the current imbalance correction circuit; Wherein, in response to the control signal, the current imbalance correction circuit is configured to inject current into at least one of the first signal path and the second signal path of the RF signal generator to compensate for the determined difference between the measured first current and the measured second current.

24. A method comprising: measuring a first current in a first signal path of a radio frequency signal generator; measuring a second current in a second signal path of the RF signal generator; as well as A current level in at least one of the first signal path and the second signal path of the radio frequency signal generator is adjusted to correct an imbalance between a measured first current and a measured second current.

25. The method according to the preceding claim, comprising: determining a difference between the measured first current and the measured second current; as well as generating a control signal based on a determined difference between the measured first current and the measured second current; Wherein adjusting the current level in at least one of the first signal path and the second signal path of the radio frequency signal generator is performed in response to the control signal to compensate for the determined difference between the measured first current and the measured second current.

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