Hardware aware joint learning

Abstract

A processor-implemented method for hardware-aware joint learning includes receiving, from a server, information corresponding to a joint-trained first artificial neural network (ANN). A current hardware capability of the device for on-device training of the jointly trained first ANN is determined. The device transmits an indication of the current hardware capability to the server. In response to the transmitted indication, the device receives, from the server, information corresponding to the jointly trained second ANN. The joint-trained second ANN is an adapted version of the joint-trained first ANN generated based on the indication of the current hardware capability.

Description

[0001] This application claims priority to U.S. patent application No. 17 / 941,121, filed on September 9, 2022, entitled “HARDWARE-AWARE FEDERATED LEARNING,” the disclosure of which is expressly incorporated herein by reference in its entirety.

[0002] Public domain

[0003] Aspects of the present disclosure relate generally to neural networks, and more particularly to techniques and apparatus for hardware-aware federated learning.

[0004] background

[0005] Federated learning is a method for collaboratively training neural networks across multiple users without collecting data at a central location. Federated learning is beneficial for applications where privacy is an important factor due to decentralized training, where raw data is not shared by edge devices. Federated learning (FL) aims to address differential privacy, continuous learning, and personalization issues by having edge (or end) devices perform training locally using collected data and only transmit weight updates instead of raw data.

[0006] Although the FL architecture can solve these fundamental problems, it is challenging to perform training on devices and can be laborious in terms of memory and computational resources. As a result, some resource-constrained devices may be prevented from participating in FL. This restriction on participation can lead to model bias and degraded model performance.

[0007] Overview

[0008] The present disclosure is set out in the independent claims respectively. Some aspects of the present disclosure are described in the dependent claims.

[0009] In various aspects of the present disclosure, a processor-implemented method includes receiving information corresponding to a first artificial neural network (ANN) of joint training from a server. The method also includes determining a current hardware capability of a device for on-device training of the first ANN of joint training. The method further includes transmitting an indication of the current hardware capability to the server. The method also includes receiving information corresponding to a second ANN of joint training from the server in response to the transmitted indication, the second ANN of joint training being an adapted version of the first ANN of joint training generated based on the indication of the current hardware capability.

[0010] In other aspects of the present disclosure, a processor-implemented method includes transmitting information corresponding to a first artificial neural network (ANN) for joint training to one or more devices. The method also includes receiving from the one or more devices a first indication of current hardware capabilities for training on a device for the first ANN for joint training. The method further includes selecting a second ANN for joint training based on the first indication of the current hardware capabilities. The second ANN for joint training includes one or more categories of the first ANN for joint training, each of the one or more categories having a different computational complexity. The method also includes transmitting information corresponding to the second ANN for joint training to the one or more devices.

[0011] Other aspects of the present disclosure relate to a device. The device includes a memory and one or more processors coupled to the memory. The processor(s) are configured to receive information corresponding to a first artificial neural network (ANN) of joint training from a server. The processor(s) are also configured to determine the current hardware capabilities of the device for training the first ANN of the joint training on the device. The processor(s) are further configured to transmit an indication of the current hardware capabilities to the server. The processor(s) are also configured to receive information corresponding to a second ANN of the joint training from the server in response to the transmitted indication, the second ANN of the joint training being an adapted version of the first ANN of the joint training generated based on the indication of the current hardware capabilities.

[0012] Other aspects of the present disclosure relate to a device. The device has a memory and one or more processors coupled to the memory. The processor(s) is configured to transmit information corresponding to a first artificial neural network (ANN) of joint training to one or more devices. The processor(s) is further configured to receive from the one or more devices a first indication of current hardware capabilities trained on a device for the first ANN of the joint training. The processor(s) is further configured to select a second ANN of joint training based on the first indication of the current hardware capabilities. The second ANN of the joint training includes one or more categories of the first ANN of the joint training, each of the one or more categories having different computational complexities. The processor(s) is also configured to transmit information corresponding to the second ANN of the joint training to the one or more devices.

[0013] Aspects generally include methods, apparatus, systems, computer program products, non-transitory computer readable media, user equipment, base stations, wireless communication devices, and processing systems as substantially described with reference to and as illustrated in the accompanying drawings and specification.

[0014] The foregoing has broadly outlined the features and technical advantages of examples according to the present disclosure in an effort to make the following detailed description better understood. Additional features and advantages will be described. The disclosed concepts and specific examples can be easily used as a basis for modifying or designing other structures for implementing the same purpose as the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the disclosed concepts, both in terms of their organization and method of operation, and the associated advantages will be better understood by considering the following description in conjunction with the accompanying drawings. Each of the accompanying drawings is provided for illustration and description purposes and not to define limitations on the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals designate correspondingly throughout.

[0017] Figure 1 An example implementation of designing a neural network using a system on a chip (SOC) including a general-purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0018] Figure 2A , 2B 2C are diagrams illustrating neural networks according to aspects of the present disclosure.

[0019] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0020] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0021] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality according to aspects of the present disclosure.

[0022] Figure 5 is a high-level block diagram illustrating an example system for hardware-aware federated learning in accordance with aspects of the present disclosure.

[0023] Fig. 6A and 6B is a flow diagram illustrating an example process for hardware-aware federated learning in accordance with aspects of the present disclosure.

[0024] Figure 7 and 8 is a flow chart illustrating a processor-implemented method for hardware-aware federated learning according to aspects of the present disclosure.

[0025] Detailed Description

[0026] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the described concepts may be practiced. This detailed description includes specific details in order to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0027] Based on this teaching, it will be appreciated by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects described can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality that are supplemented or different from the various aspects of the present disclosure described. It should be understood that any aspect of the present disclosure disclosed can be implemented by one or more elements of the claims.

[0028] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0029] Although specific aspects are described, numerous variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or goals. On the contrary, various aspects of the present disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated as examples in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings merely illustrate the present disclosure and do not limit the present disclosure, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0030] Federated learning is a decentralized form of machine learning in which one or more local clients (e.g., end devices) collaboratively train statistical models under the orchestration of a central device (e.g., server, serving cell, parameter server, etc.), while keeping the training data local and maintaining the privacy of local client data. That is, machine learning algorithms (such as deep neural networks) are trained on raw data collected from multiple local datasets contained in the end devices without receiving or accessing the raw data.

[0031] In other words, federated learning enables users (or end devices) to train machine learning models in a distributed manner. Each end device can use its local data set to train a local model and then send model updates to a central server. For example, in each round of the federated learning process, the parameter server may select several users and send a copy of the global machine learning model to the selected users. Each local training iteration of the federated learning process may be referred to as an epoch, and each communication round with the server may be referred to as a communication round. Each end device uses its own data set to calculate the parameters of the model and feeds back the corresponding updates (e.g., weight updates) to the parameter server. The parameter server aggregates all end device updates and determines updates to the global model by, for example, averaging the aggregated end device updates or other techniques. The parameter server broadcasts the new parameters of the global model to the selected users in the next round of the federated learning process. Since localized data is not transmitted, federated learning is beneficial for applications where privacy is an important factor.

[0032] As described, federated learning involves leveraging a dataset of N data points distributed across S devices. (For example ) to learn a server model (such as a neural network) with matrix-tensor parameters w without directly accessing the device-specific dataset. By defining the loss function for each end device The total security risk can be written as:

[0033]

[0034] This objective corresponds to a joint dataset with a loss L(·) for each data point In federated learning, it is beneficial to reduce communication costs. In this way, multiple gradient updates of the weight parameter w in the target internal optimization can be performed for each device S, thereby obtaining a weight parameter w S The multiple gradient updates may be referred to as local epochs (such as the amount of data passed through the entire local data set), abbreviated as E. Each end device may then communicate to the server the local weights w S Then, the server takes the average of the parameters of the local model in round t. to update the global model.

[0035] Although FL architectures can address these fundamental issues, performing training on-device is challenging and can be taxing in terms of memory and computational resources.

[0036] Due to the demand for memory and processing power, many devices may not be able to participate in FL training due to their hardware capabilities. Edge devices in FL are typically mobile devices ("UE"), which may have inherent differences in capabilities (or characteristics). For example, the hardware capabilities of different UEs may include the number and type of processors, and the amount and type of memory (e.g., speed). Dynamic hardware capabilities may include available or expected power (e.g., battery), available or expected computing resources (e.g., based on concurrently running applications), and available or expected communication bandwidth. Thus, hardware capabilities can be dynamic. In addition, the same UE may be able to train different (types of) models at different times. Hardware limitations may prevent devices with lower capabilities from reaping the benefits of FL. In addition, hardware limitations may cause deviations in the model because some users may not be able to take advantage of FL due to devices with limited hardware capabilities. Such limitations may result in poor model performance (e.g., incorrect classification).

[0037] To address these and other challenges, aspects of the present disclosure relate to hardware-aware federated learning. According to aspects of the present disclosure, the hardware capabilities of devices participating in a federated learning model may be determined, and an artificial neural network (ANN) model may be adapted based on the hardware capabilities.

[0038] Figure 1 An example implementation of a system on a chip (SOC) 100 according to certain aspects of the present disclosure is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for hardware-aware federated learning. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computing device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at CPU 102 may be loaded from a program memory associated with CPU 102 or may be loaded from memory block 118.

[0039] The SOC 100 may also include additional processing blocks customized for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may detect and recognize gestures, for example. In one implementation, the NPU is implemented in the CPU, DSP, and / or GPU. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120 (which may include a global positioning system).

[0040] SOC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into CPU 102 may include code for receiving information corresponding to the first artificial neural network (ANN) of the joint training from the server. The instructions loaded into CPU 102 may also include code for determining the current hardware capabilities of the device for on-device training of the first ANN of the joint training. The instructions loaded into CPU 102 may additionally include code for transmitting an indication of the current hardware capabilities to the server. The instructions loaded into CPU 102 may also include code for receiving information corresponding to the second ANN of the joint training from the server in response to the transmitted indication. The second ANN of the joint training is an adapted version of the first ANN of the joint training generated based on the indication of the current hardware capabilities.

[0041] In some aspects, the instructions loaded into the CPU 102 may include code for transmitting information corresponding to the first artificial neural network (ANN) of the joint training to one or more devices. The instructions loaded into the CPU 102 may also include code for receiving an indication of the current hardware capabilities of the training on the device of the first ANN for the joint training from one or more devices. The instructions loaded into the CPU 102 may additionally include code for selecting the second ANN of the joint training based on the indication of the current hardware capabilities. The second ANN of the joint training includes one or more categories of the first ANN of the joint training. Each of the one or more categories has a different computational complexity. The instructions loaded into the CPU 102 may also include code for transmitting information corresponding to the second ANN of the joint training to the one or more devices.

[0042] Deep learning frameworks can perform object recognition tasks by learning to represent the input at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Before the advent of deep learning, machine learning approaches to object recognition problems might rely heavily on human-engineered features, perhaps combined with shallow classifiers. Shallow classifiers can be two-class linear classifiers, for example, where a weighted sum of feature vector components can be compared to a threshold to predict which class the input belongs to. Human-engineered features can be templates or kernels that are customized for a specific problem domain by engineers with domain expertise. In contrast, deep learning architectures can learn to represent features similar to what a human engineer might design, but it learns through training. In addition, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0043] A deep learning architecture can learn a hierarchy of features. For example, if a first layer is presented with visual data, the first layer can learn to recognize relatively simple features (such as edges) in the input stream. In another example, if a first layer is presented with auditory data, the first layer can learn to recognize spectral power in specific frequencies. A second layer that takes the output of the first layer as input can learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0044] Deep learning architectures can perform particularly well when applied to problems that have a natural hierarchical structure. For example, the classification of motor vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can be combined in different ways at higher levels to recognize cars, trucks, and airplanes.

[0045] Neural networks can be designed to have various connectivity patterns. In a feedforward network, information is passed from lower layers to higher layers, with each neuron in a given layer communicating to neurons in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have reflow or feedback (also known as top-down) connections. In a reflow connection, the output from a neuron in a given layer can be communicated to another neuron in the same layer. The reflow architecture can help identify patterns that span more than one block of input data delivered sequentially to the neural network. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections may be helpful when the recognition of high-level concepts can assist in discerning specific low-level features of the input.

[0046] The connections between layers of a neural network can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In the fully connected neural network 202, a neuron in a first layer may communicate its output to each neuron in a second layer, so that each neuron in the second layer will receive input from each neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured so that each neuron in a layer will have the same or similar connectivity pattern, but their connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The locally connected connectivity patterns may produce spatially distinct receptive fields in higher layers because higher layer neurons in a given area may receive inputs that are tuned through training to the properties of a limited portion of the total input to the network.

[0047] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs to each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0048] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as an onboard camera) is illustrated. The DCN 200 of the current example can be trained to identify traffic signs and numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0049] The DCN 200 may be trained using supervised learning. During training, an image (such as an image 226 of a speed limit sign) may be presented to the DCN 200, and a forward pass may then be calculated to produce an output 222. The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226, a convolution layer 232 may apply a convolution kernel (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolution kernel of the convolution layer 232 may be a 5x5 kernel that generates a 28x28 feature map. In this example, since four different feature maps are generated in the first set of feature maps 218, four different convolution kernels are applied to the image 226 at the convolution layer 232. A convolution kernel may also be referred to as a filter or a convolution filter.

[0050] The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (such as 14x14) is smaller than the size of the first set of feature maps 218 (such as 28x28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate a subsequent set of one or more sets of feature maps (not shown).

[0051] exist Figure 2D In the example of , the second set of feature maps 220 is convolved to generate a first feature vector 224. In addition, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of the image 226 (such as "sign", "60", and "100"). A softmax function (not shown) can convert the numbers in the second feature vector 228 into probabilities. In this way, the output 222 of the DCN 200 is the probability that the image 226 includes one or more features.

[0052] In this example, the probability of "sign" and "60" in output 222 is higher than the probability of other features of output 222 (such as "30", "40", "50", "70", "80", "90", and "100"). Before training, output 222 generated by DCN 200 is likely to be incorrect. Thus, the error between output 222 and the target output can be calculated. The target output is the true value of image 226 (e.g., "sign" and "60"). The weights of DCN 200 can then be adjusted to align the output 222 of DCN 200 with the target output more closely.

[0053] To adjust the weights, the learning algorithm may calculate a gradient vector for the weights. The gradient may indicate the amount by which the error will increase or decrease if the weights are adjusted. At the top layer, the gradient may correspond directly to the value of the weights connecting the activated neurons in the penultimate layer to the neurons in the output layer. In the lower layers, the gradient may depend on the value of the weights and the calculated error gradient of the higher layers. The weights may then be adjusted to reduce the error. This way of adjusting the weights may be referred to as "backward propagation" because it involves a backward pass in the neural network.

[0054] In practice, the error gradient of the weights may be calculated over a small number of examples so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the error rate achievable by the entire system has stopped decreasing or until the error rate has reached a target level. After learning, a new image (e.g., image 226 of a speed limit sign) may be presented to the DCN and a forward pass through the network may produce output 222, which may be considered an inference or prediction of the DCN.

[0055] Deep belief network (DBN) is a probabilistic model including multiple layers of hidden nodes. DBN can be used to extract hierarchical representations of training data sets. DBN can be obtained by stacking multiple layers of restricted Boltzmann machines (RBM). RBM is a class of artificial neural networks that can learn probability distributions on input sets. Since RBM can learn probability distributions without information about which class each input should be classified into, RBM is often used in unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBM of DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the input and target class from the previous layer) and can be used as a classifier.

[0056] A deep convolutional network (DCN) is a network of convolutional networks configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the weights of the network by using gradient descent.

[0057] The DCN can be a feed-forward network. In addition, as described above, the connections from the neurons in the first layer of the DCN to the neuron groups in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of the DCN can be used for fast processing. The computational burden of the DCN can be much smaller than, for example, the computational burden of a neural network of similar size that includes reflow or feedback connections.

[0058] The processing of each layer of the convolutional network can be considered as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green and blue channels of a color image, the convolutional network trained on the input can be considered to be three-dimensional, with two spatial dimensions along the axis of the image and a third dimension that captures color information. The output of the convolutional connection can be considered to form a feature map in a subsequent layer, each element in the feature map (e.g., 220) receives input from a certain range of neurons in the previous layer (e.g., feature map 218) and from each channel in the multiple channels. The values ​​in the feature map can be further processed with nonlinearity (such as rectification, max (0, x)). The values ​​from adjacent neurons can be further pooled (which corresponds to downsampling) and can provide additional local invariance and dimensionality reduction. Normalization can also be applied by lateral inhibition between neurons in the feature map, which corresponds to whitening.

[0059] The performance of deep learning architectures can improve as more labeled data points become available or as computing power increases. Modern deep neural networks are routinely trained with thousands of times more computing resources than were available to a typical researcher just fifteen years ago. New architectures and training paradigms can further boost the performance of deep learning. Rectified linear units can reduce the training problem known as vanishing gradients. New training techniques can reduce over-fitting and thus enable larger models to achieve better generalization. Encapsulation techniques can abstract the data within a given receptive field and further improve overall performance.

[0060] Figure 3 is a block diagram illustrating a deep convolutional network 350. The deep convolutional network 350 may include multiple layers of different types based on connectivity and weight sharing. Figure 3 As shown in FIG. 3 , the deep convolution network 350 includes convolution blocks 354A and 354B. Each of the convolution blocks 354A and 354B may be configured with a convolution layer (CONV) 356 , a normalization layer (LNorm) 358 , and a maximum pooling layer (MAX POOL) 360 .

[0061] The convolution layer 356 may include one or more convolution filters that can be applied to the input data to generate a feature map. Although only two convolution blocks 354A, 354B are shown, the present disclosure is not limited thereto, but instead any number of convolution blocks 354A, 354B may be included in the deep convolution network 350 according to design preferences. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The maximum pooling layer 360 may provide downsampling aggregation in space to achieve local invariance and dimensionality reduction.

[0062] For example, the parallel filter banks of the deep convolutional network may be loaded onto the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In alternative embodiments, the parallel filter banks may be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the deep convolutional network 350 may access other processing blocks that may be present on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0063] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350 are weights (not shown) to be updated. The output of each layer (e.g., 356, 358, 360, 362, 364) can be used as an input to a subsequent layer (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn a hierarchical feature representation from the input data 352 (e.g., image, audio, video, sensor data, and / or other input data) supplied from the first convolutional block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 can be a set of probabilities, where each probability is a probability that the input data includes a feature from a feature set.

[0064] Figure 4 400 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functions. According to aspects of the present disclosure, by using this architecture, an application can be designed that can enable various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of SoC 420 to support adaptive rounding for post-training quantization for AI application 402 as disclosed.

[0065] The AI ​​application 402 may be configured to call functions defined in the user space 404, which may, for example, provide detection and recognition of scenes indicating the current operating location of the device. For example, the AI ​​application 402 may configure the microphone and camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0066] The runtime engine 408, which may be the compiled code of the runtime framework, may further be accessible by the AI ​​application 402. For example, the AI ​​application 402 may cause the runtime engine to request inference at a specific time interval or triggered by an event detected by the user interface of the application. Upon causing the runtime engine to provide an inference response, the runtime engine may in turn send a signal to the operating system in the operating system (OS) space 410 (such as the Linux kernel 412) running on the SOC 420. The operating system may in turn cause continuous quantization relaxation to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers (such as drivers 414, 416, or 418 for the DSP 424, the GPU 426, or the NPU 428, respectively). In an exemplary example, the deep neural network may be configured to run on a combination of processing blocks (such as the CPU 422, the DSP 424, and the GPU 426), or may run on the NPU 428.

[0067] Application 402 (e.g., an AI application) may be configured to call functions defined in user space 404 that may, for example, provide detection and recognition of a scene indicative of the current operating location of the device. For example, application 402 may configure a microphone and camera differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. Application 402 may make a request to a compiled program code associated with a library defined in a scene detection application programming interface (API) 406 to provide an estimate of the current scene. The request may ultimately rely on the output of a differential neural network configured to provide a scene estimate based on, for example, video and positioning data.

[0068] The runtime engine 408, which may be compiled code of a runtime framework, may further be accessible by the application 402. For example, the application 402 may cause the runtime engine to request scene estimation at a specific time interval or triggered by an event detected by a user interface of the application. Upon causing the runtime engine to estimate the scene, the runtime engine may in turn send a signal to an operating system 410 (such as a Linux kernel 412) running on the SOC 420. The operating system 410 may in turn cause calculations to be performed on a CPU 422, a DSP 424, a GPU 426, an NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers (such as drivers 414-418 for the DSP 424, the GPU 426, or the NPU 428, respectively). In an illustrative example, the differential neural network may be configured to run on a combination of processing blocks (such as the CPU 422 and the GPU 426), or may run on the NPU 428 (if present).

[0069] According to certain aspects of the present disclosure, each fully connected layer 362 may be configured to determine parameters of the model based on one or more desired functional characteristics of the model, and to develop the one or more functional characteristics toward the desired functional characteristics as the determined parameters are further adapted, tuned, and updated.

[0070] As indicated above, Figure 1-4 are provided as examples. Other examples may differ from those described in Figure 1-4 The content described.

[0071] Various aspects of the present disclosure relate to hardware-aware federated learning. According to various aspects of the present disclosure, the hardware capabilities of devices participating in a federated learning model may be determined, and the ANN model may be adapted based on the hardware capabilities.

[0072] Figure 5 is a high-level block diagram illustrating an example system 500 for hardware-aware federated learning in accordance with aspects of the present disclosure. Figure 5 , the system 500 includes a server 502 for managing a joint learning model. The system 500 also includes a plurality of end devices 504a-z. The end devices 504a-z may each include a mobile communication device, such as, for example, a smart phone, a tablet device, an electric vehicle, or an Internet of Things (IoT) device. Each end device (e.g., 504a-z) may have a different hardware configuration, which may include dynamic hardware capabilities. For example, some end devices (e.g., 504a) may be configured with a graphics processing unit (GPU), a neural processing unit (NPU), a digital signal processor (DSP), or may have different memory configurations. Accordingly, each end device (e.g., 504a-z) may have different capabilities for operating a joint learning model or performing on-device training of a joint learning model. According to aspects of the present disclosure, each end device (e.g., 504a-z) may be configured to evaluate the current hardware capabilities of the device. The evaluation of the current hardware capabilities may be based on, for example, physical hardware configurations (e.g., GPU, NPU, etc.) and processing capabilities. In some aspects, the current hardware capabilities may be evaluated or determined based on the current workload or other performance metrics of the end device (e.g., 504a-z). The end device 504a-z may send an indication of its current hardware capabilities. In turn, the server 502 may adapt an initial or fully functional joint learning model for each end device (e.g., 504a-z) based on the current hardware capabilities. For example, the server 502 may compress the fully functional joint learning model (e.g., via one or more of pruning, quantization, or other model compression techniques). The compressed model may be sent to a particular end device (e.g., 504a-z).

[0073] The end device (e.g., 504a-z) may continue to monitor the current hardware capabilities, and may update the server 502 so that the server 502 may continue to provide a model that is consistent with the current hardware capabilities. By doing so, the server 502 may provide a federated learning model at the optimal level that the end device (e.g., 504a-z) can accommodate. That is, the server 502 may configure a federated learning model that can be run on the end device with reduced or (to some extent) no degradation in model performance. In this way, model latency and power consumption may be beneficially reduced. Thus, the user experience and enjoyment when the model is executed in the background may also be improved.

[0074] Additionally, the joint learning model can be improved because more end devices may be able to participate in the joint learning process. Each end device (e.g., 504a-z) can retrain the model on the device individually based on locally collected data. Each end device (e.g., 504a-z) determines the model update (e.g., weight update) and sends such update to the server 502. In some aspects, the end device may choose to provide the frequency of model updates (e.g., weight updates) to the server. The frequency can be based on the current hardware capabilities. In one example, a powerful smartphone can provide weight updates when it is being charged or has no heavy workload. In another example, for end devices with lower hardware capabilities (such as IoT devices or other battery-powered devices where battery resources are more concerned), the update frequency can be adapted to keep the device running longer. Then, the server 502 jointly trains the joint learning model based on the updates received from the end devices (e.g., 504a-z).

[0075] Fig. 6A and 6B is a flow chart illustrating example processes 600 and 650 for hardware-aware federated learning according to aspects of the present disclosure. Fig. 6A At block 602, a server (e.g., Figure 5 502) can be sent to the participant end device collection (for example, Figure 5 The federated learning model may be, for example, an artificial neural network (e.g., Figure 3 350 shown in FIG. 350). The federated learning model may be a top-level model (e.g., a fully functional model). In some aspects, the federated learning model may be generated based on the top-level hardware capabilities of the participant end devices. For example, the server may survey the participant end devices and may determine the top-level hardware capabilities. The server may then generate a top-level model based on the top-level hardware capabilities.

[0076] Each participant end device may assess its current hardware capabilities. In box 604, the participant end device may determine whether the current hardware capabilities can accommodate on-device training. In some aspects, the suitability for on-device training may be evaluated based on certain key performance indicators (KPIs). KPIs may include, for example, inferences per second (IPS), double data rate read / write bandwidth, power consumption, memory footprint, or other performance indicators. In a first example, a threshold may be applied to determine whether the current hardware capabilities can accommodate on-device training (e.g., greater than 50,000 IPS). In a second example, a server may declare a set of models and a set of hardware specifications for running each model. In this way, the end device may determine whether its current hardware capabilities meet or satisfy the specifications for the declared model, and (in some aspects) may determine the model that best suits its current hardware capabilities.

[0077] The end device may determine the current hardware capabilities based on the physical hardware configuration. Additionally, in some aspects, the current hardware capabilities may be determined based on the current workload, estimated completion time, or other performance metrics. If the current hardware capabilities accommodate on-device training, then in box 606, the device retains the model (e.g., the top model). The device may operate the model on locally collected data. Additionally, the device may perform on-device training based on locally collected data. In turn, the device may send weight updates calculated during on-device training to a server (not shown).

[0078] If the device (e.g., 504b) determines that the current hardware capabilities may not accommodate on-device training, the device may send a notification to the server at block 608. The notification may include an indication of the current hardware capabilities of the device. Alternatively, in some aspects, the end device may also indicate that its current hardware capabilities may accommodate a more complex model than the announced model.

[0079] In response to the notification, at block 610, the server may adapt the model to adjust model complexity. For example, in some aspects, the server may compress the top model. The server may compress the top model using one or more of pruning, quantization, or other compression or model personalization techniques. The server may send the adapted model to the end device.

[0080] Thereafter, process 600 may return to block 604 to evaluate whether current hardware capabilities can accommodate on-device training based on the adapted model.

[0081] In this way, process 600 can be applied iteratively until each device can successfully train the federated learning model on the device.

[0082] However, since the current hardware capabilities may vary, for example, based on hardware configuration changes or workload changes, in some aspects, the process may be repeated continuously or periodically. In this way, the model complexity may be updated and (in some aspects) optimized based on the current hardware capabilities of each device.

[0083] In other aspects (not shown), the server sends a representation of the model to the set of participating end devices, rather than the entire model. In these aspects, the end device can determine whether the end device is able to participate in the training round of the model based on the representation. If so, the end device sends a message to the server accordingly, and the server then sends the initial model to the capable end device.

[0084] Reference Figure 6B In block 652, process 650 provides that the server may generate multiple categories or levels of federated learning models. The multiple categories or levels of federated learning models may have different levels of model complexity. The multiple categories or levels of federated learning models may be based on different hardware capabilities of the participant end devices. For example, the multiple categories of federated learning models may be based on different dimensions, such as hardware processors (e.g., GPU, NPU, DSP, etc.), floating point weights, fixed point weight quantization, implemented edge pruning, and the like.

[0085] In box 654, the end device may determine the current hardware capabilities. For example, the end device may determine whether the current hardware capabilities can accommodate on-device training. In some aspects, the current hardware capabilities may be determined based on the physical hardware configuration. Additionally, in some aspects, the current hardware capabilities may also be determined based on, for example, workload (e.g., the application being executed), estimated workload completion, or other performance metrics. In some other aspects, the server may send an evaluation function to a participant device (e.g., end device 504z) to discover its hardware capabilities. The evaluation function can be a program executed on the end device. The output of the program captures the hardware capabilities of the end device at a given time or over a period of time. The end device reports the hardware capabilities back to the server. The end device may use the evaluation function from time to time (periodically or event-driven) and may notify the server to negotiate a new model based on the current hardware capabilities.

[0086] At block 656, the end device (e.g., 504z) may notify the server of its current hardware capabilities. For example, the end device may report the hardware capabilities back to the server based on the output of the evaluation function. At block 658, the server may select a category or level of a federated learning model for each end device based on the current hardware capabilities. The selected category or model may be an estimate of the current hardware capabilities of the end device for the model trained on its accommodating device. At block 660, the server may transmit the selected category of the model to the end device.

[0087] Each end device may then perform on-device training based on the received model. Accordingly, the end device may collect data and operate a local model, and each participant device may be retrained on the device (e.g., based on a loss function), thereby generating a local model update (e.g., a weight update). In turn, the device may send the weight updates determined during on-device training to the server. In addition, the server may update the federated learning model for each category or level based on the weight updates for the end devices (e.g., 504a-z). For example, the server may use a weight update methodology (e.g., weight averaging) to update the weights of the federated learning model for each category. The server may also send updated model categories to the corresponding devices.

[0088] The process may return to box 654 to repeat the evaluation of the current hardware capabilities. Accordingly, the server may provide the category of models to the end device in response to any changes in the current hardware capabilities. In some aspects, the end device may initiate a model query to the server. For example, in the presence of a change in its current hardware capabilities (e.g., a change in the physical hardware configuration or a change in the workload), the end device may request the server to select a new model based on the current hardware capabilities in view of the change. In one example, the end device may be able to handle a more complex model because the pending processes previously running on it have completed. On the other hand, the device may have new processes that are competing for hardware resources and may thus be able to accommodate less complex models.

[0089] In some aspects, the end device can also train multiple categories or levels of jointly trained ANNs. For example, when the end device has considerable processing power (e.g., a hardware configuration with numerous measurement resources) and the current workload is below a threshold (e.g., less than ten percent of the processing capacity), similar to a server, the end device can train multiple categories or levels of jointly trained ANNs. Additionally, the end device can also provide these categories or levels of jointly trained ANNs to, for example, a server or other end devices. For example, when the device is charging at night, with few or no other applications competing for the end device resources, the end device can perform multiple model training without affecting device performance and user experience.

[0090] Thus, the described dynamic approach may enable end devices (e.g., Figure 5 504a-z) can continue to participate in and reap the benefits of the federated learning framework regardless of the processes competing for hardware resources on these devices. In addition, federated learning training can benefit by increasing the number of devices that can contribute to weight updates and thereby improving the federated learning model.

[0091] Figure 7 is a flow chart illustrating a processor-implemented method 700 for hardware-aware federated learning in accordance with aspects of the present disclosure.

[0092] At block 702, the processor-implemented method 700 receives information corresponding to a first artificial neural network (ANN) jointly trained from a server. For example, as described, with reference to Fig. 6A , the server can send a collection of participant end devices (for example, Figure 5 The federated learning model may be, for example, an artificial neural network (e.g., Figure 3 350 shown in ). The federated learning model can be a top-level model (e.g., a fully functional model). In some aspects, the federated learning model can be generated based on the top-level hardware capabilities of the participant end device. For example, the server can survey the participant end device and determine the top-level hardware capabilities. The server can then generate a top-level model based on the top-level hardware capabilities. In other aspects, the information can be a representation of the model.

[0093] At block 704, the processor-implemented method 700 determines the current hardware capabilities of the device for performing on-device training of the first ANN for joint training. Fig. 6A As described, the participant end device may determine whether the current hardware capabilities can accommodate on-device training. In some aspects, the adaptability of on-device training may be evaluated based on certain key performance indicators (KPIs). KPIs may include, for example, inferences per second (IPS), double data rate read / write bandwidth, power consumption, memory footprint, or other performance indicators. In some aspects, the end device may determine the current hardware capabilities based on the physical hardware configuration. Additionally, in some aspects, the current hardware capabilities may be determined based on the current workload, estimated completion time, or other performance metrics.

[0094] At block 706, the processor-implemented method 700 transmits an indication of current hardware capabilities to the server. For example, if the device (e.g., 504b) determines that the current hardware capabilities may not accommodate on-device training, the end device may send a notification to the server, the notification including an indication of the current hardware capabilities. Alternatively, in some aspects, the end device may also indicate that its current hardware capabilities can accommodate a model that is more complex than the declared model. In yet other aspects, the end device indicates whether the end device can participate in the FL process based on the received model information.

[0095] At block 708, the processor-implemented method 700 receives from the server information corresponding to a jointly trained second ANN in response to the transmitted indication, the jointly trained second ANN being an adapted version of the jointly trained first ANN generated based on the indication of the current hardware capabilities. Fig. 6A, if the device (e.g., 504b) determines that the current hardware capabilities may not accommodate on-device training, then at box 608, the device may send a notification to the server. In some aspects, the notification may include an indication of the current hardware capabilities. Alternatively, the end device may indicate that its current hardware capabilities can accommodate a more complex model than the declared model. In alternative aspects, if the end device (at box 608) sends an "incapable" message, the server sends information corresponding to the second model received at box 708. The information corresponding to the second model may be re-evaluated by the end device. On the other hand, if the end device (at box 608) sends more detailed hardware characteristics, the server may send a capability-appropriate model to the end device in box 708.

[0096] Figure 8 is a flowchart illustrating a method 800 for hardware-aware federated learning implemented by a processor according to aspects of the present disclosure. Figure 8 At block 802, the processor-implemented method 800 transmits information corresponding to a jointly trained first artificial neural network (ANN) to one or more devices.

[0097] At block 804, the processor-implemented method 800 receives from the one or more devices an indication of current hardware capabilities for on-device training of the first ANN for joint training. Figure 6B As described, at block 656, the end device (e.g., 504z) may notify the server of its current hardware capabilities. The current hardware capabilities may be based on, for example, the physical hardware configuration. Additionally, in some aspects, the current hardware capabilities may be determined based on the current workload, estimated completion time, or other performance metrics.

[0098] At block 806, the processor-implemented method 800 selects a second ANN for joint training based on an indication of current hardware capabilities, the second ANN for joint training comprising one or more classes of the first ANN for joint training, each of the one or more classes having a different computational complexity. Figure 6B As described, the server may select a category or level of a joint learning model for each end device based on the current hardware capabilities. The selected category or model may be an estimate of whether the current hardware capabilities of the end device can accommodate the model trained on the device.

[0099] At block 808, the processor-implemented method 800 transmits information corresponding to the jointly trained second ANN to the one or more devices. If the server (at block 804) receives a "no capability" message, the server sends information corresponding to the second model at block 808. On the other hand, if the server (at block 808) receives more detailed hardware characteristics, the server may send a capability appropriate model to the end device at block 808.

[0100] Example aspects

[0101] Aspect 1: A processor-implemented method comprising: receiving information corresponding to a first artificial neural network (ANN) of a joint training from a server; determining a current hardware capability of a device for on-device training of the first ANN of the joint training; transmitting an indication of the current hardware capability to the server; and receiving information corresponding to a second ANN of the joint training from the server in response to the transmitted indication, the second ANN of the joint training being an adapted version of the first ANN of the joint training generated based on the indication of the current hardware capability.

[0102] Aspect 2: The processor-implemented method of Aspect 1 further comprises: operating the jointly trained second ANN to generate inferences about locally collected data; and retraining the jointly trained second ANN on the device.

[0103] Aspect 3: The processor-implemented method of Aspect 1 or 2 further comprises transmitting the weight updates determined in the retraining to the server.

[0104] Aspect 4: A processor-implemented method as described in any of the preceding aspects, wherein the device trains multiple classes of the jointly trained first ANN, the multiple classes of the jointly trained first ANN being specified to be accommodated by different levels of the current hardware capabilities.

[0105] Aspect 5: The processor-implemented method of any of the preceding aspects, further comprising determining the current hardware capability based on one or more of a hardware configuration of the device or a current processing workload on the device.

[0106] Aspect 6: The processor-implemented method of any of the preceding aspects, wherein the jointly trained first ANN is a computationally more complex model than the jointly trained second ANN.

[0107] Aspect 7: The processor-implemented method of any of the preceding aspects, wherein the jointly trained second ANN is a compressed version of the jointly trained first ANN.

[0108] Aspect 8: A processor-implemented method as described in any of Aspects 1-6, wherein the jointly trained second ANN is one of multiple categories of the jointly trained first ANN, and the jointly trained second ANN is selected from one of the multiple categories of the jointly trained first ANN based on the current hardware capabilities.

[0109] Aspect 9: A processor-implemented method comprising: transmitting information corresponding to a first artificial neural network (ANN) for joint training to one or more devices; receiving a first indication of current hardware capabilities for training on a device for the first ANN for joint training from the one or more devices; selecting a second ANN for joint training based on the first indication of current hardware capabilities, the second ANN for joint training comprising one or more categories of the first ANN for joint training, each of the one or more categories having a different first computational complexity; and transmitting information corresponding to the second ANN for joint training to the one or more devices.

[0110] Aspect 10: The processor-implemented method of aspect 9, further comprising receiving weight updates determined during the retraining process from the one or more devices.

[0111] Aspect 11: The processor-implemented method of Aspect 9 or 10 further comprises updating the one or more categories of the jointly trained first ANN based on the received weight updates.

[0112] Aspect 12: The processor-implemented method of any of Aspects 9-11, wherein the current hardware capabilities of the one or more devices are based on one or more of a current hardware configuration or a current processing workload.

[0113] Aspect 13: The processor-implemented method of any of Aspects 9-12 further includes: receiving a second indication of current hardware capabilities for training on the device from the one or more devices; and selecting a third ANN for joint training, the third ANN for joint training including one or more categories of the first ANN for joint training, each of the one or more categories having a different computational complexity.

[0114] Aspect 14: An apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured to: receive information corresponding to a first artificial neural network (ANN) of a joint training from a server; determine a current hardware capability of a device for performing on-device training of the first ANN of the joint training; transmit an indication of the current hardware capability to the server; and receive information corresponding to a second ANN of the joint training from the server in response to the transmitted indication, the second ANN of the joint training being an adapted version of the first ANN of the joint training generated based on the indication of the current hardware capability.

[0115] Aspect 15: The apparatus of Aspect 14, wherein the at least one processor is further configured to: operate the jointly trained second ANN to generate inferences about locally collected data; and retrain the jointly trained second ANN on the device.

[0116] Aspect 16: The apparatus of Aspect 14 or 15, wherein the at least one processor is further configured to transmit the weight updates determined in the retraining to the server.

[0117] Aspect 17: The apparatus of any one of Aspects 14-16, wherein the device trains multiple classes of the jointly trained first ANN, the multiple classes of the jointly trained first ANN being designated to be accommodated by different levels of the current hardware capabilities.

[0118] Aspect 18: The apparatus of any one of Aspects 14-17, wherein the at least one processor is further configured to determine the current hardware capability based on one or more of a hardware configuration of the device or a current processing workload on the device.

[0119] Aspect 19: The apparatus of any one of Aspects 14-18, wherein the jointly trained first ANN is a computationally more complex model than the jointly trained second ANN.

[0120] Aspect 20: The apparatus of any one of Aspects 14-19, wherein the jointly trained second ANN is a compressed version of the jointly trained first ANN.

[0121] Aspect 21: An apparatus as described in any one of Aspects 14-19, wherein the jointly trained second ANN is one of multiple categories of the jointly trained first ANN, and the jointly trained second ANN is selected from one of the multiple categories of the jointly trained first ANN based on the current hardware capabilities.

[0122] Aspect 22: An apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured to: transmit information corresponding to a first artificial neural network (ANN) for joint training to one or more devices; receive from the one or more devices a first indication of current hardware capabilities for training on a device for the first ANN for joint training; select a second ANN for joint training based on the first indication of current hardware capabilities, the second ANN for joint training comprising one or more categories of the first ANN for joint training, each of the one or more categories having a different computational complexity; and transmit information corresponding to the second ANN for joint training to the one or more devices.

[0123] Aspect 23: The apparatus of Aspect 22, wherein the at least one processor is further configured to receive weight updates determined in a retraining process from the one or more devices.

[0124] Aspect 24: The apparatus of Aspect 22 or 23, wherein the at least one processor is further configured to update the one or more categories of the jointly trained first ANN based on the received weight update.

[0125] Aspect 25: The apparatus of any one of Aspects 22-24, wherein the current hardware capabilities of the one or more devices are based on one or more of a current hardware configuration or a current processing workload.

[0126] Aspect 26: An apparatus as described in any of Aspects 22-25, wherein the at least one processor is further configured to: receive a second indication of current hardware capabilities for training on the device from the one or more devices; and select a third ANN for joint training, the third ANN for joint training comprising one or more categories of the first ANN for joint training, each of the one or more categories having a different computational complexity.

[0127] In one aspect, the receiving means, determining means, transmitting means, means for receiving the second ANN for joint training, and / or selecting means may be the CPU 102, a program memory associated with the CPU 102, a dedicated memory block 118, a fully connected layer 362, and / or a routing connection processing unit 216 configured to perform the recited functions. In another configuration, the aforementioned means may be any module or any equipment configured to perform the functions recited by the aforementioned means.

[0128] The various operations of the methods described above may be performed by any suitable device capable of performing the corresponding functions. These devices may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where there are operations illustrated in the accompanying drawings, those operations may have corresponding paired device-plus-function components with similar numbers.

[0129] As used, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, and the like. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0130] As used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0131] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0132] The steps of the method or process described in conjunction with the present disclosure may be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, or many instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. A storage medium may be coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, a storage medium may be integrated into a processor.

[0133] The disclosed methods include one or more steps or actions for achieving the described methods. These method steps and / or actions may be interchangeable with each other without departing from the scope of the claims. In other words, unless a particular order of steps or actions is specified, the order and / or use of specific steps and / or actions may be changed without departing from the scope of the claims.

[0134] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented with a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link together various circuits including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus, in particular. The network adapter may be used to implement signal processing functions. For some aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, and similar circuits, which are well known in the art and will not be described further.

[0135] The processor may be responsible for managing the bus and general processing, including executing software stored on a machine-readable medium. The processor may be implemented with one or more general and / or special processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuit systems that can execute software. Software should be broadly interpreted as meaning instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. As an example, a machine-readable medium may include a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a disk, an optical disk, a hard drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be implemented in a computer program product. The computer program product may include packaging material.

[0136] In hardware implementation, the machine-readable medium can be a part separated from the processor in the processing system. However, as those skilled in the art will readily appreciate, the machine-readable medium or any part thereof can be outside the processing system. As an example, the machine-readable medium may include a transmission line, a carrier wave modulated by data, and / or a computer product separated from the device, all of which can be accessed by the processor through a bus interface. Alternatively or additionally, the machine-readable medium or any part thereof can be integrated into the processor, such as a cache and / or a general register file may be such a situation. Although the various components discussed can be described as having a specific location, such as a local component, they can also be configured in various ways, such as some components are configured as a part of a distributed computing system.

[0137] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of the machine-readable medium, all linked together with other supporting circuitry via an external bus architecture. Alternatively, the processing system can include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system can be implemented with an application specific integrated circuit (ASIC) with a processor, bus interface, user interface, supporting circuitry, and at least a portion of the machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits capable of performing the various functionalities described throughout the present disclosure. Depending on the specific application and the overall design constraints imposed on the overall system, those skilled in the art will recognize how to best implement the functionality described with respect to the processing system.

[0138] The machine-readable medium may include several software modules. These software modules include instructions that cause the processing system to perform various functions when executed by the processor. These software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. As an example, when a triggering event occurs, the software module can be loaded into the RAM from the hard drive. During the execution of the software module, the processor can load some instructions into the cache to increase the access speed. One or more cache lines can then be loaded into the general register file for execution by the processor. When the functionality of the software module is described below, it will be understood that such functionality is implemented by the processor when the processor executes the instructions from the software module. In addition, it should be appreciated that various aspects of the present disclosure produce improvements in the functionality of processors, computers, machines, or other systems that implement such aspects.

[0139] If implemented in software, each function can be stored on or transmitted by one or more instructions or codes on a computer-readable medium. Computer-readable media include both computer storage media and communication media, and these media include any media that facilitate the transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other media that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer. In addition, any connection is also properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, a server, or other remote sources using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL), or a wireless technology (such as infrared (IR), radio, and microwaves), the coaxial cable, the fiber optic cable, the twisted pair, the DSL, or the wireless technology (such as infrared, radio, and microwaves) are included in the definition of the medium. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray Disks, where disks often reproduce data magnetically, and discs reproduce data optically with lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Additionally, for other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0140] Thus, some aspects may include a computer program product for performing the operations presented. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions that can be executed by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0141] In addition, it should be appreciated that modules and / or other appropriate means for performing the described methods and techniques can be downloaded and / or otherwise obtained by a user terminal and / or base station where applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the described methods. Alternatively, the various methods described can be provided via a storage device (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk, etc.) so that once the storage device is coupled to or provided to a user terminal and / or base station, the device can obtain the various methods. In addition, any other suitable technology suitable for providing the described methods and techniques to a device can be utilized.

[0142] It will be understood that the claims are not limited to the precise configuration and components illustrated above. Various changes, substitutions and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method, comprising: receiving, from a server, information corresponding to a jointly trained first artificial neural network (ANN); Determining current hardware capabilities of a device for on-device training of the first ANN of the joint training; transmitting an indication of the current hardware capabilities to the server; as well as Information corresponding to a jointly trained second ANN is received from the server in response to the transmitted indication, the jointly trained second ANN being an adapted version of the jointly trained first ANN generated based on the indication of the current hardware capabilities.

2. The processor-implemented method of claim 1 , further comprising: operating the jointly trained second ANN to generate inferences about the locally collected data; as well as The jointly trained second ANN is retrained on the device.

3. The processor-implemented method of claim 2, further comprising transmitting to the server weight updates determined in the retraining.

4. The processor-implemented method of claim 2, wherein the device trains multiple classes of the jointly trained first ANN, the multiple classes of the jointly trained first ANN being specified to be accommodated by different levels of the current hardware capabilities.

5. The processor-implemented method of claim 1, further comprising determining the current hardware capabilities based on one or more of a hardware configuration of the device or a current processing workload on the device.

6. The processor-implemented method of claim 1, wherein the jointly trained first ANN is a computationally more complex model than the jointly trained second ANN.

7. The processor-implemented method of claim 1, wherein the jointly trained second ANN is a compressed version of the jointly trained first ANN.

8. The processor-implemented method of claim 1 , wherein the jointly trained second ANN is one of a plurality of categories of the jointly trained first ANN, the jointly trained second ANN being selected from the plurality of categories of the jointly trained first ANN based on the current hardware capabilities.

9. A processor-implemented method comprising: transmitting information corresponding to the jointly trained first artificial neural network (ANN) to one or more devices; receiving, from the one or more devices, a first indication of current hardware capabilities for on-device training of a first ANN for the jointly trained; selecting information corresponding to a jointly trained second ANN based on the first indication of current hardware capabilities, the jointly trained second ANN comprising one or more classes of the jointly trained first ANN, each of the one or more classes having a different first computational complexity; as well as Information corresponding to the jointly trained second ANN is transmitted to the one or more devices.

10. The processor-implemented method of claim 9, further comprising receiving weight updates determined during the retraining process from the one or more devices.

11. The processor-implemented method of claim 9, further comprising updating the one or more classes of the jointly trained first ANN based on the received weight updates.

12. The processor-implemented method of claim 9, wherein the current hardware capabilities of the one or more devices are based on one or more of a current hardware configuration or a current processing workload.

13. The processor-implemented method of claim 9, further comprising: receiving, from the one or more devices, a second indication of current hardware capabilities for on-device training; as well as A jointly trained third ANN is selected, the jointly trained third ANN comprising the one or more classes of the jointly trained first ANN, each of the one or more classes having a different second computational complexity.

14. An apparatus comprising: Memory; as well as at least one processor coupled to the memory, the at least one processor configured to: receiving, from a server, information corresponding to a jointly trained first artificial neural network (ANN); Determining current hardware capabilities of a device for on-device training of the first ANN of the joint training; transmitting an indication of the current hardware capabilities to the server; as well as Information corresponding to a jointly trained second ANN is received from the server in response to the transmitted indication, the jointly trained second ANN being an adapted version of the jointly trained first ANN generated based on the indication of the current hardware capabilities.

15. The apparatus of claim 14, wherein the at least one processor is further configured to: operating the jointly trained second ANN to generate inferences about the locally collected data; and The jointly trained second ANN is retrained on the device.

16. The apparatus of claim 15, wherein the at least one processor is further configured to transmit weight updates determined during retraining to the server.

17. The apparatus of claim 15, wherein the at least one processor is further configured to train multiple classes of the jointly trained first ANN, the multiple classes of the jointly trained first ANN being designated to be accommodated by different levels of the current hardware capabilities.

18. The apparatus of claim 14, wherein the at least one processor is further configured to determine the current hardware capabilities based on one or more of a hardware configuration of the device or a current processing workload on the device.

19. The apparatus of claim 14, wherein the jointly trained first ANN is a computationally more complex model than the jointly trained second ANN.

20. The apparatus of claim 14, wherein the jointly trained second ANN is a compressed version of the jointly trained first ANN.

21. The apparatus of claim 14, wherein the jointly trained second ANN is one of a plurality of categories of the jointly trained first ANN, the jointly trained second ANN being selected from the one of the plurality of categories of the jointly trained first ANN based on the current hardware capabilities.

22. An apparatus comprising: Memory; as well as at least one processor coupled to the memory, the at least one processor configured to: transmitting information corresponding to the jointly trained first artificial neural network (ANN) to one or more devices; receiving, from the one or more devices, a first indication of current hardware capabilities for on-device training of a first ANN for the jointly trained; selecting a jointly trained second ANN based on the first indication of current hardware capabilities, the jointly trained second ANN comprising one or more classes of the jointly trained first ANN, each of the one or more classes having a different first computational complexity; as well as Information corresponding to the jointly trained second ANN is transmitted to the one or more devices.

23. The apparatus of claim 22, wherein the at least one processor is further configured to receive weight updates determined during a retraining process from the one or more devices.

24. The apparatus of claim 22, wherein the at least one processor is further configured to update the one or more classes of the jointly trained first ANN based on the received weight updates.

25. The apparatus of claim 22, wherein the current hardware capabilities of the one or more devices are based on one or more of a current hardware configuration or a current processing workload.

26. The apparatus of claim 22, wherein the at least one processor is further configured to: receiving, from the one or more devices, a second indication of current hardware capabilities for on-device training; and A jointly trained third ANN is selected, the jointly trained third ANN comprising the one or more classes of the jointly trained first ANN, each of the one or more classes having a different second computational complexity.

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