Transceiver controlled antenna electron beam tilt

Abstract

A transceiver integrated circuit (IC) subarray, each transceiver IC sub-array comprises at least a first transceiver IC and a second transceiver IC physically arranged in the sub-array: the transceiver ICs are configured to process a series of co-processed aggregated signal port IQ data packets according to (i) beam tilt information received in control message packets and (ii) sub-array locations of the transceiver ICs, electron beam tilt is accomplished using one or more signal processing techniques selected from the group consisting of (i) applying an incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO), (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), and (iii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO). (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication); and (iv) applying a time delay in the discrete time domain signal transmitting the baseband signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 357,579, filed on June 30, 2022, entitled “TRANSCEIVER CONTROLLED ANTENNA ELECTRONIC BEAM TILTING,” inventors Jong-Hyun Kim and Yaniv Kafer, the entire contents of which are hereby incorporated by reference into this document for all purposes. Background Art

[0003] The present disclosure relates to the field of telecommunications, and more specifically to the distribution of signals for transmission through antenna radiating elements. It can be applied to the field of wireless communications such as 2G / 3G / 4G, LTE, Advanced LTE and 5G.

[0004] This section is intended to introduce the reader to various aspects of the art that may be related to various aspects of the present disclosure described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to promote a better understanding of various aspects of the systems and methods described herein. Therefore, it should be understood that these statements should be read from this perspective, rather than as an admission of the prior art. Summary of the invention

[0005] Described herein are methods and apparatus for implementing electronic beam tilt in a subarray of individual transceivers, wherein each transceiver is provided with the same frequency domain IQ data for processing (so-called "commonly processed IQ data"). When processing the frequency domain IQ data, each transceiver implements one or more signal processing techniques to implement the electronic beam tilt, the one or more signal processing techniques including: (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO); (ii) applying constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication); (iii) applying constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication); (iv) applying time delays in discrete time domain signals of the transmission baseband signal; or (v) a combination of the above methods. References in the specification to "one embodiment", "embodiment", "example embodiment", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic; but not every embodiment must include the particular feature, structure, or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, that feature, structure, or characteristic may be used in connection with other embodiments whether or not explicitly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1depicts one embodiment of an active antenna array assembly or active antenna unit (AAU) according to some embodiments;

[0007] Figure 2 depicts a radio unit architecture having multiple sets of serially connected transceivers for processing RF communication signals associated with corresponding sets of antenna radiating elements in accordance with some embodiments;

[0008] Figure 3 Depicted is a group of serially connected transceivers according to some embodiments, wherein an incoming packet for transmission is received at a first transceiver and propagated over a serial data connection to other transceivers in the group, and wherein the incoming RF signal is processed and packetized for forwarding back along the serial transceiver chain;

[0009] Figure 4 is an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology to respective serially connected transceiver groups;

[0010] Figure 5 An embodiment of a synchronization and clock distribution circuit for use with transceivers distributed across an active antenna array assembly is depicted;

[0011] Figure 6 depicts various clock distribution trees for providing clock signals to a transceiver array to reduce clock skew according to some embodiments;

[0012] Figure 7 is a block diagram of a distribution unit connected to a radio unit via a fronthaul data interface and a hierarchical beamformer architecture within the radio unit according to some embodiments;

[0013] Figure 8 is a graphical representation of a downlink transmit beamforming operation using a beamforming / precoding matrix operating on a user data layer to generate antenna-specific IQ data in accordance with some embodiments;

[0014] Fig. 9 is an illustration of conversion of a user data layer to a beamformed downlink transmission data stream according to a precoding operation followed by a beamforming operation according to some embodiments;

[0015] Fig.10 is an illustration of conversion of a user data layer to a beamformed data stream according to a generalized combined precoding and beamforming operation in accordance with some embodiments;

[0016] Fig.11 is an illustration of receive uplink signal processing including receive beamforming and layer decoding according to some embodiments;

[0017] Fig. 12A is an example of a transceiver device architecture for forming a group of serially connected transceivers according to some embodiments, wherein each transceiver includes an integrated digital signal processor for converting frequency domain digital data to / from time domain digital data, a plurality of integrated digital power amplifiers for converting digital baseband time domain signals to amplified analog RF signals, and an analog RF downconverter and an analog-to-digital converter;

[0018] Fig. 12B is another example of a transceiver device architecture excluding an integrated digital signal processor for converting frequency-domain digital data to / from time-domain digital data according to some embodiments;

[0019] Fig.13A and Fig. 13B are respectively generating a plurality of amplified multi-carrier RF signals according to some embodiments FIG. 12A to FIG. 12B The transceiver device transmits circuits and generates multiple down-converted and sampled OFDM signals FIG. 12A to FIG. 12B A block diagram of a receiving circuit of a transceiver device;

[0020] Fig.14 According to some embodiments, Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B a signal processing flow for dual-carrier, dual-polarization communication signals of a transceiver device;

[0021] Fig.15 According to some embodiments, Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B two serially connected transceiver devices to generate a signal processing stream of a four-carrier, dual-polarized communication signal;

[0022] Fig.16 depicts various additional details of multi-level beamforming according to some embodiments; and

[0023] Fig.17 Aspects of beamforming weight errors within a subarray-beamforming signal processing system are shown according to some embodiments. DETAILED DESCRIPTION

[0024] Figure 1An antenna array assembly 100 is depicted in accordance with some embodiments. As depicted, the antenna array assembly 100 has a grid of radiating elements (also referred to herein as antenna elements or antenna radiating elements) generally arranged in rows (e.g., rows 104) and columns (e.g., column 100) on a panel 102, which may be a printed circuit board (PCB) or other suitable support structure for the radiating elements. Positions within the grid, such as position 116, may have juxtaposed radiating elements (such as elements 112 and 114) to provide different polarizations of radiation, generally referred to as horizontal and vertical polarizations, or equivalently, positive 45 degrees (+45°) and negative 45 degrees (-45°). The radiating element grid may be as shown in FIG. Figure 1 In one embodiment, the radiating elements are positioned about 1 / 2 wavelength (λ) apart, where the wavelength λ is associated with the desired frequency operating range of the antenna array, which may be associated with the carrier frequency of the system, or more generally, the center frequency of the system, particularly in embodiments employing a frequency division duplex system (FDD) utilizing multiple carrier frequencies. Some embodiments may operate within multiple frequency bands, and in one such embodiment, such as Figure 1 The array shown in can be configured to operate in a first frequency band using a first frequency having a wavelength λ1, and in a second frequency band having a wavelength λ2=2λ1. In such an embodiment, operation in the first frequency band (λ1) can utilize adjacent antenna radiating elements spaced apart by a distance of .5λ1 as shown, but for operation in a second, lower frequency band (having a wavelength λ2), elements spaced apart by two (e.g., every other row or column) have a spacing of .5λ2 and can therefore be used for operation in the second frequency band.

[0025] Although the antenna array panel can be configured with more antenna pairs (e.g., 128, 194, 256, 512, etc.) or even fewer antennas (e.g., 32, 16, etc.), Figure 1 The particular array of depicts 64 horizontal radiating elements and 64 vertical radiating elements, juxtaposed in pairs and arranged in an 8x8 square configuration on a panel of approximately 35 to 40 centimeters by 35 to 40 centimeters, with the radiating elements spaced approximately 4.3 centimeters apart. The antenna array assembly 100 also includes a circuit board assembly 128, which includes a power module 130, a clock distribution circuit 132, a global positioning satellite (GPS) receiver 134, a processor circuit 138 for performing packet protocol processing and, in some embodiments, beamforming, etc., a network data interface 136, a power source connector 140, and a GPS connector 142.

[0026] In various embodiments described below, the radiating elements may be grouped into subarrays, such as a column subarray 106 having eight vertical radiating elements and eight horizontal radiating elements, or smaller subarrays, such as groups 108 and 122 each having four horizontal elements and four vertical elements, or groups 110, 120, 124, 126 each having two vertical radiating elements and two horizontal radiating elements. In some embodiments, the antenna subarray may include a two-dimensional set of elements, such as four cross-polarized radiating elements arranged in a square configuration, or six cross-polarized pairs arranged in a 2x3 grid. Alternatives include a set of two or more adjacent vertically polarized elements forming an antenna element subarray, and a corresponding set of vertically polarized elements of the cross-polarized pairs forming a separate subarray. In another embodiment, each cross-polarized pair of radiating elements may be an array element that is driven individually.

[0027] Each radiating element subarray may be driven by a radio frequency (RF) signal generated by a set of transceivers located near the antenna. As used herein, the term "antenna subarray" refers to a grouping of radiating elements positioned in a corresponding array pattern that are functionally related to each other primarily based on their connection to a corresponding set of cooperating RF transceiver integrated circuits (ICs) that are used to process RF signals associated with the radiating elements of the antenna subarray. In this case, the transceiver circuitry includes a set of serially connected transceiver integrated circuit packages (hereinafter referred to as "transceiver ICs") having a first transceiver IC connected to a beamformer processor via a serial data connection (or "link"), and a series of point-to-point serial data connections between the transceiver ICs, wherein, in some embodiments, the data path terminates at the last transceiver IC of the group. In alternative embodiments, the transceiver ICs may be interconnected in a ring configuration, wherein the last transceiver IC in the chain may be connected back to the beamformer processor using an additional serial data connection, or may be connected to the last transceiver IC in a separate chain of serially connected transceiver IC subarrays.

[0028] Note that in some embodiments, a given set of transceiver ICs in a transceiver IC subarray (i.e., a set of serially connected transceiver ICs) associated with a corresponding antenna subarray may be capable of processing independent RF signals for each radiating element. Thus, as used herein, the term "antenna subarray" refers to a set of antenna elements (of a potentially larger array of antenna elements) associated with a given set of transceiver ICs. In some embodiments described herein, a group of radiating elements may operate in a coordinated manner by transmitting the same or similar RF signals (or sets of RF signals for H and V polarizations) with possible phase differences therebetween in order to achieve a desired radiation pattern for beamforming, antenna tilt, or similar directivity.

[0029] Figure 2 Depicted is a radio unit architecture having multiple sets of serially connected transceivers for processing RF communication signals associated with corresponding sets of antenna radiating elements in accordance with some embodiments. Figure 2 As shown, each serially connected transceiver IC group contains at least two serially connected transceiver ICs physically arranged in a transceiver IC sub-array. Specifically, transceiver IC 222 connected to beamformer processor (referred to as "BFP" in some places herein) 202 via serial data link 206 is also serially connected to transceiver IC 232 via full-duplex serial data link 228, thereby forming a vertically oriented transceiver IC sub-array along the column of the panel array (such as grouping 110). Similarly, transceiver IC 212 is connected to transceiver IC 230, thereby forming another transceiver IC sub-array.

[0030] Each serial data link between transceiver ICs (e.g., 228) utilizes a Serdes (serializer / deserializer) transceiver or a collection of Serdes transceivers to establish a point-to-point link. In one embodiment, each transceiver IC includes two such Serdes transceivers. Alternatively, a higher number of Serdes devices may be included to provide a higher level of interconnectivity between transceiver ICs. The Serdes may utilize a standard serial data signaling format, such as a 2-level pulse amplitude modulation (PAM2) non-return-to-zero (NRZ) differential signal transmitted on a pair of wires. In one embodiment, a data rate of 6G bits per second (Gbps) PAM2 is sufficient to transmit aggregate signal port IQ data packets (including headers), as well as provide additional throughput capabilities for transmitting control plane messages to transceiver ICs. The serial link data rate may be selected to accommodate data packets to and from each transceiver IC subarray based on the desired deployment, including a desired number of independent signal ports, a desired number of component carriers, multi-band operation (thereby adding additional carriers), FDD or TDD, the number of transceiver ICs connected in the transceiver IC subarray, etc.

[0031] Additionally, as will be described in greater detail below, in various embodiments, each serial data link between the beamformer processor 202 and a given transceiver IC subarray, as well as the serial data links serially interconnecting individual transceiver ICs within a given transceiver IC subarray, may have sufficient data rates to accommodate data packets carrying IQ data in either the frequency or time domain. In this regard, as will be described in more detail below, each transceiver IC subarray may, for example, (i) receive / transmit aggregated frequency-domain IQ data packets from / to a beamformer processor where frequency-domain to time-domain conversion (on the transmit side) and time-domain to frequency-domain conversion (on the receive side) are performed at a separate transceiver IC (e.g., via iFFT (inverse fast Fourier transform) and FFT (fast Fourier transform) processing, respectively); or (ii) receive / transmit aggregated time-domain IQ data packets from / to a beamformer processor where frequency-domain to time-domain conversion (on the transmit side) and time-domain to frequency-domain conversion (on the receive side) are performed at the beamformer processor instead (e.g., via iFFT and FFT processing, respectively).

[0032] As an example of serial link data rates, one symbol of a 100Mhz OFDM 5G carrier with 30kHz subcarrier spacing will be transmitted in a 33.33 microsecond (μsec) time window. The data rate required for such transmission on two signal ports (e.g., separate signals for H and V polarizations) with 3,300 subcarriers with 2 samples (I / Q) per subcarrier (e.g., 12 bits / sample) for each of the 14 OFDM symbol slots results in 2*3,300*2*12=158.4kbps, and the 14 OFDM symbols will be transmitted in a 5ms transmission slot, resulting in a net required data rate of 158.4k*14 bits / .5ms=4.43Gbps. If 8b-10b encoding is used on the serial data link, and an additional 10% is added for packet headers and protocol overhead, then for dual signal ports, a throughput of approximately 1.1*4.43*10 / 8 Gbps = 6.1 Gbps will be required per carrier. In some embodiments, for each transceiver IC subarray (i.e., a collection of serially linked transceiver ICs), 6.1 Gbps of serial data transmission capacity is sufficient. For other embodiments with independently controlled signal ports at each transceiver IC, a total throughput of approximately 12 Gbps or even 20 Gbps is sufficient for most applications and configurations as described herein, although 30 Gbps may be achieved if desired for certain other embodiments.

[0033] For lower capacity deployments, lower serial data rates are sufficient. For example, a dual-polarized 20MHz 4G LTE data signal (which uses an FFT of size 2,048 and occupies a 66.67μsec transmission slot time window) requires a data throughput of: 2 ports * 1,200 subcarriers x 2 (I / Q samples / subcarrier) x 12 (bits / sample) / 66.67μsec window = 1,200x2x12x / 66.67μsec = approximately 864Mbps. If the data rate is increased by 10 / 8 to accommodate 8b-10b encoding, and 10% is added for overhead, the data rate is approximately 1.2Gbps.

[0034] In another embodiment of the transceiver IC serial data port, a four-wire interface can be used to double the data rate. Alternatively, so-called integral NRZ (ENRZ) signaling using correlated signals in the form of vector signal codes can be sent on four wires to carry 3 bits / baud (i.e., per signaling interval), resulting in three times the data transmission rate (at the same baud rate) instead of just two times. Thus, using a 7.5G baud / second signaling rate, a data throughput of 22.5 Gbps can be reliably achieved over the distance from the beamformer to the transceiver IC subarray. As another alternative, PAM4 signaling (in combination with NRZ or ENRZ signaling) or other vector signal formats (e.g., correlated NRZ (so-called CNRZ-5), using correlated signals to transmit 5 bits on six wires) can be used to provide increased data throughput without significantly increasing the signaling baud rate.

[0035] Overall, Figure 2 A total of 8 columns of transceiver ICs are depicted, each column having 8 transceiver ICs, for a total of 64 transceiver ICs, where each transceiver IC is configured to handle two separate transmit signals (e.g., different RF signals on the H and V signal ports) and two separate receive signals (H / V signal ports). However, because Figure 2 In the embodiment of FIG. 1 , the first two rows of 8 transceiver ICs are connected in pairs, so these 16 transceiver ICs form a single "row" 238a of 8 transceiver IC groups (also referred to herein as transceiver IC subarrays). Similarly, the other transceiver ICs are grouped into another 3 "rows" (238b, 238c, 238d), each with 8 transceiver subarrays, for a total of 8 columns x 4 rows of transceiver IC groups (32 transceiver IC subarrays). In physical dimensions, each column is the width associated with a single collocated cross-polarized antenna, but each "row" of transceiver IC groups encompasses two rows of cross-polarized antenna elements.

[0036] Further described below Figure 432 transceiver IC subarrays in an 8x4 transceiver IC subarray configuration are also depicted. However, each transceiver IC subarray includes three transceiver ICs connected in series. Note that the transceiver IC subarrays are positioned adjacent to corresponding radiating antenna elements arranged in corresponding antenna subarrays in an element-by-element manner. In some embodiments, the transceiver IC subarrays are located on the back side of the antenna array panel 102, but are still adjacent to (i.e., close to) the corresponding radiating elements for transmitting and / or receiving RF communication signals associated with a given transceiver IC. In some embodiments, the transceiver ICs may be coupled to the radiating elements via vias, intermediate structures, and / or circuits (such as transmission and reception filters mounted on a panel or positioned on a subpanel behind a structure supporting an array of antenna radiating elements).

[0037] Adjacent on an element-by-element basis refers to the relative positioning of the transceiver IC subarrays and corresponding antenna subarrays overlying one another such that each individual transceiver IC in a given transceiver IC subarray is located in an area of ​​the panel 102 associated with a corresponding antenna radiating element in the antenna array or subarray that will be used to transmit and receive signals associated with that individual transceiver IC.

[0038] As another example of being adjacent in an element-by-element manner, in some embodiments such as a frequency division duplex (FDD) system, two transceiver ICs (one transceiver IC dedicated to generating two transmit (H / V) signals at a transmit frequency and the other transceiver IC for processing two receive (H / V) signals at a receive frequency) may form a transceiver IC subarray associated with an antenna subarray consisting of a single collocated cross-polarized antenna. In a dual-band FDD configuration, four transceiver ICs may be linked as a transceiver subarray and positioned adjacent to an antenna subarray consisting of a single collocated cross-polarized antenna.

[0039] The feature of being adjacent in an element-by-element manner provides a distributed transceiver IC architecture that allows the amplified transmitted RF signal generated by each given transceiver IC to experience very little power loss or noise degradation when traversing the very short physical connection from the transceiver IC to the radiating element. In some embodiments, different ratios of transceiver ICs and radiating elements may be adjacent in pairs, such as two transceiver ICs may be placed adjacent to each set of three cross-polarized elements, and so on.

[0040] Throughout this specification, many embodiments are depicted as utilizing a transceiver IC (e.g., 212, 222, 230, 232, etc.) that includes two independent full-duplex transceivers having two transmitters / amplifiers and two independent receivers, each associated with an RF signal port (e.g., 214 or 216) interconnected to a corresponding antenna radiating element (e.g., 218, 220, respectively). Thus, in one embodiment, a single transceiver IC includes an integrated circuit having two full transceivers that transmit and receive two independent RF signals, the two full transceivers being configured such that one RF signal port (tx / rx) is associated with an H-polarized signal port (e.g., 214) and one RF signal port (tx / rx) is associated with a V-polarized signal port (e.g., 216). In such embodiments, each transceiver IC may be referred to as a 2T2R transceiver IC and may be associated with a pair of collocated cross-polarized radiating elements. As an illustrative example, each cross-polarized radiating element pair (218, 220), (224, 226), and (234, 236) is associated with a respective single transceiver integrated circuit, such as transceiver IC 212 is associated with cross-polarized radiating element (218, 220), transceiver IC 222 is associated with element (224, 226), and transceiver IC 232 is associated with element (234, 236).

[0041] In other embodiments, the transceiver ICs may each be configured to provide, for example, four separate analog RF transmit and receive paths through four independent signal ports (4T4R). Such embodiments may include dual PLLs for generating carrier frequencies for both transmit and receive carriers to fully utilize the transceiver ICs when operating in FDD signaling mode. The specific number of transceivers included within a given transceiver IC may depend on factors such as the total desired output power of the panel, the use of additional external power amplifiers, FDD or TDD operation, the data carrying capacity of the serial data link providing interconnection between the transceiver ICs, and many other factors.

[0042] More generally refer to Figure 2, the circuitry of the radio unit 200 (all of which may be deployed within a single active antenna panel assembly) includes a high throughput packet-based interface 252 to a base station or distributed unit (DU) (not shown). The interface 252 may include multiple separate physical network interfaces, such as four separate 25Gbit Ethernet links provided over a fiber optic cable using a small form factor pluggable (SFP) module 242 or a quad SFP (QSFP) module. Information may be transmitted over the interface 240 using an Ethernet protocol, a CPRI / eCPRI protocol, or a similar protocol. The beamformer processor (BFP) 202 performs pre-coding and beamforming operations on the downlink transmission data, and responsively generates aggregate signal port IQ data packets for transmission to the corresponding transceiver IC subarrays, as described below with reference to Figure 8 , Fig. 9 and Fig.10 As further described above. As noted above, in some embodiments, the IQ data packet may contain frequency domain IQ values ​​for subcarriers within an OFDM (Orthogonal Frequency Division Multiplexing) communication system (such as an LTE or 5G communication system). In other embodiments, the IQ data packet may alternatively contain time domain IQ values ​​for subcarriers within an OFDM communication system or for other carriers such as 2G GSM signals. In the uplink direction, the BFP 202 performs beamformer combining to obtain virtual beamforming antenna port signals, and further combines to recover the user data layer, as described below with respect to Fig.11 Further described.

[0043] exist Figure 2 In the depicted embodiment, the beamformer processor 202 is connected to each transceiver IC subarray via a serial data link, such as link 206. Depending on the length of the data link (depicted as 4 sets 204a, 204b, 204c, 204d, each set having 8 links), each data link may utilize a Serdes repeater / retimer 208, 210 to extend the range of the serial data link from the BFP 202 to the area in the panel 102 where a given transceiver IC subarray (and corresponding antenna subarray elements) is located. Figure 4 In the alternative embodiment shown, the BFP 400 is connected to a set of transceiver IC subarrays via a high-speed Serdes link 402, whereby a Serdes multiplexer (MUX) 404 (and corresponding high-speed links to Serdes MUXs 422, 424, 426) demultiplexes (i.e., separates) a high-rate serial data stream into lower-rate serial data streams 406, which are directed to each individual transceiver IC subarray. The Serdes MUX devices 404, 422, 424, 426 perform an inverse multiplexing operation on uplink data transmitted from the transceiver IC subarrays to the BFP 202.

[0044] refer to Figure 2 , an example transceiver IC subarray includes a transceiver IC 222 and a transceiver IC 232 coupled via a serial data link 228. The two transceiver ICs are located near their respective antenna radiating elements 224, 226 and 234, 236, respectively. In some embodiments, they are placed on one side of the PC board, adjacent to the antenna elements, and are electrically connected using through vias or through intervening circuit elements such as filters, duplexers, quadplexers, SPDT (single pole double throw) TDM switches, etc. As shown in FIG. Figure 2 As shown, each transceiver IC generates two separate RF transmission downlink (DL) signals for H polarity and V polarity, and receives and processes two separate RF uplink (UL) signals. Also depicted is an observation transceiver 246 connected to the BFP 202 via a serial data link 244, with an RF signal connection 248 interconnecting each transceiver through a calibration network.

[0045] Figure 3 A group of such serially connected transceivers is depicted which would be placed in transceiver IC subarray locations adjacent to antenna radiating elements of corresponding antenna subarrays located within the antenna panel array 102 in an element-by-element manner. Incoming packets for DL ​​transmissions are received from the BFP 300 at the first transceiver IC 312 via the serial data link 308, and at least some of these packets are propagated to other transceiver circuits in the transceiver ICs 350, 366 in the transceiver group via the serial data connections 348, 364. Similarly, incoming RF signals on the UL are processed and packetized for forwarding back along the serial data transceiver IC chain 362, 346, 310. In this embodiment, each transceiver IC is configured to handle two separate transmit signal paths and two separate receive signal paths via two separate signal ports typically associated with two corresponding antenna radiating elements. Operation in TDD Mode Figure 3 The transceiver subarray is configured such that transceiver IC 312 transmits and receives RF signals on first signal port 328 and transmits and receives RF signals on second signal port 344. Similarly, transceiver IC 350 is associated with signal ports 356 and 360, while transceiver IC 366 is associated with signal ports 370 and 378.

[0046] As previously described, the two transceiver signal ports of the transceiver IC can be interconnected to a single set of cross-polarized antenna elements. For TDD operation, this provides 2T2R (two transmissions and two receptions) signal processing capabilities. In an alternative embodiment, the two signal ports can each be connected to corresponding radiating elements in two different cross-polarized antenna pairs, for example, where the first transceiver of the transceiver IC processes the transmission and reception signals of the vertically polarized elements of the first cross-polarized radiating element pair, and the second transceiver of the same transceiver IC processes the transmission and reception signals of the vertically polarized elements of the second cross-polarized radiating element pair. The second transceiver IC can then be used to process the signals associated with the two horizontally polarized elements of the two cross-polarized pairs.

[0047] In other alternative embodiments, the output of each signal port may be split and connected to multiple radiating elements in parallel, such as one signal port connected in parallel to the vertically polarized radiating elements of two (or three, etc.) cross-polarized pairs, and another signal port connected in parallel to the horizontally polarized radiating elements of the same two (or three, etc.) cross-polarized pairs. In still other embodiments described below, the amplified RF signals produced by a transceiver IC or by multiple transceiver ICs may be provided to additional amplifier stages external to the transceiver IC, and / or combined, before being provided to the radiating elements.

[0048] In some embodiments, for example, frequency domain I / Q data packets are transmitted to a collection of serially connected transceiver ICs distributed on an active antenna panel. An aggregate data packet is a superposition of frequency domain subcarrier specific data, typically representing resource blocks (RBs) allocated across many data layers and possibly many users, with different beamforming weights applied, and therefore containing fully beamformed (including MIMO precoding when used) subcarrier IQ sample data for a specified frequency band, component carrier, and signal port. Each IQ data packet may have a single header, but still include concatenated or interleaved data for multiple signal ports (such as for H and V signal ports). Such packets may be referred to as dual signal port packets. In some embodiments, the packet header may include identification data associated with a specific transceiver IC, and may include IQ data for any number of signal ports processed by the transceiver IC, and may be generally referred to as multi-signal port data.

[0049] Figure 3The user aggregate frequency domain data of packet 302 in 0 indicates a packet of frequency domain IQ data that is processed collectively by the transceiver ICs in a given transceiver IC subarray. Packet 302 may include a header (not shown for clarity) that identifies various aspects of the type of data contained in the packet, as well as packet identification data (such as one or more of the following: frequency band ID, component carrier ID, signal port ID, and / or transceiver ID). The primary payload data in packet 302 includes subcarrier specific IQ data for a signal port (not limited to, for example, horizontally polarized RF signals for a particular component carrier, in Figure 3 The same packet (or, in some embodiments, a separate packet with a separate header and ID data field) includes subcarrier IQ data for a second signal port (e.g., for a vertically polarized RF signal of the same component carrier, e.g., Figure 3 302 is a packet of IQ data for a subcarrier having an H polarization signal port and a V polarization signal port, but the IQ data may also be interleaved, such as an IQ sample pair for the H signal port and a pair for the V signal port for subcarrier 1, followed by an IQ sample pair for H and V for subcarrier 2, etc. Each I sample and Q sample may be represented as a certain number of bits, such as 12, 14, or 16, etc., depending on the desired signal resolution. Packet 302 may contain IQ sample data for multiple subcarriers, such as 612, 1,596, 3,276, or more subcarriers, for each signal port, for a particular carrier and frequency band.

[0050] As noted above, the aggregated beamforming IQ data packets communicated on the serial data connection (link) from / to the BFP (beamformer processor) and the transceiver IC may contain (subcarrier-specific) frequency domain IQ data or (subcarrier-specific) time domain IQ data. In this regard, it should be noted that packet data transmission of aggregated beamforming frequency domain IQ data packets on the serial data connection from / to the BFP and the transceiver IC is more efficient than packet data transmission of aggregated beamforming time domain IQ data. Specifically, the frequency domain IQ data specifies the in-phase and quadrature (IQ) values ​​of a particular subcarrier to be used for data transmission (and reception) in a given communication system. However, for DL ​​signals, such as in an OFDM communication system (e.g., an LTE or 5G communication system), before converting the frequency domain IQ data to time domain digital data via iFFT, it may be necessary to insert zero values ​​into the IQ data set to account for unused subcarriers within a given component carrier (e.g., subcarriers used as guard bands), resulting in a time domain sequence of converted IQ data having many more IQ data points that need to be transmitted to the transceiver IC / transceiver IC subarray (e.g., initially transmitted from the BFP and then distributed accordingly among the transceiver ICs in a given transceiver IC subarray). Similarly, for UL signals, the frequency domain IQ data processed via FFT may exclude frequency domain values ​​of unused subcarriers, while the equivalent time domain IQ data associated with the unused subcarriers is a component of the time domain IQ data that may not be removed prior to transmitting the time domain data over a serial data connection as described herein.

[0051] In this regard, depending on the bandwidth of a given communication channel, it may be relatively important to improve the efficiency of conveying frequency domain IQ data relative to the corresponding time domain IQ data. By way of example, for a 20MHz wide LTE channel, the ratio of unused subcarriers to data modulated subcarriers will be greater than a similar ratio under a 100MHz wide LTE channel. Therefore, it becomes more efficient to convey subcarrier specific IQ data in the frequency domain rather than in the time domain. More specifically, as described above, even if a subset of subcarriers remains unused (unmodulated / unloaded with data), the time domain representation of these subcarriers will still result in complex time domain samples, thereby increasing the amount of data that needs to be transmitted on the serial data link. Additionally, the serial data link between the BFP and the transceiver IC subarray and the serial data link of the individual transceiver IC in the interconnected given transceiver subarray may have limited data carrying capacity (e.g., how much data (data rate) can be conveyed on those links per given time period). Therefore, in some embodiments, it may be more desirable to perform IQ packet data transmission from / to the BFP and between the transceiver IC in the frequency domain.

[0052] Nevertheless, various embodiments of the signal processing methods and apparatus described herein may alternatively utilize time-domain IQ data packets. More specifically, as will be described in more detail below, in some embodiments, a beamforming processor (BFP) (e.g., BFP 202, 300, 400, etc.) may be configured to include a digital signal processing architecture (e.g., iFFT and FFT processing elements) to transmit and receive time-domain IQ data packets to / from a transceiver IC / transceiver IC subarray. For example, in some embodiments, the beamforming processor may include a digital signal processor (DSP) configured with appropriate programming instructions to execute algorithms for IFFT and FFT operations. For purposes of illustration, the following may be discussed with respect to Figure 3 1. The various operating principles related to the arrangement illustrated in FIG. 1 assume that the IQ data packets communicated, for example, to / from the BFP 300 and between the various transceiver ICs are frequency domain IQ data packets.

[0053] Figure 3 The transceiver subarray depicted in is one of many such subarrays on the panel, and each serially connected transceiver IC group receives a unique aggregate signal port (or dual signal port or multi-signal port) IQ data packet data stream. Recall that each serially connected transceiver IC group has at least two serially connected transceiver ICs and is physically arranged in a transceiver IC subarray. The transceiver IC subarray is in turn positioned adjacent to a corresponding radiating antenna element arranged in a corresponding antenna subarray in an element-by-element manner.

[0054] The transceiver IC 312 receives a unique aggregate signal port IQ data packet data stream such as the user aggregate frequency domain data of packet 302 at the serial port receiver 314 (as described above) and provides the data to the split copy register 318 for further processing. In one embodiment, the split copy register 318 is a packet header processor that is configured to check the packet header to determine whether the IQ data is intended to be processed by its corresponding transceiver IC, and if so, forward the packet to the signal port split processor 320. The signal port split processor 320 (also labeled as H / V split) identifies packets or packet portions destined for different signal ports within the transceiver IC, and it can be H and V polarized signals, or other configurations as described herein. The signal port split processor 320 can be implemented as a register that performs memory write operations on the digital signal processor (DSP) memory space integrated within the transceiver IC 312. In addition, the split copy register 318 can determine that the same packet should also be forwarded to the next transceiver IC in the transceiver IC subarray for processing by one or more serially connected transceiver ICs. To reduce latency, the packet header processor or split copy register 318 need not buffer the entire signal port IQ data packet before determining to forward the packet to the next transceiver IC by sending the data to the serial data transmitter 332 for transmission on the serial link 348. In other embodiments, the packet header processor 318 may be configured to operate in a transparent mode, where all packets are saved for local processing and forwarded out of the second serial transceiver without header inspection.

[0055] For the signal port packet format 302, the aggregate IQ signal port packets are forwarded to each transceiver IC using split replica circuits 318, 352, 368 and are processed collectively by each transceiver IC. Note that transceiver IC 366 is the last transceiver IC in the chain, and in the illustrated embodiment, the split replica register 368 forwards the packet to the corresponding signal port split processor, but the serial transceivers 372 / 374 are not used.

[0056] Each transceiver IC then processes the packets by first separating the IQ data for a first signal port (H IQ data 322) and a second signal port (V IQ data 338) and providing the data to a transmitter within transceivers 321 and 335 for conversion to the time domain via an inverse fast Fourier transform (iFFT). As previously described, separate IQ port specific data may be transmitted in separate packets, in which case the signal port data may be directly stored for further processing without any separation or deinterleaving. The iFFT processing and subsequent time domain processing generates an aggregate signal port discrete time domain baseband data signal, which is then converted to an amplified radio frequency (RF) signal at ports 328, 344. The transmitters of transceivers 321, 335 (which transmit the data with respect to the first signal port) and the second signal port (V IQ data 338) are connected to the transmitters of transceivers 321 and 335. Fig. 12A and Fig.13A The RF transceiver IC (described more fully herein) includes a DSP for computing the iFFT, frequency and time domain signal processing elements (cyclic prefix addition, phase and gain adjustment, frequency offset, filtering and sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc.), and RF modulation and amplification circuitry in the form of a multi-phase carrier generator and a digital power amplifier. Note that in alternative embodiments involving, for example, communication of aggregate signal port / user IQ data packets in the time domain (as mentioned above), the iFFT processing may be performed at the beamformer processor rather than at the transceiver IC itself (e.g., as will be incorporated into the Fig. 12B explained in more detail).

[0057] Thus, some embodiments may include a method comprising: receiving a unique aggregate signal port IQ data packet data stream at each of a plurality of serially connected transceiver IC groups, each serially connected transceiver IC group comprising at least two serially connected transceiver ICs physically arranged in a transceiver IC subarray and positioned adjacent to corresponding radiating antenna elements arranged in a corresponding antenna subarray in an element-by-element manner; within each serially connected transceiver IC group, forwarding at least a subset of the aggregate signal port IQ data packets from a first transceiver IC to a next serially connected transceiver IC; transceiver IC; and at each transceiver IC of at least two serially connected transceiver ICs within each serially connected transceiver IC group: processing at least some of the aggregate signal port IQ data packets using an integrated inverse fast Fourier transform (IFFT) processor of the transceiver IC to convert the aggregate signal port IQ data packets into an aggregate signal port discrete time-domain baseband data signal; converting the aggregate signal port discrete time-domain baseband data signal into an amplified modulated RF signal using an integrated digital power amplifier and a multi-phase carrier generator of the transceiver IC; and transmitting the amplified modulated RF signal at at least one corresponding adjacent radiating antenna element of the corresponding adjacent radiating antenna elements.

[0058] In addition, some embodiments may include a device including a plurality of transceiver IC subarrays, each transceiver IC subarray including: a first transceiver IC having (i) a first serial digital data port providing a serial data connection to a beamformer processor, the first serial digital data port being configured to receive a unique aggregate signal port IQ data packet data stream; and (ii) a second serial digital data port; and a second transceiver IC having a third serial digital data port connected to the second serial data port of the first transceiver IC and providing a serial data connection to the first transceiver IC. The first transceiver IC and the second transceiver IC may be physically arranged in the transceiver IC subarray and positioned adjacent to a plurality of radiating antenna elements arranged in the antenna subarray in an element-by-element manner. The first transceiver IC in each transceiver IC subarray may further include a packet processor configured to forward at least a subset of the aggregate signal port IQ data packets received from the beamformer processor to a corresponding second transceiver IC. The first transceiver IC and the second transceiver IC may each include: a digital signal processor configured to perform an inverse fast Fourier transform (IFFT) to convert an aggregate signal port IQ data packet into an aggregate signal port discrete time-domain baseband data signal; a time-domain processing circuit configured to convert the aggregate signal port discrete time-domain baseband data signal into an oversampled signal port discrete time-domain data signal; and an integrated digital power amplifier and a multi-phase carrier generator configured to convert the oversampled signal port discrete time-domain data signal into an analog modulated RF signal.

[0059] When receiving an uplink (UL) signal, the receiver portion of the transceiver 321, 335 performs down-conversion and analog-to-digital conversion, followed by further time-domain processing (e.g., sampling rate conversion, quadrature error correction, filtering, frequency offset correction, cyclic prefix detection and removal, etc.), followed by an FFT conversion to frequency-domain IQ data values ​​for each of the multiple subcarriers in the OFDM signal. Thus, in a receive mode of operation, the transceiver IC generates a received RF signal from the received RF signal. Figure 3 IQ data packets 322, 338 depicted in FIG.

[0060] In one embodiment, the transceiver IC includes a digital signal processor (DSP) that not only performs all iFFT calculations to produce downlink (DL) transmission time domain signal port signals, but also processes the received uplink (UL) data samples via FFT to produce a received frequency domain IQ data signal associated with each of the signal ports. However, in alternative embodiments involving, for example, communication of aggregate signal port / user IQ data packets in the time domain, the FFT processing may be performed at the beamformer processor rather than at the transceiver IC itself (e.g., in conjunction with Fig. 12B explained in more detail).

[0061] With respect to embodiments associated with packet structure 302, the UL frequency-domain IQ data from each signal port may first be serially combined into a single packet in the format of packet 302, where the H and V portions represent the UL receive frequency-domain IQ information generated locally at the transceiver IC. However, as the receive IQ packet is transmitted along the transceiver IC subarray, the receive UL frequency-domain IQ packet received from another transceiver IC in the subarray on the serial data link may be combined with the locally generated receive IQ data before transmission to the next transceiver IC. Specifically, when transceiver IC 350 receives a UL IQ packet from transceiver IC 366 on link 362, the UL IQ packet processor 358 combines the received IQ data with its locally generated UL IQ data. As described more fully herein, the combination may involve sample-by-sample addition (i.e., for each subcarrier, an I data sample is added, and a Q sample is added), or the I data and Q data of one packet may have a phase rotation added prior to combination. In turn, the combined UL IQ data packets received on link 346 via the Serdes receiver 330 are further combined with locally generated UL IQ data from transceivers 321 and 335 stored in the UL signal port IQ data concatenator 336. In this manner, for embodiments associated with the packet data format 302, the amount of received data transmitted along the links 362, 346, 310 remains the same for each serial data link along the transceiver IC subarray.

[0062] Therefore, in another embodiment, a method includes: receiving modulated RF signals at multiple signal ports of each transceiver IC in a serially connected transceiver IC subarray; generating one or more frequency-domain digital data packets of subcarrier IQ data associated with each signal port by demodulating each modulated RF signal from each signal port using an FFT processor within the corresponding transceiver IC; forming multiple combined frequency-domain digital data packets from the transceiver IC using a set of serial data links between transceiver ICs in the serially connected transceiver IC subarray; and transmitting the multiple combined frequency-domain digital data packets from the transceiver IC subarray to a beamformer processor.

[0063] In addition, in some embodiments, each transceiver IC may be configured to process signals from two signal ports, such as signals from cross-polarized antenna elements, or sets of parallel elements. Other embodiments may use a transceiver IC with four separate signal ports. In each embodiment, a given signal port may receive multiple modulated carriers (each modulated carrier having a set of subcarriers), and the demodulated frequency domain data may be packetized according to the component carriers received therefrom. Thus, one or more frequency domain digital data packets of subcarrier IQ data associated with each signal port may be packetized together with header information identifying the signal port (such as a signal port id), the component carrier (such as a component carrier id), and additional identification information (e.g., a subcarrier subset id for multi-level beamforming). Each transceiver IC may participate in forming multiple combined frequency domain digital data packets by receiving frequency domain digital data packets of subcarrier IQ data from an adjacent transceiver IC via a serial data link and combining these frequency domain digital data packets with frequency domain digital data packets of subcarrier IQ data generated locally by itself. Depending on the location of a given transceiver IC within the transceiver IC sub-array, some transceiver ICs will actually receive partially formed combinations of frequency domain digital data packets.

[0064] For the embodiment associated with the packet structure 304 (note that the header is not shown for clarity), six separate signal port groups may be provided to the transceiver IC subarray from which six independent transmission signals may be generated. Generally speaking, the ability of the AAU system to generate independent RF transmission signals from the individual digital IQ data associated with each radiating element is referred to herein as full-dimensional beamforming. In this embodiment, representing the full-dimensional digitally beamformed signals, all six groups are received at the receive Serdes 314 at the transceiver IC 312 via link 308 and provided to the segmentation copy processor 318. The split copy processor 308 examines the packet headers and forwards a first set of two signal port packets (the rightmost H / V portions 324, 340 of the format 304) to the signal port split processor 320 for transmission processing of IQ data 324 by transceiver 321 (for port 328) and IQ data 340 by transceiver 335 (for port 344), and forwards the remaining four packets to the Serdes transmitter 332. The next transceiver IC 350 receives the four packets at its Serdes receiver over link 348, and the split copy processor 352 performs packet header analysis to forward the two signal port packets to its signal port split processor 354 within 350, and forwards the remaining two packets to the Serdes transmitter (TX#0 of transceiver IC 350) for transmission over link 364 to transceiver IC 366. The signal port splitting processor 354 provides the H and V signal port IQ data to its transceivers for transmission on signal ports 356, 360, respectively. The transceiver IC 366 receives and processes the remaining two IQ data packets in a similar manner for transmission on ports 370, 378. Note that for the DL IQ data packets, the amount of serial data is reduced along the transceiver IC subarray. In this embodiment, the receive processing does not involve any UL IQ packet data combination. Instead, the packets are only retransmitted from each transceiver IC (using UL IQ packet processor 358 and UL IQ packet processor 334 for concatenation / retransmission) so that all six receive UL signal port IQ packets are transmitted to the beamformer processor on link 310 (the packets may be formatted with separate headers, or may be transmitted as concatenated payloads with a single header). Note that the amount of data increases as packets from transceiver IC 366 on link 362 are concatenated with IQ data from transceiver IC 350 at UL IQ packet processor 358 for transmission on link 346. The amount of data increases again on link 310 when UL IQ data 340 and 324 from UL signal port IQ data concatenator 336 are concatenated by UL IQ packet processor 334.

[0065] In some embodiments, full dimensional beamforming groups unique to each signal port may be provided for smaller bandwidth signals such as 20 MHz data bandwidth. This may be desirable in certain deployments where the AAU panel is already configured with lower rate serial data connections in the transceiver IC subarray. Thus, even systems with lower speed serial data interconnects may support full control of the signal port signals (and corresponding radiating elements) by concatenating the individual IQ data of the interconnected transceiver ICs and extracting the relevant data set at each IC. This will allow support for MU-MIMO in the vertical plane with much higher accuracy, and support use cases associated with aerial drones (drones have data connectivity as users within the system, or by blocking interference from high altitude interfering drones).

[0066] In a third embodiment of the antenna array system, a multi-level beamforming signaling scheme may be used to provide data transmission and reception. In this embodiment, some transmission IQ data packets are processed jointly between multiple transceiver ICs to achieve a first level of beamforming resolution, while additional IQ data packet sets are allocated to each transceiver IC subarray, where each packet in a given set of additional transmission IQ data packets is processed between fewer (or even one) transceiver ICs in the transceiver IC subarray to obtain a second, higher resolution level of beamforming. Specifically, data format 306 provides a combination of beamforming resolutions, whereby two signal port IQ data packets (e.g., the first two H and V parts of 306, 326, 342) are processed by each of transceiver ICs 312, 350, and 366 for transmission in a manner similar to the signal processing described above with respect to packet format 302. Because the same IQ is transformed and transmitted by multiple corresponding radiating elements in a subarray, these IQ data packets (referred to herein as "commonly processed" IQ data) result in a first level of beamforming resolution, where beams are formed as a result of phase signal contributions emanating from other subarrays (i.e., inter-subarray beamforming). In addition, however, another set of six signal port IQ data packets (three additional H / V data sets of 306) are distributed across a given transceiver IC subarray in a manner similar to the signal processing described above with respect to the packet format 304 of all-digital beamforming data. These additional packets are dedicated to a given signal port and / or transceiver IC, and provide a unique IQ data stream for transmission by each individual signal port in a given transceiver IC subarray, thereby providing transmission and reception of a second level of beamforming resolution. Specifically, wherein beams are formed as a result of phase signal contributions from other transceiver ICs within a given subarray and phase signal contributions from other transceiver ICs within other transceiver IC subarrays (i.e., second level beamforming from both intra-subarray beamforming and inter-subarray beamforming).

[0067] have Figure 3 The packet of format 306 shown in FIG. 1 and as described below with respect to FIG. 12A to FIG. 12B , Fig.13A and Fig. 13B Multi-level beamforming, further described, utilizes processing of two separate signal port IQ packets, such as IQ data 326 and IQ data 327 (and similarly 342, 343), indicated as being combined for transmission on the same signal port. In one embodiment, the separately beamformed IQ packets may include IQ data points for different subcarriers within a set of subcarriers of a single component carrier. Thus, each transceiver IC may form its own unique combined set of IQ data points for its respective signal port prior to iFFT processing. Specifically, transceiver IC 312 combines IQ data 326 and 327 via tandem for transmission on signal port 328, while combining IQ data 342 with IQ data 343 for transmission on signal port 344. The next transceiver IC in the transceiver IC subarray, transceiver IC 350, combines IQ data 326 (same as processed by transceiver 321 of transceiver IC 312) with signal port IQ data 355, and combines IQ data 342 (same commonly processed IQ data processed by transceiver 335 of transceiver IC 312) with signal port IQ data 359. A similar unique serial combination is shown in transceiver IC 366, where IQ signal port data packets 326 and 342 are respectively combined with unique signal port IQ data 369, 377. Within the transceiver IC subarray, the commonly processed IQ packets 326 and 342 provide a first level beamforming component contributed by the subarray, while the additional set of IQ packets distributed within the transceiver IC subarray provide a second level beamforming component associated with the subarray.

[0068] In another embodiment, the individual IQ packets may have overlapping subcarriers, in which case the transceiver IC processing includes forming a weighted average of the overlapping subcarriers prior to iFFT processing. In such an embodiment, the beamformer processor may transmit one or more weights for the transceiver IC to use when forming a combination of IQ transmission data for the overlapping subcarriers.

[0069] Thus, in one embodiment, multi-level transmit beamforming includes: receiving a first level beamformed IQ packet and a plurality of second level beamformed packets at a plurality of transceiver ICs in a transceiver IC subarray via a serial data connection interconnecting the transceiver ICs; and at each transceiver IC: forming a multi-level beamformed packet by combining the first level beamformed IQ packet with at least one second level beamformed packet of the plurality of second level beamformed packets; generating a time domain signal from the multi-level beamformed packet; transmitting the multi-level beamformed signal by transmitting a corresponding amplified RF time domain signal from the transceiver IC in the transceiver IC subarray via a corresponding adjacent antenna element subarray.

[0070] In some embodiments, the first level beamformed IQ packet and each of the plurality of second level beamformed packets contain frequency domain IQ data. In other embodiments, the first level beamformed IQ packet and each of the plurality of second level beamformed packets contain time domain IQ data.

[0071] In some embodiments, multi-level beamformed packets are formed by combining the IQ samples of the individual subcarriers via concatenation, followed by processing the packet with the same iFFT operation. In other embodiments, multi-level beamformed packets are formed by combining overlapping subcarriers using weights provided via management plane messages, followed by processing with the same iFFT operation.

[0072] In yet another implementation, the IQ packets conveying data for the second level of beamforming may be associated with subcarriers of a separate component carrier. In such an implementation, the additional higher resolution beamforming data may be processed independently using a separate iFFT before combining the time domain signals of the two levels of beamforming signals. Thus, in one embodiment, multi-level transmit beamforming includes receiving a first level beamformed IQ packet and a plurality of second level beamformed packets at a plurality of transceiver ICs in a transceiver IC subarray via a serial data connection interconnecting the transceiver ICs; and at each transceiver IC: converting the first level (commonly processed) beamformed IQ packet into a time domain signal, and converting at least one of the plurality of second level beamformed IQ packets into a time domain signal individually via a separate iFFT; combining the two time domain signals to form a signal port specific multi-level beamformed time domain signal; transmitting the multi-level beamformed signal by transmitting an amplified RF time domain signal generated from the corresponding signal port specific multi-level beamformed time domain signal from the transceiver IC in the transceiver IC subarray via a corresponding adjacent antenna element subarray. The plurality of transceiver IC subarrays and their corresponding antenna element subarrays cooperatively generate the multi-level beamformed signal.

[0073] In multi-level beamforming using distribution of multi-level IQ packet data among each of a plurality of transceiver IC subarrays, a group of users may be served by aggregated IQ signal port packets that are replicated and forwarded for processing by each transceiver IC along a given transceiver IC subarray, thereby yielding a first level of beamforming resolution (as determined, for example, by the total number of unique independent signal port IQ packet streams sent to the total number of corresponding transceiver IC subarrays for processing by each transceiver IC). However, in addition, a separate group of users may be served by higher resolution beamforming by distributing additional signal port specific IQ data packets along the transceiver IC subarray for separate processing by each separate transceiver IC (i.e., non-commonly processed IQ data).

[0074] In many embodiments, note that the co-processed IQ packets for multi-level beamforming signal processing are unique to a particular transceiver IC subarray. However, in some cases, to achieve certain desired beam radiation patterns (i.e., those with an even lower degree of beamforming resolution), some co-processed IQ packets may be identical for two or more transceiver IC subarrays.

[0075] The receive UL signal processing for multi-level beamforming is also a hybrid of the above-described UL receive signal processing, where IQ data combining may be performed for a first pair of signal port IQ packets, and IQ data concatenation may be performed for additional sets of independent UL signal port IQ data packets. Thus, the first level of beamforming is performed by each transceiver IC participating in forming a UL combined frequency domain digital data packet by receiving frequency domain digital data packets of subcarrier IQ data from an adjacent transceiver IC via a serial data link and combining these frequency domain digital data packets with its own locally generated frequency domain digital data packets of subcarrier IQ data. The second level of beamformer processing involves transmitting the UL receive IQ packets along the transceiver IC subarray without combining, but rather via concatenation (sample-by-sample or packet-by-packet so as not to change the IQ samples).

[0076] In some embodiments of an array of NxM transceiver ICs configured as a set of N transceiver IC subarrays each having M serially connected transceiver ICs, multi-level beamforming can be characterized by: processing a first set of aggregated beamformed frequency-domain IQ user data according to a first level of beamforming resolution to generate N unique beamformed IQ data packets (or sets of packets, such as an IQ data set for each signal port (e.g., H and V) within the transceiver IC), each beamformed IQ data packet being used for distribution to a corresponding transceiver IC subarray among the N transceiver IC subarrays; while also processing a second set of beamformed aggregated frequency-domain IQ user data sets according to a second level of beamforming resolution to generate N different sets of M unique beamformed IQ data packets (or sets of packets for each set of signal ports of the transceiver IC), and wherein each of the N sets of M packets is distributed to a corresponding transceiver IC subarray among the N transceiver IC subarrays. Each of the various packets is sent to the N transceiver IC subarrays over a respective serial data link. Each transceiver in a given subarray will collectively process packets associated with first level beamforming data in conjunction with only a portion of the individually beamformed second level beamforming packets.

[0077] refer to Fig.16, shows an embodiment of dual level beamforming whereby the panel may be configured to process UL and DL data according to a first level of beamforming using subarray level beamforming (as shown in configuration 1604) utilizing three dual polarization elements per subarray 1606 and provide beams (e.g., 1612) within a scan range 1614. In the illustrated embodiment, the subarray level beamformer generates beamformed IQ packets for frequency content 1618, which are processed jointly within each respective subarray as described with respect to IQ data 326 and 342. The same panel may simultaneously be configured (as shown in configuration 1600) to provide another or second level of beamforming with higher phase resolution, having a unique beamformed IQ data set for producing a unique signal at each cross-polarization element 1602. In the embodiment shown, the subarray level beamformer generates beamformed IQ packets for frequency content 1618, which are processed jointly within each respective subarray as described with respect to IQ data 326 and 342. Fig.16 In an embodiment of the present invention, frequency content 1616 may be allocated to high-resolution beamforming levels, such as data 327, 343, 355, 359, 369, and 377. The frequency content of frequency range 1616 and frequency range 1618 may correspond to different subcarriers within a single component carrier, or may be separate component carriers, etc., as described herein.

[0078] Note that in the second level of beamforming, due to the higher phase resolution, the individual beams (e.g., 1608) can be steered across a wider scan range 1610. In contrast, the scan angle in subarray beamforming (where multiple signal ports transmit and receive signals processed according to a common IQ beamforming grouping) has a limited scan range due to the increased quantization error in the beamforming weights, as shown in FIG. Fig.17. Specifically, the scan angles of two representative beams represented by the diagonal lines labeled "desired BF weights" depict two separate beams with different scan angles. In full-dimensional beamforming, IQ data for each signal port is formed using desired weights with phases as indicated, including, for example, points 1702, 1710, and 1706 for lower scan angles and example points 1712, 1720, and 1716 for steeper scan angles (as shown by dashed lines). However, in subarray beamforming, the jointly processed beamformed IQ data may be generated using the average phase of the desired beams across the elements in a given subarray, which is shown by the example phases 1704, 1710, 1708 of one beam and the phases 1714, 1718, 1720 of the steeper beam. The corresponding beamforming weight phase error is shown with the line labeled "BF weight error". Note that steeper scan angles have higher beamformer weight errors. Thus, the second level of beamforming allows for larger scan angles because there are no quantization errors, and the subarray beamforming has a reduced scan range. Note that for a two-element subarray, the beamforming weights used to form the individual beams can be an average between two desired phase values, or a value between two desired weight phases. Finer phase control avoids what is sometimes referred to as "quantization lobes," which result from the applied weights being constrained to be the same for several adjacent elements in the subarray. Quantization lobes increase with increasing scan angle.

[0079] In short, full-dimensional beamforming is done with a higher level of precision in the beamformer weights, whereas subarray beamforming is performed with an average of the desired weights, thereby introducing errors. Therefore, an element with full-dimensional control configured according to configuration 1600 has a larger scan range than a subarray beamforming configuration 1604 that beamforms using an average bf weight for each given beam (such as a UE-specific beam, or a spatial multiplexing layer beam, etc.).

[0080] The multi-level beamforming described herein can be used to provide high quality service to a group of users (such as those located in a high-rise building within a cell sector) without sacrificing coverage of other user devices located on the ground (e.g., by limiting the allocated bandwidth). Similarly, the system enables support for communications with drones and other high-altitude devices in conjunction with ground-based user devices. The system described herein is configured to provide these alternative beamforming transmissions between user devices within a single radio unit.

[0081] A multi-mode beamforming system may be configured to sequentially or dynamically allocate OFDM transmissions on a slot-by-slot basis according to two or more levels of beamforming resolution. Specifically, a first time transmission time interval (TTI) or even a first OFDM symbol slot may be allocated to a user device that is beamformed according to a first level of subarray-level beamforming such that during transmit signal processing, transmit IQ data packets sent to each transceiver IC subarray are processed jointly by each transceiver IC within each such subarray. Similarly, during signal reception, the processed IQ data packets for each transceiver IC are combined as they are transmitted from transceiver IC to transceiver IC along the serially connected transceiver ICs in each subarray. In a second or subsequent time slot, frequency resource blocks may be allocated to the user equipment for higher resolution beamforming, including fully steered beamforming IQ data according to a second level of higher phase resolution beamforming, wherein separate transmit IQ packets are separately formed for serial data transmission and sent to each transceiver IC subarray for separate processing by specifically addressed transceiver ICs within each such subarray.

[0082] In some embodiments, the transmission bandwidth associated with a fully controlled digital beamforming IQ data packet (i.e., the number of IQ sample pairs corresponding to the number of modulated subcarriers) may be less than the bandwidth utilized by the jointly processed IQ data packets, such as a comparison between the jointly processed packet data 302 and the fully digital beamforming packet data 304. In some embodiments, a method of multi-level beamforming includes: receiving a first level beamforming frequency domain IQ data packet and a plurality of second level beamforming frequency domain IQ data packets at a transceiver IC subarray having a plurality of interconnected transceiver ICs (ICs), the transceiver ICs being interconnected via a plurality of serial data connections; at each transceiver IC of the transceiver IC subarray: forming a multi-level beamforming frequency domain IQ data set by combining beamformed frequency domain IQ data from the first level beamforming frequency domain IQ data packet with beamformed frequency domain IQ data from a selected second level beamforming frequency domain IQ data packet from the plurality of second level beamforming frequency domain IQ data packets; generating a discrete time domain signal from the multi-level beamforming frequency domain IQ data set using a digital signal processor (DSP) within the transceiver IC; generating a modulated radio frequency (RF) signal from the discrete time domain signal; and transmitting the multi-level beamformed signal by transmitting a corresponding modulated RF signal from the transceiver IC in the transceiver IC subarray via a corresponding adjacent antenna element subarray. Transmitting the multi-level beamformed signals may be performed by transmitting respective modulated RF signals from transceiver ICs in a plurality of transceiver IC subarrays via a corresponding plurality of adjacent antenna element subarrays.

[0083] In some embodiments, the method includes receiving a first level beamformed frequency domain IQ data packet and a plurality of second level beamformed frequency domain IQ data packets at a transceiver integrated circuit (IC) subarray, wherein receiving further includes: forwarding the first level beamformed frequency domain IQ data packets from a first transceiver IC of the transceiver IC subarray to an additional transceiver IC of the transceiver IC subarray for common processing; and forwarding only a subset of the second level beamformed frequency domain IQ data packets of the plurality of second level beamformed frequency domain IQ data packets from the first transceiver IC to the additional transceiver IC. In some embodiments, the subset of the second level beamformed frequency domain IQ data packets is identified according to a packet header. Some methods combine the beamformed frequency domain IQ data from a first level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from a selected second level beamforming frequency domain IQ data group from a second level beamforming frequency domain IQ data group by concatenating the beamformed frequency domain IQ data from the first level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from a selected second level beamforming frequency domain IQ data group from the second level beamforming frequency domain IQ data group before frequency domain to time domain conversion. In some examples, combining the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets with the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets is performed by forming a weighted sum of the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets and the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets before frequency domain to time domain conversion. The weighted sum may be calculated based on beamforming weights received from the beamformer.

[0084] In other embodiments, combining the beamformed frequency domain IQ data from the first-level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from the selected second-level beamforming frequency domain IQ data group from the second-level beamforming frequency domain IQ data group is accomplished in the time domain by: converting the beamformed frequency domain IQ data from the first-level beamforming frequency domain IQ data group into a first-level beamforming time domain signal; converting the beamformed frequency domain IQ data from the selected second-level beamforming frequency domain IQ data group from the second-level beamforming frequency domain IQ data group into a second-level beamforming time domain signal; and adding the first-level beamforming time domain signal to the second-level beamforming time domain signal.

[0085] The first level beamformed frequency domain IQ data packets and the selected second level beamformed frequency domain IQ data packets of the second level beamformed frequency domain IQ data packets may be associated with different component carriers. The method may involve queuing the data packets according to the location of the expected transceiver ICs so that the second level beamformed frequency domain IQ data packets are received for processing by the transceiver IC at the end of the transceiver IC subarray before the second level beamformed frequency domain IQ data packets are received for processing by the transceiver IC at the beginning of the transceiver IC subarray.

[0086] In some alternative embodiments, as noted above, a method of multi-level (transmit) beamforming may include receiving a first level beamformed time-domain IQ data packet and a plurality of second level beamformed time-domain IQ data packets at a transceiver integrated circuit (IC) subarray, wherein receiving further comprises: forwarding the first level beamformed time-domain IQ data packet from a first transceiver IC of the transceiver IC subarray to an additional transceiver IC of the transceiver IC subarray for common processing; and forwarding only a subset of the second level beamformed time-domain IQ data packets of the plurality of second level beamformed time-domain IQ data packets from the first transceiver IC to the additional transceiver IC. In some embodiments, the subset of the second level beamformed time-domain IQ data packets is identified according to a packet header. Some alternative methods may combine the beamformed time domain IQ data from the first level beamformed time domain IQ data group with the beamformed time domain IQ data of the selected second level beamformed time domain IQ data group from the second level beamformed time domain IQ data group directly in the time domain, for example by adding the beamformed time domain IQ data from the first level beamformed time domain IQ data group together with the beamformed time domain IQ data of the selected second level beamformed time domain IQ data group from the second level beamformed time domain IQ data group.

[0087] Some example embodiments of an apparatus include: a beamformer processor configured to generate a frequency-domain IQ data packet for a first level of beamforming and a plurality of frequency-domain IQ data packets for a second level of beamforming; a transceiver integrated circuit (IC) subarray connected to the beamformer processor and having a plurality of interconnected transceiver ICs interconnected via a plurality of serial data connections; each transceiver IC of the transceiver IC subarray including: a digital signal processor (DSP) configured to form a frequency-domain IQ data set for multi-level beamforming and to generate a discrete time-domain signal from the frequency-domain IQ data set for multi-level beamforming; an RF modulator configured to generate a modulated RF signal from the discrete time-domain signal; and an antenna element subarray connected to the transceiver IC subarray and configured to transmit the multi-level beamformed signal by transmitting a corresponding modulated RF signal from a transceiver IC in the transceiver IC subarray. The transceiver IC subarray may include a first transceiver IC having a packet header processor configured to forward first level beamformed frequency domain IQ data packets from the first transceiver IC to an additional transceiver IC in the transceiver IC subarray for common processing and configured to forward only a subset of second level beamformed frequency domain IQ data packets from the first transceiver IC to the additional transceiver IC. The packet header processor may be configured to identify the subset of second level beamformed frequency domain IQ data packets based on a packet header.

[0088] The DSP may be configured to combine the beamformed frequency domain IQ data from the first level beamforming frequency domain IQ data group with the beamformed frequency domain IQ data from the selected second level beamforming frequency domain IQ data group from the second level beamforming frequency domain IQ data group before frequency domain to time domain conversion. The DSP may be configured to combine the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets with the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets by forming a weighted sum of the beamformed frequency domain IQ data from the first level beamformed frequency domain IQ data packets and the beamformed frequency domain IQ data from the selected second level beamformed frequency domain IQ data packets from the second level beamformed frequency domain IQ data packets before frequency domain to time domain conversion. The DSP may be configured to calculate the weighted sum based on the beamforming weights received from the beamformer processor.

[0089] In some embodiments, the DSP is configured to: convert beamformed frequency domain IQ data from a frequency domain IQ data group of a first level beamforming into a time domain signal of the first level beamforming; convert beamformed frequency domain IQ data of a selected second level beamforming frequency domain IQ data group from a frequency domain IQ data group of a second level beamforming into a time domain signal of the second level beamforming; and add the time domain signal of the first level beamforming to the time domain signal of the second level beamforming.

[0090] The apparatus may include a packet header processor configured to identify a separate component carrier associated with a selected second-level beamformed frequency-domain IQ data packet of the first-level beamformed frequency-domain IQ data packet and a second-level beamformed frequency-domain IQ data packet. The beamformer processor may be configured to transmit the second-level beamformed frequency-domain IQ data packet for processing by a transceiver IC at an end of the transceiver IC subarray before transmitting the second-level beamformed frequency-domain IQ data packet for processing by a transceiver IC at a beginning of the transceiver IC subarray. The apparatus may also include a plurality of transceiver IC subarrays and a corresponding plurality of adjacent antenna element subarrays configured to transmit multi-level beamformed signals.

[0091] Some alternative embodiments of an apparatus include: a beamformer processor configured to generate a first level beamformed time domain IQ data packet and a plurality of second level beamformed time domain IQ data packets; a transceiver integrated circuit (IC) subarray connected to the beamformer processor and having a plurality of interconnected transceiver ICs interconnected via a plurality of serial data connections; each transceiver IC of the transceiver IC subarray including: a digital front end signal processing circuit configured to form a multi-level beamformed time domain IQ data set, and to generate a discrete time domain signal from the separated first level beamformed time domain IQ data set and the second level beamformed time domain IQ data set. The first level time domain IQ data and the second level time domain IQ data may have different sampling rates, and the digital front end circuit may interpolate each of the first level time domain IQ data and the second level time domain IQ data to a common sampling rate before additively combining the discrete time signals. Some embodiments include a radio frequency modulator configured to generate a modulated radio frequency (RF) signal from the discrete time domain signal; and an antenna element subarray connected to the transceiver IC subarray and configured to transmit multiple levels of beamformed signals by transmitting corresponding modulated RF signals from transceiver ICs in the transceiver IC subarray. The transceiver IC subarray may include a first transceiver IC having a packet header processor configured to forward a first level of beamformed time domain IQ data packet from the first transceiver IC to an additional transceiver IC in the transceiver IC subarray for common processing and to forward only a subset of a second level of beamformed time domain IQ data packet from the first transceiver IC to the additional transceiver IC. The packet header processor may be configured to identify the subset of the second level of beamformed time domain IQ data packet based on a packet header.

[0092] Some embodiments may utilize full-dimensional beamforming data streams in a serially connected transceiver array. In these embodiments, each signal port has a unique signal for fully controlling the beamforming phase. Therefore, unique packets are sent to each transceiver IC subarray, and these unique packets (by a combination of one or more field IDs, or a combination of ID sets) are addressed to each transceiver in the subarray. The packets can be time-ordered to account for latency, so that the IQ packets addressed to the transceiver IC at the end of the serially linked transceiver IC chain are sent first so that they are received at the end of the array. Therefore, the packets can be ordered in a round-robin manner, where the first packet is sent to each transceiver IC so that processing can start at each IC, and then additional packets are sent to each transceiver IC.

[0093] Each transceiver has a serial link and a packet header analyzer circuit for performing header checks, where each stream to each subarray includes a separate data packet with unique digital beamforming data addressed to a separate transceiver within the set of serially connected transceivers. The packet header analyzer within each transceiver Serdes can make per-packet forwarding decisions. In one configuration, packet bandwidth is equally allocated between the two signal paths of each transceiver IC, such as packets for two signal ports (H and V).

[0094] When receiving signals in serially linked transceiver ICs in a subarray, the serial data rate between ICs is limited, and therefore subarray beamforming may include receiving IQ data combinations before transmission back to the beamformer. In some embodiments, combining weights are provided to the transceivers in a given subarray so that these combining weights will adjust the phase as part of receive combining. Electronic tilting is one such case.

[0095] Figure 4 is an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology from the DL / UL beamformer 400 to corresponding serially connected groups of transceiver ICs (e.g., one such transceiver IC subarray is a set of transceiver ICs connected via serial links 418 and 420). In this embodiment, the beamformer 400 has a high rate serial data connection (e.g., 402) to an intermediate SerdesMUX device 404 (as well as connections to 422, 424, 426), each of which then provides a separate serial data connection (e.g., link set 406). The separate serial connections from each Serdes MUX can utilize a lower data rate for connection to a corresponding subset of the transceiver IC subarrays 421a, 421b, 421c, 421d. In Figure 4 In an embodiment of the present invention, the subset of transceiver IC subarrays 421a includes eight transceiver IC subarrays, each of which has three transceiver ICs connected to corresponding antenna elements. Note that for clarity, the remaining set of transceiver IC subarrays 421b, 421c, 421d are depicted in a simplified manner (including connectivity to a simplified set of antenna element subarrays).

[0096] Figure 4 The transceiver IC subarray is also configured in a time division duplex (TDD) configuration with a SPDT (single pole double throw) switch 412. The received signal may be filtered via filter 410 and amplified with a low noise amplifier (LNA) 408. Signal couplers (e.g., 414, 416) are also depicted, which provide a signal copy of the transmitted RF signal (typically at a much lower power) to a monitoring or observation transceiver 428 via a calibration port 430.

[0097] Figure 5 Embodiments of a synchronization and clock distribution circuit 500 for use with transceiver ICs distributed across an active antenna array assembly are depicted. More specifically, some embodiments include a method comprising: receiving a clock signal and at least one synchronization pulse signal at each transceiver IC in a plurality of transceiver IC subarrays, wherein each transceiver IC subarray comprises a corresponding set of serially connected transceiver ICs. The method further comprises, at each transceiver IC: (i) synchronizing the transceiver IC with other transceiver ICs in the corresponding set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state based on the received at least one synchronization pulse signal; (ii) generating a carrier frequency signal using a phase-locked loop (PLL) circuit including the DSM circuit; and (iii) processing frequency domain in-phase and quadrature (IQ) data using the generated carrier frequency signal.

[0098] In addition, some embodiments include an apparatus comprising: a plurality of transceiver IC subarrays, wherein each transceiver IC subarray includes a respective set of serially connected transceiver ICs; a beamformer processor coupled to the plurality of transceiver IC subarrays, wherein the beamformer processor is configured to generate at least one synchronization pulse signal and provide the at least one synchronization pulse signal to each transceiver IC; and a plurality of clock buffer circuits coupled to the beamformer processor via a clock distribution circuit, wherein the plurality of clock buffer circuits are configured to output a plurality of clock signals. , and providing a corresponding clock signal to each transceiver IC, and wherein each transceiver IC is configured to: (i) receive the corresponding clock signal and the at least one synchronization pulse signal; (ii) synchronize the transceiver IC with other transceiver ICs in a corresponding set of serially connected transceiver ICs by resetting the delta-sigma modulator (DSM) circuit to a predetermined state according to the received at least one synchronization pulse signal; (ii) generate a carrier frequency signal using a phase-locked loop (PLL) circuit including the delta-sigma modulator (DSM) circuit; and (iv) process frequency domain IQ data using the generated carrier frequency signal.

[0099] Return to reference Figure 5Within the beamformer processor circuit 502, clock signals may be generated from a clock and data recovery (CDR) circuit 508 using a data interface circuit 506, which may then be provided to a dual PLL clock circuit 512, which provides clock signals 522, 524 for use by the beamformer processor 502, which in turn may generate another clock signal on line 526. The clock signals may be transmitted to the transceiver IC (e.g., Figure 5 540) is provided by a clock buffer 536 that receives input from a clock distribution circuit 534 driven by PLL2 532, PLL1 530 in conjunction with a system reference clock based on a selection from MUX 528. Thus, in some embodiments, the clock distribution circuit 534 is driven by the clock signal (on line 526) from the beamformer processor 502 and the system reference clock.

[0100] In some embodiments, the distributed clock signal is a high frequency signal with a frequency range of 50MHz to 150MHz. In addition, in some embodiments, the clock buffer clock circuit 536 is configured to adjust the clock signal timing at the output of each clock buffer circuit so that the corresponding clock signal is received by each transceiver IC at substantially the same time. For example, in an exemplary embodiment, the clock buffer circuit 536 can be programmed and can be configured to adjust the clock signal timing at each output to consider the signal transmission delay associated with the clock signal path so that the clock signal (specifically, the rising edge and / or falling edge transition of the clock signal) arrives at each transceiver IC with a low relative skew. In this regard, low skew means arriving at substantially the same time so that the arrival time is distributed in a range of less than one nanosecond or two nanoseconds from each other. In some embodiments, low skew refers to less than 333 picoseconds (1 / 3 nanosecond). In this regard, the clock buffer 536 can be adjusted according to the calibration process.

[0101] In some embodiments, in addition to receiving substantially synchronized clock signals, transceiver ICs (e.g., transceiver IC 540) are also synchronized with respect to each other at a macro timing level for one or more purposes via the addition of at least one synchronization pulse signal. Specifically, the transceiver ICs (which may be interconnected in a transceiver IC subarray via an asynchronous serial data bus and also directly or indirectly interconnected with the beamformer processor 502, as described herein) have one or more subsystems that may benefit from further synchronization. In some embodiments, such as Figure 5 As shown in , such a synchronization pulse signal (denoted as a "SYNC" pulse signal) is generated by the beamformer processor 502 and provided to each transceiver IC for further synchronization.

[0102] In some embodiments, such as Figure 5 , the synchronization pulse signals ("SYNC" pulses) generated by the beamformer processor 502 may be processed by an additional buffer tree network 527 so that the corresponding synchronization pulse signals are received by each transceiver IC at substantially the same time in a manner similar to a clock signal. More specifically, in some embodiments, multiple transceiver ICs organized into transceiver IC subarrays may be distributed in different locations across the antenna panel. Similar to the clock distribution described above, the corresponding synchronization pulse signals may have different signal transmission delays associated with different physical signal paths to the various transceiver ICs, which may be dispersed on the antenna panel. For example, depending on the physical location of a given transceiver IC on the panel, a longer signal path of a SYNC pulse may suffer greater signal degradation than a shorter signal path.

[0103] In some embodiments, the buffer tree network 527 can be configured to distribute the synchronization pulse signal in a tree-like manner by branching the SYNC pulses to different panel areas in a synchronous manner. For example, in such a network, the main buffer circuit can provide a given number of outputs that drive a corresponding number of at least auxiliary buffer circuits distributed on different areas of the panel and provide synchronization pulse signals to the transceiver ICs located in those corresponding areas. In some embodiments, the timing of the output signal from the main buffer circuit can be adjusted (e.g., delayed) accordingly, so that the distributed auxiliary buffers receive the synchronization pulse signal substantially simultaneously. Subsequently, the auxiliary buffer circuits can each provide multiple separate outputs to drive the corresponding number of transceiver ICs in the corresponding areas of the panel, and the output signal timing (e.g., signal delay) can be adjusted so that the corresponding synchronization pulse signal is received by each transceiver IC at substantially the same time / simultaneously.

[0104] In an exemplary embodiment, the buffer tree network 527 may be implemented by a signal distribution chip / IC that may be programmable through a suitable calibration process to adjust the timing of the synchronization pulse signal so that the SYNC pulses actually arrive at each transceiver IC substantially simultaneously. In this regard, such a distribution chip may be configured, for example, to selectively delay the buffered signal output to accommodate signal transmission delays associated with different signal paths of the SYNC pulses.

[0105] In one aspect, each of the transceiver ICs physically distributed on the antenna array assembly is configured to independently process a low-skew distributed (e.g., high frequency) clock signal and responsively generate a carrier frequency signal for processing transmit and receive modulated RF signals. Thus, a voltage-controlled oscillator (VCO) of each transceiver IC for generating a carrier phase to modulate a transmit signal and mixing / down-converting a received RF signal is closely aligned across the transceiver IC subarrays distributed on the antenna array assembly.

[0106] In some embodiments, the transceiver IC VCO employed herein uses a VCO adjustment loop that includes a phase-locked loop (PLL) circuit having a delta-sigma modulator (DSM) 544, a multi-mode divider (MMD) 546, a phase / frequency detector (PFD) 548, a loop filter 550, a VCO 552, and a divider 554. The fractional divider in the VCO adjustment loop is used to adjust the division modulus (i.e., the division ratio) used by the MMD 546. The MMD 546 utilizes a divisor value sequence obtained from the DSM 544.

[0107] In this regard, as noted above, some embodiments described herein include a method comprising (among other things): synchronizing a transceiver IC with other transceiver ICs in a corresponding set of serially connected transceiver ICs (in a corresponding transceiver subarray) by resetting the DSM circuit to a predetermined state based on at least one received synchronization pulse signal; and generating a carrier frequency signal using a PLL circuit that includes the DSM circuit.

[0108] Additionally, in one embodiment, in order to generate a carrier frequency signal using a PLL circuit (which includes a DSM circuit), each transceiver IC is configured to (i) use the DSM circuit to set the frequency division ratio of the MMD, and (ii) provide the frequency division signal from the MMD to the PFD for comparison with the clock signal to further adjust the frequency division ratio of the MMD. In another embodiment, the DSM circuit includes a plurality of accumulators, and wherein in order to reset the DSM circuit to a predetermined state according to at least one received synchronization pulse signal, each transceiver IC is further configured to set the plurality of accumulators of the DSM circuit according to at least one received synchronization pulse signal.

[0109] In general, various embodiments described herein utilize DSM circuits (such as DSM 544) to increase the frequency resolution of the carrier frequency signal generated by each transceiver IC for processing the transmission and reception modulated RF signals. In this regard, in some embodiments, the DSM circuit is configured to use a time-varying sequence representing a fractional input portion in conjunction with a fixed integer input portion to obtain a relatively high resolution carrier frequency. In one example, when the DSM circuit is used in a PLL circuit, the VCO frequency resolution can be as fine as .114 Hz. The DSM circuit operation is described in more detail below.

[0110] like Figure 5 As depicted, the DSM 544 may include a fractional input (FRAC IP) block 572, a DSM accumulator (DSMACC) 574, a fractional output (FRAC OP) block 576, and a summing circuit 578. In operation, the FRACP IP receives an input 570 including a digital fractional input value and generates a corresponding fractional input portion, which is input into the DSMMACC 574. As further shown, the DSM accumulator 574 and the FRAC OP 576 form a loop. Generally speaking, in this loop, the fractional input portion passed to the DSM accumulator 574 at the current time is also referenced from the FRAC OP 576 back to the DSM accumulator. Here, the current fractional output is subtracted from the current fractional input portion value stored in the accumulator 574. Although not shown in FIG. Figure 5 Although not explicitly shown in the exemplary embodiment, DSMACC 574 includes multiple accumulators, each of which can (i) receive a previously stored version of its accumulated output, (ii) use feedback from FRAC OP 576 to subtract the current fractional output, and (iii) pass the result to a subsequent accumulator.

[0111] As a result of the above operations, the total fractional output produced by FRAC OP 576 is provided to summing circuit 578. Then, summing circuit 578 sums (adds) the fractional output portion with the actual integer input portion 580 to generate a desired divisor value, which is provided as an input to MMD 546. In some embodiments, the output of DSM 544 is in the form of a divisor control word (e.g., a set of data bits) that configures what divisor MMD 546 uses. Due to the time-varying nature of the fractional input portion, the control word will also vary over time. However, for a given operating interval, on average, a desired ratio can be achieved.

[0112] As noted above, in one embodiment, transceiver IC 540 is synchronized with other transceiver ICs in its corresponding transceiver IC subarray by resetting a DSM circuit (such as DSM 544) to a predetermined state in response to at least one received synchronization pulse signal. Figure 5 As further shown in the example of , the transceiver 540 is configured to receive such a synchronization pulse signal (here, the "SYNC" pulse signal from the beamformer processor 502), wherein the synchronization pulse signal is provided to the DSMACC 574 so as to set multiple accumulators of the DSMACC 574 according to the synchronization pulse signal.

[0113] In some embodiments, the reset provided by the sync pulse signal is a one-time event performed, for example, during startup.Thereafter, transceiver IC synchronization can be automatically obtained due to the global shared high-speed clock distributed to each transceiver IC (as described above).

[0114] During normal operation, MMD 546 will utilize the divisor ratio sequence obtained from DSM 544. In this way, the divisor sequence used to divide the VCO frequency from VCO 552 (or the divided signal provided by a divider such as divider 554) will be the same across all transceiver ICs. Therefore, in some embodiments, MMD 546 is configured to utilize the divisor ratio sequence provided by DSM 544, where the divisor sequence is synchronized across all transceiver ICs according to the synchronization pulse signal.

[0115] like Figure 5 As further shown, the divided frequency signal from the MMD 546 is provided to a PFD 548 for comparison with the high frequency distributed clock signal from the clock buffer 536. The PFD 548 generates a phase error signal, which is then filtered by a loop filter 550 having a transfer function H(z). The filtered phase error signal is then provided to a VCO 552 to correct the phase error. Synchronization of the VCO phase error measurement circuitry (such as the DSM 544 divisor sequence) across the transceiver ICs reduces jitter in the carrier frequency used for transmit and receive signal processing between the transceiver ICs.

[0116] In addition, if Figure 5As shown, the output carrier frequency signal of the frequency divider 554 may be provided to a digital delay line (DDL) 556. In some embodiments, the DDL 556 is configured to generate a carrier frequency signal having multiple phases at an output 558. For example, in one embodiment, the multiple phases may include at least four phases of 0 degrees, 45 degrees, 90 degrees, and 135 degrees, wherein the carrier frequency is in the range of 3.6 GHz to 4 GHz. As will be described in further detail below, the generated carrier phases (and, for example, their inversion) may be used by a multi-phase digital power amplifier for RF modulation. More specifically, in some embodiments, a multi-phase DPA may be used to modulate a discrete time domain signal representing DL (downlink) frequency domain IQ data onto a generated carrier frequency signal, wherein the multi-phase DPA uses the selected phase of the generated carrier frequency signal for RF modulation. The phase may be selected based on the discrete time domain signal.

[0117] On the other hand, the transmit and receive signal processing circuits within the transceiver IC may use a numerically controlled oscillator (NCO), such as Figure 5 The NCO 542 shown in FIG. 5 is used to provide frequency shifting (conversion) via time domain complex multiplication, as described herein with respect to FIG. Fig.13A , Fig. 13B As described.

[0118] The NCO may also utilize components that may benefit from synchronization of the SYNC pulse signal. In some embodiments, the NCO utilizes a phase accumulator that is incremented by a frequency control word (FCW) at each clock interval. If the individual NCOs in different transceiver ICs have different phase accumulator values, this may introduce phase offsets in the transmit and receive signal processing. Synchronization of the NCO phase accumulator circuits across transceiver ICs reduces phase offsets in the transmit and receive signal processing between transceiver ICs.

[0119] Return to reference Figure 5 In the example of FIG. 5 , NCO 542 includes FCW register 562, phase accumulator (PACC) 564, and phase-amplitude converter (PAC) 566. Figure 5As shown, the FCW register 562 can receive the FCW input 560 (e.g., from a DSP, etc.) and responsively generate a FCW to be loaded into the PACC 564 at each clock interval. Generally speaking, the FCW is a series of data bits and represents a phase increment value. In some embodiments, the FCW register 562 will be configured to use the FCW to generate a corresponding phase increment (e.g., via a lookup table, etc.). In some embodiments, the PACC 564 is configured to add the corresponding phase increment to its internal memory register. In this way, the phase value accumulated by the PACC 564 through the step-like phase increment is a binary representation of an angle that starts at 0 degrees, ramps up to 360 degrees, wraps around to 0 degrees again and restarts at the next cycle (clock interval). The output phase value of the PACC 564 is then passed to the PAC 566 for conversion to a complex sine to be output by the NCO 542. PAC 566 is configured to convert the accumulated phase value from PACC 564 into a dual output of a sine and cosine function corresponding to the angle of the phase value, representing the real and imaginary components that form a complex sinusoid at NCO output 568 .

[0120] Additionally, in some embodiments, the NCO 542 receives a synchronization pulse signal to reset the NCO 542 based on the synchronization pulse signal. This can synchronize the NCO phase accumulator circuit across the transceiver IC, as noted above. More specifically, in some embodiments, the phase accumulator of the NCO is reset based on the received synchronization pulse signal. Figure 5 As shown in the example of , the SYNC pulse signal is provided to the PACC 564 of the NCO 542 to reset the PACC 564. With this phase accumulation reset in each transceiver IC, all transceiver ICs distributed across the active antenna array assembly can begin phase value accumulation at 0 degrees.

[0121] Note (as described in conjunction with the operation of the DSM circuit), some embodiments provide a sync pulse signal reset as a one-time event performed, for example, at some time during startup. Thereafter, transceiver IC synchronization may be automatically achieved due to the global shared high-speed clock distributed to each transceiver IC (as described above).

[0122] In addition, the synchronized NCO 542 may be used to provide frequency shifting (conversion) via time domain complex multiplication, as described herein in conjunction with Fig.13A , Fig. 13B For example, the transmission side signal processing ( Fig.13A ), the NCO 542 may be configured to multiply the time domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range (such as a separate frequency range that does not overlap with other component carriers). Fig. 13B), the signal received by the transceiver IC 540 may be shifted to a desired baseband signal via complex multiplication by the NCO 542.

[0123] Additionally, in some embodiments, a synchronized NCO 542 may be used to operate on frequency domain data to provide incremental phase rotation to subcarrier specific frequency domain IQ data for electronic beam tilt, as described herein. Of course, multiple instances of NCO 542 may be used for various signal processing functions as described herein.

[0124] like Figure 6 As depicted in the various embodiments illustrated in , clock distribution is configured according to signal lines routed across panel 102 to provide clock signals to transceiver IC subarrays to reduce clock skew. As noted above, in some embodiments, multiple clock buffer circuits (e.g., 536) may be configured to adjust the timing of the clock signals at the output of each clock buffer circuit so that the corresponding clock signals are received by each transceiver IC at substantially the same time. In some other embodiments, multiple transceiver IC subarrays, beamformer processors (e.g., 502), and multiple clock buffer circuits are all physically co-located within the antenna array assembly, and each clock buffer circuit is physically distributed across the antenna array assembly in a physical location corresponding to the physical location of one or more transceiver IC subarrays.

[0125] For purposes of illustration, in one embodiment, the clock signal distribution has a tree-like structure that symmetrically provides clock signals to each transceiver IC subarray, such as subarray 600 (which may be one or more transceiver IC subarrays). Specifically, in the illustrated embodiment, a given branch clock signal from clock buffer 610 is transmitted to clock signal conductor 606, which is split to provide clock signals on lines 602, 608, which drive another set of clock buffers (e.g., buffer 604 driven by line 602) and are then provided to the transceiver IC subarray (e.g., 600). In one embodiment, the four clock buffers of level 610 may be provided by the clock distribution circuit 534. In addition, each clock buffer 536 is physically distributed across the antenna array assembly to serve transceiver IC subarrays that are also physically distributed across the antenna array assembly. In the illustrated embodiment, each clock buffer may provide eight separate clock outputs to eight separate transceiver ICs. Figure 6 In the embodiment of FIG. 6 , one clock buffer circuit is depicted as clock buffers 603, 604, which provide clock signals to four transceiver ICs within block 600 and four transceiver ICs below the block, as shown.

[0126] Figure 77 is a block diagram of a system 700 of a distribution unit (DU) 702 having a baseband transmission unit 706, a pre-coding unit 710 (receiving a scheduler input 708), a channel estimation unit 714, and a baseband reception unit 716. The DU 702 includes an ORAN interface 712 for connecting to a radio unit (RU) 704 via a fronthaul data interface that carries control information (C-plane 718), management information (M-plane 720), and user data (U-plane 722). A hierarchical beamformer architecture 722 within the radio unit 704 is also depicted. The hierarchical beamformer 722 includes a main (primary) beamformer processor 724 (or simply "main beamformer 724") and auxiliary beamformer processors BF#1 (728), BF#2 (734), BF#3 (736), and BF#4 (738) (or simply "second-level beamformers"), which are connected via serial data links (e.g., link 726 from the main beamformer 724 to BF#1). In one embodiment of the hierarchical beamformer architecture 722, the main beamformer 724 calculates the complete beamforming matrix (e.g., about Figures 8 to 10 ) and allocates portions of the beamforming matrix to second level beamformers (e.g., BF#1 to 4).

[0127] In addition, the main beamformer 724 also communicates the associated user data layer to each second-level beamformer. As noted above, the beamforming processor within the radio unit may be configured to transmit and receive IQ data packets in the time domain or the frequency domain. In some embodiments, each second-level beamformer may receive the associated user data layer in the form of frequency domain IQ data from the main beamformer 724, and then calculate the signal port-specific aggregate frequency domain IQ data packets for the transceiver IC (or transceiver IC subarray) they serve. In an alternative embodiment, each second-level beamformer may similarly receive the associated user data layer from the main beamformer 724 in the form of frequency domain IQ data via a corresponding serial data link 726, but instead first convert the frequency domain IQ data to time domain IQ data, and then calculate the signal port-specific aggregate IQ data packets (now instead containing time domain data) for the transceiver IC (or transceiver IC subarray) they serve. In this regard, each of the second-level beamformers 728, 834, 736, and 738 will be configured with appropriate iFFT processing (e.g., a digital signal processor (DSP) configured with appropriate programming instructions to perform an algorithm for IFFT operations) for converting frequency-domain IQ data into time-domain IQ data.

[0128] exist Figure 7In the illustrated embodiment, RU 704 is depicted as having beamformer connections to transceiver ICs 730, which may be individual transceiver ICs having two or four signal ports for driving antenna elements 732, or may be a sub-array of transceiver ICs connected serially in accordance with various embodiments described herein. Figure 4 The Serdes mux device (eg, 404) may also implement part of the BF processor 728 of the hierarchical beamformer arrangement.

[0129] As noted above, some embodiments such as Figure 7 The embodiments depicted in FIG. 7 include a hierarchical beamformer arrangement having a main (primary) beamforming processor 724 and a set of auxiliary beamformer processors 728, 734, 736, 738. In these embodiments, the primary beam processor assigns beamforming combining weights (combined with pre-decoder combining weights, as appropriate) to form a complete beamforming matrix (as shown in FIG. 1 ). Figure 8 ), and then distributes portions of the beamforming matrix to respective auxiliary beamformer processors. More specifically, in some embodiments, the transceiver IC subarrays may be partitioned according to their physical locations on a panel (e.g., 100), wherein each set of transceiver IC subarrays in a given partition is served by and interconnected with a corresponding auxiliary beamforming processor, wherein the auxiliary beamformer processors may be distributed across the panel to be adjacent to or within the partition. In some embodiments, each distributed auxiliary beamformer processor also receives a frequency domain subcarrier IQ user data layer, and applies respective distributed beamforming weights to the IQ user data layer to compute fully beamformed IQ data points for distribution to the partitioned subset of its respective transceiver IC subarray (wherein the fully beamformed IQ data points may be in either a frequency domain format or a time domain format, as noted above).

[0130] Embodiments of the auxiliary beamformer processors may include digital signal processor circuits that execute software instructions to perform matrix multiplication operations, or may take the form of data registers interconnected with hardware multiplier circuits to perform matrix operations. The hardware may include a hardware processor, a field programmable gate array (FPGA), dedicated digital logic, or a combination thereof. In addition, in some embodiments, the auxiliary beamformer processors may each include a digital signal processor (DSP) configured to execute software instructions to perform iFFT processing for converting frequency domain IQ data to time domain IQ data (when, for example, the IQ data received from the primary beamformer processor is in the frequency domain), and to perform FFT processing for converting time domain IQ data to frequency domain IQ data (when, for example, the IQ data to be sent to the primary beamformer processor is in the time domain).

[0131] Figure 8 8 is a graphical representation of a downlink transmit beamforming operation. User data is represented by layers of data along dimension 818, with subcarrier-specific IQ data for each such layer depicted along dimension 816. In some embodiments, the user data layers along dimension 818 are frequency-domain IQ data layers (e.g., such as data layers distributed over corresponding links 726 to separate auxiliary beamformers, as in conjunction with Figure 7 816). Each data layer (such as layers 820, 822) may actually be aggregate user data for one or more users, with different users being assigned / allocated different subcarrier subsets represented along dimension 816. In addition, a given user may be assigned one or more data layers (along dimension 818), such as in the case of spatial multiplexing.

[0132] A beamformer (e.g., 202, 300, 400, 724 (primary beamformer), etc.) calculates beamforming weights for a set of carriers along dimension 802, specific to a user data layer represented by IQ data along dimension 800, and for a signal port along dimension 804. Figure 8As shown in , the beamforming weights depicted on the top layer of the matrix (i.e., the horizontal slice of the matrix along dimension 802 by 800) are applied to the data layer (816 x 818) according to the matrix multiplication to generate the top layer (at the top of dimension 826) of beamformed IQ data, where the subcarriers are along dimension 824. Note that for simplicity, the rows or layers along the beamforming dimension 804 alternate between H and V polarizations, such that, for example, elements 806, 808 each include separate signal port weights, such as "H" weights and "V" weights, which are then independently used to combine data layers, such as layers 820, 822, respectively. The H / V weight pairs depicted as interleaved in the matrix columns in the vertical direction (dimension 804) may be related in some operating modes, or may be completely independently selected beams for the H and V components (i.e., signal ports). The columns of the beamforming matrix, such as columns 807 or 809, may be applied to a given set of subcarriers in a corresponding given data layer according to the desired beamforming operation. Note that the beamforming matrix may also be incorporated into the precoding matrix calculation to form a linear combination of the data layer according to the desired precoding matrix. In this manner, the beamformer matrix is ​​used to operate on the user data layer to generate signal port specific IQ data.

[0133] exist Figure 8 In the illustrated embodiment, each set of beamformed IQ data points is packetized and transmitted to a corresponding transceiver IC subarray, as described with respect to Figure 3 In some embodiments, the packetized IQ data may be maintained in the frequency domain. However, in other embodiments, the packetized IQ data may be converted to time domain IQ data instead. In some embodiments, the IQ data for the 64 signal ports along dimension 826 includes IQ data for 32 H signal ports and 32 V signal ports. Each of the four signal port specific IQ data segments 828, 830, 832, and 834 of 826 contains 16 beamformed IQ data packets, which may be combined via concatenation into a format similar to Figure 3 Each of the eight H / V IQ packets contains time domain or frequency domain IQ data and is sent to a corresponding transceiver IC subarray via a single serial data link, such as along Figure 28a. The IQ data of sections 830, 832, and 834 are each similarly packetized into eight unique IQ data packet streams and sent to eight corresponding transceiver subarrays within transceiver subarray rows 238b, 238c, and 238d, respectively. In this embodiment, each dual signal port IQ data packet may be processed jointly by two serially connected transceiver ICs. Alternatively, each of the eight H / V packets obtained from section 828 may be sent to Figure 4 The corresponding transceiver IC subarrays in the first row of transceiver IC subarray 421a of FIG. 4, wherein the dual signal port IQ groups are similarly allocated to the rows of transceiver IC subarrays 421b, 421c, 421d. Figure 4 In an embodiment of the present invention, each beamformed IQ data packet is processed jointly by three serially connected transceiver ICs.

[0134] With respect to the multi-level beamformed IQ data packets 850 (which represent beamformed IQ data for one embodiment of a transceiver IC subarray), the beamformer processor may be configured to generate a commonly processed IQ data packet 864 (in a time domain or frequency domain format) for one signal port (representing, for example, subcarrier IQ data for all subcarriers or a subset of subcarriers of one component carrier of a signal port) and a second commonly processed IQ data packet 866 for a second signal port (wherein the second commonly processed IQ data packet 866 is in a time domain or frequency domain format, depending on, for example, the format of the commonly processed IQ data packet 864 for the first port) for use by the transceiver ICs to process signals according to the first level of beamforming, which transceiver ICs are also simultaneously generating a second level of higher resolution beamforming. The second level of beamforming is based on the beamforming for the individual transceiver ICs and their respective horizontal signal ports (H1, H2, H3, etc.) Figure 8 ) and for use by individual transceiver ICs and their corresponding vertical signal ports (V1, V2, V3, as indicated in FIG. Figure 8 858, 860, 862 of the fully digital beamforming (indicated in FIG. 1 ) as previously described with respect to Figure 3 Furthermore, as previously described, the second level beamformed IQ data packet may include subcarriers associated with the same component carrier as the co-processed IQ data packet, or subcarriers associated with a second component carrier.

[0135] More specifically, the first beamformed IQ data packet may include IQ data 864 (labeled Hc, where "c" indicates IQ data for common processing), 866 (Vc) for common processing by all transceiver ICs in a given transceiver IC subarray (e.g., three separate transceiver ICs, each capable of 2T2R operation). Three additional packets of transceiver IC-specific IQ data, respectively including data 852 concatenated with data 858; data 854 concatenated with data 860; and data 856 concatenated with data 862, are also transmitted to the transceiver IC subarray, wherein a first transceiver IC combines the common processed data 864 with data 852 and the common processed data 866 with data 858. Another transceiver IC combines the common processed data 864 with data 854 and the common processed data 866 with data 860, and a third transceiver IC combines the common processed data 864 with data 856 and the common processed data 866 with data 862.

[0136] Fig. 9 900 of dimension L (i.e., the number of layers) to beamformed downlink transmission IQ data packets at logical baseband ports 926'm,k=uiu represented by matrix [Z] 904 of dimension M. In some embodiments, the user data layers 906, 916, 918 remain in frequency domain format until the data associated therewith is beamformed. After the beamforming operation is completed, in some embodiments, the beamformed downlink transmission IQ data may be packetized to form frequency domain beamformed downlink transmission IQ data. However, in other embodiments, after the beamforming operation is completed, the beamformed downlink transmission frequency domain IQ data may instead be first converted into beamformed downlink transmission time domain IQ data and then transmitted to the corresponding transceiver IC (e.g., such as Figure 7 730) or a subarray of transceiver ICs (e.g., Fig. 9 The transceiver subarrays 914 in are previously grouped. Fig. 9, data layer [X] 900 is pre-coded by matrix PM 920 according to a pre-coding operation to obtain logical antenna port signals 922 represented by matrix [Y] 902, followed by a beamforming operation by digital beamforming matrix DB 924 using various beamforming beam indices (e.g., "beam Idx") with weights such as "beam 1" 910, which applies the beam weights and distributes the appropriately weighted pre-coded signals at node 908 (which are pre-coded linear combinations of data layers 906, 916, 918) over various logical baseband ports 926 (also depicted as IQ information 828, 830, 832, 834) represented by matrix [Z] 904. Each beamformed packet of matrix [Z] (such as IQ data packet 912) is transmitted to its corresponding transceiver IC subarray 914.

[0137] As noted above, in some embodiments, the IQ data subjected to the precoding and beamforming operations is frequency domain IQ data, which may then be packetized to generate frequency domain IQ data packets 912 that are transmitted to its corresponding transceiver IC subarray 914. However, in other embodiments, after the precoding and beamforming operations, the beamformed / precoded frequency domain IQ data may instead first be converted to the time domain, and then packetized to generate time domain IQ data packets 912 that are transmitted to its corresponding transceiver IC subarray 914.

[0138] Fig.10 1000 is an illustration of a conversion of a user data layer to a beamformed IQ data stream according to a generalized combined precoding and beamforming matrix 1012 operation 1000 resulting from matrix multiplication of a precoding matrix PM 920 and a beamforming matrix DB 924. A user IQ data layer [X] 1004 is provided by a processor 1002 which provides user IQ data that has been processed according to standard coding, cyclic redundancy check (CRC), rate matching (RM), and resource element (RE) mapping. The data layer [X] 1004 is processed in the transform 1000 according to the generalized spatial multiplexer / beamformer matrix PM to generate a logical baseband port IQ signal packet 1014 represented by a signal port IQ data matrix [Z] 1006 for transmission to a transceiver IC subarray (such as subarray 1008) over a corresponding serial data link. As used herein, the terms "beamforming" and "beamforming matrix" refer to the described combined beamforming / precoding operation, whether implemented in a single matrix operation or in multiple separate matrix operations. Fig. 9As depicted, the IQ data packets transmitted from each respective logical baseband port 1014 (and thus after beamforming / precoding operations) to its corresponding transceiver IC subarray 1008 may be either time domain IQ data packets (if converted to the time domain) or frequency domain IQ data packets.

[0139] Fig.11 1104. It is an illustration of receive uplink signal processing including receive beamforming and layer decoding. Each transceiver IC subarray 1108 provides the received IQ data to the beamformer processor as a logical baseband port 1116 represented by the matrix [Z] 1106. In some embodiments, the IQ data received by the beamformer processor can be frequency domain IQ data or time domain IQ data. In embodiments where the received IQ data is in the time domain, a conversion to frequency domain IQ data can be performed at the beamformer processor (when received via the logical baseband port 1116) via an FFT operation. The virtual antenna port signal 1112 can be formed according to the matrix [Y] 1104. Finally, the individual data layers 1110 represented by the matrix [X] 1102 can be recovered.

[0140] Fig. 12A A block diagram depicts an example of a single transceiver IC device architecture according to some embodiments. Fig. 12A The transceiver IC device architecture illustrated in is also suitable for forming a serially connected transceiver group. The transceiver IC is suitable for operating in FDD mode and TDD mode. By way of example, Fig. 12A The configuration depicted in is connected for operation in TDD mode. In addition, it should be noted that Fig. 12AThe embodiment of exemplifies a situation in which the transceiver IC 1200 receives and transmits frequency domain IQ data packets (e.g., directly from / to a beamformer processor (e.g., BFP 200, 300, 400, 722, etc. or from / to another transceiver IC). The transceiver IC 1200 includes multiple signal processing paths for both transmit signal processing and receive signal processing. For DL ​​transmit signal processing, the transceiver IC 1200 includes a serial data receiver RX#0 1202 for receiving frequency domain IQ data packets via a serial data receiver 1202. The serial data receiver 1202 includes: a data buffer for storing a plurality of deserialized data words; and a data analysis circuit for performing packet header analysis to determine whether the received packet is intended to be processed by the current transceiver IC and / or whether it is intended to be processed by one or more other transceiver ICs in the transceiver IC subarray. In the event that the packet is to be processed locally, the packet is forwarded via 1206 (such as via memory storage or direct memory access (DMA) operations) to a DSP memory 1210 that can be accessed by an integrated digital signal processor (DSP) 1215. In an alternative embodiment, the header check may be performed by the DSP 1215, which places data in the DSP memory 1210 that is designated for retransmission via Serdes transmitter TX#1 1262.

[0141] The DSP 1215 includes programming stored in non-volatile memory that, when executed, causes the DSP 1215 to execute an algorithm 1214 for converting frequency-domain digital IQ data into time-domain digital data. The stored algorithm instructions include processor instructions for iFFT operations 1214 and also include instructions for extending the converted data by adding a cyclic prefix (CP).

[0142] In subarray beamforming as described herein, each IC in a given subarray processes the same frequency-domain (or alternatively time-domain) IQ packets for transmission (referred to herein as "commonly processed" IQ data), and during reception generates frequency-domain (or alternatively time-domain) IQ packets that are transmitted as they travel toward a beamformer processor (e.g., as previously described in conjunction with Figure 7The phase of each IQ data packet processed together is aggregated at each transceiver IC as it traverses the cascaded set of transceiver ICs on a path from the auxiliary beamformer processor and the main beamformer processor described above. Because the signal processed together by the transceiver ICs is an aggregated beamformed signal having components from multiple data layers and multiple individual beams, it is not possible to adjust the individual beams within a given subarray of the jointly processed IQ data packet. However, a unique phase rotation can be applied to the aggregated beamformed signal at each element (i.e., each signal port) in the subarray, which will have the effect of tilting the entire composite / aggregated beamformed signal. Therefore, when beam tilt is desired, the transceiver is configured to incrementally adjust the phase of each jointly processed IQ data packet according to the position of the radiating element driven by the transceiver IC in the IC subarray. Without incremental adjustment of the phase at each subarray element, true tilt cannot be obtained because only one element may be aligned, and for a given downward (upward) tilt, the wavefronts from the remaining elements will be incrementally advanced (or delayed) according to their positions in the subarray. In this way, beam tilt can be achieved through digital baseband signal processing without directly adjusting any signal components in the analog domain (including no adjustment of the VCO phase).

[0143] More specifically, when a linear array of antenna elements is physically "tilted" (a vertical array tilted up / down in altitude, or a horizontal array tilted left / right in azimuth), the result can be viewed as an incremental time delay of signal transmission (or reception) across the antenna elements of the array, thereby changing the direction in which the propagating wavefronts constructively add to form the main lobe (and destructively combine to form the null). Electronic tilting is the process of applying appropriate signal delays without actually physically repositioning the antenna. The relationship between the time delay and the corresponding signal phase change depends on the tilt angle as well as the frequency of the signal. That is, a given time delay between two signals is equivalent to a linear phase shift in the frequency content of the signals, where a given time delay results in a lower phase change at lower frequencies within the signal and a linear higher phase change at higher frequencies. Thus, for narrowband signals, a specific time delay roughly translates into a specific phase shift between the delayed signals. But for wideband signals, such as 50MHz or 100MHz or larger OFDM signals, a given time delay affects the phase of the OFDM subcarriers differently. In a phased array, each subcarrier is still rotated by the same phase, which results in a nonlinear phase characteristic commonly referred to as beam squint. In OFDM signals with bandwidths of approximately 100 MHz, a certain amount of beam squint is acceptable.

[0144] Thus, electronic beam tilt in a physically static array can be achieved by various methods performed by individual transceivers as described herein, including: (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO); (ii) applying constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication); (iii) applying constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication); (iv) applying a time delay in the discrete time domain signal of the transmitted baseband signal; or (v) a combination of the above methods. Note that methods (ii) and (iii) will result in a certain amount of beam squint deformation.

[0145] In this regard, beam tilting may be achieved by applying a linearly increasing phase rotation across the subcarriers by a complex multiplier 1212, which is implemented as Figure 5 The NCO 542 of the embodiment of the present invention is a numerically controlled oscillator (NCO) described herein. The NCO 1212 is configured to provide a complex sequence with a linearly increasing phase for multiplication with a corresponding subcarrier frequency domain IQ data point sequence. For a desired beam tilt, an initial phase and an incremental rate at which the phase increases from subcarrier to subcarrier are determined, and these values ​​are loaded into the NCO phase accumulator 564 and the FCW register 562, respectively. The phase increment value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the subcarrier spacing, (iii) the carrier frequency, and (iv) the location of a particular radiating element driven by the transceiver IC. In general, to achieve a beam tilt of an angle φ, for a given subcarrier frequency (1 / λ), at a position n within the array, the phase rotation θ is given by:

[0146] θ=nπ(λ c / λ)sin(φ),

[0147] For the carrier wavelength λ c , the distance between the elements is d = λ c / 2. In receive beam tilt operation, the NCO may be implemented in the complex multiplier 1238 after FFT processing.

[0148] Alternatively, the complex multiplication 1212 may be configured to provide a constant phase rotation to each frequency domain IQ data point prior to transformation via the iFFT 1214 to implement an approximate time delay to achieve beam tilt. For a desired beam tilt, a frequency domain phase rotation represented by a single complex number is determined and loaded into the complex multiplier 1212. The frequency domain phase value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the array position of a particular radiating element driven by the transceiver IC, and (iii) the carrier frequency. In a receive beam tilt operation, a constant phase rotation may be implemented in the complex multiplier 1238 after FFT processing.

[0149] In some embodiments, beam tilt is implemented by applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication). For a desired beam tilt, a time domain phase rotation represented by a single complex number is determined and this value is loaded into a complex multiplier (which may also simultaneously implement a gain function). Such a complex multiplier may be, for example, Fig.13A , which illustrates the transmit time domain signal processing portion of the transceiver IC, as will be described in more detail below. The time domain phase value may be determined based on one or more different factors, including (i) the desired beam tilt angle, and (ii) the position of the particular radiating element driven by the transceiver IC. In receive beam tilt operations, the constant phase rotation may be implemented in the complex multiplier (along with the gain function), for example, prior to FFT processing, which may be performed at the transceiver IC or beamformer processor, as noted above. Such a complex multiplier may be, for example, Fig. 13B The complex multiplier 1386 depicted in FIG. 1 illustrates the receive time domain signal processing portion of the transceiver, as will be described in more detail below.

[0150] In some other embodiments, beam tilt is achieved by applying a time delay to the discrete time domain signal of the transmit baseband signal (rather than phase rotation via complex multiplication as in the above embodiments). For the desired beam tilt, the time domain delay is determined and loaded into the Fig.13A The time domain delay value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the time domain sampling rate, and (iii) the location of the specific radiating element driven by the transceiver IC. In receive beam tilt operation, the time domain delay value may be determined based on one or more different factors, including (i) the desired beam tilt angle, (ii) the time domain sampling rate, and (iii) the location of the specific radiating element driven by the transceiver IC. Fig. 13B Time delay is implemented in the delay buffer 1378 shown.

[0151] In yet other embodiments, a combination of the above methods may be used. In one particular embodiment, the electronic beam tilt may consist of a coarse adjustment and a fine adjustment, where the coarse beam tilt may be implemented by applying a linearly increasing phase rotation across the subcarriers by a complex multiplier 1212 implemented as an NCO using a finite resolution or a finite number of bits, and the fine resolution may be implemented by further adjustments in the time domain, such as a time delay or a time domain constant phase rotation.

[0152] For various embodiments of beam tilt phase adjustment, the phase rotation may be specified by a control message provided to the transceiver IC. A specific phase value may be provided, or a phase index value may be included in the control message, or in the header of the IQ data packet itself. The phase index value may be used to retrieve a pre-calculated phase value from, for example, a lookup table. In some embodiments, the transceiver IC may combine factors to calculate a specific rotation to be applied (e.g., a desired tilt angle may be provided, and the transceiver IC may adjust the phase rotation based on its predetermined position within an array and / or transceiver IC subarray). Such phase rotation may be used to implement beam tilt phase rotation.

[0153] In some embodiments, beam tilt can be achieved using a combination of linear phase rotation applied in the frequency domain, a constant phase rotation in the time domain followed by an iFFT transformation, or a time delay in the time domain. In some embodiments, frequency domain rotation can achieve coarse tilt or an approximation of the desired beam tilt, while time domain rotation can achieve fine tilt. This can be particularly useful when larger tilt angles are desired.

[0154] In other embodiments, dynamic adjustment of the tilt angle may be achieved on a slot-by-slot basis, greatly enhancing the available scan range and coverage from the panel array using subarray beamforming. In such embodiments, the beam tilt information and which slots, subcarriers, or component carriers to use may be specified via a control message.

[0155] In one embodiment, electronic antenna beam tilt is implemented in a transceiver subarray by distributing beamformed IQ data packets to multiple serially connected transceiver ICs for common processing by the transceivers. The IQ data packets have individual IQ values ​​for corresponding multiple subcarriers. At each transceiver IC, electronic beam tilt phase rotation is applied. In some embodiments, the application of beam tilt phase rotation is accomplished by changing the phase of each IQ modulated subcarrier based on the desired antenna tilt and array position. The phase change can be a constant phase rotation applied to all subcarriers, or it can be a linear increase phase rotation increased from subcarrier to subcarrier. Phase adjustment can be specified according to one or more control messages. The control message can be specific to a given subarray, a transceiver IC within a subarray, or specific to a separate transceiver IC. Phase adjustment can be specified according to time delay, frequency domain multiplication rotation, or time domain complex rotation, or equivalent data. A given transceiver IC can also combine phase adjustment data with array position data unique to the transceiver IC to calculate the final phase adjustment.

[0156] Return to reference Fig. 12A , the time domain IQ data is stored in the DSP memory 1216, which can be accessed by the transmission time domain signal processing circuit 1217 (about Fig.13A 12, circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time domain signal processing circuits 1220, 1230, each of which provides a baseband time domain OFDM signal (each signal is a single component carrier signal or a multi-component carrier signal) to a corresponding digital power amplifier (DPA) circuit 1222, 1232.

[0157] In one embodiment, DPA 1220, 1232 performs simultaneous RF modulation and amplification, which can be the final power amplification of the RF signal. In some embodiments, the DPA provides pre-amplification of the RF signal, which is then applied to an external power amplifier that drives the radiating antenna element. The external power amplifier is adjacently distributed on the active antenna panel assembly in an element-by-element manner. DPA 1220, 1232 is provided with multiple RF carrier phases, which are derived from a system phase-locked loop (SYSPLL) and further processed by a synchronous RF PLL 1262, which drives an RF carrier generator VCO1260. The selected RF carrier phase is used to switch the amplifier unit within the DPA. As described herein, a specific RF carrier phase and the corresponding number of activated cells that determine their relative amplitudes are selected based on the time domain IQ data points provided by circuits 1220, 1230.

[0158] The transceiver IC 1200A also includes a receive time domain signal processing circuit 1241 (for Fig. 13B 12), the receive time domain signal processing circuit is used to down-convert the analog RF signal via an IQ mixer driven by VCO 1260, and the IQ mixer generates separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) within circuits 1244, 1252. The sampled signals are then processed by time domain filtering and down-sampling circuits 1242, 1250. The processed time domain signals are then stored in DSP memory 1216 for further processing, including CP removal and conversion to subcarrier specific frequency domain IQ data via an FFT algorithm ("FFT" 1240 in FIG. 12). DSP 1215 includes programming stored in non-volatile memory, which when executed causes DSP 1215 to execute an algorithm for converting time domain digital data to frequency domain digital IQ data. A linearly increasing phase rotation can then be applied to each frequency domain IQ (i.e., subcarrier) value using an NCO (e.g., 1238), which is also an embodiment of electronic beam tilt. The received IQ frequency domain data is then processed by the MUX / combining circuit 1264 for transmission to the serial data bus via serial transmitter TX#0 1204.

[0159] Fig. 12B A block diagram depicts another example of a single transceiver IC device architecture according to some embodiments. Fig. 12A implementation plan, Fig. 12B The transceiver IC device architecture illustrated in is also suitable for forming a serially connected transceiver group. Fig. 12A , the transceiver IC 1200B is suitable for operating in both FDD mode and TDD mode. By way of example, Fig. 12B The configuration depicted in is connected for operation in TDD mode. In addition, it should be noted that unlike Fig. 12A implementation plan, Fig. 12B An alternative embodiment of the present invention illustrates a case in which the transceiver IC 1200B receives and transmits time domain IQ data packets from / to a beamformer processor (e.g., directly from / to BFP 200, 300, 400, 722, etc. or from / to another transceiver IC). The transceiver IC 1200B includes multiple signal processing paths for both transmit signal processing and receive signal processing. However, in the present embodiment, the transceiver IC 1200B is configured to process IQ data entirely in the time domain without additional processing elements involved in frequency domain to time domain conversion of IQ data (transmit side) and frequency domain to time domain conversion of IQ data (receive side), such as in combination with Fig. 12A The transceiver IC device architecture shown in FIG.

[0160] More specifically, for DL ​​transmission signal processing, the transceiver IC 1200B includes a serial data receiver RX#0 1202, which is now configured to receive time domain IQ data packets via the serial data receiver 1202. Fig. 12A As in the transceiver IC device architecture of , the serial data receiver 1202 includes: a suitable data buffer for storing a plurality of deserialized data words; and a data analysis circuit for performing packet header analysis to determine whether the received time domain IQ data packet is intended to be processed by the current transceiver IC and / or whether it is intended to be processed by one or more other transceiver ICs in the transceiver IC subarray. In the case where the packet is to be processed locally, it is forwarded to the memory 1211 via the link 1206, such as via memory storage or direct memory access (DMA) operations. In an alternative embodiment, the header check may be performed, for example, via a dedicated DSP element (not shown) coupled to the memory 1211, which places the data in the memory 1211 to be retransmitted via the Serdes transmitter TX#1 1262.

[0161] Recalling Fig. 12A In an embodiment of the invention, the frequency domain IQ data packets are stored in a DSP memory 1210 accessible to a DSP 1215, which is configured to execute an algorithm 1214 for converting the frequency domain digital IQ data into time domain digital IQ data, wherein such algorithm includes processor instructions for iFFT operation 1214 and also for extending the converted data by adding a cyclic prefix (CP). Although not explicitly shown, in some embodiments, the memory 1211 can be a DSP memory that can be read by a DSP processor (not shown) that is configured with appropriate programming instructions to perform the addition of CP to the time domain digital IQ data. In an alternative embodiment, such CP addition can be performed alternatively by a dedicated circuit (not shown) that is configured to re-read a portion of the time domain IQ data, for example, from the memory 1211, whereby such a re-read portion can be used as a CPE and then fed to the transmission time domain signal processing circuit 1217 by the dedicated circuit along with the rest of the time domain IQ data.

[0162] Note that adding CP to the time-domain IQ data typically increases the amount of data used for subsequent time-domain baseband signal processing. Therefore, ideally, the addition of CP occurs at the digital front-end circuitry of the transceiver IC 1200B to reduce the amount of data that would need to be communicated over the serial data link between the beamformer processor and a given transceiver IC / transceiver subarray. However, in alternative embodiments, it is possible for the addition of CP to occur at the beamformer processor instead.

[0163] Return to reference Fig. 12B In some embodiments, the time domain IQ data stored in the memory 1211 can be accessed (directly or indirectly) by the transmit time domain signal processing circuit 1217 (with respect to Fig.13A As previously described in conjunction with Fig. 12A As depicted, circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time domain signal processing circuits 1220, 1230, each of which provides a baseband time domain OFDM signal (each signal is a single component carrier signal or a multi-component carrier signal) to a corresponding digital power amplifier (DPA) circuit 1222, 1232. The operation of DPA 1220 and 1232 is combined with Fig. 12A The operations described in the embodiments are basically the same and are omitted here for brevity.

[0164] As in transceiver IC 1200A, in some embodiments, transceiver IC 1200B similarly includes receive time domain signal processing circuit 1241 (with respect to Fig. 13B 1244, 1252). Fig. 12A As shown in , the sampled signal is then processed by time domain filtering and downsampling circuits 1242, 1250.

[0165] In this embodiment, the processed time domain signal may then be stored in memory 1211 for further processing. In some embodiments, the further processing may include CP removal. As noted above, in some embodiments, memory 1211 may be a DSP memory that can be read by a DSP processor (not shown) that is configured with appropriate programming instructions to further perform the removal of CP from the time domain digital IQ data on the receiving side. In an alternative embodiment, such CP removal may alternatively be performed by a dedicated circuit (not shown) that is configured to, for example, re-read a portion of the time domain IQ data from memory 1211, remove the re-read portion as CP, and store the modified time domain IQ data back in memory 1211.

[0166] As noted above, in some embodiments, the transceiver IC 1200B is configured to process IQ data entirely in the time domain without additional processing elements involved in frequency-domain to time-domain conversion of the IQ data (transmit side) and frequency-domain to time-domain conversion of the IQ data (receive side), such as in conjunction with Fig. 12A The transceiver IC device architecture shown in FIG. 1 is described. Therefore, on the receiving side, the processed time domain digital data does not need to be passed through the Fig. 12A The FFT operation in the embodiment of 1204 is converted into frequency domain digital IQ data. Conversely, the received time domain IQ data may be processed by the MUX / combining circuit 1264 for transmission to a serial data bus via the serial transmitter TX#0 1204, such as for transmission to a beamformer processor. Subsequent time domain to frequency domain IQ data conversion may be performed at the beamformer processor, as previously described herein.

[0167] As previously discussed, when beam tilt is desired, the transceiver ICs described herein can be configured to incrementally adjust the phase of each commonly processed IQ data packet based on the position of the radiating elements driven by the transceiver ICs in a given IC subarray. In addition, electronic beam tilt is the process of applying appropriate signal delays without actually physically repositioning the antenna. As previously discussed, electronic beam tilt in a physical static array can be achieved by various methods performed by a separate transceiver described herein, including: (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO); (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication); (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication); (iv) applying a time delay in a discrete time domain signal that transmits the baseband signal; or (v) a combination of the above methods. A detailed discussion of these different methods has been provided above and is therefore not repeated.

[0168] However, note that Fig. 12B In the implementation scheme (different from Fig. 12A ), the transceiver IC 1200B is configured to process IQ data entirely in the time domain. Therefore, electronic beam tilting methods involving applying, for example, a phase rotation (e.g., incremental or constant) to each subcarrier frequency domain IQ data point (or any other suitable frequency domain based electronic beam tilting technique for that matter) are not applicable to Fig. 12B In contrast, electronic beam tilting may be implemented via any suitable time domain technique, such as by applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication) or by applying a time delay in the discrete time domain signal that transmits the baseband signal, as discussed herein. For example, in Fig. 12B In the process, the time domain IQ data (after CP addition operation) is passed to the transmission time domain signal processing circuit 1217 (about Fig.13A further described) and is processed therein for electron beam tilting by performing complex multiplications in the time domain or by applying a time delay.

[0169] Fig.13A1300 is a block diagram of an example of a time domain signal processing circuit 1217 according to some embodiments. Time domain IQ data is received directly or indirectly from a memory via line 1302 (and similarly, lines 1304, 1344, 1346) and applied to a signal path power detector and to a gain unit 1306 for adjusting power levels. As described above, the memory may be a DSP memory or may be a memory coupled to a dedicated circuit (e.g., as described above in conjunction with Fig. 12B In some embodiments described). In addition, in some embodiments, the gain multiplier may also include a complex phase that rotates each time domain value by the same phase. This time domain phase rotation can be used to apply an approximate time delay, which can be used to implement electronic beam tilt. Although this corresponds to a phase rotation of the same phase for each constituent subcarrier, rather than a linearly increasing phase rotation, this is accurate enough for a bandwidth of approximately 100 MHz in the frequency range of the frequency band used for LTE and 5G signals. The signal is filtered by an FIR filter stage 1308, which also includes one of a plurality of interpolation stages to increase the sampling rate of the discrete time domain signal. The discrete time digital UL signal is then processed by a numerically controlled oscillator (NCO) 1310. The NCO (e.g., 1310) can be configured to multiply the time domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range (such as a separate frequency range that does not overlap with other component carriers). In some embodiments, one transmission signal may be slightly shifted up in frequency, while another transmission signal (such as a separate component carrier provided on connection 1304) may be slightly shifted down using a corresponding NCO so that two time domain signals representing, for example, two component carriers may be added together without the frequency content of one signal overlapping the frequency content of the other signal. The signal is further processed by a delay buffer 1312, which allows for precise time offset adjustment of the transmission signal. In some embodiments, the delay buffer 1312 is used to provide per-carrier delay adjustment. The delay buffer 1312 compensates for the different processing times of different supported subcarrier spacings (SCS) and bandwidths. Assuming that all filtering is performed with an FIR filter for each carrier, the adjustable delay per carrier is the difference between the larger delay and the shortest delay, which is approximately 10 μs. However, sharing the function with a window relaxes this requirement.

[0170] The other discrete time domain signals on lines 1304, 1344, and 1346 are similarly processed as the discrete time domain signal on line 1302. In some embodiments, the discrete time domain signals on lines 1302, 1304, 1344, and 1346 are generated by frequency domain to time domain conversion from DSP 1215, such as in combination with Fig. 12AIn other embodiments, the discrete time domain signals on lines 1302, 1304, 1344, and 1346 are generated from time domain IQ data received by the transceiver IC, such as in combination with Fig. 12B 1328b (and DPA 1328c, 1328d of signal port 1350) from the modulator / amplifier DPA 1328a, 1328b of the first signal port 1342 of the RF signal adder 1340. The corresponding DPA (e.g., as shown in FIG. 1324) is used to correct the phase and amplitude distortion present in the modulator / amplifier DPA 1328a, 1328b (and DPA 1328c, 1328d of signal port 1350) of the first signal port 1342 of the RF signal adder 1340. FIG. 12A to FIG. 12B Each section 1328a to 1328d of the DPAs 1222 and 1232 shown includes a clock domain crossing circuit 1330, a cascaded integrator-comb (CIC) filter 1332, a mapper circuit 1334, a delay circuit 1336, and a final DPA stage 1338.

[0171] Fig. 13B An example of a receive time domain signal processing circuit 1241 according to some embodiments is depicted. Digital samples from the ADC are received by a clock domain crossing circuit 1362 and adjusted for DC offset by a DC offset circuit 1364. An IQ multiplier 1366 may be used to provide automatic gain control of the baseband time domain signal in response to the power measured by a power detector PD 1368. A quadrature error compensation circuit (QEC 1370) provides compensation for frequency-dependent quadrature errors in the RX analog front end. In one embodiment, the QEC circuit 1370 divides the time domain signal (having a sampling rate of, for example, 245.76 MHz) into 16 frequency bins, each 15.36 MHz. Each frequency bin is added to the mirror frequency bin content shaped by a complex multiplier. A notch filter 1372 may be used to reduce any undesirable out-of-band signals.

[0172] MUX 1374 may be configured to selectively direct receive signal samples from path RX0 (1360) or RX1 (1394) to any or all of RX signal paths 1376, 1392, 1396, or 1398. Some examples of different possibilities are: RX0 to all 4 RX signal paths; RX1 to all 4 RX signal paths; RX0 to RX signal paths 1376 and 1392 and RX1 to RX signal paths 1396 and 1398; and RX0 to RX signal path 1376 and RX1 to RX signal paths 1392, 1396, and 1398. Each RX signal path includes a delay buffer (e.g., 1378), an NCO (e.g., 1380), a FIR filter and downsampler (e.g., 1384, 1382), and a power detector (e.g., PD 1390). Note that the gain multiplier (e.g., 1386) may also implement a constant phase rotation on the time domain signal. In such an embodiment, this is equivalent to a constant phase shift applied to each subcarrier, rather than a linearly increasing phase shift across the subcarriers, but still provides a suitable approximation of the time delay for the purpose of achieving electronic beam tilt. FIR 1382 may also include a notch filter for removing component carriers that are not processed by a given signal path. In some embodiments, NCO 1380 may be used to apply a time domain frequency shift that moves the desired component carrier to the low passband of notch filter 1382.

[0173] Fig.14 Depicted according to some embodiments FIG. 12A to FIG. 12B and FIG. 13A to FIG. 13B A generalized configuration of an example signal processing for dual-carrier, dual-polarization communication signals of a transceiver IC device of FIG. 1 . More specifically, Fig.14 The example of the signal processing configuration shown in may be applicable in embodiments involving communication of data packets associated with two different carriers (e.g., two component carriers), where each carrier signal has two polarizations (e.g., horizontal and vertical polarizations as described above). In an exemplary embodiment, the transceiver device is a transceiver IC. In addition, in Fig.14 In an example configuration, the transceiver IC operates in a TDD mode within an OFDM modulated wireless network such as an LTE-based or 5G-based communication system.

[0174] like Fig.14 As shown, the transceiver device (IC) 1400 includes a first serial communication port 1406 (eg, a first serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.14 0) and a second serial communication port 1434 (eg, a second serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.14Note, however, that although the transceiver IC is shown as having two separate serial communication ports (1406 and 1434), Fig.14 In the example embodiment of the present invention, only one of the ports 1406 and 1434 is used. More specifically, as shown, only the serial communication port 1406 is connected to the serial data links 1402 and 1404 for communicating data to / from the transceiver IC, while the serial communication port 1434 is not actively used. However, in some embodiments, the transceiver IC may also be serially connected to a second transceiver IC (e.g., as described in various embodiments described herein (see, e.g., Figures 2 to 4 )).

[0175] Generally speaking, as previously indicated, the transceiver IC may be configured to process four separate transmit component carriers and four separate receive component carriers. The transceiver IC is configured with at least two separate transmit signal port paths (chains) and at least two separate receive signal port paths (chains) typically associated with two corresponding antenna radiating elements, but other configurations are possible, as described herein. In addition, generally speaking, the transceiver IC may include numerous signal processing elements, such as an integrated digital signal processor (DSP) for converting frequency domain digital data to / from time domain digital data (via multiple iFFTs and FFTs) and for cyclic prefix addition and removal (in an implementation in which the IQ data packets received by / transmitted from the transceiver IC are in the frequency domain), multiple integrated modulated digital power amplifiers (DPAs) for converting digital baseband time domain signals into amplified analog RF signals, analog RF downconverters, and analog-to-digital converters, etc.

[0176] refer to Fig.14In some embodiments, the serial communication port 1406 may receive a data packet stream (e.g., four multiplexed data packet streams) for DL ​​(downlink) transmission via the serial data link 1402 (e.g., from a beamformer processor), wherein the packets include packets for a first component carrier (hereinafter, "carrier C1") for each of the horizontal (H) and vertical (V) polarizations and IQ data packets for a second different component carrier (hereinafter, "carrier C2"). For simplicity, the combination of two different component carriers and horizontal and vertical polarizations are denoted herein as "C1H", "C2H", "C1V", and "C2V", respectively. In the UL (uplink) direction, the serial communication port 1406 may receive an IQ data packet stream (e.g., four multiplexed IQ data sets for four OFDM subcarrier sets) for each of the two H and V polarizations for each of the two carriers C1 and C2, and transmit these IQ data packet streams via the serial data link 1404 (e.g., to the beamformer processor).

[0177] Notice, Fig.14 The example transceiver IC configuration illustrated in FIG. 14 assumes that packets received at or transmitted from the serial port communication port 1406 contain frequency domain subcarrier specific digital IQ data. However, it should be understood that in alternative embodiments, the transceiver IC 1400 may be configured to instead receive and transmit (e.g., from / to a beamformer processor) data packets containing time domain subcarrier specific digital IQ data (see, e.g., FIG. 14 ). Fig. 12B and corresponding description for one example of such a configuration). In such alternative (time domain only) implementations, the iFFT and FFT processing may be offloaded from the transceiver IC to, for example, a beamformer processor, as described above. Additionally, in some implementations, different carrier packets (containing frequency domain IQ data or time domain IQ data) destined for the same transceiver IC may contain unique carrier IDs and be addressed to the same transceiver IC.

[0178] like Fig.14 As shown in FIG. 1 , the serial communication port 1406 may be coupled to a signal processing unit 1408, which includes several elements configured to provide various digital signal processing functions, such as those previously described in conjunction with FIG. FIG. 12A to FIG. 12B and FIG. 13A to FIG. 13B In some embodiments, the signal processing unit 1408 may be a single digital signal processor (DSP) that performs all iFFT and FFT calculations as well as other signal processing functions (not explicitly shown) associated with, for example, frequency / time domain I / Q data signals.

[0179] In operation, in the downlink (DL) transmission direction, an IQ packet data stream for DL ​​transmission received via link 0 (1406) may be provided to a demultiplexer (or similar element, such as a memory segment according to a memory map) 1410, which may separate the received data into two corresponding data streams for two separate transmission chains: one IQ data stream for a dual-carrier horizontally polarized signal (C1H / C2H signal) to be transmitted from a signal port coupled to a radiating element 1422, and another IQ data stream for a dual-carrier vertically polarized signal (C1V / C2V signal) to be transmitted from a signal port coupled to a radiating element 1430. Element 1412 (e.g., in the form of DSP memory) may further separate the horizontal and vertical frequency domain components (data points) of the subcarriers of each corresponding component carrier C1 and C2, which are then sent to four separate iFFT / CP (IFFT / cyclic prefix) elements 1414 for frequency domain to time domain conversion to generate four separate discrete time domain baseband data signals, two signals per carrier frequency and two signals per signal polarization. Although not explicitly shown, additional time domain and frequency domain processing may include, for example, cyclic prefix addition, frequency offset, phase and gain adjustment, filtering, and sample rate conversion.

[0180] In practice, as described above, incoming data is split into four separate transmission paths. More specifically, Fig.14 As shown, the output of unit 1408 includes (i) two separate discrete time-domain baseband data signals 1416 and 1418, represented as C1H (1416) and C2H (1418), and (ii) two separate discrete time-domain baseband data signals 1426 and 1428, represented as C1V (1426) and C2V (1428). As shown, after frequency domain to time domain conversion, time domain signals C1H (1416) and C2H (1418) are added (summed) in time, and C1V (1426) and C2V (1428) are added (summed) in time, and the result of the signal addition is provided to a corresponding TX / DPA element 1420, which generally represents a transmit RF chain and a digital power amplifier, to generate an amplified analog RF signal C1H / C2H (1424) for a horizontal signal port and an amplified analog RF signal C1V / C2V (1432) for a vertical signal port. Signals 1424 and 1432 are then provided to corresponding radiating elements 1422 and 1430 via corresponding SPDTs for transmission. Note that, although not explicitly shown, as previously described herein, additional time domain processing may include, for example, additional sampling rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc.

[0181] In operation, in the receive direction, the data modulated dual component carrier RF uplink signal can be received by the transceiver IC (1400) at the horizontal and vertical signal ports via the radiating elements 1422 and 1430. For ease of discussion and for example only, assume that the amplified analog RF signal C1H / C2H (1424) and the amplified analog RF signal C1V / C2V (1432) are now the uplink signals received by the transceiver IC. Fig.14 As shown in FIG. 14 , horizontally and vertically polarized RF signals may be provided to separate LNA / DC / ADC elements 1446 via respective SPDTs. The LNA / DC / ADC elements 1446 may perform RF to baseband signal conversion, analog to digital signal conversion, followed by, for example, further time domain processing (e.g., quadrature error correction, filtering, etc. (not explicitly shown)).

[0182] As further shown, the output of element 1446 includes two copies of the discrete time domain baseband data signal. These two signals are filtered by FIR filters 1442, 1444, but one of these signals is first shifted in frequency by the NCO (within filter 1442 or 1444) to separate the component carriers. The separated carriers are represented as C1H (1442) and C2H (1444). Two additional identical discrete time domain baseband data signals are provided to filters 1426 and 1428, and (after NCO conversion and FIR filtering) time domain signals representing the component carrier time domain signals are generated, which are represented as C1V (provided by filter 1448) and C2V (provided by filter 1450). These four separate time domain baseband signals 1442, 1444, 1148 and 1450 (two signals per carrier and two signals per polarization) are then input into the DSP 1408 for signal processing, including CP removal and conversion (via FFT element 1440) from the time domain IQ signal samples to frequency domain IQ data representing the amplitude and phase of the corresponding subcarriers of the corresponding component carrier.

[0183] Thus, in this embodiment, the receive RF signal is effectively split into four discrete time-domain baseband data signals for processing on four separate receive paths. More specifically, the C1H signal (1442), C2H signal (1444), C1V signal (1448), and C2V signal (1450) are parsed, for example, by memory mapping, for four separate FFT signal processing operations (e.g., 1440) for time-domain to frequency-domain conversion (via FFT) to generate four separate frequency-domain IQ data packets (or packet streams, where each packet in the stream represents a symbol time within a time slot) for each of the two component carrier frequencies and for each signal polarization.

[0184] Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sampling rate conversion, filtering, cyclic prefix detection and removal, etc., as described above. After the conversion performed by FFT element 1440, elements 1436, 1438 (e.g., in the form of DSP memory and digital logic) may then formulate IQ data packets for different component carriers associated with both component carriers C1 and C2 for each polarization (H or V). Note that in an alternative embodiment that does not involve time-domain to frequency-domain conversion (as indicated above), IQ data packets for different component carriers associated with component carriers C1 and C2 for each polarization (H or V) may instead be formulated in the time domain.

[0185] As further illustration of other embodiments, Fig.15 A generalized configuration of an example signal processing for generating a four-carrier, dual-polarized communication signal by two serially connected transceiver devices of FIG. 12 and FIG. 13 is depicted according to some embodiments. More specifically, Fig.15 1 shows a transceiver device architecture 1500 including a first transceiver device 1504a and a second transceiver device 1504b. Fig.14 As shown, in an exemplary embodiment, the transceiver device is a transceiver IC and operates in TDD mode within an OFDM modulation system such as a 5G-based or LTE-based communication system. Fig.14 The various operating principles and nomenclature described apply to Fig.15 Therefore, some operational details will be omitted or summarized for ease of discussion.

[0186] refer to Fig.15 , the first transceiver device (IC) 1504a includes a first serial communication port 1506 (eg, a first serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 0) and a second serial communication port 1530 (e.g., a second serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 Similarly, the second transceiver device (IC) 1504b includes a first serial communication port 1546 (eg, a first serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 0) and a second serial communication port 1562 (e.g., a second serial port transmitter / receiver, such as a Serdes transmitter / receiver) (in Fig.15 1 ). Transceiver devices (ICs) 1504a and 1504b are serially connected via a bidirectional serial data link 1544.

[0187] In some embodiments, the serial communication port 1506 may receive an IQ data packet stream (eight sets of IQ data, grouped into four carrier-specific H / V combinations, or in the depicted embodiment, into eight separate data packet streams) for DL ​​transmission via a bidirectional serial data link 1502 (e.g., from a beamformer processor), wherein the packets include IQ subcarrier data for four different component carriers (hereinafter, "carrier C1," "carrier C2," "carrier C3," and "carrier C4") for each of the horizontal (H) and vertical (V) polarizations. For simplicity, the combinations of four different carriers on the horizontal and vertical polarizations are denoted herein as "C1H," "C2H," "C3H," "C4H," "C1V," "C2V," "C3V," and "C4V," respectively. In the UL (uplink) direction, the serial communication port 1506 can receive data packet streams for each of the four carriers C1, C2, C3 and C4 for each of the two H and V polarizations (e.g., eight multiplexed data packet streams) and transmit these data packet streams via the same bidirectional serial data link 1502 (e.g., to a beamformer processor).

[0188] Note that Fig.15 In the transceiver device architecture 1500 illustrated in FIG. 1 , it will be assumed, by way of example, that packets received at or transmitted from the serial port communication port 1506 contain frequency domain subcarrier specific digital IQ data. However, it should be understood that in alternative embodiments, each transceiver device 1504a and 1505b may be configured accordingly (see, e.g., Fig. 12B and corresponding description for one example of such a configuration), such that packets received at or transmitted from the serial port communication port 1506 (e.g., from / to the beamformer processor) instead contain time-domain subcarrier-specific digital IQ data. In this regard, the iFFT and FFT processing can be moved from the transceiver device (IC) side to the beamformer processor, as described above.

[0189] In operation, in the DL transmission direction, the first transceiver IC (1504a) receives a packetized IQ data stream for DL ​​transmission via port 1506. The first transceiver IC is configured to process data associated with the first two carriers (i.e., C1H, C2H, C1V, and C2V) for each polarization. Fig.14In the transmission operation described, the first transceiver IC (1504a) performs signal processing to separate (via a demultiplexer or similar element (1508)) the received IQ data for carriers C1 and C2 into respective data sets for two separate transmission paths: one IQ data stream for a dual-carrier horizontally polarized signal (C1H / C2H signal) and another IQ data stream for a dual-carrier vertically polarized signal (C1V / C2V signal). As generally shown by elements 1510 and 1520 (denoted as "C1H / C2H" and "C1V / C2"), as shown Fig.14 , the horizontal and vertical frequency domain components of the subcarriers of each corresponding component carrier C1 and C2 can be further split and processed by four separate iFFT / CP elements to generate four separate discrete time-domain baseband data signals (two signals for each component carrier and two signals for each signal polarization), which are then added in pairs in time, where the results of the signal addition (C1H+C2H and C1V+C2V) are provided to the corresponding TX / DPA elements 1512 and 1522 to generate modulated and amplified analog RF signals C1H / C2H for the horizontal signal port of the transceiver IC 1504a and amplified analog RF signals C1V / C2V for the vertical signal port of the transceiver IC 1504a.

[0190] and Fig.14 Unlike the embodiments of the present invention, the packet data associated with the other two carriers C3 and C4 received at port 1506 is forwarded to the second transceiver IC (1504b) for processing. More specifically, the first transceiver IC (1504a) can be configured to forward the IQ data packets for carriers C3 and C4 for each polarization (i.e., C3H, C4H, C3V, and C4V) to the second transceiver IC 1504b for processing. In some embodiments, different carrier packets destined for the first transceiver IC or the second transceiver IC may contain a unique carrier ID and be addressed to the corresponding transceiver IC through one or more identification fields in the IQ data packets. Therefore, the first transceiver IC can be configured to examine the incoming packets to determine which packets are intended for the first transceiver IC and which packets are to be forwarded to the second transceiver IC.

[0191] In some embodiments, the first transceiver IC may forward those packets via internal path 1532 to its second serial communication port 1530, which is serially interconnected with a second transceiver IC (i.e., serial communication port 1546 within the second transceiver IC) via serial data link 1544. The second transceiver IC performs similar signal processing as the first transceiver IC (but with respect to carriers C3 and C4) via elements 1548, 1550, 1556, 1552, and 1558 to output amplified analog RF signals C3H / C4H and C3V / C4V on two signal ports of transceiver IC 1504b.

[0192] Subsequently, (i) the two signals C1H / C2H and C3H / C4H for horizontal polarization can be combined via summing element 1514 to produce a combined signal 1518, which is provided to radiating element 1516 for transmission via the first SPDT, and (ii) the two signals C1V / C2V and C3V / C4V for vertical polarization can be combined via summing element 1524 to produce a combined signal 1528, which is provided to radiating element 1526 for transmission via the second SPDT.

[0193] Similarly, in the receive direction, the data modulated four-carrier dual-polarized RF uplink signal may be received by two serially connected transceiver ICs (1504a and 1504b) via radiating elements 1516 and 1526 corresponding to the horizontal and vertical signal ports, respectively. Fig.14 In the present invention, for ease of discussion and for example only, it is assumed that the analog RF signals C1H / C2H / C3H / C4H (1518) and the analog RF signals C1V / C2V / C3V / C4V (1628) are now the received uplink signals.

[0194] like Fig.15 As shown in FIG. , the RF signal (1518) received on the horizontally polarized antenna element 1516 is provided to the RX / LNA element 1538 within the first transceiver IC (1504a) via the corresponding SPDT, and the RF signal (1528) received on the vertically polarized antenna element is provided to the RX / LNA element 1570 within the second transceiver IC (1504b) via the corresponding SPDT. Fig.14, each of the corresponding horizontal and vertical receive RX / LNA chains can be configured to perform RF to baseband signal conversion, analog to digital signal conversion, etc. to output a first four-carrier discrete time domain signal on the horizontal receive path and a second four-carrier discrete time domain signal on the vertical path. Thus, in some embodiments, the output of the RX / LNA 1538 element can be a first four-carrier discrete time domain signal on the horizontal polarization receive path, and the output of the RX / LNA element 1570 can be a second four-carrier discrete time domain signal on the vertical polarization receive path. Note that in this embodiment, each transceiver IC processes four component carriers in one of the RX / LNA elements, while the other RX / LNA elements (1542, 1576) are disabled.

[0195] Return to reference Fig.15 , with respect to horizontal polarization, the output of the RX / LNA element 1538 includes discrete time-domain baseband data signals 1536 and 1540 to be processed on two separate signal processing branches, wherein (i) carriers C1 and C2 represented as C1H / C2H (1536) are processed on one branch, and (ii) carriers C3 and C4 represented as C3H / C4H (1540) are processed on the other branch. Similarly, with respect to vertical polarization, the output of the RX / LNA element 1570 may include discrete time-domain baseband data signals 1568 and 1574 to be processed on two separate signal processing branches, wherein (i) carriers C1 and C2 represented as C1V / C2V (1568) are processed on one branch, and carriers C3 and C4 represented as C3V / C4V (1574) are processed on the other branch.

[0196] As combined Fig.14 The various principles of operation of the described receive signal processing (including, for example, conversion from a time domain signal to frequency domain IQ data) will similarly apply to Fig.15The receive paths of the arrangement are described above and will not be repeated in detail here. For illustration, in some embodiments, the received C1H / C2H signal (1536) for horizontal polarization can be separated from C3H / C4H by time domain FIR filtering, notch filtering, etc., and further separated into constituent component carriers C1H and C2H by time domain filtering in one signal path to remove the C2H component to obtain C1H, while the other path includes complex multiplication via a numerically controlled oscillator (NCO) frequency to shift the C2H component to the desired baseband signal, followed by additional filtering to remove the residual component of C1H. Thus, one transceiver IC (1504a) can receive four component carriers on a single receive RF signal port (e.g., via either of the H or V polarized antenna elements) and parse the signal into four separate component carriers. In the illustrated embodiment, the four separate component carriers C1H, C2H, C3H, C4H are all separated using time domain signal processing and then sent to four separate FFT operations (in some embodiments, all performed by a single DSP processor) for time domain to frequency domain conversion. Similarly, the C1V / C2V / C3V / C4V signals (1528) for vertical polarization, initially processed by a single LNA and ADC 1570, are processed via filtering, frequency offset (i.e., NCO modulation), and further filtering to be conditioned for four separate FFT operations for time domain to frequency domain conversion. Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, etc., as described above.

[0197] After the time domain to frequency domain conversion, in this embodiment, elements 1534 and 1566 (on the horizontal and vertical paths, respectively) then route and / or store in memory the IQ data points of the subcarriers associated with the individual component carriers C1, C2, C3, and C4 for each respective polarization (H or V). The frequency domain IQ data for all four component carriers per polarization may be further combined into packet data streams (e.g., eight packet data streams, or four combined V / H packet streams) for transmission (e.g., to a beamformer processor) from two serially connected transceiver ICs (1504a and 1504b) over a bidirectional serial link 1502.

[0198] More specifically, in this regard, frequency domain IQ packet data corresponding to vertically polarized signals of four carriers C1, C2, C3, and C4 may be received at the serial communication port 1562 of the second transceiver IC (1504b). The second transceiver IC may be configured to forward those data packets to its other serial communication port 1546 via an internal link 1564, which is serially interconnected with the first transceiver IC (i.e., the serial communication port 1530 within the first transceiver IC) via a serial data link 1544. Although not in Fig.15 1502, but in some embodiments, the packet data output by element 1534 (for horizontal polarizations of all four carriers C1, C2, C3, C4) may be combined by multiplexing packet data corresponding to vertically polarized signals of the four carriers C1, C2, C3, and C4 received at serial communication port 1530 to produce an IQ data packet stream to be sent on data link 1532 to serial data link transceiver 1506 for communication to the beamformer processor via serial communication link 1502. Note, however, that in alternative embodiments not involving time-domain to frequency-domain conversion (as indicated above), the frequency-domain IQ data for all four component carriers of each polarization may alternatively be combined in the time domain into a packet data stream (for transmission over bidirectional serial link 1502 (e.g., to the beamformer processor)).

[0199] Additionally, in Fig.15 In an embodiment, DL and UL signal processing are not performed symmetrically across the serially connected transceiver ICs: DL transmit signal processing is divided according to component carrier (both H and V polarities of C1 and C2 are processed in the first transceiver IC (1504a) and both polarities of C3 and C4 are processed in the second transceiver IC (1504b)), while UL receive signal processing is divided according to polarity (all H polarities of C1, C2, C3 and C4 are processed by the first transceiver IC (1504a) and all V polarities of C1, C2, C3 and C4 are processed by the second transceiver IC (1504b)). In some embodiments, this has the advantage on the transmit side of relaxing the bandwidth requirements on the transmit modulator to span only two component carriers (e.g., C1, C2 are processed in a first transceiver IC (1504a), and C3, C4 are processed in a second transceiver IC (1504b)), while having the advantage on the receive side of not splitting the receive RF signal to two different signal ports of two different transceiver ICs prior to processing via down-conversion and sampling via ADC. Thus, in the described embodiments, a dual-polarized four-component carrier system can be implemented using the wideband capabilities of the receiver portion of the transceiver IC to process receive signals having a bandwidth of four component carriers, while also relaxing the transmit modulator / amplifier bandwidth requirements to accommodate transmit signals having a bandwidth of only two component carriers.

Claims

1. A device, comprising: a plurality of transceiver integrated circuit (IC) subarrays, each transceiver IC subarray comprising at least a first transceiver IC and a second transceiver IC physically arranged in the subarray; The first transceiver IC has: a first serial digital data port providing a serial data connection to a beamformer processor, the first serial digital data port being configured to receive control message packets and a series of commonly processed aggregate signal port IQ data packets; a transmit signal processing circuit configured to process a series of commonly processed aggregate signal port IQ data packets based on (i) beam tilt information received in a control message packet and (ii) a subarray position of the first transceiver IC; and a second serial digital data port; and The second transceiver IC has: a third serial digital data port connected to the second serial data port of the first transceiver IC and providing a serial data connection to the first transceiver IC and configured to receive control message packets and a series of commonly processed aggregate signal port IQ data packets from the first transceiver IC; a transmit signal processing circuit configured to process a series of commonly processed aggregate signal port IQ data packets based on (i) beam tilt information received in a control message packet and (ii) an array position of the second transceiver IC; and A plurality of radiating antenna elements are arranged in an antenna subarray and are respectively positioned adjacent to the plurality of transceiver integrated circuit (IC) subarrays in an element-by-element manner.

2. An apparatus according to claim 1, wherein the transmission signal processing circuit is configured to perform one or more signal processing techniques selected from the group consisting of: (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO), (ii) applying constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), and (iv) applying a time delay in the discrete time domain signal of the transmission baseband signal.

3. The apparatus of claim 1 , wherein the first transceiver IC further comprises a receive signal processing circuit configured to process a series of commonly processed aggregate signal port IQ data packets based on (i) beam tilt information received in a control message packet and (ii) the subarray position of the first transceiver IC.

4. An apparatus according to claim 3, wherein the received signal processing circuit is configured to perform one or more signal processing techniques selected from the group consisting of: (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO), (ii) applying constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), and (iv) applying a time delay in the discrete time domain signal of the received baseband signal.

5. A method comprising: distributing beamformed frequency-domain IQ data packets to a plurality of serially connected transceiver ICs for common processing by the transceivers; At each transceiver IC, electronic beam tilt phase rotation is applied.

6. The method of claim 5, wherein applying beam tilt phase rotation comprises changing the phase of each IQ modulated subcarrier based on a desired antenna tilt and array position.

7. The method of claim 6, wherein the phase change is a constant phase rotation applied to all subcarriers, or a linearly increasing phase rotation that increases from subcarrier to subcarrier. The method of claim 6 , wherein the phase adjustment can be specified based on one or more control messages.

9. The method of claim 5, further comprising receiving a control message containing beam tilt information in the form of phase adjustment parameters selected from the group consisting of: time delay, frequency domain multiplicative rotation, time domain complex rotation, and phase index value.

10. The method of claim 5, wherein the electronic beam tilt comprises a coarse beam tilt adjustment and a fine beam tilt adjustment, wherein the coarse beam tilt adjustment is achieved by applying a linearly increasing phase rotation on the subcarrier and the fine beam tilt adjustment is achieved by further adjustment in the time domain.

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