Heterogeneous TSV chip reliability test device based on wire bonding

Abstract

The present invention relates to a wire-bonding-based heterogeneous TSV chip reliability test device, comprising: a heterogeneous TSV chip, a chip fixture, a test PCB board and a test unit; the heterogeneous TSV chip is mounted on the chip fixture; the chip fixture is mounted on the test PCB board; the test PCB board is mounted on the test unit; the heterogeneous TSV chip comprises: a silicon substrate and a plurality of TSV test link groups; the silicon substrate is provided with a plurality of test blocks, and each test block is provided with at least one TSV test link group; the TSV test link group comprises a plurality of TSV test links, and the link types of the plurality of TSV test links are different; between different test blocks, the number of TSV structures contained in TSV test links of the same type is different; each TSV test link is provided with three wire bonding parts, and the TSV test link is based on wire bonding between the wire bonding parts and pads of the test PCB board.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a heterogeneous TSV chip reliability test device based on wire bonding. Background Art

[0002] As advanced chip manufacturing processes advance toward 3 nm, transistor density on a wafer's two-dimensional plane is approaching physical limits, accompanied by a significant increase in chip R&D costs and a lengthening of development cycles. Consequently, "Moore's Law" has broken down. Consequently, three-dimensional integrated packaging based on through-silicon-via (TSV) structures has emerged. 3D integrated packaging integrates wafers vertically through TSVs and stacking, resulting in smaller, higher-bandwidth, lower-latency, and higher-performance packaged chips. It can also achieve heterogeneous integration with microelectromechanical systems (MEMS), resulting in functionally integrated, high-performance, and low-cost chip products. These significant advantages have garnered significant attention from both academia and engineering communities, and related products are gradually moving from the laboratory to market applications.

[0003] As Moore's Law gradually fades, the traditional technology approach of improving chip performance by increasing the two-dimensional density of transistors has reached a bottleneck. Consequently, three-dimensional integrated packaging based on through-silicon-via (TSV) structures has emerged. Three-dimensional integrated packaging integrates wafers vertically using TSVs, enabling smaller, higher-bandwidth, lower-latency, and higher-performance packaged chips. With the diversification of chip functionality, heterogeneous integration is also a major development path for semiconductor technology in the post-Moore era. Therefore, the fusion of three-dimensional integrated packaging and heterogeneous integration will be a key development direction for future high-performance chips. As a typical and key structure in three-dimensional integrated packaging, TSVs provide energy, signal routing, and mechanical support within the chip. Their reliability directly impacts chip performance and service life, necessitating scientific, comprehensive, and accurate reliability testing and evaluation.

[0004] However, for heterogeneous chips, the distribution of TSVs varies depending on their functional requirements. This means that TSVs in different locations are subject to varying degradation stresses, leading to significant differences in the performance and service life of different TSVs. This indicates that the layout of TSVs in heterogeneous chips and the presence of redundant structures have a significant impact on chip reliability. Current research on TSV structural reliability primarily relies on finite element thermal simulation, supplemented by experimental studies. The few experimental studies that have designed dedicated TSV test chips have not focused on the heterogeneity of the TSV interconnect structure within the chip, significantly limiting the reliability assessment of heterogeneous 3D integrated chips. Summary of the Invention

[0005] The object of the present invention is to provide a heterogeneous TSV chip reliability test device based on wire bonding.

[0006] To achieve the above-mentioned object of the invention, the present invention provides a wire-bonding-based heterogeneous TSV chip reliability test device, comprising: a heterogeneous TSV chip, a chip fixture, a test PCB board and a test unit;

[0007] The heterogeneous TSV chip is detachably mounted on the chip fixture;

[0008] The chip fixture is detachably mounted on the test PCB board;

[0009] The test PCB is detachably mounted on the test unit, and the test PCB is electrically connected to the test unit;

[0010] The heterogeneous TSV chip is connected to the test PCB board by wire bonding;

[0011] The heterogeneous TSV chip includes: a silicon substrate and a plurality of TSV test link groups arranged on the silicon substrate;

[0012] The silicon substrate is provided with a plurality of test blocks, and each of the test blocks is provided with at least one TSV test link group;

[0013] The TSV test link group includes multiple TSV test links, and the link types of the multiple TSV test links are different;

[0014] The number of TSV structures included in the TSV test links of the same type is different between different test blocks;

[0015] Each of the TSV test links is provided with three wire bonding parts, and the TSV test link is selectively wire-bonded with the pads of the test PCB board based on the wire bonding parts and using a Kelvin chain four-wire test method.

[0016] According to one aspect of the present invention, the TSV test link includes: a central TSV structure and a peripheral TSV structure;

[0017] There are multiple peripheral TSV structures, and the multiple peripheral TSV structures are regularly distributed on a circle with the central TSV structure as the center.

[0018] According to one aspect of the present invention, a plurality of first TSV test link groups are provided in a first test block of the silicon substrate;

[0019] The first TSV structure pitches adopted by the first TSV test links in different first TSV test link groups are different;

[0020] A plurality of second TSV test link groups are provided in a second test block of the silicon substrate;

[0021] The second TSV structure pitches adopted by the second TSV test links in different second TSV test link groups are the same or different;

[0022] The second central TSV structure of the second TSV test link in the second TSV test link group is an interconnected redundant structure composed of multiple TSV structures;

[0023] The number of TSV structures included in the second central TSV structures of different second TSV test link groups is different;

[0024] A plurality of third TSV test link groups are provided in a third test block of the silicon substrate;

[0025] The third TSV structure pitches adopted by the third TSV test links in different third TSV test link groups are the same or different;

[0026] A third surrounding TSV structure in the third TSV test link of the third TSV test link group is an interconnection redundant structure composed of multiple TSV structures;

[0027] In different third TSV test link groups, the number of TSV structures included in the third surrounding TSV structures using the interconnection redundancy structure is different;

[0028] A plurality of fourth TSV test link groups are provided in a fourth test block of the silicon substrate;

[0029] The fourth TSV structure pitches adopted by the fourth TSV test links in different fourth TSV test link groups are the same or different;

[0030] The fourth central TSV structure and the fourth peripheral TSV structure of the fourth TSV test link of the fourth TSV test link group are respectively interconnected redundant structures formed by multiple TSV structures;

[0031] In different fourth TSV test link groups, the number of TSV structures included in the fourth central TSV structure and the fourth peripheral TSV structure using the interconnection redundancy structure is different.

[0032] According to one aspect of the present invention, the second TSV structure pitches used by the second TSV test links of the plurality of second TSV test link groups are the same, the third TSV structure pitches used by the third TSV test links of the plurality of third TSV test link groups are the same, the fourth TSV structure pitches used by the fourth TSV test links of the plurality of fourth TSV test link groups are the same, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitch of the same first TSV test link; or,

[0033] The second TSV structure pitches adopted by the second TSV test links of the multiple second TSV test link groups are different, the third TSV structure pitches adopted by the third TSV test links of the multiple third TSV test link groups are different, and the fourth TSV structure pitches adopted by the fourth TSV test links of the multiple fourth TSV test link groups are different, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitches of different first TSV test links.

[0034] According to one aspect of the present invention, the TSV test link further comprises: a top electrode, a bottom electrode;

[0035] The top electrode and the bottom electrode are electrically connected to the central TSV structure and the surrounding TSV structure contained in each TSV test link based on the link type of the TSV test link;

[0036] The three wire bonding portions are arranged in one-to-one correspondence with the test points of the TSV test link, and the wire bonding portions are arranged on the upper side of the corresponding top electrodes;

[0037] One of the three wire bonding portions corresponds to the central TSV structure of the TSV test link, and the remaining wire bonding portions selectively correspond to the peripheral TSV structures.

[0038] According to one aspect of the present invention, the silicon substrate comprises: a silicon substrate, an oxide layer disposed on the upper side of the silicon substrate, an upper dielectric layer disposed on the upper side of the oxide layer, a lower first dielectric layer disposed on the lower side of the silicon substrate, and a lower second dielectric layer disposed on the lower side of the lower first dielectric layer;

[0039] The top electrode is arranged between the upper dielectric layer and the oxide layer;

[0040] The bottom electrode is disposed between the lower first dielectric layer and the lower second dielectric layer.

[0041] According to one aspect of the present invention, the chip fixture is in the form of a regular plate as a whole, and is provided with a chip mounting hole penetrating the body thereof;

[0042] The chip mounting hole is a stepped hole;

[0043] The heterogeneous TSV chip is detachably mounted in the chip mounting hole, wherein a transition fit is adopted between the heterogeneous TSV chip and the chip mounting hole.

[0044] According to one aspect of the present invention, the test PCB board is a regular board as a whole;

[0045] The test PCB is provided with a fixture installation area, a test area and a fixed installation area;

[0046] The pads are regularly arranged around the fixture mounting area;

[0047] At least one test area is provided on the test PCB board, and the test area is electrically connected to the pad;

[0048] The test area is provided with a plurality of test points corresponding one to one with the pads;

[0049] A plurality of fixed installation areas are provided along the circumference of the test PCB board, and each of the fixed installation areas is provided with a fixed installation structure for fixing the test PCB board body;

[0050] The chip fixture is detachably connected to the fixture mounting area.

[0051] According to one aspect of the present invention, the fixture installation area is configured as a through hole penetrating the test PCB board or as a groove opening on one side of the test PCB board, wherein the chip fixture (2) transitionally fits with the through hole or groove of the fixture installation area (3b);

[0052] The fixed installation structure is a through hole.

[0053] According to one aspect of the present invention, the test unit comprises:

[0054] A temperature and humidity test chamber, used to apply temperature stress and humidity stress to the heterogeneous TSV chip;

[0055] A vibration table, used for applying vibration stress to the heterogeneous TSV chip;

[0056] A power supply and signal generator, used to apply electrical stress to the heterogeneous TSV chip;

[0057] A signal acquisition device, electrically connected to the test PCB board, for collecting electrical signals;

[0058] The vibration table is installed in the temperature and humidity test box;

[0059] The test PCB is mounted on the vibration table based on the fixed installation area.

[0060] According to a solution of the present invention, this solution can not only realize single stress loading test, but also conveniently and comprehensively realize multi-stress loading (temperature, current / voltage, humidity, vibration) of actual heterogeneous TSV chips, realizing scientific, comprehensive and accurate evaluation of TSV structure reliability through experimental means.

[0061] According to a solution of the present invention, the heterogeneous TSV chip of this solution can realize the individual or combined lead-out of any TSV structure through the wire bonding part on one side, has a flexible and variable test sample volume, and has the characteristics of low cost, high flexibility and modularity, and can provide a hardware foundation for the reliability test and evaluation of the TSV structure.

[0062] According to a solution of the present invention, by setting electrodes on TSV, not only can diversified connections of multiple TSV structures be achieved, but also the lead-out of TSV structures can be conveniently achieved by wire bonding, which provides effective guarantee for the flexible testing of the present invention.

[0063] According to a solution of the present invention, the problem of difficulty in chip reliability testing based on wire bonding is effectively solved, and the test is stable, reliable, flexible and diverse, with low cost and high test efficiency.

[0064] According to one solution of the present invention, the heterogeneous TSV chip of the present invention can selectively implement multi-stress testing on a single TSV and multiple TSV links.

[0065] According to one solution of the present invention, during the implementation of the test, the natural frequency of the test device can be adjusted and corrected, thereby meeting the needs of vibration testing and improving the test flexibility and applicability of the solution.

[0066] According to one solution of the present invention, during the testing process, the present invention implements online testing of the electrical performance of different test loops based on the Kelvin chain four-wire test method, thereby clarifying the impact of factors such as TSV number, layout, and redundant structure on TSV reliability, and providing necessary calibration data and reference basis for the optimized design of heterogeneous TSV chips.

[0067] According to one solution of the present invention, the present invention provides more test ports to realize online testing of different TSV links, which can greatly improve test efficiency while ensuring the consistency of the service environment; at the same time, the present invention provides TSV test links under multiple distribution parameter combinations, which can directly clarify the direct impact of different distribution parameters on TSV reliability based on reliability testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 is a perspective view schematically showing a heterogeneous TSV chip according to an embodiment of the present invention;

[0069] Figure 2 The diagram schematically shows the distribution of heterogeneous TSV chips on a wafer, where (a) shows the link layout of the heterogeneous TSV chip, and (b) shows the TSV structure distribution diagram in the heterogeneous TSV chip;

[0070] Figure 3 is a three-dimensional structural diagram schematically showing a TSV test link according to an embodiment of the present invention;

[0071] Figure 4 Schematically shows a test block distribution diagram of a heterogeneous TSV chip according to an embodiment of the present invention;

[0072] Figure 5 is a cross-sectional view schematically showing a heterogeneous TSV chip according to one embodiment of the present invention;

[0073] Figure 6 is a structural diagram schematically showing a chip holder according to one embodiment of the present invention;

[0074] Figure 7 FIG2 is a diagram schematically showing a combined installation structure of a heterogeneous TSV chip and a chip fixture according to an embodiment of the present invention;

[0075] Figure 8 Schematically shows the structure of a test PCB board according to one embodiment of the present invention;

[0076] Figure 9 FIG2 is a diagram schematically showing a combined installation structure of a heterogeneous TSV chip, a chip fixture, and a test PCB board according to an embodiment of the present invention;

[0077] Figure 10 FIG. 1 is a diagram schematically showing a connection structure between a wire bonding portion and a pad according to an embodiment of the present invention. DETAILED DESCRIPTION

[0078] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0079] When describing the embodiments of the present invention, the orientation or positional relationship expressed by the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or positional relationship shown in the relevant drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0080] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments cannot be described one by one here, but the embodiments of the present invention are not limited to the following embodiments.

[0081] Combine Figure 1 、 Figure 2 、 Figure 3 and Figure 4 As shown, according to one embodiment of the present invention, a heterogeneous TSV chip reliability test device based on wire bonding of the present invention includes: a heterogeneous TSV chip 1, a chip fixture 2, a test PCB board 3 and a test unit; in this embodiment, the heterogeneous TSV chip 1 is detachably mounted on the chip fixture 2; the chip fixture 2 is detachably mounted on the test PCB board 3; the test PCB board 3 is detachably mounted on the test unit, and the test PCB board 3 is electrically connected to the test unit; wherein, the heterogeneous TSV chip 1 is wire-bonded to the test PCB board 3. In this embodiment, the heterogeneous TSV chip 1 includes: a silicon substrate 11 and a plurality of TSV test link groups 12 arranged on the silicon substrate 11; wherein, a plurality of test blocks are arranged on the silicon substrate 11, and each test block is provided with at least one TSV test link group 12; further, the TSV test link group 12 has a plurality of TSV test links 12a, and the link types of the plurality of TSV test links 12a are different; wherein, the TSV test links 12a in a TSV test link group 12 can be set to four to correspond to four link types respectively, which is specifically: 2, 4, 6, and 8 surrounding TSV structures are evenly arranged on the circumference of a circle with a central TSV structure as the center; of course, the TSV test links 12a in each TSV test link group 12 can also be set to other numbers, such as five, six, etc., to correspond to the increase or decrease of corresponding link types.

[0082] In this embodiment, the area of ​​each test block can be allocated according to the number of arranged TSV test link groups 12 and the number and distribution of TSV test links 12a. For example, four test blocks are provided on the silicon substrate 11, namely: a first test block A, a second test block B, a third test block C and a fourth test block D. Accordingly, according to the specific number and distribution of TSV test links 12a, the area of ​​the first test block A can be divided into the largest area, while the areas of the second test block B and the third test block C can be divided into the same area, and the area of ​​the fourth test block D can be the smallest. Among them, the TSV test links 12a in the first test block A, the second test block B, the third test block C and the fourth test block D are the largest. The number of 2a is set in a ratio of 4:2:2:1, so that there are a sufficient number of TSV test links 12a in the first test block A, which can be used to fully clarify the influence of the TSV structure pitch and the number of surrounding TSV structures on the reliability of the central TSV structure; the second test block B is used to clarify the influence of the number of surrounding TSV structures on the reliability of the central TSV structure under different redundancy forms; the third test block C is used to clarify the influence of the number of surrounding TSV structures and the surrounding TSV structures under different redundancy forms on the reliability of the central TSV structure; the fourth test block D is used to clarify the influence of the number of different surrounding TSV structures and redundancy forms on the reliability of the central TSV structure with different redundancy forms.

[0083] Therefore, through the chip structure set up as described above, each test block can have different effects. Therefore, for each test block, there is no need to repeatedly set the other three types of pitches in the first test block A, and the analysis of all the above-mentioned influencing factors can be achieved, which effectively reduces the complexity of the chip structure of the present invention.

[0084] In this embodiment, the number of TSV structures included in the TSV test link 12a of the same type is different between different test blocks. For example, the number of TSV structures included in the TSV test link 12a of the same type is different between the first test block A and the second test block B, the number of TSV structures included in the TSV test link 12a of the same type is different between the second test block B and the third test block C, and the number of TSV structures included in the TSV test link 12a of the same type is different between the third test block C and the fourth test block D.

[0085] In this embodiment, each TSV test link 12a is provided with three wire bonding parts 12aI, and the TSV test link 12a is selectively wire-bonded to the pads 3a of the test PCB board 3 based on the wire bonding parts 12aI and using the Kelvin chain four-wire test method.

[0086] Combine Figure 2 、 Figure 3 and Figure 4 As shown, according to one embodiment of the present invention, the TSV test link 12a includes: a central TSV structure 12a1 and a surrounding TSV structure 12a2; wherein, there are multiple surrounding TSV structures 12a2, and the multiple surrounding TSV structures 12a2 are regularly distributed on the circumference of the circle with the central TSV structure 12a1 as the center; specifically, the multiple surrounding TSV structures 12a2 are distributed at equal intervals on the circumference of the circle with the central TSV structure 12a1 as the center.

[0087] To further facilitate the description of this solution, the TSV test link groups 12 on each test block can be named respectively. The TSV test link group 12 on the first test block A is named the first TSV test link group 12A, the TSV test link 12a in the first TSV test link group 12A is named the first TSV test link 12aA, the central TSV structure 12a1 in the first TSV test link 12aA is named the first central TSV structure 12a1A, and the surrounding TSV structure 12a2 in the first TSV test link 12aA is named the first surrounding TSV structure 12a2A.

[0088] The TSV test link group 12 on the second test block B is named a second TSV test link group 12B, the TSV test link 12a in the second TSV test link group 12B is named a second TSV test link 12aB, the central TSV structure 12a1 in the second TSV test link 12aB is named a second central TSV structure 12a1B, and the surrounding TSV structure 12a2 in the second TSV test link 12aB is named a second surrounding TSV structure 12a2B.

[0089] The TSV test link group 12 on the third test block C is named a third TSV test link group 12C, the TSV test link 12a in the third TSV test link group 12C is named a third TSV test link 12aC, the central TSV structure 12a1 in the third TSV test link 12aC is named a third central TSV structure 12a1C, and the surrounding TSV structure 12a2 in the third TSV test link 12aC is named a third surrounding TSV structure 12a2C.

[0090] The TSV test link group 12 on the fourth test block D is named a fourth TSV test link group 12D, the TSV test link 12a in the fourth TSV test link group 12D is named a fourth TSV test link 12aD, the central TSV structure 12a1 in the fourth TSV test link 12aD is named a fourth central TSV structure 12a1D, and the surrounding TSV structure 12a2 in the fourth TSV test link 12aD is named a fourth surrounding TSV structure 12a2D.

[0091] Combine Figure 2 and Figure 4 As shown, according to one embodiment of the present invention, a plurality of first TSV test link groups 12A are provided in the first test block A of the silicon substrate 11; wherein, four first TSV test link groups 12A are provided in the first test block A, and each first TSV test link group 12A contains four first TSV test links 12aA of different types. In this embodiment, the first TSV structure pitches used by the first TSV test links 12aA in different first TSV test link groups 12A are different; specifically, between different first TSV test link groups 12A, the first TSV structure pitches of the same type of first TSV test links 12aA can be flexibly controlled by controlling the radius of the circumference of the first peripheral TSV structure 12a2A around the first central TSV structure 12a1A, wherein the first TSV structure pitches between adjacent first TSV test link groups 12A are arranged in a sequentially increasing manner, and the first TSV structure pitches selected in each first TSV test link group 12A are set according to actual measurement needs, as long as no interference occurs, and will not be further elaborated here.

[0092] Combine Figure 2 and Figure 4 As shown, according to one embodiment of the present invention, multiple second TSV test link groups 12B are provided in the second test block B of the silicon substrate 11. Two second TSV test link groups 12B are provided in the second test block B, and each second TSV test link group 12B contains four different types of second TSV test links 12aB. The four types of second TSV test links 12aB are consistent with the four types of first TSV test links 12aA. Accordingly, the second TSV structure pitches used by the second TSV test links 12aB in different second TSV test link groups 12B are the same or different.

[0093] In this embodiment, the second central TSV structure 12a1B of the second TSV test link 12aB in the second TSV test link group 12B is an interconnected redundant structure composed of multiple TSV structures; wherein, the number of TSV structures included in the second central TSV structure 12a1B of different second TSV test link groups 12B is different; specifically, the second central TSV structure 12a1B in one second TSV test link group 12B adopts an interconnected redundant structure composed of two TSV structures, and the second central TSV structure 12a1B in another second TSV test link group 12B adopts an interconnected redundant structure composed of four TSV structures. In this embodiment, in order to facilitate the reliable connection of multiple TSV structures, regular metal plates can be correspondingly set at the ends of multiple TSV structures to achieve mutual interconnection redundancy. If the metal electrode needs to be connected at the end of the TSV structure, the regular metal plate can be set integrally with the metal electrode. If the metal electrode does not need to be connected at the end of the TSV structure, the regular metal plate is set independently. When an interconnection redundant structure consisting of two TSV structures is adopted, the regular metal plate used is an oblong metal plate. If an interconnection redundant structure consisting of four TSV structures is adopted, the regular metal plate used is a circular metal plate. In this way, the layout position of adjacent TSV structures in each interconnection redundant structure can be unified.

[0094] Combine Figure 2 and Figure 4 As shown, according to one embodiment of the present invention, multiple third TSV test link groups 12C are provided in the third test block C of the silicon substrate 11. Specifically, two third TSV test link groups 12C are provided in the third test block C, and each third TSV test link group 12C contains four different types of third TSV test links 12aC. The four types of third TSV test links 12aC are consistent with the four types of first TSV test links 12aA. Accordingly, the third TSV test links 12aC in different third TSV test link groups 12C may have the same or different third TSV structure pitches.

[0095] In this embodiment, one of the third surrounding TSV structures 12a2C in the third TSV test link 12aC of the third TSV test link group 12C is an interconnected redundant structure composed of multiple TSV structures. For example, the second third surrounding TSV structure 12a2C clockwise from the port of the third TSV test link 12aC is configured as a redundant structure. Of course, other third surrounding TSV structures 12a2C may also be configured as redundant structures, but the control of a single variable (redundancy form, number of redundancies, and location of redundancies) must be ensured. The number of TSV structures included in the third surrounding TSV structures 12a2C that utilize an interconnected redundant structure varies between different third TSV test link groups 12C. Specifically, the third surrounding TSV structure 12a2C in one third TSV test link group 12C utilizes an interconnected redundant structure composed of two TSV structures, while the third surrounding TSV structure 12a2C in another third TSV test link group 12C utilizes an interconnected redundant structure composed of four TSV structures. In this embodiment, in order to facilitate the reliable connection of multiple TSV structures, regular metal plates can be correspondingly set at the ends of multiple TSV structures to achieve mutual interconnection redundancy. If the metal electrode needs to be connected at the end of the TSV structure, the regular metal plate can be set integrally with the metal electrode. If the metal electrode does not need to be connected at the end of the TSV structure, the regular metal plate is set independently. When an interconnection redundant structure consisting of two TSV structures is adopted, the regular metal plate used is an oblong metal plate. If an interconnection redundant structure consisting of four TSV structures is adopted, the regular metal plate used is a circular metal plate. In this way, the layout position of adjacent TSV structures in each interconnection redundant structure can be unified.

[0096] Combine Figure 2 and Figure 4 As shown, according to one embodiment of the present invention, a plurality of fourth TSV test link groups 12D are provided in a fourth test block D of a silicon substrate 11. Two fourth TSV test link groups 12D are provided in the fourth test block D, and each fourth TSV test link group 12D contains two fourth TSV test links 12aD of different types. The two types of fourth TSV test links 12aD are selected based on the four types of first TSV test links 12aA. Accordingly, the fourth TSV structure pitches used by the fourth TSV test links 12aD in different fourth TSV test link groups 12D may be the same or different.

[0097] In this embodiment, the fourth central TSV structure 12a1D and one fourth peripheral TSV structure 12a2D of the fourth TSV test link 12aD of the fourth TSV test link group 12D each utilize interconnected redundant structures comprised of multiple TSV structures. For example, the second fourth peripheral TSV structure 12a2D clockwise from the port of the fourth TSV test link 12aD is configured as a redundant structure. Of course, other fourth peripheral TSV structures 12a2D may also be configured as redundant structures, but control of a single variable (redundancy form, number of redundancies, and location of redundancies) must be ensured. Specifically, the number of TSV structures included in the fourth central TSV structure 12a1D and the fourth peripheral TSV structure 12a2D utilizing interconnected redundant structures varies across different fourth TSV test link groups 12D. Specifically, the fourth central TSV structure 12a1D and the fourth peripheral TSV structure 12a2D in one fourth TSV test link group 12D each employ an interconnection redundant structure consisting of two TSV structures, while the fourth central TSV structure 12a1D and the fourth peripheral TSV structure 12a2D in another fourth TSV test link group 12D each employ an interconnection redundant structure consisting of four TSV structures. In this embodiment, to facilitate reliable connection of multiple TSV structures, regular metal plates may be provided at the ends of the multiple TSV structures to achieve mutual interconnection redundancy. If metal electrodes need to be connected to the ends of the TSV structures, the regular metal plates may be provided integrally with the metal electrodes. If metal electrodes are not required to be connected to the ends of the TSV structures, the regular metal plates may be provided independently. When the interconnection redundant structure consisting of two TSV structures is employed, the regular metal plates employed are oblong metal plates. When the interconnection redundant structure consisting of four TSV structures is employed, the regular metal plates employed are circular metal plates. This facilitates uniform arrangement of adjacent TSV structures in each interconnection redundant structure.

[0098] Combine Figure 2 and Figure 4 As shown, according to one embodiment of the present invention, the second TSV structure pitches adopted by the second TSV test links 12aB of the plurality of second TSV test link groups 12B are the same, the third TSV structure pitches adopted by the third TSV test links 12aC of the plurality of third TSV test link groups 12C are the same, and the fourth TSV structure pitches adopted by the fourth TSV test links 12aD of the plurality of fourth TSV test link groups 12D are the same, and the second TSV structure pitch, the third TSV structure pitch, and the fourth TSV structure pitch are set based on the first TSV structure pitch of the same first TSV test link 12aA;

[0099] In another embodiment, the second TSV structure pitches adopted by the second TSV test links 12aB of the multiple second TSV test link groups 12B are different, the third TSV structure pitches adopted by the third TSV test links 12aC of the multiple third TSV test link groups 12C are different, and the fourth TSV structure pitches adopted by the fourth TSV test links 12aD of the multiple fourth TSV test link groups 12D are different, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitches of different first TSV test links 12aA, wherein the selected first TSV test link 12aA can be set according to specific actual needs, which will not be repeated here.

[0100] Combine Figure 3 and Figure 5 As shown, according to one embodiment of the present invention, the TSV test link 12a further includes: a top electrode 12a3 and a bottom electrode 12a4; wherein the top electrode 12a3 and the bottom electrode 12a4 are electrically connected to the central TSV structure 12a1 and the surrounding TSV structure 12a2 contained therein based on the link type of each TSV test link 12a; three wire bonding parts 12aI are set in one-to-one correspondence with the measuring points of the TSV test link 12a, and the wire bonding parts 12aI are set on the upper side of the corresponding top electrode 12a3; one of the three wire bonding parts 12aI corresponds to the central TSV structure 12a1 of the TSV test link 12a, and the remaining wire bonding parts 12aI selectively correspond to the surrounding TSV structures 12a2. For example, the remaining wire bonding parts 12aI are selected to be set at the surrounding TSV structures 12a2 at the head and tail of the TSV test link 12a.

[0101] In this embodiment, the wire bonding portion 12aI is a long strip of metal, which includes: a first bonding portion and a second bonding portion fixed to each other; wherein the first bonding portion and the second bonding portion are both long strips, and the second bonding portion is arranged at one end of the first bonding portion perpendicular to the first bonding portion; in this embodiment, the end of the first bonding portion away from the second bonding portion is electrically connected to the selected TSV structure. In this embodiment, if the TSV structure on which the wire bonding portion 12aI is installed adopts a redundant structure, the wire bonding portion 12aI is installed on the symmetry axis of the corresponding regular metal plate to achieve a balance in position relative to each TSV structure; wherein the wire bonding portion 12aI is welded to the regular metal plate. Furthermore, in order to achieve accurate and reliable relative position during installation, a corresponding fitting groove can be provided on the regular metal plate, thereby enabling the wire bonding portion 12aI to be welded to each other in a manner that cooperates with the fitting groove to avoid slippage and deviation of the wire bonding portion 12aI during the welding process.

[0102] like Figure 5 As shown, according to one embodiment of the present invention, the silicon substrate 11 includes: a silicon base 111, an oxide layer 112 arranged on the upper side of the silicon base 111, an upper dielectric layer 113 arranged on the upper side of the oxide layer 112, a lower first dielectric layer 114 arranged on the lower side of the silicon base 111, and a lower second dielectric layer 115 arranged on the lower side of the lower first dielectric layer 114; in this embodiment, the top electrode 12a3 is arranged between the upper dielectric layer 113 and the oxide layer 112; the bottom electrode 12a4 is arranged between the lower first dielectric layer 114 and the lower second dielectric layer 115.

[0103] like Figure 2 As shown, according to one embodiment of the present invention, the heterogeneous TSV chip 1 of the present invention is prepared based on 8-inch wafer tape-out, and is distributed on the wafer in a rectangular arrangement, wherein the heterogeneous TSV chip 1 adopts a square structure with a side length of L chip , the distance between them is L t , the diameter of the TSV structure is D TSV .

[0104] Combine Figure 6 and Figure 7 As shown, according to one embodiment of the present invention, the chip holder 2 is generally in the form of a regular plate, and a chip mounting hole 2a is provided on the chip holder 2 that passes through the body thereof. In this embodiment, the chip holder 2 is generally in the form of a square, and the chip mounting hole 2a is coaxially arranged at the center of the chip holder 2. Among them, the chip mounting hole 2a is a stepped hole; wherein, the chip mounting hole 2a includes a first mounting hole portion and a second mounting hole portion arranged coaxially, the outer dimensions of the first mounting hole portion are matched with the outer dimensions of the heterogeneous TSV chip 1, and the outer dimensions of the second mounting hole portion are smaller than the outer dimensions of the heterogeneous TSV chip 1, and then a step for the heterogeneous TSV chip 1 to contact is formed at the connection position of the first mounting hole portion and the second mounting hole portion, thereby realizing the detachable installation of the heterogeneous TSV chip 1 in the chip mounting hole 2a, wherein a transition fit is adopted between the heterogeneous TSV chip 1 and the chip mounting hole 2a, thereby ensuring a gap-free fit between the various structures to ensure the stability of the test structure during the test process (various load loading processes); further, the detachable connection method between the heterogeneous TSV chip 1 and the chip mounting hole 2a can be further combined with a threaded connection or a snap connection to achieve a stable connection.

[0105] In this embodiment, the structural dimension parameters of the chip holder 2 can be found in Table 1.

[0106] Table 1

[0107]

[0108] Combine Figure 8 and Figure 9 As shown, according to one embodiment of the present invention, the test PCB board 3 is generally a regular plate. Specifically, the test PCB board 3 is provided with a fixture installation area 3b, a test area 3c, and a fixed installation area 3d. The pads 3a are regularly arranged around the fixture installation area 3b. In this embodiment, at least one test area 3c is provided on the test PCB board 3, and the test area 3c is electrically connected to the pads 3a. In this embodiment, four test areas 3c can be provided, thereby achieving uniform distribution around the fixture installation area 3b to facilitate connection with the pads 3a around the fixture installation area 3b. The test area 3c is provided with multiple test points corresponding to the pads 3a. When electrically connecting the test PCB board 3 to the test unit, it can be connected to the test points on the test area 3c via wires, effectively avoiding the difficulty of directly connecting to the wire bonding portion 12aI in the TSV test link 12a. Furthermore, multiple fixed installation areas 3d are provided along the circumference of the test PCB board 3, and each fixed installation area 3d is provided with a fixed installation structure for fixing the main body of the test PCB board 3; the fixed installation structure provided can conveniently realize the fixed installation of the test PCB board 3, thereby improving the testing convenience of this solution.

[0109] In this embodiment, the chip clamp 2 is detachably connected to the clamp mounting area 3b.

[0110] Combine Figure 8 and Figure 9 As shown, according to one embodiment of the present invention, the fixture mounting area 3b is configured as a through-hole extending through the test PCB 3 or as a recess opening on one side of the test PCB 3. The dimensions of the fixture mounting area 3b are configured to match those of the heterogeneous TSV chip 1, thereby enabling accurate installation of the chip fixture 2. In this embodiment, if the fixture mounting area 3b is configured as a through-hole extending through the test PCB 3, the through-hole can also be configured as a stepped hole. The chip fixture 2 can be accurately positioned by abutting against the stepped hole. Similarly, if the fixture mounting area 3b is configured as a recess, accurate securing of the chip fixture 2 can also be achieved. A transition fit is employed between the chip fixture 2 and the fixture mounting area 3b, thereby ensuring a gap-free fit between the various structures and ensuring stability of the test structure during testing (including various load loading processes). Furthermore, the detachable connection between the chip fixture 2 and the fixture mounting area 3b can be further combined with threaded or snap-fit ​​connections to achieve a secure connection.

[0111] In this embodiment, the fixed installation structure is a through hole. By setting the fixed installation structure as a through hole, it is convenient for fasteners such as threaded connectors to pass through, thereby achieving fixed installation of the test PCB board 3.

[0112] According to one embodiment of the present invention, the test unit includes: a temperature and humidity test chamber, a vibration table, a power supply and signal generator, and a signal acquisition device; wherein, the temperature and humidity test chamber is used to load temperature stress and humidity stress on the heterogeneous TSV chip 1; the vibration table is used to load vibration stress on the heterogeneous TSV chip 1; the power supply and signal generator are used to load electrical stress on the heterogeneous TSV chip 1; the signal acquisition device is electrically connected to the test PCB board 3 for collecting electrical signals; in this embodiment, the vibration table is installed in the temperature and humidity test chamber; the test PCB board 3 is installed on the vibration table based on the fixed installation area 3d.

[0113] Through the above settings, this solution can conveniently implement single stress loading or multi-stress combination loading on the heterogeneous TSV chip 1 through the set test unit, effectively improving the test comprehensiveness of this solution.

[0114] To further illustrate this solution, the test process of this solution is further described with reference to the accompanying drawings.

[0115] (1) Clarify the test objectives, i.e., determine multiple stress types (e.g., at least one of temperature, humidity, electrical stress, and vibration) and load parameters (e.g., temperature range and loading cycle, humidity range and loading cycle, electrical stress range and loading cycle, vibration evaluation rate range and vibration magnitude), and the TSV test link (test object) of the heterogeneous TSV chip 1;

[0116] (2) Connect the wire bonding portion 12a1 of the TSV test link to be tested to the corresponding pad 3a of the test PCB board 3 by wire bonding (see Figure 10 ), and connect the test points of the corresponding test area 3c on the test PCB board 3 to the corresponding modules of the test unit (such as power supply and signal generator and / or signal acquisition device) through high temperature resistant silicone wires;

[0117] (3) The test PCB board 3 is mounted on a vibration table, and vibration tests, temperature stress tests, humidity stress tests, electrical stress tests, etc. are performed on the test PCB board 3, chip fixture 2, and heterogeneous TSV chip 1 assembly to achieve reliability testing and analysis under multiple stress states.

[0118] Through the above arrangement, the overall structure of the heterogeneous TSV chip 1, chip fixture 2, and test PCB board 3 in the present invention can conveniently implement multiple stress loading, thereby conveniently and flexibly implementing multiple stress reliability testing. Specifically, the heterogeneous TSV chip 1 can be mounted on the chip fixture 2 as a bare die, with both its upper and lower surfaces conveniently exposed to the test environment, fully enabling the reliability testing of the entire heterogeneous TSV chip 1 in a multi-stress environment.

[0119] The above contents are merely examples of specific solutions of the present invention. For devices and structures not described in detail, it should be understood that they can be implemented by adopting general devices and methods available in the art.

[0120] The above description is merely one embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A reliability test device for heterogeneous TSV chips based on wire bonding, characterized in that: include: Heterogeneous TSV chip (1), chip fixture (2), test PCB board (3) and test unit; The heterogeneous TSV chip (1) is detachably mounted on the chip fixture (2); The chip fixture (2) is detachably mounted on the test PCB board (3); The test PCB board (3) is detachably mounted on the test unit, and the test PCB board (3) is electrically connected to the test unit; The heterogeneous TSV chip (1) is connected to the test PCB board (3) by wire bonding; The heterogeneous TSV chip (1) comprises: a silicon substrate (11) and a plurality of TSV test link groups (12) arranged on the silicon substrate (11); The silicon substrate (11) is provided with a plurality of test blocks, and each of the test blocks is provided with at least one TSV test link group (12); The TSV test link group (12) comprises a plurality of TSV test links (12a), and the link types of the plurality of TSV test links (12a) are different; The number of TSV structures included in the TSV test link (12a) of the same type is different between different test blocks; Three wire bonding parts (12aI) are provided in each TSV test link (12a), and the TSV test link (12a) is selectively wire-bonded to the pads (3a) of the test PCB board (3) based on the wire bonding parts (12aI) and using a Kelvin chain four-wire test method; The TSV test link (12a) includes: a central TSV structure (12a1) and a peripheral TSV structure (12a2); There are multiple peripheral TSV structures (12a2), and the multiple peripheral TSV structures (12a2) are regularly distributed on a circle with the central TSV structure (12a1) as the center; The area of ​​each test block is allocated according to the number of arranged TSV test link groups (12) and the number and distribution of TSV test links (12a).

2. The heterogeneous TSV chip reliability test device according to claim 1, characterized in that: A plurality of first TSV test link groups (12A) are provided in a first test block of the silicon substrate (11); The first TSV test links (12aA) in different first TSV test link groups (12A) use different first TSV structure pitches; A plurality of second TSV test link groups (12B) are provided in a second test block of the silicon substrate (11); The second TSV structure pitches adopted by the second TSV test links (12aB) in different second TSV test link groups (12B) are the same or different; The second central TSV structure (12a1B) of the second TSV test link (12aB) in the second TSV test link group (12B) is an interconnected redundant structure composed of multiple TSV structures; The number of TSV structures included in the second central TSV structures (12a1B) of different second TSV test link groups (12B) is different; A plurality of third TSV test link groups (12C) are provided in a third test block of the silicon substrate (11); The third TSV structure pitches adopted by the third TSV test links (12aC) in different third TSV test link groups (12C) are the same or different; A third surrounding TSV structure (12a2C) in the third TSV test link (12aC) of the third TSV test link group (12C) is an interconnected redundant structure composed of multiple TSV structures; In different third TSV test link groups (12C), the number of TSV structures included in the third surrounding TSV structure (12a2C) adopting the interconnection redundant structure is different; A plurality of fourth TSV test link groups (12D) are provided in a fourth test block of the silicon substrate (11); The fourth TSV structure pitches adopted by the fourth TSV test links (12aD) in different fourth TSV test link groups (12D) are the same or different; The fourth central TSV structure (12a1D) and the fourth peripheral TSV structure (12a2D) of the fourth TSV test link (12aD) of the fourth TSV test link group (12D) are interconnected redundant structures formed by multiple TSV structures; In the fourth TSV test link group (12D), the number of TSV structures included in the fourth central TSV structure (12a1D) and the fourth peripheral TSV structure (12a2D) using the interconnection redundant structure is different.

3. The heterogeneous TSV chip reliability test device according to claim 2, characterized in that: The second TSV structure pitches adopted by the second TSV test links (12aB) of the plurality of second TSV test link groups (12B) are the same, the third TSV structure pitches adopted by the third TSV test links (12aC) of the plurality of third TSV test link groups (12C) are the same, the fourth TSV structure pitches adopted by the fourth TSV test links (12aD) of the plurality of fourth TSV test link groups (12D) are the same, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitch of the same first TSV test link (12aA); or, The second TSV structure pitches adopted by the second TSV test links (12aB) of the plurality of second TSV test link groups (12B) are different, the third TSV structure pitches adopted by the third TSV test links (12aC) of the plurality of third TSV test link groups (12C) are different, the fourth TSV structure pitches adopted by the fourth TSV test links (12aD) of the plurality of fourth TSV test link groups (12D) are different, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitches of different first TSV test links (12aA).

4. The heterogeneous TSV chip reliability test device according to claim 3, characterized in that: The TSV test link (12a) further includes: a top electrode (12a3) and a bottom electrode (12a4); The top electrode (12a3) and the bottom electrode (12a4) are electrically connected to the central TSV structure (12a1) and the surrounding TSV structure (12a2) contained in each TSV test link (12a) based on the link type of the TSV test link (12a); The three wire bonding parts (12aI) are arranged in one-to-one correspondence with the test points of the TSV test link (12a), and the wire bonding parts (12aI) are arranged on the upper side of the corresponding top electrodes (12a3); One of the three wire bonding portions (12aI) corresponds to the central TSV structure (12a1) of the TSV test link (12a), and the remaining wire bonding portions (12aI) selectively correspond to the peripheral TSV structures (12a2).

5. The heterogeneous TSV chip reliability test device according to claim 4, characterized in that: The silicon substrate (11) comprises: a silicon base (111), an oxide layer (112) arranged on the upper side of the silicon base (111), an upper dielectric layer (113) arranged on the upper side of the oxide layer (112), a lower first dielectric layer (114) arranged on the lower side of the silicon base (111), and a lower second dielectric layer (115) arranged on the lower side of the lower first dielectric layer (114); The top electrode (12a3) is arranged between the upper dielectric layer (113) and the oxide layer (112); The bottom electrode (12a4) is arranged between the lower first dielectric layer (114) and the lower second dielectric layer (115).

6. The heterogeneous TSV chip reliability test device according to claim 5, characterized in that: The chip fixture (2) is in the form of a regular plate as a whole, and is provided with a chip mounting hole (2a) penetrating the body of the chip fixture (2); The chip mounting hole (2a) is a stepped hole; The heterogeneous TSV chip (1) is detachably mounted in the chip mounting hole (2a), wherein a transition fit is adopted between the heterogeneous TSV chip (1) and the chip mounting hole (2a).

7. The heterogeneous TSV chip reliability test device according to claim 6, characterized in that: The test PCB board (3) is in the form of a regular plate as a whole; The test PCB board (3) is provided with a fixture installation area (3b), a test area (3c) and a fixed installation area (3d); The solder pads (3a) are regularly arranged around the fixture installation area (3b); At least one test area (3c) is provided on the test PCB board (3), and the test area (3c) is electrically connected to the soldering pad (3a); The test area (3c) is provided with a plurality of test points corresponding one-to-one to the pads (3a); A plurality of fixed installation areas (3d) are provided along the circumference of the test PCB board (3), and each of the fixed installation areas (3d) is provided with a fixed installation structure for fixing the body of the test PCB board (3); The chip fixture (2) is detachably connected to the fixture mounting area (3b).

8. The heterogeneous TSV chip reliability test device according to claim 7, characterized in that: The fixture installation area (3b) is configured as a through hole penetrating the test PCB board (3) or as a groove opening on one side of the test PCB board (3), wherein the chip fixture (2) is transitionally matched with the through hole or groove of the fixture installation area (3b); The fixed installation structure is a through hole.

9. The heterogeneous TSV chip reliability test device according to claim 8, characterized in that: The test unit includes: A temperature and humidity test chamber, used for applying temperature stress and humidity stress to the heterogeneous TSV chip (1); A vibration table, used for applying vibration stress to the heterogeneous TSV chip (1); A power supply and signal generator, used for applying electrical stress to the heterogeneous TSV chip (1); A signal acquisition device, electrically connected to the test PCB board (3), for collecting electrical signals; The vibration table is installed in the temperature and humidity test box; The test PCB board (3) is installed on the vibration table based on the fixed installation area (3d).

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