Display panel and display device

Abstract

The invention relates to a display panel and a display device, and the display panel comprises a first insulating layer which is located between an active layer and a first metal layer; the first insulating layer is provided with a first through hole; the planarization layer is located between the first metal layer and the pixel electrode layer; the planarization layer is provided with a second through hole; the first electrode is electrically connected with the active layer through the first through hole; the connecting part of the pixel electrode is electrically connected with the first electrode through the second through hole; the first through hole and the second through hole are overlapped along the direction perpendicular to the plane where the substrate is located. By compressing the physical area of the hole area, the purpose of compressing the size of the shading layer is achieved, then the aperture opening ratio of pixels is increased, and the overall penetration rate of the display panel is increased.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to meet customers' outdoor use needs and enhance product competitiveness, the demand for brightness is increasing. To achieve high brightness of the display panel, it is necessary to increase the number of lamps and the corresponding driving circuit. This solution is costly and will also generate large power consumption, which cannot meet the current market demand for low-cost and long battery life. At present, improving the transmittance of the LCD panel has become the preferred solution to increase the brightness of the LCD module.

[0003] Therefore, how to improve the transmittance of the display panel to enhance the brightness of the display panel is a problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a display panel and a display device.

[0005] In a first aspect, the present disclosure provides a display panel, comprising:

[0006] substrate;

[0007] An active layer, located on one side of the substrate;

[0008] A first metal layer, located on a side of the active layer away from the substrate, the first metal layer comprising a first electrode;

[0009] A first insulating layer, located between the active layer and the first metal layer; the first insulating layer is provided with a first through hole;

[0010] a pixel electrode layer, located on a side of the first metal layer away from the substrate; the pixel electrode layer comprises a plurality of pixel electrodes; the pixel electrodes comprise a main body portion and a connecting portion electrically connected to each other, the main body portion and the connecting portion being arranged along a first direction;

[0011] A planarization layer, located between the first metal layer and the pixel electrode layer; the planarization layer is provided with a second through hole;

[0012] The first electrode is electrically connected to the active layer through the first through hole; the connecting portion of the pixel electrode is electrically connected to the first electrode through the second through hole;

[0013] Along a direction perpendicular to a plane where the substrate is located, the first through hole overlaps with the second through hole.

[0014] In a second aspect, the present disclosure further provides a display device, comprising any display panel as provided in the first aspect.

[0015] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0016] In the display panel provided by the present disclosure, the first insulating layer is provided with a first through hole, and the second through hole is provided after being flattened. In the prior art, the first through hole and the second through hole do not overlap in the direction perpendicular to the plane where the substrate is located, so the physical area occupied by the two is relatively large, resulting in a relatively large area that needs to be covered by the light-shielding layer. However, the first through hole provided by the present disclosure and the second through hole on the flattening layer overlap in the direction perpendicular to the plane where the substrate is located, reducing the space occupied by the two through holes. Therefore, the purpose of compressing the size of the light-shielding layer can be achieved by compressing the physical area of ​​the hole area, thereby increasing the aperture ratio of the sub-pixel and improving the overall penetration rate of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 It is a schematic diagram of a partial structure of a display panel in the prior art;

[0020] Figure 2 A schematic diagram of a partial structure of a display panel provided in an embodiment of the present disclosure;

[0021] Figure 3 A method for providing an embodiment of the present disclosure Figure 2 Schematic diagram of the membrane structure cut at A1A1';

[0022] Figure 4 A schematic diagram of a partial structure of a display panel provided in an embodiment of the present disclosure;

[0023] Figure 5 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0024] Figure 6 A method for providing an embodiment of the present disclosure Figure 5 Schematic diagram of the membrane structure cut at A2A2';

[0025] Figure 7 A method for providing an embodiment of the present disclosure Figure 5 Schematic diagram of the membrane structure cut at A3A3';

[0026] Figure 8 A schematic diagram of a local structure of a hole area provided in an embodiment of the present disclosure;

[0027] Fig. 9 A schematic diagram of the actual structure of an overlapping area of ​​a first through hole and a second through hole provided in an embodiment of the present disclosure;

[0028] Fig.10 A schematic diagram of a display effect of a display panel provided in an embodiment of the present disclosure;

[0029] Fig.11 A schematic diagram of a partial structure of another hole area provided in an embodiment of the present disclosure;

[0030] Fig.12 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0031] Fig.13 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0032] Fig.14 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0033] Fig.15 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0034] Fig.16 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0035] Fig.17 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present disclosure;

[0036] Fig.18 A schematic diagram of a membrane layer structure provided in an embodiment of the present disclosure;

[0037] Fig.19 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0038] Fig. 20 The embodiment of the present disclosure provides a Fig.19 Schematic diagram of the membrane structure cut at A5A5';

[0039] Fig.21 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0040] Fig. 22 A method for providing an embodiment of the present disclosure Fig.21 Schematic diagram of the membrane layer structure intercepted by A6A6'. DETAILED DESCRIPTION

[0041] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0043] Figure 1 is a schematic diagram of a partial structure of a display panel in the prior art, referring to Figure 1 The display panel includes an array substrate and a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. The array substrate usually has a plurality of sub-pixels arranged in an array and is provided with a plurality of data lines and scan lines, and the color filter substrate is provided with opening areas corresponding to the plurality of sub-pixels one by one, and the area of ​​the opening area is smaller than the sub-pixel. The color filter substrate includes a shading layer, such as a black matrix (BM), and the shading layer is also provided with openings. The shading layer can cover the area of ​​the color filter substrate except the opening area.

[0044] Figure 1 Only a partial structural schematic diagram of the array substrate is provided, and the structure is explained by taking a sub-pixel as an example. Figure 1It includes a pixel electrode 101, a data line 102 and a scan line 103, wherein the data line 102 extends along a first direction, for example, along the Y direction, and the scan line 103 extends along a second direction, for example, along the X direction, and the first direction intersects with the second direction. The data line 102 intersects with the scan line 103 to form a plurality of sub-pixels. The sub-pixel is provided with a gate, an active layer 104, a source / drain 105 and a pixel electrode 101, wherein the gate is electrically connected to the scan line 103, an active layer 104 is provided above the gate, and the active layer is also in contact with the source / drain 105. The gate is not shown in the figure, but it can be understood that it is provided below the active layer 104 and connected to the scan line 103. The pixel electrode 101 is electrically connected to the active layer 104 via the source / drain electrode 105. Since there are other film layers between the active layer 104 and the pixel electrode 101, such as an insulating layer and a planarization layer, it is usually necessary to set a through hole in the insulating layer and the planarization layer. For example, the source / drain electrode 105 is electrically connected through a through hole in the insulating layer between the source / drain electrode 105 and the active layer 104, and the pixel electrode 101 is electrically connected through a through hole in the planarization layer between the pixel electrode 101 and the source / drain electrode 105. The through hole is usually set at Figure 1 The hole region 106 in the circuit does not show the specific position relationship and size of each hole, but is only used to show the position. The source / drain electrode 105 can be used as the source electrode or the drain electrode of the thin film transistor according to its actual function.

[0045] In the prior art, the insulating layer through holes and the planarization layer through holes do not overlap in the direction perpendicular to the plane where the substrate is located, so as to avoid the formation of a large film layer step difference caused by the superposition of the insulating layer through hole depth and the planarization layer through hole depth, which brings difficulties to the overlap of the pixel electrode and the source / drain 105. This also leads to a large physical area occupied by the insulating layer through holes and the planarization layer through holes. In order to avoid the hole area being exposed, the size of the light shielding layer on the color filter substrate also needs to be designed to be larger to completely cover the hole area to avoid the hole area being unobstructed, which poses a risk of contrast deterioration. The data line 101, the scanning line 102, the source and drain 105, etc. are all covered by the light shielding layer, and the sub-pixel aperture ratio is low, resulting in a low penetration rate, and the display panel cannot reduce power consumption.

[0046] In order to solve the above defects, the present disclosure provides a display panel. Figure 2 A partial structural diagram of a display panel provided in an embodiment of the present disclosure is shown in FIG. Figure 3 A method for providing an embodiment of the present disclosure Figure 2 The schematic diagram of the film structure cut by A1A1' in the embodiment of the present disclosure is mainly for Figure 1 The A area in is improved, so Figure 2 and Figure 3 Only a part of the structure of the sub-pixel is shown and explained.

[0047] refer to Figure 2 and Figure 3 The display panel includes: a substrate 210 , an active layer 220 , a first metal layer 230 , a first insulating layer 240 , a pixel electrode layer 250 and a planarization layer 260 .

[0048] The active layer 220 is located on one side of the substrate 210 .

[0049] The first metal layer 230 is located on a side of the active layer 220 facing away from the substrate 210 . The first metal layer 230 includes a first electrode 231 .

[0050] The first insulating layer 240 is located between the active layer 220 and the first metal layer 230 ; the first insulating layer 240 is provided with a first through hole 241 .

[0051] The pixel electrode layer 250 is located on the side of the first metal layer 230 away from the substrate 210; the pixel electrode layer 250 includes a plurality of pixel electrodes 251; the pixel electrode 251 includes a main body 2511 and a connecting part 2512 electrically connected to each other, and the main body 2511 and the connecting part 2512 are arranged along the first direction.

[0052] The planarization layer 260 is located between the first metal layer 230 and the pixel electrode layer 250 ; the planarization layer 260 is provided with a second through hole 261 .

[0053] The first electrode 231 is electrically connected to the active layer 220 through the first through hole 241 ; the connection portion 2512 of the pixel electrode 251 is electrically connected to the first electrode 231 through the second through hole 261 .

[0054] Along a direction perpendicular to the plane where the substrate is located, the first through hole 241 overlaps with the second through hole 261 .

[0055] Exemplarily, the display panel includes a substrate 210, which may be a rigid substrate such as glass or a flexible substrate such as PI (Polyimide) for supporting and protecting the film layer thereon. The present disclosure does not specifically limit the material of the substrate 210.

[0056] The display panel includes an array substrate, which may include a substrate 210 and thin film transistors arranged in an array on the substrate 210, and the thin film transistors include an active layer, a gate, a source electrode and a drain electrode, wherein the gate electrode, the source electrode and the drain electrode may be formed by a metal layer.

[0057] Specifically, the active layer 220 and the first metal layer 230 are disposed on one side of the substrate 210 , and the first metal layer is located on the side of the active layer 220 facing away from the substrate 210 .

[0058] The material of the active layer 220 includes any one of amorphous silicon, polycrystalline silicon, and oxide semiconductor.

[0059] The first metal layer 230 includes a first electrode 231, and the first electrode 231 is electrically connected to the active layer 220, wherein the first electrode 231 is a source electrode or a drain electrode. An insulating layer 240 is also provided between the active layer 220 and the first metal layer 230 to isolate other signal lines from contacting the active layer 220 to avoid signal crosstalk. However, the first electrode 231 formed by the first metal layer 230 needs to be electrically connected to the active layer 220, and thus, a first through hole 241 is provided on the first insulating layer 240, so that the first electrode 231 can be electrically connected to the active layer 220 through the first through hole 241 for signal transmission.

[0060] The first insulating layer 240 is located between the active layer 220 and the first metal layer 230. Figure 3 and Fig.18 As shown, the first insulating layer 240 may include a gate insulating layer 242 and an interlayer insulating layer 243 which are stacked, the gate insulating layer 242 being located between the active layer 220 and the gate 290, and the interlayer insulating layer 243 being located between the gate 290 and the first metal layer 230. The material forming the first insulating layer 24 may be any one of SiNx, SiON, SiO2, etc., and may be formed by chemical vapor deposition, physical vapor deposition, atomic force deposition, etc. The first insulating layer 240 includes the gate insulating layer 242 and the interlayer insulating layer 243, and a through hole, i.e., a first through hole 241, may be formed in the same process step. The first through hole 241 penetrates the gate insulating layer 242 and the interlayer insulating layer 243, and the depth of the first through hole 241 is the sum of the thickness of the gate insulating layer 242 and the thickness of the interlayer insulating layer 243. In other embodiments, the first insulating layer 240 can be a single-layer insulating layer. For example, the film layer structure of the array substrate includes a substrate, a gate, a gate insulating layer, an active layer, an interlayer insulating layer, and a source / drain layer stacked in sequence. In this case, the first insulating layer can only include an interlayer insulating layer, and the first through hole penetrates the interlayer insulating layer, and the depth of the first through hole is the thickness of the interlayer insulating layer.

[0061] The display panel further includes a pixel electrode layer 250, which is located on the side of the first metal layer 230 away from the substrate 210. The pixel electrode layer 250 includes a plurality of pixel electrodes 251, and each pixel electrode 251 includes a main body 2511 and a connecting portion 2512 that are electrically connected to each other. The main body 2511 is at least partially located in the opening area of ​​the sub-pixel, and the main body 2511 can cooperate with the common electrode to provide an electric field for driving the liquid crystal molecules to rotate, while the connecting portion 2512 is electrically connected to the first electrode 231. The main body 2511 and the connecting portion 2512 are arranged along a first direction, that is, arranged along the Y direction, and the first direction is a direction parallel to the plane where the substrate 210 is located. The pixel electrode layer 250 is a transparent conductive layer, and the material of the pixel electrode 251 may include indium tin oxide (ITO).

[0062] In the process of preparing the display panel, a thin film transistor structure can be made by stacking film layers. Since the film layers in the thin film transistor have different patterns, the film layers are stacked to form an upper surface with a concave-convex structure. In order to provide a flat surface for the pixel electrode layer prepared later, a flattening layer 260 is also provided to play the role of a flat film layer. The material forming the flattening layer 260 can be a transparent resin or other transparent insulating material, such as an acrylic polymer or a silicon polymer, and can be formed by inkjet printing, spraying, etc. The flattening layer 260 can be provided between the first metal layer 230 and the pixel electrode layer 250. The pixel electrode 251 needs to be electrically connected to the first electrode 231. Therefore, a second through hole 261 is provided on the flattening layer 260 so that the connecting portion 2512 of the pixel electrode 251 can contact the first electrode 231 through the second through hole 261. The thickness of the planarization layer 260 is greater than that of the first insulating layer 240 . For example, the thickness of the planarization layer 260 is 3 to 5 times that of the first insulating layer 240 . The area of ​​the overlapping region between the first through hole 241 of the first insulating layer 240 and the second through hole 261 of the planarization layer 260 needs to be considered.

[0063] It should be noted that Figure 2 and Figure 3 The cross-sectional position does not reflect that the first electrode 231 is electrically connected to the connecting portion 2512 of the pixel electrode 251, but only reflects that the planarization layer is provided with a second through hole 261, but does not mean that the first electrode 231 is not in contact with the pixel electrode 251, but the content reflected in the cross-sectional position is different.

[0064] In addition, reference Figure 2 The display panel is also provided with a light shielding layer 200 to completely cover the hole area to avoid the risk of contrast deterioration due to the hole area being unblocked. The light shielding layer 200 can be provided on the color filter substrate or on the array substrate. The embodiment of the present disclosure does not limit this, as long as it can play a shielding role. Figure 2The light shielding layer provided in the figure is only used to illustrate the relative position relationship between the light shielding layer and other structures when viewed from a line of sight perpendicular to the plane where the display panel is located. It is not limited to whether the light shielding layer is located in the array substrate or in the color filter substrate. Figure 2 The same understanding as the shading layer.

[0065] In the prior art, the first through hole 241 and the second through hole 261 are usually located in different areas, that is, the first through hole 241 and the second through hole 261 do not overlap in area A, and the area where the first through hole 241 and the area where the second through hole 261 are located need to be covered by the light shielding layer 200 to avoid exposure of the hole area, resulting in problems such as metal reflection. Therefore, the area of ​​the light shielding layer 200 is too large, and the area of ​​the opening area is limited, which affects the penetration rate of the display panel. Based on this, the embodiment of the present disclosure overlaps the first through hole 241 and the second through hole 261 in a direction perpendicular to the plane where the substrate 210 is located, reducing the space occupied by the first through hole 241 and the second through hole 261 in a direction parallel to the plane where the substrate 210 is located, thereby achieving the purpose of compressing the hole area. The area occupied by the hole area is reduced, and the area that needs to be covered by the light shielding layer 200 is also reduced accordingly, thereby increasing the size of the opening area of ​​the sub-pixel and improving the aperture ratio.

[0066] Specifically, Figure 2 and Figure 3 As shown, for example, the first direction is the Y direction, and the first through hole 241 and the second through hole 261 overlap in the first direction Y. The overlap of the two through holes in the first direction can be understood as adjusting the relative positions of the first through hole 241 and the second through hole 261 along the first direction Y so that in the direction perpendicular to the plane where the substrate 210 is located, there is an overlapping area between the area where the first through hole 241 is located and the area where the second through hole 261 is located, and the size of the second through hole 261 in the first direction Y and the size in the second direction X can both be larger than the corresponding size of the first through hole 241, and the edges of the first through hole 241 and the second through hole 261 extending along the second direction overlap. In the prior art, the first through hole and the second through hole are usually arranged along the first direction Y and do not overlap, resulting in a larger occupied area. After overlapping, the total length of the hole area formed by the two through holes in the first direction Y is reduced, thereby reducing the hole area and improving the aperture ratio.

[0067] In the display panel provided by the present disclosure, the first insulating layer is provided with a first through hole, and the planarization layer is provided with a second through hole. In the prior art, the first through hole and the second through hole do not overlap in the direction perpendicular to the plane where the substrate is located, so the physical area occupied by the two is relatively large, resulting in a relatively large area that needs to be covered by the light-shielding layer 200. However, the first through hole on the first insulating layer and the second through hole on the planarization layer provided by the present disclosure overlap in the direction perpendicular to the plane where the substrate is located, thereby reducing the space occupied by the two through holes. Therefore, the physical area of ​​the hole area can be compressed to achieve the purpose of compressing the size of the light-shielding layer, thereby increasing the aperture ratio of the sub-pixel and improving the overall penetration rate of the display panel.

[0068] It should be noted that the embodiment of the present disclosure does not specifically limit the overlapping position of the first through hole 241 and the second through hole 261. Figure 2 As shown, the side walls of the first through hole 241 and the second through hole 261 on the side of the main body 2511 close to the pixel electrode 251 overlap, that is, the side wall of the second through hole 261 is located in the first through hole 241, and the second through hole 261 partially overlaps with the first through hole 241. The first through hole 241 can also overlap with other side walls, which can compress the physical area of ​​the hole area and increase the area of ​​the opening area.

[0069] In some embodiments, Figure 4 A partial structural diagram of a display panel provided in an embodiment of the present disclosure, referring to Figure 4 In the second direction, the second through hole 261 includes a first side wall a1 and a second side wall a2 opposite to each other, and the second direction intersects the first direction. In the direction perpendicular to the plane where the substrate is located, the first through hole 241 at least overlaps with the first side wall a1 of the second through hole 261.

[0070] Exemplarily, the first direction is the Y direction, the second direction is the X direction, the first direction intersects with the second direction, and the first direction Y and the second direction X are both parallel to the plane where the substrate is located. In the second direction X, the second through hole 261 includes a first side wall a1 and a second side wall a2. In order to compress the physical area of ​​the hole area, the embodiment of the present disclosure needs to overlap the first through hole 241 with the second through hole 261. For example, in a direction perpendicular to the plane where the substrate is located, the first through hole 241 at least overlaps with the first side wall a1 of the second through hole 261, and the planarization layer 260 partially fills the first through hole 241. The area of ​​the first through hole 241 not filled by the planarization layer 260 can be covered by the passivation layer 280. In order to achieve the purpose of compressing the hole area and increasing the aperture ratio, thereby improving the penetration rate of the display panel. The first through hole overlaps with the first side wall a1 of the second through hole 261, which reduces the length of the hole area in the first direction Y to a certain extent. Therefore, the physical area of ​​the hole area can be compressed in the first direction Y to achieve the purpose of compressing the size of the light shielding layer, specifically, to achieve the purpose of compressing the size of the light shielding layer extending along the second direction X in the first direction Y, thereby improving the aperture ratio of the sub-pixel and the overall transmittance of the display panel. Figure 4 The first through hole 241 only overlaps with the first side wall a1 of the second through hole 261, thereby minimizing the length of the hole region in the first direction Y.

[0071] In some embodiments, Figure 5 A partial structural diagram of another display panel provided in an embodiment of the present disclosure is shown. Figure 6 A method for providing an embodiment of the present disclosure Figure 5 Schematic diagram of the membrane structure cut by A2A2'. Figure 7 A method for providing an embodiment of the present disclosure Figure 5 Schematic diagram of the membrane structure cut by A3A3', refer to Figure 5-Figure 7 In the first direction, the second through hole 261 includes a third side wall a3 and a fourth side wall a4 opposite to each other, and along the direction perpendicular to the plane where the substrate is located, the first through hole 241 also overlaps with the third side wall a3.

[0072] Exemplarily, the first direction is the Y direction, and the second direction is the X direction. The second through hole 261 includes a first side wall a1 and a second side wall a2 opposite to each other in the second direction X, and includes a third side wall a3 and a fourth side wall a4 opposite to each other in the first direction Y. Among them, the third side wall a3 is close to the sub-pixel of the sub-pixel, that is, the distance between the third side wall a3 and the main body 2511 of the pixel electrode 251 of the sub-pixel is closer, and the fourth side wall a4 is far away from the main body 2511 of the sub-pixel. In the embodiment of the present disclosure, the first through hole 241 overlaps with the first side wall a1 and the third side wall a3 of the second through hole 261. Figure 5 It can be seen that Figure 5The first through hole 241 overlaps the first side wall a1 and the third side wall a3 of the second through hole 261, which reduces the space occupied by the first through hole 241 in the first direction Y and the second direction X, and reduces the physical area occupied by the hole area. Figure 5 By intercepting the position of A2A2' in Figure 6 ,Depend on Figure 6 It can be seen that part of the first through hole 241 overlaps with the second through hole 261. The first through hole 241 is located at the upper right corner of the second through hole 261, and the first through hole 241 and the second through hole 261 overlap in a direction perpendicular to the plane where the substrate is located, thereby reducing the space occupied by the two through holes, and the length of the hole area can be compressed in both the first direction Y and the second direction X, and then the physical area of ​​the hole area is compressed, so as to achieve the purpose of compressing the size of the light shielding layer, improve the aperture ratio of the sub-pixel, and improve the overall penetration rate of the display panel.

[0073] Furthermore, since the overlapping area is located at the corner of the second through hole 261, the first through hole 241 can be prevented from overlapping with other through holes in the second through hole 261, thereby preventing the display effect of the display panel from being affected. For example, the second through hole 261 includes a through hole 281 of the passivation layer 280, and the through hole of the passivation layer is used to electrically connect the pixel electrode 251 to the first electrode 231, and the overlap of the first through hole 241 with the through hole may affect the performance of the pixel electrode 251 and the first electrode 231. By overlapping the first through hole 241 with the first side wall a1 and the third side wall a3 of the second through hole 261, that is, arranging the first through hole 241 at the upper right corner of the second through hole 261, the first through hole 241 can be prevented from overlapping with the through hole 281 of the passivation layer 280, thereby preventing the performance of the display panel from being affected.

[0074] In some embodiments, Figure 8 A schematic diagram of a local structure of a hole area provided in an embodiment of the present disclosure, referring to Figure 8 The overlapping area of ​​the first through hole 241 and the second through hole 261 has a first size along the first direction and a second size along the second direction, and the first size is greater than or equal to the second size; wherein the second direction intersects with the first direction.

[0075] For example, Figure 8As shown, for example, the first direction is the Y direction, the second direction is the X direction, and the first direction intersects the second direction. The first through hole 241 overlaps with the second through hole 261 in a direction perpendicular to the plane where the substrate is located, and the first side wall a1 and the third side wall a3 of the first through hole 241 and the second through hole 261 overlap, thereby reducing the total length of the two through holes in the first direction Y and the total length of the two through holes in the second direction X, thereby compressing the hole area. Among them, the overlapping area of ​​the first through hole 241 and the second through hole 261 has a first dimension h1 along the first direction Y and a second dimension h2 along the second direction, and the first dimension h1 and the second dimension h2 are the lengths reduced in each direction after overlapping. Reference Figure 2 , considering the structure of the sub-pixel, the pixel electrode 251 and the opening area both extend along the first direction Y, and the area where each through hole is set is closer to the opening area of ​​the sub-pixel in the first direction Y, that is, close to the main body of the pixel electrode. By adjusting the size of the light-shielding layer 200 covering the first direction Y, it is easier to improve the aperture ratio. Therefore, the larger the overlapping area between the first through hole 241 and the second through hole 261 in the first direction Y, the smaller the physical space occupied by the hole area in the first direction Y. Therefore, the area that needs to cover the light-shielding layer 200 will also be correspondingly smaller to improve the aperture ratio of the sub-pixel. Therefore, in the embodiment of the present disclosure, the first size h1 is greater than or equal to the second size h2. For example, the area of ​​the overlapping area between the first through hole and the second through hole is a constant value of 5.4um. 2 In the embodiment of the present disclosure, h1 can be 3um and h2 can be 1.8um. ​​The physical space occupied by the through hole is minimized in the first direction Y, and the aperture ratio of the sub-pixel is improved. By setting the size of the overlapping area of ​​the first through hole 241 and the second through hole 261 in the first direction Y to be greater than or equal to its size in the second direction X, in addition to reducing the size of the hole area in the first direction Y, it can also ensure that the area of ​​the overlapping area of ​​the first through hole 241 and the second through hole 261 is not too small, reducing the obvious impact of process fluctuations on the overlap amount, and at the same time, it can also avoid overlapping with the through hole of the passivation layer.

[0076] In some embodiments, the overlapping area of ​​the first through hole and the second through hole may be 10%-30% of the area of ​​the second through hole.

[0077] In some embodiments, the overlapping area of ​​the first through hole and the second through hole is 15%-20% of the area of ​​the second through hole.

[0078] Exemplarily, after the first through hole overlaps with the second through hole, the physical area of ​​the hole area can be compressed to achieve the purpose of compressing the size of the light-shielding layer, thereby increasing the aperture ratio of the sub-pixel and the overall penetration rate of the display panel. However, in order to avoid affecting the display effect of the display panel, the overlapping area of ​​the first through hole and the second through hole should be limited. If the overlapping area of ​​the first through hole and the second through hole is too small, under the influence of the process, once there are dimensional fluctuations in the various film layers, through holes and other structures of the display panel, there will be large differences in the area of ​​the overlapping areas of the holes in different pixels. This difference will bring the risk of abnormal mura visual effects, which will have a great impact on the display effect. For example, it is easy to cause irregular yellowing mura phenomenon and abnormal visual effects. Fig. 9 A schematic diagram of the actual structure of the overlapping area of ​​a first through hole and a second through hole provided in an embodiment of the present disclosure, Fig.10 A schematic diagram of a display effect of a display panel provided in an embodiment of the present disclosure, referring to Figure 9-10 , Fig. 9 Two different schematic diagrams of the actual structure of the first through hole 241 and the second through hole 261 are provided, and the dotted box is the overlapping area of ​​the two through holes. Among them, the area of ​​the overlapping area of ​​the first through hole 241 and the second through hole 261 in Figure a is larger than the area of ​​the overlapping area of ​​the first through hole 241 and the second through hole 261 in Figure b. If the hole overlapping area is as shown in Figure b, it is easy to cause a large difference in the area of ​​the hole overlapping area in different sub-pixels due to fluctuations in process conditions during the production process of the display panel, resulting in the following Fig.10 The display effect shown results in irregular yellowing mura phenomenon and abnormal visual effects.

[0079] If the overlapping area of ​​the first through hole and the second through hole is too large, the first through hole may overlap with the third through hole, affecting the reliability of the electrical connection between the pixel electrode at the third through hole and the first electrode. Therefore, the embodiment of the present disclosure limits the overlapping area of ​​the first through hole and the second through hole, and can make the overlapping area 10%-30% of the area of ​​the second through hole, and further, make the overlapping area 15%-20% of the area of ​​the second through hole, so as to ensure that the overlapping through holes will not affect the function of the display panel, and can improve the aperture ratio of the sub-pixel and the penetration rate of the display panel.

[0080] It should be noted that, for display panels of different sizes and types, the overlapping area between the first through hole and the second through hole may also be in other ranges, as long as the display panel is ensured to work normally and the transmittance can be improved. The embodiments of the present disclosure are only used as examples.

[0081] In some embodiments, continue to refer to Figure 5-Figure 7The display panel further includes: a common electrode layer 270, located between the planarization layer 260 and the pixel electrode layer 250, a passivation layer 280 is provided between the common electrode layer 270 and the pixel electrode layer 250, the passivation layer is provided with a third through hole 281, the third through hole 281 is located in the second through hole 261, and the connection portion 2512 of the pixel electrode 251 is electrically connected to the first electrode 231 through the third through hole 281. In a direction perpendicular to the plane where the substrate is located, the third through hole 281 does not overlap with the first through hole 241.

[0082] The display panel is also provided with a common electrode layer 270. Under the action of voltage, an electric field is formed between the pixel electrode layer 250 (pixel electrode 251) and the common electrode layer 270 to drive the liquid crystal to rotate to achieve the desired display effect. Among them, the common electrode layer 270 is located between the planarization layer 260 and the pixel electrode layer 250. A passivation layer 280 is also provided between the common electrode layer 270 and the pixel electrode layer 250. The passivation layer 280 is used to protect the film layer below it, prevent oxidation, and prevent them from being contaminated by moisture and impurities, so as to avoid damage to the performance of the display panel. Among them, the passivation layer 280 includes a third through hole 281, and the third through hole 281 is located in the second through hole 261. The pixel electrode 251 needs to be electrically connected to the first electrode 231 below through the third through hole 281 and the second through hole 261. In addition, because the penetration rate of the display panel needs to be improved, the first through hole 241 and the second through hole 261 need to overlap to compress the physical area occupied by the hole area. When the first through hole 241 overlaps with the second through hole 261, the first through hole 241 may overlap with the third through hole 281, affecting the structure of the pixel electrode 251 and the first electrode 231 at the third through hole 281, and the electrical connection reliability between the pixel electrode 251 and the third through hole 281. In order to avoid the above situation, the embodiment of the present disclosure defines the positional relationship between the first through hole 241 and the third through hole 281, and the third through hole 281 does not overlap with the first through hole 241 in the direction perpendicular to the plane where the substrate is located. Among them, the common electrode layer 270 is a transparent conductive layer, for example, formed by ITO. The material forming the passivation layer 280 can be an inorganic material, such as SiO2 and Si3N4, or an organic material, such as PI, or other photoresist materials, which is not limited by the embodiment of the present disclosure.

[0083] Specifically, along Figure 5 By intercepting the position of A3A3' in Figure 7 ,Depend on Figure 7The position of the third through hole 281 can be observed in the figure. The third through hole 281 is located in the second through hole 261. The pixel electrode 251 is electrically connected to the first electrode 231 through the third through hole 281 and the second through hole 261, while the first through hole 241 does not overlap with the third through hole 281, but overlaps with the second through hole 261. Therefore, the embodiment of the present disclosure can ensure that the first through hole 241 and the second through hole 261 overlap to reduce the space occupied by the first through hole 241 and the second through hole 261, thereby compressing the physical area of ​​the hole area, improving the aperture ratio of the sub-pixel and the liquid crystal deflection efficiency, and improving the overall transmittance of the display panel, and can also avoid the first through hole 241 and the third through hole 281 from overlapping to affect the pixel electrode 251 and the first electrode 231.

[0084] In some embodiments, Fig.11 A schematic diagram of a local structure of another hole area provided in an embodiment of the present disclosure is provided. In order to clearly illustrate the relative position relationship between the second through hole and the fourth through hole, Fig. 9 Only the second through hole and the fourth through hole are provided. Fig.11 Combined with Figure 5-Figure 7 The display panel also includes: a common electrode layer 270, located between the planarization layer 260 and the pixel electrode layer 250; the common electrode layer 270 is provided with a plurality of fourth through holes 271; the projection of the second through hole 261 on the substrate 210 is located within the projection of the fourth through hole 271 on the substrate 210; the connection portion 2511 of the pixel electrode 251 overlaps with the second through hole 261.

[0085] Along the first direction, the second through hole 261 includes a third side wall a3 and a fourth side wall a4 relative to each other, the fourth through hole 271 has a fifth side wall a5 and a sixth side wall a6 relative to each other, and along the direction perpendicular to the plane where the substrate 210 is located, the pixel electrode 251 overlaps with the third side wall a3 and the fifth side wall a5.

[0086] In the first direction, there is a first distance between the third side wall a3 and the fifth side wall a5, and there is a second distance between the fourth side wall a4 and the sixth side wall a6, and the first distance is smaller than the second distance.

[0087] For example, reference Figure 5-Figure 7 The display panel further includes a common electrode layer 270, and the common electrode layer 270 is provided with a plurality of fourth through holes 271, Figure 5Only one fourth through hole 271 is exemplified. The projection of the second through hole 261 on the substrate 210 is located within the projection of the fourth through hole 271 on the substrate 210, and the connecting portion 2511 of the pixel electrode 251 overlaps with the second through hole 261. The fourth through hole 271 also needs to be covered by the light shielding layer 200 to avoid exposure of the hole area. If the fourth through hole 271 is exposed, it will affect the dark state display and cause light leakage in the display panel. When driving the liquid crystal to rotate, the electric field generated by the position where the fourth through hole 271 is set in the common electrode layer 270 is weak, and the driving ability for the liquid crystal is weak or non-existent, so that the corresponding liquid crystal of this part is not deflected, affecting the liquid crystal deflection efficiency. Therefore, the size of the fourth through hole 271 can also be adjusted to improve the liquid crystal deflection efficiency and improve the overall transmittance of the display panel.

[0088] Specifically, refer to Fig.11 , for example, the first direction is set as the Y direction, the second direction is set as the X direction, and the first direction intersects with the second direction. Along the first direction, the second through hole 261 includes a third side wall a3 and a fourth side wall a4 relative to each other, and the fourth through hole 271 has a fifth side wall a5 and a sixth side wall a6 relative to each other. Along the direction perpendicular to the plane where the substrate 210 is located, the pixel electrode 251 overlaps with the third side wall a3 and the fifth side wall a5. It can be understood that the third side wall a3 and the fifth side wall a5 are close to the main body 2511 of the pixel electrode 251, while the fourth side wall a4 and the sixth side wall a6 are far away from the main body 2511. In the first direction Y, there is a first distance h3 between the third side wall a3 and the fifth side wall a5, and there is a second distance h4 between the fourth side wall a4 and the sixth side wall a6. In the prior art, the first distance is usually equal to the second distance. In the embodiment of the present disclosure, the first distance h3 is smaller than the second distance h4, that is, the second through hole 261 is not designed to be centered in the fourth through hole 271, and the size of the first distance is reduced so that the first distance is smaller than the second distance, that is, the distance between the fifth side wall a5 of the fourth through hole 271 and the second through hole 261 is compressed. On the one hand, the size of the light shielding area in the first direction Y can be effectively compressed under the premise of ensuring that the process capability requirements are met, and the black area problem of the opening area of ​​the pixel near the connecting portion 2512 of the pixel electrode 251 is improved. On the other hand, the first distance h3 is greater than zero, so as to avoid the common electrode layer 270 extending into the second through hole 261 of the planarization layer 260 and short-circuiting with the pixel electrode 251. It can not only achieve the purpose of compressing the size of the light shielding layer and improving the aperture ratio of the sub-pixel, but also improve the liquid crystal deflection efficiency, and ensure that the fourth through hole 271 is covered by the light shielding layer 200, avoid light leakage problems, and improve the overall penetration rate of the display panel.

[0089] In an embodiment where the second through hole 261 is designed to be non-centered within the fourth through hole 271, the size of the fourth through hole 271 in the first direction Y may be smaller than the size thereof in the second direction X. In a specific implementation, in a solution where the size of the fourth through hole in the first direction Y is the same as the size in the second direction X, the position of the fifth side wall a5 of the fourth through hole 271 may be adjusted to achieve that the second through hole 261 is located in a non-centered position of the fourth through hole 271.

[0090] In some embodiments, Fig.12 A partial structural diagram of another display panel provided in an embodiment of the present disclosure, referring to Fig.12 , and combined with Figure 5-Figure 7 The display panel also includes: a common electrode layer 270, located between the planarization layer 260 and the pixel electrode layer 250, a passivation layer 280 is arranged between the common electrode layer 270 and the pixel electrode layer 250, the passivation layer 280 is provided with a third through hole 281, the third through hole 281 is located in the second through hole 261, and the connecting portion 2512 of the pixel electrode 251 is electrically connected to the first electrode 231 through the third through hole 281.

[0091] Along the first direction, the second through hole 261 includes a third side wall a3 and a fourth side wall a4 opposite to each other, and the third through hole 281 includes a seventh side wall a7 and an eighth side wall a8, the third side wall a3 is located on a side of the fourth side wall a4 close to the main body 2512, and the seventh side wall a7 is located on a side of the eighth side wall a8 close to the main body 2511.

[0092] A side of the connecting portion 2512 away from the main body portion 2511 is a first side. Along the first direction, the first side S1 is located between the fourth side wall a4 and the eighth side wall a8.

[0093] For example, reference Figure 5-Figure 7 The display panel also includes a common electrode layer 270, and a passivation layer 280 is also provided between the common electrode layer 270 and the pixel electrode layer 250. The passivation layer 280 insulates the common electrode layer 270 and the pixel electrode layer 250 from each other and protects the film layer thereunder. The passivation layer 280 includes a third through hole 281, and the third through hole 281 is located in the second through hole 261. The pixel electrode 251 needs to be electrically connected to the first electrode 231 thereunder via the third through hole 281 and the second through hole 261. In the embodiment disclosed herein, by adjusting the position of the third through hole, compressing the size of the light shielding layer, and increasing the aperture ratio of the sub-pixel, the overall penetration rate of the display panel is improved.

[0094] Specifically, refer to Fig.12For example, the first direction is set as the Y direction, the second direction is set as the X direction, and the first direction Y intersects with the second direction X. Along the first direction Y, the third through hole 281 includes a seventh side wall a7 and an eighth side wall a8, and the seventh side wall a7 is located on the side of the eighth side wall a8 close to the main body 2511 of the pixel electrode 251, that is, the seventh side wall a7 is closer to the opening area, and the eighth side wall a8 is far away from the opening area. Along the first direction Y, the second through hole 261 includes a third side wall a3 and a fourth side wall a4 opposite to each other, and the third side wall a3 is located on the side of the fourth side wall a4 close to the main body 2512, that is, for the opening area and the light shielding area corresponding to the same sub-pixel, the third side wall a3 is closer to the opening area, and the fourth side wall a4 is far away from the opening area. The side of the connecting portion 2512 of the pixel electrode 251 away from the main body 2511 is the first side S1. Compared with the solution in which the first side S1 of the pixel electrode 251 is located on the side of the fourth side wall a4 away from the third side wall a3 (i.e., the connecting portion 2512 of the pixel electrode 251 completely covers the second through hole 261), in the first direction Y, the distance between the first side S1 of the pixel electrode 251 and the pixel electrode of the adjacent row increases, providing adjustment space for the position of the pixel electrode in the adjacent row. In one embodiment, the position of the end of the pixel electrode in the adjacent row can be adjusted toward the position of the first side of the pixel electrode of the row, so that the end of the pixel electrode of the adjacent row extends the shading area, solving the problem of black area caused by insufficient liquid crystal driving at the end of the pixel electrode.

[0095] After the position of the first side S1 of the pixel electrode 251 is adjusted along the first direction Y, the first side of the connecting portion 2512 of the pixel electrode 251 is closer to the third through hole 281, and the first side is located between the fourth side wall a4 and the eighth side wall a8. Optionally, the first side S1 may be flush with the fourth side wall a4, or the first side S1 may be flush with the eighth side wall a8.

[0096] Taking into account the influence of process errors, when the distance between the first side S1 and the fourth side wall a4 is less than or equal to 0.5 microns, the first side S1 is considered to be flush with the fourth side wall a4, and when the distance between the first side S1 and the eighth side wall a8 is less than or equal to 0.5 microns, the first side S1 is considered to be flush with the eighth side wall a8.

[0097] After the first side S1 of the connecting portion 2512 of the pixel electrode 251 moves upward, the sixth side wall a6 of the fourth through hole 271 of the common electrode layer 270 can also move upward along with the connecting portion 2512 of the pixel electrode 251, thereby compressing the size of the light-shielding layer 200, increasing the aperture ratio of the sub-pixel, and improving the overall transmittance of the display panel.

[0098] It should be noted that, when the type and size of the display panel are different, the distance between the first layer and the eighth side wall may also be in other ranges, and the embodiment of the present disclosure is only used as an example.

[0099] In some embodiments, Fig.13 A partial structural diagram of another display panel provided in an embodiment of the present disclosure is shown. Fig.14 A partial structural diagram of another display panel provided in an embodiment of the present disclosure, referring to Fig.13 and Fig.14 , and combined with Figure 5-Figure 7 The display panel further includes: a common electrode layer 270 located between the planarization layer 260 and the pixel electrode layer 250; the common electrode layer 270 is provided with a plurality of fourth through holes 271, and along the first direction, the fourth through holes 271 have opposite fifth side walls a5 and sixth side walls a6.

[0100] Two pixel electrodes 251 adjacent to each other along the first direction are respectively a first pixel electrode 2501 and a second pixel electrode 2502 . The connection portion 2512 of the first pixel electrode 2501 is located between the main portion 2511 of the first pixel electrode 2501 and the main portion 2511 of the second pixel electrode 2502 .

[0101] For the fourth through hole 271 overlapping with the connecting portion 2512 of the first pixel electrode 2501 in a direction perpendicular to the plane of the substrate, along the first direction, its sixth side wall a6 is located on the side of its fifth side wall a5 close to the second pixel electrode 2502, and the distance range between the side of the second pixel electrode 2502 close to the first pixel electrode 2501 and the sixth side wall a6 of the fourth through hole 271 is [0um, 0.5um].

[0102] For example, reference Figure 5-Figure 7 The display panel includes a common electrode layer 270, and the common electrode layer 270 is provided with a plurality of fourth through holes 271, Figure 5 Only one fourth through hole 271 is exemplified. The projection of the second through hole 261 on the substrate 210 is located within the projection of the fourth through hole 271 on the substrate 210. For example, the first direction is set to the Y direction, the second direction is set to the X direction, and the first direction intersects with the second direction. Along the first direction Y, the fourth through hole 271 has a relative fifth side wall a5 and a sixth side wall a6. The display panel includes a plurality of pixel electrodes 251 arranged in an array, and there is a certain spacing between adjacent pixel electrodes 251, and the spacing needs to be covered by the shading layer 200. In the prior art, the spacing between adjacent pixel electrodes 251 is large, so that the area covered by the shading layer 200 is large, thereby affecting the aperture ratio of the display panel and affecting the overall transmittance. Based on this, the embodiment of the present disclosure achieves the purpose of compressing the shading layer 200 by reducing the spacing between adjacent pixel electrodes 251, thereby improving the aperture ratio of the display panel and improving the transmittance of the display panel.

[0103] Specifically, refer to Fig.13 and Fig.14, the embodiment of the present disclosure provides two pixel electrodes 251 adjacent to each other along the first direction Y, a first pixel electrode 2501 and a second pixel electrode 2502, wherein the connection portion 2512 of the first pixel electrode 2501 is located between the main portion 2511 of the first pixel electrode 2501 and the main portion 2511 of the second pixel electrode 2502. The common electrode layer includes a fourth through hole 271, and in a direction perpendicular to the plane where the substrate is located, the fourth through hole 271 overlaps with the connection portion 2512 of the first pixel electrode 2501, and the area of ​​the fourth through hole 271 is relatively large, and along the first direction Y, the fourth through hole 271 includes a fifth side wall a5 and a sixth side wall a6. The sixth side wall a6 is located on the side of the fifth side wall a5 close to the second pixel electrode 2502, and the distance between the sixth side wall and the side of the second pixel electrode 2502 close to the first pixel electrode 2501 is a spacing h5.

[0104] Specifically, there are two cases of reducing the spacing between the first pixel electrode 2501 and the second pixel electrode 2502. The first case is that the side of the second pixel electrode 2502 close to the first pixel electrode 2501 does not overlap with the sixth side wall a6 of the fourth through hole 271, and the second case is that the side of the second pixel electrode 2502 close to the first pixel electrode 2501 overlaps with the sixth side wall a6 of the fourth through hole 271, which can be referred to respectively. Fig.13 and Fig.14 By adjusting the position of the side of the second pixel electrode 2502 close to the first pixel electrode 2501 so that it extends toward the area covered by the light shielding layer, the black area problem caused by the side of the second pixel electrode 2502 close to the first pixel electrode 2501 can be improved, and the liquid crystal driving efficiency in the opening area can be improved. Fig.13 , the side of the second pixel electrode 2502 close to the first pixel electrode 2501 does not overlap with the sixth side wall a6 of the fourth through hole 271. At this time, the smaller the spacing, the smaller the area of ​​the light shielding layer 200, and the aperture ratio of the display panel will also increase. For example, the distance range is set to [0um, 0.5um]. When the spacing h5 is less than or equal to 0.5um, the length of the light shielding layer 200 in the first direction Y is effectively reduced, and the area of ​​the light shielding layer 200 is compressed. Preferably, when the spacing h5 is 0um, the improvement effect is best. Reference Fig.14, the side of the second pixel electrode 2502 close to the first pixel electrode 2501 overlaps with the sixth side wall a6 of the fourth through hole 271, that is, the side of the second pixel electrode 2502 close to the first pixel electrode 2501 extends to the fourth through hole 271 of the first pixel electrode 2501. At this time, the larger the spacing, the smaller the area of ​​the light shielding layer 200 is set, and the aperture ratio of the display panel will also increase. For example, the distance range is set to [0um, 0.5um]. When the spacing h5 is less than or equal to 0.5um, the length of the light shielding layer 200 in the first direction Y is effectively reduced, and the area of ​​the light shielding layer 200 is compressed. Preferably, when the spacing h5 is 0.5um, the improvement effect is best.

[0105] Since the adjacent first pixel electrode and the second pixel electrode are located in the same film layer and are usually formed by the same patterning process, if the distance between adjacent pixel electrodes is too small, incomplete etching may occur, resulting in a short circuit between the two. Therefore, it is necessary to ensure that there is a certain distance between the two. Fig.13 and Fig.14 As shown, the distance h6 between the first pixel electrode 2501 and the second pixel electrode 2502 should meet a certain range and cannot be too small. Figure 12-14 , by placing the lower end of the first pixel electrode 2501 (such as Fig.12 The position of the first side S1) in the middle is adjusted along the first direction Y toward the position of the third through hole 281 to provide space for adjusting the position of the second pixel electrode 2502. The position of the side of the second pixel electrode 2502 facing the first pixel electrode 2501 is adjusted along the first direction Y toward the first pixel electrode 2501 so that the end of the second pixel electrode 2502 (the end close to the first pixel electrode 2501) extends to the area covered by the shading layer 200 to improve the black area problem caused by the end of the second pixel electrode 2502.

[0106] It should be noted that the embodiment of the present disclosure sets the distance range to [0um, 0.5um] as only an optional implementation, and within this range, the desired effect can be achieved. When the display panel is different, the size is different, or the material is different, the distance range can also be set to other schemes, and the embodiment of the present disclosure does not limit this.

[0107] In some embodiments, Fig.15 A partial structural diagram of another display panel provided in an embodiment of the present disclosure, and combined with Figures 5 to 7 The display panel further includes a light shielding layer 200 , and the light shielding layer 200 includes a plurality of openings 201 .

[0108] Along a direction perpendicular to the plane of the substrate 210 , the opening 211 overlaps with the main body 2511 of the pixel electrode 251 , the position of the light-shielding layer 200 where no opening is set overlaps with the fourth through hole 271 , and the side of the second pixel electrode 2502 close to the first pixel electrode 2501 overlaps with the light-shielding layer 200 .

[0109] For example, Fig.15 Two pixel electrodes 251 adjacent to each other along a first direction Y are provided, namely, a first pixel electrode 2501 and a second pixel electrode 2502, wherein a connection portion 2512 of the first pixel electrode 2501 is located between a main portion 2511 of the first pixel electrode 2501 and a main portion 2511 of the second pixel electrode 2502. The display panel further includes a common electrode layer 270, and the common electrode layer 270 includes a fourth through hole 271, and the fourth through hole 271 overlaps with the connection portion 2512 of the pixel electrode 251 in a direction perpendicular to the plane where the substrate is located.

[0110] in, Fig.15 The light shielding layer 200 is provided with two openings 201 (for example only, the actual light shielding layer is provided with multiple openings). Fig.13 It can be seen that along the direction perpendicular to the plane where the substrate 210 is located, the opening 201 overlaps with the main body 2511 of the pixel electrode 251, exposing the main body 2511 of the pixel electrode 251. The position of the light shielding layer 200 where no opening is set overlaps with the fourth through hole 271. In order to maximize the liquid crystal efficiency in this area and reduce the area where the light shielding layer is set, the distance between adjacent pixel electrodes 251 can be reduced. For example, the position of the end of the second pixel electrode 2502 can be adjusted toward the direction of the first pixel electrode 2501, so that the distance between it and the first pixel electrode 2501 is closer, so that the side of the second pixel electrode 2502 close to the first pixel electrode 2501 overlaps with the light shielding layer 200, which can reduce the black area problem at the edge of the pixel electrode, maximize the liquid crystal efficiency in this area, reduce the area where the light shielding layer is set on the entire display panel, and improve the aperture ratio. For example, in the prior art, the distance between the edge of the second pixel electrode 2502 close to the first pixel electrode 2501 and the first pixel electrode 2501 is 3.1um. With this structure, the distance can be reduced to 2.6um. Optionally, the actual suitable compression range is determined according to the process capability, and the embodiments of the present disclosure do not impose any limitation on this.

[0111] In some embodiments, Fig.16 A partial structural diagram of another display panel provided in the embodiment of the present disclosure, referring to Fig.16 The main body 2511 of the pixel electrode 251 includes a plurality of branch electrodes, each of which includes a first end and a second end; the first end of each branch electrode is electrically connected to the connecting portion 2512; and the second ends of each branch electrode are not connected to each other.

[0112] Exemplarily, the pixel electrode 251 provided in the embodiment of the present disclosure includes a main body portion 2511 and a connecting portion 2512, wherein the main body portion 2511 includes a plurality of branch electrodes, for example Fig.16 The main body 2511 in the embodiment includes two branch electrodes. The embodiment of the present disclosure does not limit the number of branch electrodes, and is only used as an example. Each branch electrode includes a first end and a second end. The first end is a side close to the connecting portion 2512 and is electrically connected to the connecting portion 2512. The second end is a side away from the connecting portion 2512, and the second ends of the branch electrodes are not connected to each other. Compared with the prior art, in which the second ends of the branch electrodes are electrically connected to each other, the second ends of the branch electrodes in the embodiment of the present disclosure are not connected to each other, so that the direction of the electric field generated in the area is consistent. Therefore, the direction of the electric field force on the liquid crystal at the second end of each branch electrode is consistent, so that the deflection angle of the liquid crystal can be accurately controlled, and the liquid crystal driving ability is improved.

[0113] Fig.17 A partial structural diagram of another display panel provided in an embodiment of the present disclosure is shown. Fig.18 A schematic diagram of a membrane structure provided in an embodiment of the present disclosure, referring to Fig.17 and Fig.18 , Fig.17 A sub-pixel is provided, and the display panel includes a light shielding layer 200, and the light shielding layer 200 is provided with an opening 201, and the opening 201 overlaps with the main body 2511 of the pixel electrode 251. As shown in the figure, a gate signal line 301 is also provided, which is electrically connected to the gate 290, and also includes a data line 302, and the data line 302 is electrically connected to the second electrode 232, and the second electrode 232 is electrically connected to the active layer 220 through a via 304. The gate signal line 301, the active layer 303, the gate 290, the second electrode 232 and the connecting portion 2512 of the pixel electrode 251 are all overlapped with the light shielding layer 200, and the light shielding layer 200 can avoid display abnormalities caused by metal reflection and the like. Exemplarily, the display panel further includes a substrate 210, a buffer layer 212, a gate insulating layer 242, an interlayer insulating layer 243, a planarization layer 260, a first transparent conductive layer ITO1 / common electrode layer COM / 270, a passivation layer 280, and a second transparent conductive layer ITO2 / pixel electrode layer PIXEL / 250. Among them, the gate 290 overlaps with the active layer 220, and the second electrode 232 is connected to the data line 302 or uses the data line 302. Among them, when the drain / first electrode 231 is electrically connected to the pixel electrode, it is necessary to set the through hole mentioned in the above embodiment, which can be understood with reference to the above drawings. The embodiments of the present disclosure are not repeated here, and are only used to show the relationship between the film layers of the display panel.

[0114] In some embodiments, Fig.19A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure is shown in FIG. Fig. 20 The embodiment of the present disclosure provides a Fig.19 Schematic diagram of the membrane structure cut off at A5A5', refer to Fig.19 and Fig. 20 , further comprising a plurality of supporting columns 40 and a plurality of sub-pixels 30 of different colors.

[0115] The sub-pixels 30 include first-type sub-pixels 31 and second-type sub-pixels 32 arranged in an array; a support column is disposed on a side of the first-type sub-pixels 31 away from the second-type sub-pixels 32; wherein the second-type sub-pixels 32 are green sub-pixels.

[0116] For example, Fig.19 Some sub-pixels 30 are provided, which are first-type sub-pixels 31 and second-type sub-pixels 32 arranged in an array. In order to improve the support of the display panel, support columns 40 are usually arranged around the sub-pixels, but the existence of the support columns 40 will also affect the aperture ratio of the display panel caused by the sub-pixels. In order to balance the support and the aperture ratio, support columns can be arranged at specific positions to improve the aperture ratio to a certain extent, and also ensure the support effect on the display panel. Fig.19 As shown, the first type of sub-pixel 31 and the second type of sub-pixel 32 have different colors. The second type of sub-pixel 32 is a green sub-pixel. Since the human eye is more sensitive to green, after the green sub-pixel is blocked, when the screen of the display panel switches, the human eye can easily recognize the difference caused by the green sub-pixel, which affects the display effect. Therefore, in the embodiment of the present disclosure, a support column 40 is set on the side of the first type of sub-pixel 31 away from the second type of sub-pixel 32 to reduce the blocking of the green sub-pixel, which can improve the aperture ratio and prevent it from being recognized by the human eye. For example, the first type of sub-pixel 31 includes a red sub-pixel 311 and a blue sub-pixel 312, and the green sub-pixel 32 is located between the red sub-pixel 311 and the blue sub-pixel 312. When setting the support column 40, it is set on the side of the red sub-pixel 311 and the blue sub-pixel 312 away from the green sub-pixel to achieve the desired effect. Fig. 20 The specific position relationship of the support column 40 in the film layer is shown. Fig. 20It can be known that the gate signal line 301 and the data line 302 are arranged on the side of the support column 40 close to the substrate 210, and the lower alignment film 401 is also arranged on the side of the support column 40 close to the substrate 210, and the upper alignment film 402 is arranged on the side of the support column 40 away from the substrate 210. An optical adhesive layer 403 is arranged on the side of the upper alignment film 402 away from the support column 40, which plays a role in flattening the color filter substrate. The color filter substrate also includes a color resistance layer 404, which can include color resistances of different colors, such as red color resistance, blue color resistance and green color resistance, which plays a role in filtering, can replace the polarizer, and reduce the film thickness of the display panel. It can be seen that the existence of the support column 40 also affects the area where the color resistance is set, and therefore, it will cause the aperture ratio of the display panel to be smaller. A glass substrate 405 is arranged on the side of the color resistance layer 404 and the light shielding layer 200 away from the substrate to form a display panel.

[0117] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including a display panel as in any one of the above display panel embodiments. Therefore, the display device has the technical features of the display panel provided in the embodiment of the present disclosure, and can achieve the beneficial effects of the display panel provided in the embodiment of the present disclosure. For the similarities, refer to the above description of the display panel provided in the embodiment of the present disclosure, and no further description is given here.

[0118] For example, Fig.21 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure is shown in FIG. Fig. 22 The embodiment of the present disclosure provides a Fig.21 Schematic diagram of the membrane structure cut off at A6A6'. Fig.21 and Fig. 22 As shown, the display device 1000 provided in the embodiment of the present disclosure includes the display panel 10 provided in any of the above embodiments of the present disclosure. The display device 1000 includes the display panel 10 and the backlight module 110, wherein the display panel 10 includes an array substrate 120 and a color filter substrate 130, and also includes a liquid crystal layer 140 located between the array substrate 120 and the color filter substrate 130. Fig.21 The embodiment only takes a mobile phone as an example to illustrate the display device. It can be understood that the display device provided in the embodiment of the present application can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not make special limitations on this.

[0119] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel, and thus can solve the same technical problems as the above-mentioned display panel embodiment and achieve the same technical effects, which will not be repeated here.

[0120] The embodiments of the present disclosure also provide a method for preparing a display panel, which is used to prepare any of the display panels provided in the above embodiments and can achieve corresponding beneficial effects. The similarities can be understood by referring to the explanation of the display panel above and will not be repeated here.

[0121] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0122] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate; An active layer, located on one side of the substrate; A first metal layer, located on a side of the active layer away from the substrate, the first metal layer comprising a first electrode; a first insulating layer, located between the active layer and the first metal layer; The first insulating layer is provided with a first through hole; a pixel electrode layer, located on a side of the first metal layer away from the substrate; the pixel electrode layer comprises a plurality of pixel electrodes; the pixel electrodes comprise a main body portion and a connecting portion electrically connected to each other, the main body portion and the connecting portion being arranged along a first direction; A planarization layer, located between the first metal layer and the pixel electrode layer; the planarization layer is provided with a second through hole; The first electrode is electrically connected to the active layer through the first through hole; the connecting portion of the pixel electrode is electrically connected to the first electrode through the second through hole; Along a direction perpendicular to a plane where the substrate is located, the first through hole overlaps with the second through hole.

2. The display panel according to claim 1, characterized in that: In a second direction, the second through hole includes a first side wall and a second side wall opposite to each other, and the second direction intersects with the first direction; Along a direction perpendicular to a plane where the substrate is located, the first through hole at least overlaps with the first side wall of the second through hole.

3. The display panel according to claim 2, characterized in that: In the first direction, the second through hole includes a third side wall and a fourth side wall that are opposite to each other. In a direction perpendicular to the plane where the substrate is located, the first through hole also overlaps with the third side wall.

4. The display panel according to claim 1, characterized in that: An overlapping area between the first through hole and the second through hole has a first size along the first direction and a second size along the second direction, and the first size is greater than or equal to the second size; wherein the second direction intersects with the first direction.

5. The display panel according to claim 1, characterized in that: The overlapping area of ​​the first through hole and the second through hole is 15%-20% of the area of ​​the second through hole.

6. The display panel according to claim 1, characterized in that: Also includes: a common electrode layer, located between the planarization layer and the pixel electrode layer, a passivation layer is provided between the common electrode layer and the pixel electrode layer, the passivation layer is provided with a third through hole, the third through hole is located in the second through hole, and the connection portion of the pixel electrode is electrically connected to the first electrode through the third through hole; In a direction perpendicular to the plane where the substrate is located, the third through hole does not overlap with the first through hole.

7. The display panel according to claim 1, characterized in that: Also includes: a common electrode layer, located between the planarization layer and the pixel electrode layer; the common electrode layer is provided with a plurality of fourth through holes; the projection of the second through hole on the substrate is located within the projection of the fourth through hole on the substrate; the connection portion of the pixel electrode overlaps with the second through hole; Along the first direction, the second through hole includes a third side wall and a fourth side wall opposite to each other, the fourth through hole has a fifth side wall and a sixth side wall opposite to each other, and along a direction perpendicular to the plane where the substrate is located, the pixel electrode overlaps with the third side wall and the fifth side wall; In the first direction, there is a first distance between the third side wall and the fifth side wall, and there is a second distance between the fourth side wall and the sixth side wall, and the first distance is smaller than the second distance.

8. The display panel according to claim 1, characterized in that: Also includes: a common electrode layer, located between the planarization layer and the pixel electrode layer, a passivation layer is provided between the common electrode layer and the pixel electrode layer, the passivation layer is provided with a third through hole, the third through hole is located in the second through hole, and the connection portion of the pixel electrode is electrically connected to the first electrode through the third through hole; Along the first direction, the second through hole includes a third side wall and a fourth side wall opposite to each other; the third through hole includes a seventh side wall and an eighth side wall, the third side wall is located on a side of the fourth side wall close to the main body, and the seventh side wall is located on a side of the eighth side wall close to the main body; A side of the connecting portion away from the main body portion is a first side. Along the first direction, the first side is located between the fourth side wall and the eighth side wall.

9. The display panel according to claim 1, characterized in that: The device further comprises: a common electrode layer located between the planarization layer and the pixel electrode layer; the common electrode layer is provided with a plurality of fourth through holes, and along the first direction, the fourth through holes have opposite fifth side walls and sixth side walls; The two pixel electrodes adjacent to each other along the first direction are respectively a first pixel electrode and a second pixel electrode, and the connecting portion of the first pixel electrode is located between the main portion of the first pixel electrode and the main portion of the second pixel electrode; For the fourth through hole overlapping with the connecting portion of the first pixel electrode in a direction perpendicular to the plane of the substrate, along the first direction, its sixth side wall is located on the side of its fifth side wall close to the second pixel electrode, and the distance range between the side of the second pixel electrode close to the first pixel electrode and the sixth side wall of the fourth through hole is [0um, 0.5um].

10. The display panel according to claim 1, characterized in that: Also included is a light shielding layer, the light shielding layer including a plurality of openings; Along a direction perpendicular to the plane of the substrate, the opening overlaps with the main body of the pixel electrode, the position of the light-shielding layer where no opening is set overlaps with the fourth through hole, and the side of the second pixel electrode close to the first pixel electrode overlaps with the light-shielding layer.

11. The display panel according to claim 1, characterized in that: The main body of the pixel electrode includes a plurality of branch electrodes, each of which includes a first end and a second end; the first end of each of the branch electrodes is electrically connected to the connecting portion; and the second ends of each of the branch electrodes are not connected to each other.

12. The display panel according to claim 1, characterized in that: The first insulating layer includes a gate insulating layer and an interlayer insulating layer which are stacked; The display panel further includes a second metal layer, the second metal layer includes a gate, the gate insulating layer is located between the active layer and the gate, and the interlayer insulating layer is located between the gate and the first metal layer; The first through hole penetrates the gate insulating layer and the interlayer insulating layer.

13. The display panel according to claim 1, characterized in that: Also included are a plurality of support pillars and a plurality of sub-pixels of different colors; The sub-pixels include a first type of sub-pixels and a second type of sub-pixels arranged in an array; the support column is arranged on a side of the first type of sub-pixels away from the second type of sub-pixels; wherein the second type of sub-pixels are green sub-pixels.

14. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 13.

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