Array substrate and display device

Abstract

The invention discloses an array substrate and a display device, the array substrate comprises a first substrate and a sub-pixel, and the sub-pixel comprises a transistor and a pixel electrode which are connected; the pixel electrode comprises a main conductive part, the main conductive part comprises at least one first group of sub-conductive parts and at least one second group of sub-conductive parts, and the first group of sub-conductive parts and the second group of sub-conductive parts are alternately arranged in a first direction; the first group of sub-conductive parts comprises first connecting strips extending in the first direction, and the ends, opposite to the first connecting strips, of the first group of sub-conductive parts are open ends; the second group of sub-conductive parts comprises second connecting strips extending in the first direction, and the ends, opposite to the second connecting strips, of the second group of sub-conductive parts are open ends; in the second direction, the first connecting strip is closer to the transistor than the second connecting strip; the sum of the lengths of the first connecting strips in the at least one first group of sub-conductive parts is smaller than the sum of the lengths of the second connecting strips in the at least one second group of sub-conductive parts; the first direction intersects the second direction.

Description

[0001] This application is a divisional application of the invention application with an application date of April 6, 2021, Chinese application number 202180000716.X, and invention name “Pixel electrode, array substrate and display device”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0003] With the continuous development of liquid crystal panels, high-resolution products are constantly being developed; however, for high-resolution pixels such as 8K, the pixel pitch (i.e., Dot pitch) is small, and the storage capacitor (i.e., Cst) is small. Therefore, the pixel voltage is more easily pulled by the data voltage, which easily leads to asymmetric pulling on both sides of the pixel, making the grayscale V-Crosstalk (i.e., V-type crosstalk) more serious, affecting the display effect.

[0004] Public Content

[0005] The purpose of the present disclosure is to provide a pixel electrode, an array substrate and a display device, thereby overcoming one or more problems caused by limitations and defects of the related art at least to a certain extent.

[0006] A first aspect of the present disclosure provides a pixel electrode, comprising: a first edge conductive portion and a second edge conductive portion arranged at intervals in a first direction, and a main conductive portion at least partially located between the first edge conductive portion and the second edge conductive portion, the main conductive portion being connected to the first edge conductive portion and the second edge conductive portion, respectively, the main conductive portion comprising at least one first group of sub-conductive portions and at least one second group of sub-conductive portions, the first group of sub-conductive portions and the second group of sub-conductive portions being alternately arranged in the first direction;

[0007] The first group of sub-conductive parts includes a first connecting strip, the first connecting strip extends in the first direction and has a first surface and a second surface opposite to each other in the second direction; the first group of sub-conductive parts has a first slit located on a side of the first surface away from the second surface, and an end of the first slit away from the first connecting strip is an open end;

[0008] The second group of sub-conductive parts includes a second connecting strip located on a side of the first gap away from the first connecting strip and connected to the first group of sub-conductive parts, the second connecting strip extends in the first direction and has a third surface and a fourth surface opposite to each other in the second direction, the third surface is located on a side of the fourth surface close to the first surface; and the second group of sub-conductive parts includes a second gap located on a side of the third surface away from the fourth surface, and an end of the second gap away from the second connecting strip is an open end;

[0009] Wherein, in the second direction, the pixel electrode is configured such that the first connecting bar is closer to the transistor than the second connecting bar; and an end of the first edge conductive portion or the second edge conductive portion away from the second connecting bar is configured to be connected to the transistor;

[0010] Wherein, the sum of the lengths of the first connecting bars in the at least one first group of sub-conductive parts is smaller than the sum of the lengths of the second connecting bars in the at least one second group of sub-conductive parts;

[0011] The first direction intersects with the second direction.

[0012] In an exemplary embodiment of the present disclosure,

[0013] The first group of sub-conductive parts further includes a plurality of first electrode strips arranged at intervals in the first direction, the plurality of first electrode strips are located at a position of the first surface away from the second surface and connected to the first surface; and the first gap is provided between two adjacent first electrode strips;

[0014] The second group of sub-conductive parts further includes a plurality of second electrode strips arranged at intervals in the first direction, the plurality of second electrode strips are located at a position of the third surface away from the fourth surface and connected to the third surface; and a second gap is provided between two adjacent second electrode strips;

[0015] The third surface of the second connecting strip is connected to the end of the first electrode strip closest to the second group of sub-conductive parts and away from the first connecting strip.

[0016] In an exemplary embodiment of the present disclosure, the length of the first connecting bar is smaller than the length of the second connecting bar.

[0017] In an exemplary embodiment of the present disclosure, the main conductive portion includes one of the first group of sub-conductive portions and one of the second group of sub-conductive portions.

[0018] The first edge conductive portion is located on a side of the plurality of first electrode strips away from the second group of sub-conductive portions, and is located at a position where the first surface of the first connecting strip is away from the second surface; the first edge conductive portion is connected to the first surface, and has a third gap with the first electrode strip adjacent thereto, and an end of the third gap away from the first connecting strip is an open end;

[0019] The second edge conductive portion is located on a side of the plurality of second electrode strips away from the first group of sub-conductive portions, and is located at a position where the third surface of the second connecting strip is away from the fourth surface; the second edge conductive portion is connected to the third surface, and has a fourth gap with the second electrode strip adjacent thereto, and an end of the fourth gap away from the second connecting strip is an open end.

[0020] In an exemplary embodiment of the present disclosure, the first electrode strips, the first slits and the third slits extend in the same direction and intersect with the first direction and the second direction; and the second electrode strips, the second slits and the fourth slits extend in the same direction and intersect with the first direction and the second direction.

[0021] In an exemplary embodiment of the present disclosure, the widths of the first electrode strips, the second electrode strips, the first slits, the second slits, the third slits, and the fourth slits are equal.

[0022] In an exemplary embodiment of the present disclosure, the first electrode strips and the second electrode strips extend in the same direction, and the second gap is provided between adjacent first electrode strips and second electrode strips.

[0023] In an exemplary embodiment of the present disclosure, an extension direction of the first electrode strip and an extension direction of the second electrode strip are arranged in a mirror image with respect to the second direction.

[0024] In an exemplary embodiment of the present disclosure, the second group of sub-conductive parts further includes an adjustment part, the adjustment part is located on a side of the plurality of second electrode strips close to the first group of sub-conductive parts, and is located at a position where the third surface of the second connecting strip is away from the fourth surface, and the adjustment part is connected to the third surface of the second connecting strip; wherein,

[0025] A fifth gap is formed between the adjustment portion and the first electrode strip adjacent thereto, and a sixth gap is formed between the adjustment portion and the second electrode strip adjacent thereto;

[0026] The ends of the fifth slit and the sixth slit away from the second connecting strip are both open ends;

[0027] The fifth slit has the same extension direction and the same width as the first slit, and the sixth slit has the same extension direction and the same width as the second slit.

[0028] In an exemplary embodiment of the present disclosure, the adjustment portion includes a first adjustment bar and a second adjustment bar, the fifth gap is formed between the first adjustment bar and the first electrode bar, and the sixth gap is formed between the second adjustment bar and the second electrode bar; wherein,

[0029] The first adjustment strips extend in the same direction as the first electrode strips and have the same width, and the second adjustment strips extend in the same direction as the second electrode strips and have the same width;

[0030] One end of the first adjustment bar and the second adjustment bar in the extension direction is connected to the third surface of the second connection bar, and the other ends are connected to each other.

[0031] In an exemplary embodiment of the present disclosure, a ratio of a sum of lengths of the first connection bars in the at least one first group of sub-conductive parts to a sum of lengths of the second connection bars in the at least one second group of sub-conductive parts is 0.1 to 0.9.

[0032] According to a second aspect of the present disclosure, an array substrate is provided, comprising a first substrate and sub-pixels located on the first substrate and arranged in an array along a first direction and a second direction, wherein the sub-pixels comprise a transistor and a pixel electrode as described in any one of the above, and an end of a first edge conductive portion or a second edge conductive portion of the pixel electrode away from a second connecting bar is connected to the transistor;

[0033] In the second direction, the transistor is disposed closer to the first connecting bar than to the second connecting bar of the pixel electrode.

[0034] In an exemplary embodiment of the present disclosure, an orthographic projection of the transistor on the first substrate and an orthographic projection of the first connecting bar of the pixel electrode on the first substrate are arranged opposite to each other in the first direction.

[0035] In an exemplary embodiment of the present disclosure, in two adjacent pixel electrodes in the second direction:

[0036] The first edge conductive portion of one is connected to the transistor at an end away from the second connecting bar and is closer to the transistor connected thereto than the second edge conductive portion thereof;

[0037] The second edge conductive portion of the other one is connected to the transistor at a point away from the end of the second connecting bar and is closer to the transistor connected thereto than the first edge conductive portion thereof.

[0038] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of data lines formed on the first substrate, the data lines extend in the first direction, and the data lines and the sub-pixels are alternately arranged in the second direction;

[0039] Among them, in the pixel electrode of the sub-pixel, the spacing between the first connecting bar and the data line closest thereto is a first spacing, the spacing between the second connecting bar and the data line closest thereto is a second spacing, and the first spacing and the second spacing are equal.

[0040] In an exemplary embodiment of the present disclosure, each of the data lines is connected to transistors of the sub-pixels located on the same side of the data line in the second direction and adjacent thereto;

[0041] Among them, the first electrode and the second electrode of the transistor are arranged in the same layer as the data line and are located on the side of the pixel electrode close to the first substrate; the first electrode of the transistor is connected to the data line, and the second electrode of the transistor is connected to the second edge conductive part or the first edge conductive part of the pixel electrode through a switching via.

[0042] In an exemplary embodiment of the present disclosure, the first electrode and the second electrode of the transistor are arranged at intervals in the first direction, and the interval between the first electrode and the second electrode in the first direction is a third interval;

[0043] Wherein, the ratio of the sum of the lengths of the first connecting bars in the at least one first group of sub-conductive parts to the third interval is 2 to 20.

[0044] In an exemplary embodiment of the present disclosure, the sub-pixel further includes a common electrode, which is located on a side of the pixel electrode close to the first substrate and is insulated from the pixel electrode;

[0045] Furthermore, the orthographic projection of the common electrode on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate, and does not overlap with the orthographic projection of the data line on the first substrate.

[0046] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of scan lines and a plurality of common lines formed on the first substrate and extending in the second direction, the scan lines and the common lines are alternately arranged in the first direction, and the orthographic projections of the scan lines on the first substrate do not overlap with the orthographic projections of the common lines on the first substrate;

[0047] The scanning line and the common line are arranged in the same layer, and the scanning line and the common line are located on a side of the data line close to the first substrate and are insulated from the data line;

[0048] Wherein, one side of the sub-pixel in the first direction is adjacent to the common line, and the other side is adjacent to the scan line;

[0049] Wherein, each of the scan lines is connected to the gates of transistors of the sub-pixels located on the same side of the scan line in the first direction and adjacent thereto;

[0050] Wherein, each of the common lines is connected to the common electrodes of the sub-pixels located on the same side of the common line in the first direction and adjacent thereto.

[0051] In an exemplary embodiment of the present disclosure, a portion of the scan line constitutes a gate of the transistor, and the common electrode contacts the common line.

[0052] A third aspect of the present disclosure provides a display device, comprising any one of the above-mentioned array substrates and an opposing substrate arranged in a box with the array substrate.

[0053] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0054] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0056] Figure 1 A schematic structural diagram of a pixel electrode according to an embodiment of the present disclosure is shown;

[0057] Figure 2 A schematic structural diagram of a pixel electrode according to another embodiment of the present disclosure is shown;

[0058] Figure 3 A schematic structural diagram of a pixel electrode described in the related art is shown;

[0059] Figure 4 A schematic structural diagram of a minimum repeating unit of an array substrate according to an embodiment of the present disclosure is shown;

[0060] Figure 5 A schematic structural diagram of a minimum repeating unit of an array substrate according to another embodiment of the present disclosure is shown;

[0061] Figure 6 A schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0062] The technical solution of the present disclosure is further specifically described below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar figure numbers indicate the same or similar parts. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of the present disclosure and should not be construed as a limitation of the present disclosure.

[0063] In addition, in the following detailed description, for the purpose of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details.

[0064] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0065] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various regions, layers and / or parts, these regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one region, layer and / or part from another.

[0066] like Figure 1 and Figure 2 As shown, an embodiment of the present disclosure provides a pixel electrode 10, which can be applied to liquid crystal display products, but is not limited thereto. Specifically, the pixel electrode 10 may include a first edge conductive portion 101 and a second edge conductive portion 102 arranged at intervals in a first direction Y, and a main conductive portion at least partially located between the first edge conductive portion 101 and the second edge conductive portion 102. The main conductive portion is connected to the first edge conductive portion 101 and the second edge conductive portion 102, respectively, and the main conductive portion may include at least one first group of sub-conductive portions and at least one second group of sub-conductive portions, and the first group of sub-conductive portions and the second group of sub-conductive portions are alternately arranged in the first direction Y.

[0067] like Figure 1 and Figure 2As shown, the first group of sub-conductive parts mentioned above may include a first connecting strip 103 and a plurality of first electrode strips 104 arranged at intervals in a first direction Y. The first connecting strip 103 extends in the first direction Y (i.e., the length direction of the first connecting strip 103 is the first direction Y). The first connecting strip 103 may have a first surface 103a and a second surface 103b opposite to each other in the second direction X. It should be noted that the first direction Y may intersect with the second direction X. Preferably, the first direction Y may be perpendicular to the second direction X. The plurality of first electrode strips 104 may be located at a position where the first surface 103a is away from the second surface 103b and connected to the first surface 103a. A gap is formed between two adjacent first electrode strips 104, which may be defined as a first gap S1. The ends of the two adjacent first electrode strips 104 away from the first connecting strip 103 are disconnected from each other, i.e., the end of the first gap S1 away from the first connecting strip 103 is open. For the convenience of description, the end of the first gap S1 away from the first connecting strip 103 may be defined as an open end.

[0068] like Figure 1 and Figure 2 As shown, the second group of sub-conductive parts mentioned above includes a second connecting strip 105 and a plurality of second electrode strips 106 arranged at intervals in the first direction Y, and the second connecting strip 105 extends in the first direction Y (i.e., the length direction of the second connecting strip 105 is the first direction Y). The second connecting strip 105 may have a third surface 105a and a fourth surface 105b opposite to each other in the second direction X. In the second direction X, the third surface 105a of the second connecting strip 105 may be located on the side of the fourth surface 105b thereof close to the first surface 103a of the first connecting strip 103. The third surface 105a of the second connecting strip 105 may be connected to the first electrode strip 104 close to the second group of sub-conductive parts, specifically to the end of the first electrode strip 104 away from the first connecting strip 103. It should be understood that the first electrode strip 104 close to the second group of sub-conductive parts mentioned here refers to the first electrode strip 104 in the first group of sub-conductive parts that is closest to the second group of sub-conductive parts. The plurality of second electrode strips 106 are located at a position where the third surface 105a of the second connecting strip 105 is away from the fourth surface 105b and are connected to the third surface 105a of the second connecting strip 105. A gap is formed between two adjacent second electrode strips 106, which can be defined as a second gap S2. The ends of the two adjacent second electrode strips 106 away from the second connecting strip 105 are disconnected from each other, that is, the end of the second gap S2 away from the second connecting strip 105 is open. For the convenience of description, the end of the second gap S2 away from the second connecting strip 105 can be defined as an open end.

[0069] In the embodiment of the present disclosure, the pixel electrode 10 can be connected to the transistor 20 (eg, Figure 4 and Figure 5 Specifically, the end of the first edge conductive portion 101 or the second edge conductive portion 102 away from the second connecting bar 105 can be configured to be connected to the transistor 20; and in the second direction X, the pixel electrode 10 is configured such that the first connecting bar 103 is closer to the transistor 20 than the second connecting bar 105. It should be understood that the transistor 20 can be connected to the data line 40 (such as Figure 4 and Figure 5 as shown) connection.

[0070] In summary, in the embodiment of the present disclosure, the first slit S1 and the second slit S2 of the pixel electrode 10 are not completely closed around, that is, the end of the first slit S1 close to the second connecting bar 105 is an open end, and the end of the second slit S2 close to the first connecting bar 103 is an open end. It should be understood that when the pixel electrode 10 of the embodiment of the present disclosure is applied to a display product, the open end of the first slit S1 and the open end of the second slit S2 can be respectively connected to the data lines 40 (such as Figure 4 and Figure 5 As shown) adjacent, this design is compared to Figure 3 In the related art shown in , the pixel electrode 1 with the gap 1a fully closed on all sides can effectively reduce the range of the dark field area of ​​the liquid crystal display product when applied to the liquid crystal display product, thereby improving the transmittance of the liquid crystal display product.

[0071] It should be understood that if Figure 4 and Figure 5 As shown, there is a lateral capacitance between the first electrode 201 and the second electrode 202 of the transistor 20. In the second direction X, the transistor 20 is closer to the first connecting bar 103 than the second connecting bar 105; that is, when the display product is driven, the side of the pixel electrode 10 where the first connecting bar 103 is located is closer than the side where the second connecting bar 105 is located (such as Figure 4 and Figure 5 The right side of the pixel electrode shown in FIG. 1 will have an additional lateral capacitance generated between the first electrode 201 and the second electrode 202 of the transistor 20; that is, Figure 4 and Figure 5 The pixel electrode 10 shown in the figure has a left side capacitance including a lateral capacitance between the first connecting bar 103 and the data line 40 and a lateral capacitance between the first electrode 201 and the second electrode 202 of the transistor 20, and a right side capacitance including a lateral capacitance between the second connecting bar 105 and the data line 40. Therefore, it can be seen that Figure 4 and Figure 5 The left side of the pixel electrode 10 shown in the figure has more lateral capacitance generated between the first electrode 201 and the second electrode 202 of the transistor 20 than the right side.

[0072] If the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 is designed to be greater than or equal to the sum of the lengths of the second connecting bars 105 of each second group of sub-conductive parts, that is, the sum of the capacitances generated between each first connecting bar 103 of the pixel electrode 10 and the data line 40 adjacent thereto is greater than or equal to the sum of the capacitances generated between each second connecting bar 105 and the data line 40 adjacent thereto; since the side where the first connecting bar 103 of the pixel electrode 10 is located has more lateral capacitance generated between the first electrode 201 and the second electrode 202 of the transistor 20 than the side where the second connecting bar 105 is located, therefore, the pixel electrode 10 The total capacitance on the side where the first connecting bar 103 is located is greater than the total capacitance on the side where the second connecting bar 105 is located, so that the two sides of the pixel electrode 10 are pulled differently by the data voltage, making the grayscale V-Crosstalk phenomenon of the display product more serious; based on this, in order to improve the grayscale V-Crosstalk phenomenon of the product, in the embodiment of the present disclosure, the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 can be designed to be less than the sum of the lengths of the second connecting bars 105 of each second group of sub-conductive parts; it should be noted that the length mentioned here refers to the length in its extension direction.

[0073] Optionally, the ratio of the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 to the sum of the lengths of the second connecting bars 105 of each second group of sub-conductive parts may be 0.1 to 0.9, such as 0.1, 0.3, 0.5, 0.7, 0.9, etc., but not limited to this; for example, the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 may range from 30μm to 90μm, such as 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, etc., but not limited to this; the sum of the lengths of the second connecting bars 105 of each first group of sub-conductive parts in the pixel electrode 10 may range from 60μm to 120μm, such as 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 110μm, etc., but not limited to this.

[0074] It should be noted that the ratio of the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 of the embodiment of the present disclosure to the sum of the lengths of the second connecting bars 105 of each second group of sub-conductive parts, the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10, and the sum of the lengths of the second connecting bars 105 of each first group of sub-conductive parts in the pixel electrode 10 are not limited to the numerical range mentioned above, and can be specifically determined according to the size of the transistor 20; that is, when designing a product, the size of the transistor 20 in the product can be determined first, so that the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20 can be determined first, and then the length of the first connecting bar 103 and the length of the second connecting bar 105 of the pixel electrode 10 are designed and adjusted, so that the total capacitance on the side where the first connecting bar 103 of the pixel electrode 10 is located is equal to or substantially equal to the total capacitance on the side where the second connecting bar 105 is located (that is, within the error range), thereby improving the product grayscale V-Crosstalk phenomenon.

[0075] In addition, it should be understood that the number of the first group of sub-conductive portions and the second group of sub-conductive portions in the main conductive portion of the pixel electrode 10 of the embodiment of the present disclosure may be the same, for example: both are one, two, etc.; but not limited to this, the number of the first group of sub-conductive portions and the second group of sub-conductive portions in the main conductive portion of the pixel electrode 10 may also be different, that is: the number of the first group of sub-conductive portions in the main conductive portion of the pixel electrode 10 is greater than or less than the number of the second group of sub-conductive portions, etc.

[0076] Among them, when the number of the first group of sub-conductive parts and the number of the second group of sub-conductive parts in the pixel electrode 10 are the same, the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the aforementioned pixel electrode 10 is designed to be smaller than the sum of the lengths of the second connecting bars 105 of each second group of sub-conductive parts. It can be understood that: the length of the first connecting bar 103 of the first group of sub-conductive parts in the pixel electrode 10 is smaller than the length of the second connecting bar 105 of the second group of sub-conductive parts.

[0077] like Figure 1 and Figure 2As shown, the main conductive portion of the pixel electrode 10 of the embodiment of the present disclosure may include a first group of sub-conductive portions and a second group of sub-conductive portions. At this time, the first edge conductive portion 101 of the pixel electrode 10 is located on a side of the plurality of first electrode strips 104 away from the second group of sub-conductive portions, and is located at a position where the first surface 103a of the first connecting strip 103 is away from the second surface 103b; and its first edge conductive portion 101 may be connected to the first surface 103a, and has a third gap S3 between it and the adjacent first electrode strip 104, and the adjacent first edge conductive portion 101 and the end of the first electrode strip 104 away from the first connecting strip 103 are disconnected from each other, that is: the end of the third gap S3 away from the first connecting strip 103 is open, wherein, for the convenience of description The end of the third slit S3 away from the first connecting strip 103 can be defined as an open end; the second edge conductive portion 102 is located on a side of the plurality of second electrode strips 106 away from the first group of sub-conductive portions, and is located at a position where the third surface 105a of the second connecting strip 105 is away from the fourth surface 105b; the second edge conductive portion 102 is connected to the third surface 105a, and has a fourth slit S4 with the second electrode strip 106 adjacent thereto, and the ends of the adjacent second edge conductive portions 102 and the second electrode strip 106 away from the second connecting strip 105 are disconnected from each other, that is, the end of the fourth slit S4 away from the first connecting strip 103 is open, wherein, for the convenience of description, the end of the fourth slit S4 away from the second connecting strip 105 can be defined as an open end.

[0078] Optionally, the first electrode strips 104, the first slits S1, and the third slits S3 extend in the same direction to ensure display uniformity at the first group of sub-conductive portions of the pixel electrode 10; and the first electrode strips 104, the first slits S1, and the third slits S3 extend in directions that intersect with the first direction Y and the second direction X mentioned above to reduce color deviation. Similarly, the second electrode strips 106, the second slits S2, and the fourth slits S4 extend in the same direction to ensure display uniformity at the second group of sub-conductive portions of the pixel electrode 10; and the second electrode strips 106, the second slits S2, and the fourth slits S4 extend in directions that intersect with the first direction Y and the second direction X mentioned above to reduce color deviation.

[0079] Furthermore, the widths of the first electrode strip 104, the second electrode strip 106, the first slit S1, the second slit S2, the third slit S3 and the fourth slit S4 are equal to better ensure the uniformity of product display; it should be noted that the width mentioned here is the dimension in the direction perpendicular to its extension direction.

[0080] In an optional embodiment of the present disclosure, Figure 1As shown, the aforementioned first electrode strips 104 and second electrode strips 106 may extend in the same direction, that is, the first electrode strips 104 and second electrode strips 106 may extend in the same direction, that is, the pixel electrode 10 of the present disclosure may be a single-domain structure, which may reduce the difficulty of design. It should be noted that, in this embodiment, the gap between adjacent first electrode strips 104 and second electrode strips 106 may be the aforementioned second gap S2.

[0081] In another optional embodiment of the present disclosure, Figure 2 As shown, the extension direction of the first electrode strip 104 can be mirrored with the extension direction of the second electrode strip 106 about the second direction X, that is, the pixel electrode 10 of the present disclosure can be a dual-domain structure, which can expand the viewing angle of the product; it should be noted that, in the embodiment of the present disclosure, the angle between the extension direction of the first electrode strip 104 and the extension direction of the second electrode strip 106 can be an acute angle.

[0082] Among them, when the pixel electrode 10 is a dual-domain structure, as Figure 2 As shown, the second group of sub-conductive portions of the pixel electrode 10 may further include an adjustment portion 107. This adjustment portion 107 may be located on one side of the plurality of second electrode strips 106 close to the first group of sub-conductive portions and located at a position of the third surface 105a of the second connecting strip 105 away from the fourth surface 105b. This adjustment portion 107 may be connected to the third surface 105a of the second connecting strip 105.

[0083] Specifically, Figure 2 As shown, a fifth gap S5 is formed between the adjustment portion 107 and the first electrode strip 104 adjacent thereto, and a sixth gap S6 is formed between the adjustment portion 107 and the second electrode strip 106 adjacent thereto; the ends of the adjacent adjustment portion 107 and the first electrode strip 104 away from the second connecting strip 105 are disconnected from each other, and the ends of the adjacent adjustment portion 107 and the second electrode strip 106 away from the second connecting strip 105 are disconnected from each other, that is, the ends of the fifth gap S5 and the sixth gap S6 away from the second connecting strip 105 are open, wherein, for the convenience of description, the ends of the fifth gap S5 and the sixth gap S6 away from the second connecting strip 105 can be defined as open ends; wherein, the fifth gap S5 can extend in the same direction and have the same width as the first gap S1 mentioned above, and the sixth gap S6 can extend in the same direction and have the same width as the second gap S2; such a design can ensure that the electric field at the junction of the first group of sub-conductive portions and the second group of sub-conductive portions in the pixel electrode 10 is closer to the electric field at other places of the pixel electrode 10, thereby ensuring display uniformity.

[0084] For example, Figure 2As shown, the adjustment portion 107 may include a first adjustment bar 107a and a second adjustment bar 107b, the fifth gap S5 mentioned above is formed between the first adjustment bar 107a and the first electrode bar 104, and the sixth gap S6 mentioned above is formed between the second adjustment bar 107b and the second electrode bar 106; wherein, the extension direction of the first adjustment bar 107a may be the same as the extension direction of the first electrode bar 104 and the width is equal, and the extension direction of the second adjustment bar 107b may be the same as the extension direction of the second electrode bar 106 and the width is equal, so as to further ensure the uniformity of the electric field, thereby ensuring the display uniformity.

[0085] It should be noted that one end of the first adjustment bar 107a and the second adjustment bar 107b in their extension direction is connected to the third surface 105a of the second connecting bar 105, and the other ends can be connected to each other. It should be understood that a gap pattern is formed between the first adjustment bar 107a and the second adjustment bar 107b in the embodiment of the present disclosure, and such a design can reduce the dark field area.

[0086] Among them, if the width of the gap pattern formed between the first adjustment strip 107a and the second adjustment strip 107b is relatively large, a spacer (not shown in the figure) connected to the third surface 105a of the second connecting strip 105 may be provided in the gap pattern to divide the gap pattern into a gap extending in the same and equal direction as the aforementioned first gap S1, and another gap extending in the same and equal direction as the second gap S2; if the width of the gap pattern formed between the first adjustment strip 107a and the second adjustment strip 107b is relatively small, the spacer may not be provided.

[0087] In addition, it should be understood that when the area of ​​the adjustment portion 107 in the embodiment of the present disclosure is small, the aforementioned first adjustment bar 107a, second adjustment bar 107b and gap pattern are not provided, that is, the adjustment portion 107 may be a whole block structure without a gap pattern, depending on the specific circumstances.

[0088] In summary, the pixel electrode 10 of the embodiment of the present disclosure may be an integrated structure. For example, the pixel electrode 10 of the embodiment of the present disclosure may be a transparent electrode, and its material may be ITO (indium tin oxide) material, but is not limited thereto, and may also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO).

[0089] The present disclosure also provides an array substrate that can be used in a liquid crystal display device, but is not limited thereto. Figure 1 , Figure 2 and Figures 4 to 6As shown, the array substrate of the present disclosure may also include a first substrate 30, sub-pixels located on the first substrate 30 and arranged in an array along a first direction Y and a second direction X, a plurality of data lines 40 formed on the first substrate 30, a plurality of scan lines 60 and a plurality of common lines 70 formed on the first substrate 30; it should be noted that the first direction Y mentioned in the embodiment of the present disclosure may be referred to as a column direction, and the second direction X may be referred to as a row direction.

[0090] The array substrate of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0091] like Figure 6 As shown, the first substrate 30 may be a single-layer structure, but is not limited thereto, and may also include a multi-layer structure. For example, the material of the first substrate 30 may be glass, but is not limited thereto, and may also be other materials, such as polyimide (PI) and other materials, depending on the specific situation.

[0092] like Figure 4 and Figure 5 As shown, the data lines 40 may extend in the first direction Y (i.e., the column direction), and the data lines 40 may be arranged alternately with the sub-pixels in the second direction X (i.e., the row direction). In the embodiment of the present disclosure, each data line 40 is connected to each sub-pixel located on the same side of the data line 40 in the second direction X and adjacent thereto, that is, each column of data lines 40 is connected to each sub-pixel adjacent thereto and located in the same column, so as to provide data signals to the sub-pixels in the same column.

[0093] For example, the data line 40 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium. For example, the multilayer structure is a multi-metal layer stack, such as a titanium, aluminum and titanium three-layer metal stack (Ti / Al / Ti).

[0094] like Figure 4 and Figure 5 As shown, the scan line 60 and the common line 70 can extend in the second direction X, and the scan line 60 and the common line 70 are alternately arranged in the first direction Y. It should be understood that the orthographic projection of the scan line 60 on the first substrate 30 does not overlap with the orthographic projection of the common line 70 on the first substrate 30.

[0095] For example, the scanning line 60 and the common line 70 are arranged in the same layer. In the present disclosure, "arranged in the same layer" refers to using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (mask, also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0096] Among them, combined Figures 4 to 6 As shown, the scan line 60 and the common line 70 can be located on the side of the data line 40 close to the first substrate 30 and are insulated from the data line 40, that is, a gate insulation layer 80 is set between the scan line 60 and the common line 70 and the data line 40. It should be understood that the gate insulation layer 80 is set as a whole layer.

[0097] In the embodiments of the present disclosure, Figure 4 and Figure 5 As shown, an adjacent row of scan lines 60 and a row of common lines 70 may be a group and are arranged corresponding to a row of sub-pixels, that is, each row of sub-pixels is adjacent to a row of common lines 70 on one side in the first direction Y, and is adjacent to a row of scan lines 60 on the other side; wherein each scan line 60 is connected to each of the sub-pixels adjacent to it on the same side in the first direction Y, that is, each row of scan lines 60 may be connected to the sub-pixels adjacent to it and located in the same row, so as to provide a scan signal to the sub-pixels in the same row; and each common line 70 is connected to each of the sub-pixels adjacent to it on the same side in the first direction Y, that is, each row of common lines 70 may be connected to the sub-pixels adjacent to it and located in the same row, so as to provide a common signal to the sub-pixels in the same row.

[0098] For example, the scan line 60 and the common line 70 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed of molybdenum, aluminum, titanium, etc.

[0099] In the implementation of the present disclosure, Figure 4 and Figure 5 As shown, the sub-pixel may include a pixel electrode 10, a transistor 20 and a common electrode 50; wherein:

[0100] The structure of the pixel electrode 10 may refer to the contents described in any of the above embodiments, and the specific structure may refer to Figure 1 and Figure 2 As shown, no further repetition is given here.

[0101] like Figure 4 and Figure 5As shown, in the pixel electrode 10 of the sub-pixel, the spacing between the first connecting bar 103 and the data line 40 closest thereto is a first spacing h1, and the spacing between the second connecting bar 105 and the data line 40 closest thereto is a second spacing h2. The first spacing h1 may be equal to the second spacing h2, which facilitates the subsequent design of the sizes of the first connecting bar 103 and the second connecting bar 105 and reduces the difficulty of manufacturing. However, it should be understood that the first spacing h1 may also be different from the second spacing h2, depending on the specific circumstances.

[0102] Combination Figures 4 to 6 As shown, the transistor 20 may include an active layer 203, a gate, and a first electrode 201 and a second electrode 202 disposed in the same layer. For example, the first electrode 201 and the second electrode 202 may be disposed in the same layer as the aforementioned data line 102. A gate insulating layer 80 may be disposed between the gate of the transistor 20 and the active layer 203 to insulate the gate and the active layer 203 from each other. The gate insulating layer 80 may be made of an inorganic material, such as silicon oxide, silicon nitride, and other inorganic materials.

[0103] It should be noted that the gate electrode can be arranged in the same layer as the aforementioned scanning line 60, and this gate electrode can be a part of the aforementioned scanning line 60, that is, a partial structure of the scanning line 60 can be used as the gate electrode of the transistor 20 to realize the connection between the scanning line 60 and the transistor 20; and the first pole 201 and the second pole 202 can be respectively connected to the two doping regions (i.e., the source doping region and the drain doping region) of the active layer 203, and the first pole 201 can also be connected to the data line 40 to realize the connection between the data line 40 and the transistor 20, and the second pole 202 can be connected to the pixel electrode 10, specifically, the end of the first edge conductive portion 101 or the second edge conductive portion 102 of the pixel electrode 10 away from the second connecting bar 105 can be connected to the second pole 202 of the transistor 20 to realize the connection between the transistor 20 and the pixel electrode 10.

[0104] Among them, Figure 4 and Figure 5 As shown, in the second direction X, the transistor 20 of each sub-pixel is arranged closer to the first connecting bar 103 than the second connecting bar 105 of its pixel electrode 10, so that the total capacitance on the side where the first connecting bar 103 of the pixel electrode 10 is located is equal to or substantially equal to the total capacitance on the side where the second connecting bar 105 is located, thereby improving the product grayscale V-Crosstalk phenomenon.

[0105] Furthermore, the orthographic projection of the transistor 20 on the first substrate 30 and the orthographic projection of the first connecting bar 103 of the pixel electrode 10 on the first substrate 30 are arranged opposite to each other in the first direction Y.

[0106] Alternatively, if Figure 4 and Figure 5As shown, two adjacent sub-pixels in the second direction X are used as the minimum repeating unit, wherein, in two adjacent pixel electrodes 10 in the second direction X: the first edge conductive portion 101 of one is connected to the transistor 20 away from the end of the second connecting bar 105, and is closer to the transistor 20 connected thereto than the second edge conductive portion 102 thereof; the second edge conductive portion 102 of the other is connected to the transistor 20 away from the end of the second connecting bar 105, and is closer to the transistor 20 connected thereto than the first edge conductive portion 101 thereof; that is, as Figure 5 As shown, the second connecting bar 105 of one and the first connecting bar 103 of the other are both adjacent to the data line 40 therebetween, and the first connecting bar 103 of one and the second connecting bar 105 of the other are both away from the data line 40 therebetween. In short, one of the two adjacent pixel electrodes 10 in the second direction X can be obtained by vertically flipping the other (i.e., mirroring the second direction X). Such a design can reduce and balance the dark field area while expanding the product viewing angle, but is not limited to this; the connection relationship between the two adjacent pixel electrodes 10 and the transistor 20 in the second direction X can also be made the same, depending on the specific situation.

[0107] It should be noted that the structure of the first edge conductive portion 101 or the second edge conductive portion 102 of one of the two adjacent pixel electrodes 10 in the second direction X can be designed to be completely identical to the first edge conductive portion 101 or the second edge conductive portion 102 of the other, but is not limited thereto. Slight adjustments can also be made according to actual conditions, as long as the total capacitance on the side where the first connecting bar 103 of the pixel electrode 10 is located is equal to or substantially equal to the total capacitance on the side where the second connecting bar 105 is located, thereby improving the product grayscale V-Crosstalk phenomenon.

[0108] For example, the transistor 20 of the embodiment of the present disclosure may be a bottom gate type, that is, a gate may be first formed on the first substrate 30, and the gate may include a metal material or an alloy material, such as molybdenum, aluminum, and titanium, to ensure good conductivity; then, a gate insulating layer 80 is formed on the first substrate 30, such as Figure 6As shown, the gate insulating layer 80 may cover the gate; then, an active layer 203 is formed on the side of the gate insulating layer 80 away from the first substrate 30, that is, the active layer 203 is located on the side of the gate away from the first substrate 30, and the active layer 203 overlaps with the orthographic projection of the gate on the first substrate 30. For example, the orthographic projection of the active layer 203 on the first substrate 30 may be located within the orthographic projection of the gate on the first substrate; the first pole 201 and the second pole 202 may be formed after the active layer 203 is formed, wherein a portion of the first pole 201 may be located on the side of the active layer 203 away from the first substrate 30 and in contact with the source doping region of the active layer 203, and a portion of the second pole 202 may be located on the side of the active layer 203 away from the first substrate 30 and in contact with the drain doping region of the active layer 203.

[0109] It should be noted that the contact mentioned in the embodiment of the present disclosure refers to the two components being directly attached together without any other film layer between them, that is, the two components do not need to be connected through other structures (e.g., transfer vias). In addition, it should be noted that the transistor of the embodiment of the present disclosure is not limited to the bottom gate type mentioned above, but can also be a top gate type.

[0110] In the embodiments of the present disclosure, Figure 4 and Figure 5 As shown, the first electrode 201 and the second electrode 202 of the transistor 20 can be arranged at intervals in the first direction Y, and the spacing between the first electrode 201 and the second electrode 202 in the first direction Y can be a third spacing h3; wherein, the length design of the first connecting bar 103 and the second connecting bar 105 in the pixel electrode 10 mentioned above is related to the size selection of the transistor 20. Specifically, the ratio of the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 to the third spacing h3 can be 2 to 20, such as: 2, 5, 8, 11, 14, 17, 20, etc. For example, the third spacing h3 can be 2μm, 3μm, 4μm, 5μm, 6μm, etc., but is not limited to this, and can also be other values.

[0111] It should be noted that the sum of the lengths of the first connecting bars 103 of each first group of sub-conductive parts in the pixel electrode 10 is not only related to the third spacing S3 mentioned above, but also related to the thickness and length of the first pole 201 and the second pole 202, wherein the thickness, length and third spacing h3 of the first pole 201 and the second pole 202 are the key to determining the size of the lateral capacitance generated between the first pole 201 and the second pole 202 in the transistor 20, that is, the length design of the first connecting bar 103 and the second connecting bar 105 in the pixel electrode 10 mainly depends on the lateral capacitance generated between the first pole 201 and the second pole 202 in the transistor 20.

[0112] For example, the thickness of the first electrode 201 and the second electrode 202 in the transistor 20 may be to for example: And so on, but not limited to this, it can also be other values; and the length of the first electrode 201 and the second electrode 202 in the transistor 20 can be 5μm to 50μm, for example: 5μm, 15μm, 25μm, 35μm, 45μm, 50μm, etc., but not limited to this, it can also be other values.

[0113] It should be understood that the first electrode 201 and the second electrode 202 of the transistor 20 are not limited to being arranged at intervals in the first direction Y, but can also be arranged at intervals in the second direction X. It should be noted that when the first electrode 201 and the second electrode 202 of the transistor 20 are arranged at intervals in the second direction X, the third spacing h3 mentioned above can be understood as the spacing between the first electrode 201 and the second electrode 202 in the second direction X.

[0114] In addition, it should be noted that the length of the first electrode 201 and the second electrode 202 in the transistor 20 refers to the size in a direction perpendicular to the arrangement direction of the first electrode 201 and the second electrode 202 .

[0115] In the embodiments of the present disclosure, Figure 6 As shown, the first electrode 201 and the second electrode 202 of the transistor 20 can be located on the side of the pixel electrode 10 close to the first substrate 30. That is, when manufacturing this array substrate, the first electrode 201 and the second electrode 202 of the transistor 20 can be manufactured first, and then the pixel electrode 10 can be manufactured.

[0116] Among them, Figure 6 As shown, a passivation layer 90 may be provided between the first electrode 201 and the second electrode 202 of the transistor 20 and the pixel electrode 10. The passivation layer 90 may be an inorganic film layer such as silicon nitride, but is not limited thereto, and may also be an organic film layer. It should be noted that at this time, the first edge conductive portion 101 or the second edge conductive portion 202 of the pixel electrode 10 mentioned above may be connected to the second electrode 202 of the transistor 20 through the transfer via P.

[0117] In the embodiments of the present disclosure, Figure 6 As shown, the common electrode 50 may be located on a side of the pixel electrode 10 close to the first substrate 30 and insulated from the pixel electrode 10. For example, the common electrode 50 may be formed on the first substrate 30 before the active layer 203 is formed, that is, the common electrode 50 and the pixel electrode 10 may be insulated by a gate insulating layer 80 and a passivation layer 90 that are stacked.

[0118] Among them, Figure 4 and Figure 6As shown, the positive projection of the common electrode 50 on the first substrate 30 may overlap with the positive projection of the common line 70 on the first substrate 30, wherein the common electrode 50 may be in contact with the common line 70 mentioned above. Specifically, the common electrode 50 may be formed on the first substrate 30 before the common line 70, but is not limited to this, and may also be formed on the first substrate 30 after the common line 70 is formed on the first substrate 30.

[0119] It should be understood that the orthographic projection of the common electrode 50 on the first substrate 30 overlaps with the orthographic projection of the pixel electrode 10 on the first substrate 30 , and does not overlap with the orthographic projection of the data line 40 on the first substrate 30 .

[0120] For example, the material of the common electrode 50 may be the same as that of the pixel electrode 10. The common electrode 50 may be a transparent electrode made of ITO (indium tin oxide) material, but is not limited thereto. It may also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO).

[0121] In the embodiment of the present disclosure, the common electrode 50 may be a plate-shaped electrode, that is, no gap is provided on the common electrode 50, but it is not limited thereto, and a slit may also be provided, depending on the specific situation.

[0122] The embodiment of the present disclosure further provides a display device, which may be a liquid crystal display device, but is not limited thereto. The display device of the embodiment of the present disclosure may include the array substrate described in any of the above embodiments, which will not be repeated here.

[0123] The display device may also include an opposing substrate (not shown in the figure) arranged in a box with the array substrate and a liquid crystal layer (not shown in the figure) located between the array substrate and the opposing substrate. The liquid crystal molecules of the liquid crystal layer may be negative liquid crystals to improve the transmittance, but are not limited to this and may also be positive liquid crystals.

[0124] In the embodiment of the present disclosure, the display device may further include a spacer, and the spacer may be integrated on the opposite substrate, but is not limited thereto, and may also be integrated on the array substrate, depending on specific circumstances.

[0125] Among them, the opposing substrate disclosed in the present invention may include a second substrate (not shown in the figure) and a black matrix layer (not shown in the figure) located on the side of the second substrate close to the array substrate, and the black matrix layer may have a shielding area and a light-transmitting area. The orthographic projection of the shielding area on the first substrate 30 may completely cover the aforementioned data lines 40, scanning lines 60, common lines 70, sub-pixel transistors 20 and spacers, etc., and the shielding area may also cover the edges of the common electrode 50 and the pixel electrode 10; and the orthographic projection of the light-transmitting area on the first substrate 30 may be located within the orthographic projection of the common electrode 50 and the pixel electrode 10 on the first substrate 30.

[0126] In addition, the counter substrate of the present disclosure may further include a color filter layer, and the color filter layer may include a red filter block, a green filter block, a blue filter block, and the like.

[0127] It should be noted that the color filter layer is not limited to being integrated in the opposing substrate, but may also be integrated in the array substrate, depending on the specific situation.

[0128] According to the embodiments of the present disclosure, the specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a television, a car display, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.

[0129] It should be noted that, in addition to the array substrate, opposing substrate and liquid crystal layer mentioned above, the display device also includes other necessary components and components. Taking the display as an example, it may also include a backlight module, a casing, a main circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements based on the specific use requirements of the display device, which will not be repeated here.

[0130] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein: It comprises a first substrate (30) and sub-pixels located on the first substrate (30) and arranged in an array along a first direction (Y) and a second direction (X), wherein the sub-pixels comprise transistors (20) and pixel electrodes (10) connected to the transistors (20); The pixel electrode (10) comprises: a main conductive portion, the main conductive portion comprising at least one first group of sub-conductive portions and at least one second group of sub-conductive portions, the first group of sub-conductive portions and the second group of sub-conductive portions being alternately arranged in the first direction (Y); The first group of sub-conductive parts comprises a first connecting strip (103), the first connecting strip (103) extends in the first direction (Y) and has a first surface (103a) and a second surface (103b) opposite to each other in the second direction (X); the first group of sub-conductive parts comprises a first slit (S1) located on a side of the first surface (103a) away from the second surface (103b), and an end of the first slit (S1) away from the first connecting strip (103) is an open end; The second group of sub-conductive parts comprises a second connecting strip (105), the second connecting strip (105) extends in the first direction (Y), the second connecting strip (105) is at least partially connected to one side of the first group of sub-conductive parts in the first direction (Y), the second connecting strip (105) has a third surface (105a) and a fourth surface (105b) opposite to each other in the second direction (X), and in the second direction (X), the third surface (105a) is located between the fourth surface (105b) and the first surface (103a); and the second group of sub-conductive parts has a second slit (S2) located on a side of the third surface (105a) away from the fourth surface (105b), and an end of the second slit (S2) away from the second connecting strip (105) is an open end; Wherein, in the second direction (X), the pixel electrode (10) is configured such that the first connecting bar (103) is closer to the transistor (20) than the second connecting bar (105); wherein the sum of the lengths of the first connecting strips (103) in the at least one first group of sub-conductive parts is less than the sum of the lengths of the second connecting strips (105) in the at least one second group of sub-conductive parts; Wherein, the first direction (Y) intersects with the second direction (X).

2. The array substrate according to claim 1, wherein: The first group of sub-conductive parts also includes a plurality of first electrode strips (104) arranged at intervals in the first direction (Y), the plurality of first electrode strips (104) are located at a position of the first surface (103a) away from the second surface (103b) and connected to the first surface (103a); and the first gap (S1) is provided between two adjacent first electrode strips (104); The second group of sub-conductive parts also includes a plurality of second electrode strips (106) arranged at intervals in the first direction (Y), the plurality of second electrode strips (106) are located at a position of the third surface (105a) away from the fourth surface (105b) and connected to the third surface (105a); and a second gap (S2) is provided between two adjacent second electrode strips (106); The third surface (105a) of the second connecting strip (105) is connected to the end of the first electrode strip (104) closest to the second group of sub-conductive parts and away from the first connecting strip (103).

3. The array substrate according to claim 2, wherein: The length of the first connecting strip (103) is smaller than the length of the second connecting strip (105).

4. The array substrate according to claim 3, wherein: The pixel electrode (10) further comprises: a first edge conductive portion (101) and a second edge conductive portion (102) arranged at intervals in a first direction (Y); the main conductive portion is at least partially located between the first edge conductive portion (101) and the second edge conductive portion (102); and the main conductive portion is connected to the first edge conductive portion (101) and the second edge conductive portion (102), respectively; The main conductive part includes one of the first group of sub-conductive parts and one of the second group of sub-conductive parts, The first edge conductive portion (101) is located on a side of the plurality of first electrode strips (104) away from the second group of sub-conductive portions, and is located at a position where the first surface (103a) of the first connecting strip (103) is away from the second surface (103b); the first edge conductive portion (101) is connected to the first surface (103a), and has a third gap (S3) with the first electrode strip (104) adjacent thereto, and an end of the third gap (S3) away from the first connecting strip (103) is an open end; The second edge conductive portion (102) is located on a side of the plurality of second electrode strips (106) away from the first group of sub-conductive portions, and is located at a position where the third surface (105a) of the second connecting strip (105) is away from the fourth surface (105b); the second edge conductive portion (102) is connected to the third surface (105a), and has a fourth gap (S4) with the second electrode strip (106) adjacent thereto, and an end of the fourth gap (S4) away from the second connecting strip (105) is an open end.

5. The array substrate according to claim 4, wherein: The first electrode strip (104), the first slit (S1) and the third slit (S3) extend in the same direction and intersect with the first direction (Y) and the second direction (X); and the second electrode strip (106), the second slit (S2) and the fourth slit (S4) extend in the same direction and intersect with the first direction (Y) and the second direction (X).

6. The array substrate according to claim 5, wherein: The widths of the first electrode strip (104), the second electrode strip (106), the first slit (S1), the second slit (S2), the third slit (S3) and the fourth slit (S4) are equal.

7. The array substrate according to claim 6, wherein: The first electrode strips (104) and the second electrode strips (106) extend in the same direction, and the second gaps (S2) are provided between adjacent first electrode strips (104) and second electrode strips (106).

8. The array substrate according to claim 6, wherein: The extension direction of the first electrode strip (104) and the extension direction of the second electrode strip (106) are arranged in a mirror image with respect to the second direction (X).

9. The array substrate according to claim 8, wherein: The second group of sub-conductive parts further comprises an adjustment part (107), the adjustment part (107) being located on a side of the plurality of second electrode strips (106) close to the first group of sub-conductive parts and being located at a position where the third surface (105a) of the second connecting strip (105) is away from the fourth surface (105b), the adjustment part (107) being connected to the third surface (105a) of the second connecting strip (105); wherein, A fifth gap (S5) is formed between the adjustment portion (107) and the first electrode strip (104) adjacent thereto, and a sixth gap (S6) is formed between the adjustment portion (107) and the second electrode strip (106) adjacent thereto; The ends of the fifth slit (S5) and the sixth slit (S6) away from the second connecting strip (105) are both open ends; The fifth slit (S5) has the same extension direction and the same width as the first slit (S1), and the sixth slit (S6) has the same extension direction and the same width as the second slit (S2).

10. The array substrate according to claim 9, wherein: The adjustment portion (107) comprises a first adjustment strip (107a) and a second adjustment strip (107b), the fifth gap (S5) is formed between the first adjustment strip (107a) and the first electrode strip (104), and the sixth gap (S6) is formed between the second adjustment strip (107b) and the second electrode strip (106); wherein, The first adjustment strip (107a) extends in the same direction as the first electrode strip (104) and has the same width, and the second adjustment strip (107b) extends in the same direction as the second electrode strip (106) and has the same width; One end of the first adjustment strip (107a) and the second adjustment strip (107b) in the extension direction thereof is connected to the third surface (105a) of the second connection strip (105), and the other ends are connected to each other.

11. The array substrate according to any one of claims 1 to 10, wherein: The ratio of the sum of the lengths of the first connecting strips (103) in the at least one first group of sub-conductive parts to the sum of the lengths of the second connecting strips (105) in the at least one second group of sub-conductive parts is 0.1 to 0.

9.

12. The array substrate according to claim 1, wherein: It also includes a plurality of data lines (40) formed on the first substrate (30), the data lines (40) extending in the first direction (Y), and the data lines (40) and the sub-pixels are alternately arranged in the second direction (X); In the pixel electrode (10) of the sub-pixel, the spacing between the first connecting bar (103) and the data line (40) closest thereto is a first spacing (h1), the spacing between the second connecting bar (105) and the data line (40) closest thereto is a second spacing (h2), and the first spacing (h1) and the second spacing (h2) are equal.

13. The array substrate according to claim 12, wherein: The pixel electrode (10) further comprises: a first edge conductive portion (101) and a second edge conductive portion (102) arranged at intervals in a first direction (Y); the main conductive portion is at least partially located between the first edge conductive portion (101) and the second edge conductive portion (102); and the main conductive portion is connected to the first edge conductive portion (101) and the second edge conductive portion (102), respectively; Each of the data lines (40) is connected to the transistors (20) of the sub-pixels located on the same side of the data line in the second direction (X) and adjacent thereto; The first electrode (201) and the second electrode (202) of the transistor (20) are arranged in the same layer as the data line (40), and are located on a side of the pixel electrode (10) close to the first substrate (30); the first electrode (201) of the transistor (20) is connected to the data line (40), and the second electrode (202) of the transistor (20) is connected to the second edge conductive portion (102) or the first edge conductive portion (101) of the pixel electrode (10) through a transfer via (P).

14. The array substrate according to claim 13, wherein: The first electrode (201) and the second electrode (202) of the transistor (20) are arranged at intervals in the first direction (Y), and the distance between the first electrode (201) and the second electrode (202) in the first direction (Y) is a third distance (h3); The ratio of the sum of the lengths of the first connecting strips (103) in the at least one first group of sub-conductive parts to the third spacing (h3) is 2 to 20.

15. The array substrate according to claim 13, wherein: The sub-pixel further comprises a common electrode (50), which is located on a side of the pixel electrode (10) close to the first substrate (30) and is insulated from the pixel electrode (10); Furthermore, the orthographic projection of the common electrode (50) on the first substrate (30) overlaps with the orthographic projection of the pixel electrode (10) on the first substrate (30), and does not overlap with the orthographic projection of the data line (40) on the first substrate (30).

16. The array substrate according to claim 15, wherein: The array substrate further comprises a plurality of scanning lines (60) and a plurality of common lines (70) formed on the first substrate (30) and extending in the second direction (X), the scanning lines (60) and the common lines (70) being arranged alternately in the first direction (Y), and the orthographic projections of the scanning lines (60) on the first substrate (30) do not overlap with the orthographic projections of the common lines (70) on the first substrate (30); The scanning line (60) and the common line (70) are arranged in the same layer, and the scanning line (60) and the common line (70) are located on a side of the data line (40) close to the first substrate (30) and are insulated from the data line (40); Wherein, one side of the sub-pixel in the first direction (Y) is adjacent to the common line (70), and the other side is adjacent to the scanning line (60); Wherein, each of the scanning lines (60) is connected to the gate of the transistor (20) of each of the sub-pixels located on the same side of the scanning line in the first direction (Y) and adjacent thereto; Each of the common lines (70) is connected to the common electrodes (50) of the sub-pixels located on the same side of the common line in the first direction (Y) and adjacent thereto.

17. The array substrate according to claim 16, wherein: Part of the scan line (60) constitutes the gate of the transistor (20), and the common electrode (50) is in contact with the common line (70).

18. The array substrate according to claim 1, wherein: The orthographic projection of the transistor (20) on the first substrate (30) and the orthographic projection of the first connecting bar (103) of the pixel electrode (10) on the first substrate (30) are arranged opposite to each other in the first direction (Y).

19. The array substrate according to claim 18, wherein: The pixel electrode (10) further comprises: a first edge conductive portion (101) and a second edge conductive portion (102) arranged at intervals in a first direction (Y); the main conductive portion is at least partially located between the first edge conductive portion (101) and the second edge conductive portion (102); and the main conductive portion is connected to the first edge conductive portion (101) and the second edge conductive portion (102), respectively; In two adjacent pixel electrodes (10) in the second direction (X): In one of the pixel electrodes (10): the first edge conductive portion (101) is connected to the transistor (20) at an end away from the second connecting bar (105) in the second direction (X), and the first edge conductive portion (101) is closer to the transistor (20) connected to the pixel electrode (10) than the second edge conductive portion (102); In another pixel electrode (10): the second edge conductive portion (102) is connected to the transistor (20) at an end away from the second connecting bar (105) in the second direction (X), and the second edge conductive portion (102) is closer to the transistor (20) connected to the pixel electrode (10) than the first edge conductive portion (101).

20. A display device, wherein: The invention comprises the array substrate according to any one of claims 1 to 19 and an opposing substrate arranged in a box with the array substrate.

Images