Array substrate, manufacturing method of array substrate and display device

Abstract

The invention belongs to the technical field of display, and particularly relates to an array substrate, a manufacturing method of the array substrate and a display device. The array substrate comprises a first power supply structure and a second power supply structure which are located on the same side of a substrate. The pixel electrode is located on the side, away from the substrate, of the first power supply structure and connected with the first power supply structure; the common electrode is connected with the second power supply structure and located on the side, away from the substrate, of the second power supply structure; the color resistance layer is located between the substrate and the first power supply structure and between the substrate and the second power supply structure. The color resistance layer is arranged between the substrate and the first power supply structure and between the substrate and the second power supply structure, the pixel electrode is arranged on the side, away from the substrate, of the first power supply structure, and the common electrode is arranged on the side, away from the substrate, of the second power supply structure, so that the situation that the pixel electrode and the common electrode penetrate through the color resistance layer is reduced; and the probability of breakage of the pixel electrode and the common electrode is reduced.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to an array substrate, a method for manufacturing the array substrate, and a display device. Background Art

[0002] COA (color filter on array) technology refers to the technology of directly making a color resist layer on an array substrate. The COA technology can reduce the aperture ratio loss caused by the alignment accuracy between the array substrate and the opposing substrate, and can effectively solve the problems such as light leakage caused by alignment deviation in the display device box-aligning process, and can significantly improve the aperture ratio.

[0003] In the current COA array substrates, the gate, gate insulation layer, semiconductor layer, source, drain and other structural layers in the transistor are first made on the substrate, and then the color resist layer and the planar layer are successively made on the side of the transistor away from the substrate, a via is formed on the planar layer, and a pixel electrode and a common electrode are formed on the side of the planar layer away from the color resist layer. The pixel electrode and the common electrode are mounted on the inner wall of the via to achieve connection with the drain and other power supply electrodes in the transistor through the via and obtain voltage.

[0004] In an array substrate, the color resist layer is usually thicker. When the pixel electrode and the common electrode need to be connected to the power supply electrode such as the drain in the thin film transistor through the via, the via needs to pass through the flat layer and the thicker color resist layer, which results in a very large via depth. When the pixel electrode and the common electrode are mounted on the via and connected to the power supply electrode such as the drain in the thin film transistor, the deeper via can easily cause the pixel electrode and the common electrode mounted thereon to break in the film layer, which will lead to a decrease in the manufacturing yield of the array substrate. Summary of the invention

[0005] The purpose of the present application is to provide an array substrate, a method for manufacturing an array substrate, and a display device, which can reduce the penetration of pixel electrodes and common electrodes through the color resist layer and reduce the probability of breakage of pixel electrodes and common electrodes by arranging a color resist layer between a substrate and a first power supply structure, and between a substrate and a second power supply structure, and arranging a pixel electrode on a side of the first power supply structure away from the substrate, and arranging a common electrode on a side of the second power supply structure away from the substrate.

[0006] The present disclosure provides an array substrate, comprising:

[0007] substrate;

[0008] The first power supply structure and the second power supply structure are both arranged on the same surface of the substrate;

[0009] a pixel electrode, located at a side of the first power supply structure away from the substrate and connected to the first power supply structure;

[0010] a common electrode, the common electrode being connected to the second power supply structure and being located on a side of the second power supply structure away from the substrate, the common electrode and the pixel electrode being spaced apart, the first power supply structure being used to supply power to the pixel electrode, and the second power supply structure being used to supply power to the common electrode, so that an electric field is formed between the pixel electrode and the common electrode;

[0011] The color resist layer is located between the substrate and the first power supply structure and between the substrate and the second power supply structure to reduce the pixel electrode and the common electrode from penetrating through the color resist layer.

[0012] In an exemplary embodiment of the present disclosure, the array substrate includes a first flat layer, the first flat layer is located on a side of the color resist layer away from the substrate, the first flat layer is located on a side of the first power supply structure away from the pixel electrode, and the first flat layer is also located on a side of the second power supply structure away from the common electrode.

[0013] In an exemplary embodiment of the present disclosure, the thickness of the color resist layer is in the range of 2um-3um, and the thickness of the first planar layer is in the range of 0.3um-0.4um.

[0014] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0015] A gate, located at a side of the color resist layer away from the substrate;

[0016] A first insulating layer, located on a side of the gate away from the color resist layer;

[0017] A semiconductor layer, located on a side of the first insulating layer away from the gate;

[0018] a source electrode, wherein the source electrode and the first power supply structure are both located on a side of the semiconductor layer away from the first insulating layer, and the source electrode and the first power supply structure are spaced apart from each other;

[0019] The second power supply structure comprises:

[0020] A power supply electrode, located on a side of the color resist layer away from the substrate;

[0021] The second insulating layer is located on a side of the power supply electrode away from the color resist layer.

[0022] In an exemplary embodiment of the present disclosure, the gate electrode and the power supply electrode are arranged in the same layer, and the first insulating layer and the second insulating layer are arranged in the same layer.

[0023] In an exemplary embodiment of the present disclosure, the array substrate further includes a second flat layer, the second flat layer at least covers a side of the first power supply structure away from the color resist layer, and covers a side of the second power supply structure away from the color resist layer, the pixel electrode and the common electrode are located on a side of the second flat layer away from the substrate,

[0024] The second planar layer is provided with a first via hole and a second via hole. The pixel electrode is connected to the first power supply structure through the first via hole, and the common electrode is connected to the power supply electrode through the second via hole.

[0025] In an exemplary embodiment of the present disclosure, the array substrate further includes a second flat layer, the second flat layer at least covers a side of the pixel electrode away from the color resist layer, and covers a side of the second power supply structure away from the color resist layer, the pixel electrode is located between the first insulating layer and the second flat layer, and the pixel electrode is connected to the first power supply structure, and the common electrode is located on a side of the second flat layer away from the substrate.

[0026] The second planar layer is provided with a second via hole, and the common electrode is connected to the power supply electrode through the second via hole.

[0027] The present disclosure provides a method for manufacturing an array substrate, the steps of the manufacturing method comprising:

[0028] forming a color resist layer on one side of the substrate;

[0029] Forming a first power supply structure and a second power supply structure on a side of the color resist layer away from the substrate;

[0030] A pixel electrode and a common electrode are formed on the side of the first power supply structure and the second power supply structure away from the substrate, wherein the pixel electrode is connected to the first power supply structure, the common electrode is connected to the second power supply structure, and the pixel electrode and the common electrode are spaced apart.

[0031] In an exemplary embodiment of the present disclosure, before the step of forming the first power supply structure and the second power supply structure on the side of the color resist layer away from the substrate, the manufacturing method further includes: forming a first planar layer on the side of the color resist layer away from the substrate;

[0032] The step of forming a first power supply structure and a second power supply structure on a side of the color resist layer away from the substrate comprises:

[0033] forming a gate and a power supply electrode on a side of the color resist layer away from the substrate;

[0034] forming an insulating layer on a side of the gate and the power supply electrode away from the color resist layer;

[0035] forming a semiconductor layer on a side of the insulating layer away from the gate;

[0036] A source electrode and a first power supply structure are formed on a side of the semiconductor layer away from the insulating layer, and the source electrode and the first power supply structure are spaced apart.

[0037] The present disclosure provides a display device, which includes any array substrate as described above.

[0038] This application scheme has the following beneficial effects:

[0039] The present disclosure provides an array substrate, a method for manufacturing the array substrate, and a display device. In the array substrate, a first power supply structure, a second power supply structure, a pixel electrode, a common electrode, and a color resist layer are arranged on the same side of a substrate, the color resist layer is arranged between the substrate and the first power supply structure, and between the substrate and the second power supply structure, and the pixel electrode is arranged on a side of the first power supply structure away from the substrate, and the common electrode is arranged on a side of the second power supply structure away from the substrate, so that when the pixel electrode is connected to the first power supply structure and the common electrode is connected to the second power supply structure, the pixel electrode and the common electrode can be reduced from penetrating the color resist layer, thereby reducing the probability of the pixel electrode and the common electrode being broken, thereby improving the manufacturing yield of the array substrate.

[0040] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0041] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0043] Figure 1 It is a schematic diagram of the cross-sectional structure of a COA array substrate in IPS mode in the related art.

[0044] Figure 2 It is a schematic diagram of the cross-sectional structure of an array substrate in the FFS mode in the related art.

[0045] Figure 3It is a schematic diagram of the cross-sectional structure of a COA array substrate in FFS mode in the related art.

[0046] Figure 4 Schematic diagram of the cross-sectional structure of the COA array substrate in the IPS mode in the embodiment of the present disclosure.

[0047] Figure 5 Schematic diagram of the cross-sectional structure of the COA array substrate in the FFS mode in the embodiment of the present disclosure.

[0048] Figure 6 The figure is a flow chart of a method for manufacturing an array substrate in an embodiment of the present disclosure.

[0049] Figure 7 Another schematic diagram of the process of manufacturing the array substrate in the embodiment of the present disclosure is shown.

[0050] Figure 8 It is a flowchart of a method for manufacturing a first power supply structure and a second power supply structure in an embodiment of the present disclosure.

[0051] Description of reference numerals:

[0052] 1. Array substrate;

[0053] 11. substrate; 12. color resist layer; 13. first flat layer; 141. gate; 142. insulating layer; 142a. first insulating layer; 142b. second insulating layer; 143. semiconductor layer; 144. source; 145. first power supply structure; 146. power supply electrode; 147. second power supply structure; 15. second flat layer; 151. first via hole; 152. second via hole; 16. pixel electrode; 17. common electrode; 18. flat layer. DETAILED DESCRIPTION

[0054] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concept of the example embodiments to those skilled in the art.

[0055] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0056] The present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be understood as limiting the present disclosure.

[0057] At present, in the relevant technical solutions for the array substrate 1 manufactured by COA (color filter on array) technology, a transistor including a gate, a source, a drain and other structures is first formed on a substrate 11, and then a color resist layer 12, a planarization layer 18, a pixel electrode 16, and a common electrode 17 are sequentially formed on the side of the transistor away from the substrate 11.

[0058] like Figure 1 As shown, in the array substrate 1 of the IPS (In-Plane Switching) mode, the pixel electrode 16 and the common electrode 17 are both arranged on the side of the flat layer 18 away from the substrate 11, and the pixel electrode 16 and the common electrode 17 are arranged at intervals, and the pixel electrode 16 and the common electrode 17 are connected to the transistor through a via. At this time, the via will penetrate the flat layer and the thicker color resist layer 12, resulting in a larger via depth, and the via morphology is difficult to control, which can easily cause the aperture ratio of the via to be too large, thereby causing the problem of reduced pixel aperture ratio, and when the pixel electrode 16 and the common electrode 17 are mounted on the via and connected to the transistor, the inner wall slope angle of the deeper via is too steep, which can easily cause the pixel electrode 16 and the common electrode 17 mounted thereon to have a film layer break, thereby causing a decrease in the manufacturing yield of the array substrate 1.

[0059] like Figure 2 As shown, in a related technology of an array substrate 1 in a FFS (Fringe Field Switching, in-plane switching) mode, no other structural layer is set between the pixel electrode 16 and the transistor, and no via is set, but the pixel electrode 16 and the transistor are directly connected. In this array substrate 1, the color resist layer 12 (not shown in the figure) is set between the transistor and the common electrode 17, and the common electrode 17 is connected to the transistor through the via. At this time, the via will still pass through the thicker color resist layer 12, and it is also impossible to solve the problem that the common electrode 17 film is easy to break due to the via being too deep. If the color resist layer 12 and the flat layer 18 are placed between the pixel electrode 16 and the common electrode 17, the interlayer between the pixel electrode 16 and the common electrode 17 will be too thick, so that the thickness between the pixel electrode 16 and the common electrode 17 increases, the electric field becomes weak, and then the power consumption of the array substrate 1 increases. In addition, the color resist layer 12 is usually made of organic material, and the risk of charge residue will increase when it is sandwiched between the electric field.

[0060] like Figure 3 As shown, in another related technology of the array substrate 1 of the FFS mode, a transistor is first formed on the substrate 11, and then a color resist layer 12, a planar layer 18, a pixel electrode 16, an insulating layer 142 and a common electrode 17 are sequentially formed on the side of the transistor away from the substrate 11. In this technical solution, the pixel electrode 16 and the common electrode 17 are layered by the insulating layer 142, and the pixel electrode 16 and the common electrode 17 are arranged in layers and overlapped, and are both connected to the transistor through vias. Since the color resist layer 12 and the planar layer 18 are located between the transistor and the pixel electrode 16, and between the transistor and the common electrode 17, it is impossible to avoid the vias passing through the thicker color resist layer 12, and there is still a problem that the vias are deep, which may cause the pixel electrode 16 and the common electrode 17 to be easily broken.

[0061] In order to solve the problem that the pixel electrode 16 and the common electrode 17 in the array substrate 1 in the related technical solution are penetrated through the thicker color resist layer 12 to achieve connection with the transistor, thereby causing the pixel electrode 16 and the common electrode 17 to be easily broken, the present disclosure provides an array substrate 1, such as Figures 4 to 5 As shown, the array substrate 1 includes: a substrate 11, a first power supply structure 145, a second power supply structure 147, a pixel electrode 16, a common electrode 17 and a color resist layer 12. The first power supply structure 145 and the second power supply structure 147 are both arranged on the same surface of the substrate 11; the pixel electrode 16 is located on the side of the first power supply structure 145 away from the substrate 11, and the pixel electrode 16 is connected to the first power supply structure 145. The common electrode 17 is located on the side of the second power supply structure 147 away from the substrate 11, and is connected to the second power supply structure 147. The common electrode 17 and the pixel electrode 16 are arranged at intervals, and the first power supply structure 145 is used to supply power to the pixel electrode 16, and the second power supply structure 147 is used to supply power to the common electrode 17, so that an electric field is formed between the pixel electrode 16 and the common electrode 17. The color resist layer 12 is located between the substrate 11 and the first power supply structure 145, and the color resist layer 12 is also located between the substrate 11 and the second power supply structure 147.

[0062] In the disclosed embodiment, the substrate 11 may be made of sapphire, silicon carbide, silicon, and other materials, but is not limited thereto. The substrate 11 may also be made of gallium arsenide, aluminum nitride, zinc oxide, and other materials. The material for making the substrate 11 may be adjusted according to actual needs.

[0063] It should be noted that the substrate 11 in the present disclosure may have good light transmittance to reduce the possibility of the substrate 11 blocking the light when the light passes through the substrate 11 into a wide viewing angle, thereby improving the transmittance of the light in the array substrate 1.

[0064] The present disclosure arranges the color resist layer 12 between the substrate 11 and the first power supply structure 145, and between the substrate 11 and the second power supply structure 147, and arranges the pixel electrode 16 on the side of the first power supply structure 145 away from the substrate 11, and arranges the common electrode 17 on the side of the second power supply structure 147 away from the substrate 11, so that when the pixel electrode 16 is connected to the first power supply structure 145 and the common electrode 17 is connected to the second power supply structure 147, the pixel electrode 16 and the common electrode 17 can be reduced from penetrating the color resist layer 12, and the possibility of the pixel electrode 16 and the common electrode 17 being easily broken due to the connection path between the pixel electrode 16 and the first power supply structure 145 and the connection path between the common electrode 17 and the second power supply structure 147 being too long is reduced, thereby improving the manufacturing yield of the array substrate 1, reducing the materials used to make the pixel electrode 16 and the common electrode 17, and reducing the manufacturing cost of the array substrate 1.

[0065] Furthermore, the array substrate 1 in the embodiment of the present disclosure may also include a first flat layer 13, which is located on the side of the color resist layer 12 away from the substrate 11. At the same time, the first flat layer 13 is also located on the side of the first power supply structure 145 away from the pixel electrode 16, and on the side of the second power supply structure 147 away from the common electrode 17.

[0066] It should be noted that the color resist layer 12 in the present disclosure may include color resist blocks of multiple different colors so that the emitted light appears in color. When a plurality of color resist blocks are formed, there may be a certain height difference between the plurality of color resist blocks. Therefore, when the first power supply structure 145 and the second power supply structure 147 are arranged on the surface of the color resist layer 12 and connected to the uneven color resist layer 12, the first power supply structure 145 and the second power supply structure 147 may be broken or even fall off from the color resist layer 12. The present disclosure forms a first flat layer 13 on the side of the color resist layer 12 away from the substrate 11 to flatten the surface of the color resist layer 12, reduce the potential difference on the side of the first flat layer 13 away from the substrate 11, and reduce the possibility of the first power supply structure 145 and the second power supply structure 147 being broken or even falling off, thereby improving the manufacturing yield of the array substrate 1 and extending the service life of the array substrate 1.

[0067] The thickness of the color resist layer 12 ranges from 2um to 3um. Specifically, the thickness of the color resist layer 12 can be 2um, 2.1um, 2.2um, 2.3um, 2.4um, 2.5um, 2.6um, 2.7um, 2.8um, 2.9um, 3um, etc., but is not limited thereto. The thickness of the color resist layer 12 can be set according to actual conditions. The color resist layer 12 is used to filter light of different wavelengths so that light of a specific wavelength can pass through the color resist layer 12 and enter the wide field of view, thereby adjusting the wavelength of light emitted to the wide field of view. If the thickness of the color resist layer 12 is less than 2um, the color resist layer 12 has a poor light filtering effect, and may not be able to achieve a good light filtering effect. If the thickness of the color resist layer 12 is greater than 3um, the light blocking effect of the color resist layer 12 will be increased, which may result in too low light transmittance.

[0068] In the embodiment of the present disclosure, the material for making the first flat layer 13 can be an organic material, such as: acrylic resin (polymethyl methacrylate, also called PMMA), acrylic resin, silicone resin and the like, but not limited thereto. The first flat layer 13 can also be made of inorganic materials to improve the stress matching between the first flat layer 13 and the first power supply structure 145 and the second power supply structure 147.

[0069] It should be noted that the first flat layer 13 in the present disclosure may also have good insulation properties. When the material used to make the color resist layer 12 has conductive properties, the first flat layer 13 located between the color resist layer 12 and the first power supply structure 145 and the second power supply structure 147 may play an insulating role, thereby reducing the possibility of the color resist layer 12 interfering with the power supply from the first power supply structure 145 to the pixel electrode 16 and the second power supply structure 147 to the common electrode 17, thereby ensuring the stability of the power supply when the array substrate 1 is working.

[0070] The thickness of the first flat layer 13 ranges from 0.3um to 0.4um. Specifically, the thickness of the first flat layer 13 may be 0.3um, 0.31um, 0.32um, 0.33um, 0.34um, 0.35um, 0.36um, 0.37um, 0.38um, 0.39um, 0.4um, etc., but not limited thereto. The thickness of the first flat layer 13 may be set according to actual conditions. Since the first flat layer 13 has the function of flattening the side of the color resist layer 12 away from the substrate 11, if the thickness of the first flat layer 13 is less than 0.3um, the thickness of the first flat layer 13 may be less than the terrain difference formed between different color resist blocks on the color resist layer 12, which may result in an insignificant flattening effect. If the thickness of the first flat layer 13 is greater than 0.4um, the thickness of the first flat layer 13 is much greater than the terrain difference formed on the surface of the color resist layer 12. If the first flat layer 13 is too thick, the array substrate 1 will be too thick as a whole, which is not conducive to achieving a thin and light product.

[0071] The array substrate 1 in the present disclosure includes a transistor, wherein the transistor may include, in addition to the first power supply structure 145 described above, a gate 141, a first insulating layer 142a, a semiconductor layer 143, and a source 144. The gate 141 is located on the side of the color resist layer 12 away from the substrate 11; the first insulating layer 142a is located on the side of the gate 141 away from the color resist layer 12; the semiconductor layer 143 is located on the side of the first insulating layer 142a away from the gate 141; the source 144 and the first power supply structure 145 are both located on the side of the semiconductor layer 143 away from the first insulating layer 142a, and the source 144 and the first power supply structure 145 are spaced apart.

[0072] It should be noted that the first power supply structure 145 is an electrode corresponding to the source 144 . When a high voltage is applied to the gate 141 , the transistor is turned on, so that the voltage can enter the first power supply structure 145 from the source 144 and supply power to the pixel electrode 16 through the first power supply structure 145 .

[0073] The first insulating layer 142a can be made of insulating materials such as silicon nitride (SiNx), acrylic resin, acrylic resin, silicone resin, etc., which is used to prevent current from flowing between the gate 141 and the semiconductor layer 143, while allowing the electric field of the gate 141 to affect the charge distribution in the semiconductor layer 143, but is not limited to this. The first insulating layer 142a can also be made of other materials with good insulating properties, which can be determined according to actual conditions.

[0074] In the embodiment of the present disclosure, the second power supply structure 147 may include a power supply electrode 146 and a second insulating layer 142b. The power supply electrode 146 is located on the side of the color resist layer 12 away from the substrate 11, and the power supply electrode 146 is spaced apart from the gate 141. The second insulating layer 142b is located on the side of the power supply electrode 146 away from the color resist layer 12.

[0075] The second insulating layer 142b can be made of insulating materials such as silicon nitride, acrylic resin, acrylic resin, silicone resin, etc. to isolate the power supply electrode 146 from other devices to prevent other devices from causing electrical interference to the power supply electrode 146. At the same time, it can also prevent other devices and water vapor in the air from damaging the power supply electrode 146, thereby extending the service life of the array substrate 1.

[0076] Furthermore, the gate 141 and the power supply electrode 146 in the embodiment of the present disclosure can be arranged on the same layer. By arranging the gate 141 and the power supply electrode 146 on the same layer, the gate 141 and the power supply electrode 146 can be simultaneously manufactured by a one-time forming process, thereby reducing the manufacturing process of the array substrate 1 and improving the manufacturing efficiency of the array substrate 1.

[0077] In addition, the first insulating layer 142a and the second insulating layer 142b can also be arranged in the same layer. The first insulating layer 142a and the second insulating layer 142b can be formed simultaneously through a one-time formation process, which can reduce the production process of the array substrate 1 and improve the production efficiency of the array substrate 1.

[0078] The array substrate 1 may further include a second planar layer 15 , and the second planar layer 15 may cover a side of the second power supply structure 147 away from the color resist layer 12 .

[0079] It should be noted that covering the second flat layer 15 on the side of the second power supply structure 147 away from the color resist layer 12 can protect the second power supply structure 147 and reduce the possibility of damage caused by contact between the second power supply structure 147 and water vapor in the air or other devices.

[0080] To reduce the possibility of short circuit between the pixel electrode 16 and the common electrode 17 , the second planar layer 15 can be made of insulating materials such as silicon nitride, acrylic resin, acrylic resin, siloxane resin, etc., thereby extending the service life of the array substrate 1 .

[0081] In addition, the second flat layer 15 in the present disclosure can also cover the side of the first power supply structure 145 away from the color resist layer 12 and / or the side of the pixel electrode 16 away from the color resist layer 12. Specifically, the second flat layer 15 can be set according to the positional relationship between the pixel electrode 16 and the common electrode 17 in the array substrate 1.

[0082] Specifically, the positions of the pixel electrode 16 and the common electrode 17 in the array substrate 1 may refer to the following two embodiments.

[0083] Embodiment 1

[0084] like Figure 4 As shown, in the embodiment of the present disclosure, the pixel electrode 16 and the common electrode 17 are both located on the side of the second planar layer 15 away from the substrate 11, and the pixel electrode 16 and the common electrode 17 are spaced apart. The second planar layer 15 is provided with a first via hole 151 and a second via hole 152. The pixel electrode 16 is connected to the first power supply structure 145 through the first via hole 151, and the pixel electrode 16 obtains a voltage through the first power supply structure 145. The common electrode 17 is connected to the power supply electrode 146 through the second via hole 152, and the common electrode 17 obtains a voltage through the power supply electrode 146. After obtaining the voltage, an electric field parallel to the substrate 11 is formed between the pixel electrode 16 and the common electrode 17.

[0085] In the embodiment of the present disclosure, the second flat layer 15 can cover the side of the first power supply structure 145 away from the color resist layer 12 and the side of the second power supply structure 147 away from the color resist layer 12. By providing the second flat layer 15, the possibility of the first power supply structure 145 and the second power supply structure 147 being damaged by contact with water vapor in the air or other devices can be reduced. At the same time, the second flat layer 15 can also improve the structural instability problem caused by stress between the pixel electrode 16 and the first power supply structure 145, and between the common electrode 17 and the second power supply structure 147.

[0086] Embodiment 2

[0087] like Figure 5 As shown, in the embodiment of the present disclosure, the pixel electrode 16 is located between the first insulating layer 142a and the second flat layer 15, and the pixel electrode 16 is connected to the first power supply structure 145 to obtain a voltage through the first power supply structure 145, and the common electrode 17 is located on the side of the second flat layer 15 away from the substrate 11, and the second flat layer 15 is provided with a second via hole 152, and the common electrode 17 is connected to the power supply electrode 146 through the second via hole 152 to obtain a voltage through the power supply electrode 146. At this time, the pixel electrode 16 and the common electrode 17 are arranged in layers, that is, the pixel electrode 16 and the common electrode 17 are arranged in an overlapping manner with each other through the second flat layer 15.

[0088] In the embodiment of the present disclosure, the second flat layer 15 can cover the side of the pixel electrode 16 away from the color resist layer 12 and the side of the second power supply structure 147 away from the color resist layer 12. By providing the second flat layer 15, the possibility of the pixel electrode 16 and the second power supply structure 147 being damaged by contact with water vapor in the air or other devices can be reduced. At the same time, when part of the common electrode 17 extends to the top of the pixel electrode 16 to form an electric field, the second flat layer 15 located between the common electrode 17 and the pixel electrode 16 can optimize the electric field distribution between the pixel electrode 16 and the common electrode 17.

[0089] like Figures 6 to 8 As shown, the present disclosure provides a method for manufacturing an array substrate 1 , and the steps of the manufacturing method include: S1 , forming a color resist layer 12 on one side of a substrate 11 .

[0090] A layer of color resist material may be coated on the substrate 11 first, and the color resist material may be exposed, developed, and etched to obtain the color resist layer 12. By providing the color resist layer 12, outgoing light of different wavelengths may be selectively filtered.

[0091] When the color resist layer 12 includes color resist blocks of multiple different colors, for example, the color resist layer 12 includes red color resist blocks, green color resist blocks, and blue color resist blocks, a layer of red color resist material may be first coated on the substrate 11, and then the red color resist material may be exposed, developed, and etched to obtain red color resist blocks. Then, a layer of green color resist material may be coated on the substrate 11, and the green color resist material may be exposed, developed, and etched to obtain green color resist blocks. Then, a layer of blue color resist material may be coated on the substrate 11, and the blue color resist material may be exposed, developed, and etched to obtain blue color resist blocks. The present disclosure enables the array substrate 1 to emit light of multiple different colors by providing color resist blocks of different colors.

[0092] S2 . Form a first power supply structure 145 and a second power supply structure 147 on a side of the color resist layer 12 away from the substrate 11 .

[0093] S3. A pixel electrode 16 and a common electrode 17 are formed on the side of the first power supply structure 145 and the second power supply structure 147 facing away from the substrate 11, wherein the pixel electrode 16 is connected to the first power supply structure 145, the common electrode 17 is connected to the second power supply structure 147, and the pixel electrode 16 and the common electrode 17 are spaced apart from each other.

[0094] The present disclosure forms a color resist layer 12 on a substrate 11, forms a first power supply structure 145 and a second power supply structure 147 on a side of the color resist layer 12 away from the substrate 11, and then forms a pixel electrode 16 on a side of the first power supply structure 145 away from the color resist layer 12, and forms a common electrode 17 on a side of the second power supply structure 147 away from the color resist layer 12, so as to reduce the pixel electrode 16 and the common electrode 17 from penetrating the color resist layer 12, thereby shortening the connection path between the pixel electrode 16 and the first power supply structure 145 and the connection path between the common electrode 17 and the second power supply structure 147, reducing the possibility of the pixel electrode 16 and the common electrode 17 being broken, thereby improving the manufacturing yield of the array substrate 1 and extending the service life of the array substrate 1.

[0095] It should be noted that if Figure 7 As shown, before the step of forming the first power supply structure 145 and the second power supply structure 147 on the side of the color resist layer 12 away from the substrate 11 , the method for manufacturing the array substrate 1 may further include: S21 , forming a first planar layer 13 on the side of the color resist layer 12 away from the substrate 11 .

[0096] The first flat layer 13 covers the side of the color resist layer 12 facing away from the substrate 11 to reduce the potential difference on the side of the color resist layer 12 facing away from the substrate 11, thereby reducing the possibility that the first power supply structure 145 and the second power supply structure 147 are broken or even fall off due to the potential difference when they are connected to the color resist layer 12. This improves the stability of the connection between the first power supply structure 145 and the second power supply structure 147 and the color resist layer 12, ensuring that the array substrate 1 can continue to work normally under long-term use, thereby extending the service life of the array substrate 1.

[0097] like Figure 8 As shown, the step of forming the first power supply structure 145 and the second power supply structure 147 on the side of the color resist layer 12 away from the substrate 11 may include: S22, forming a gate 141 and a power supply electrode 146 on the side of the color resist layer 12 away from the substrate 11.

[0098] It should be noted that the gate 141 and the power supply electrode 146 can be arranged in the same layer. When the material used to make the gate 141 and the power supply electrode 146 is the same, a gate material layer can be formed on the side of the color resist layer 12 away from the substrate 11, and then the gate material layer is etched to simultaneously form the gate 141 and the power supply electrode 146, thereby simplifying the manufacturing process of the array substrate 1 and improving the manufacturing efficiency of the array substrate 1.

[0099] However, the present invention is not limited thereto, and the gate 141 and the power supply electrode 146 may also be formed by two coating and etching processes, respectively. For example, a gate material may be coated on the side of the color resist layer 12 away from the substrate 11, and the gate material may be etched to form the gate 141, and then a power supply electrode material may be coated on the side of the color resist layer 12 away from the substrate 11, and the power supply electrode material may be etched to form the power supply electrode 146.

[0100] S23 , forming an insulating layer 142 on a side of the gate electrode 141 and the power supply electrode 146 away from the color resist layer 12 .

[0101] The insulating layer 142 may include a first insulating layer 142a and a second insulating layer 142b. The first insulating layer 142a is located on the side of the gate 141 facing away from the substrate 11, and the second insulating layer 142b is located on the side of the power supply electrode 146 facing away from the substrate 11. The insulating layer 142 at least covers the surface of the gate 141 and the power supply electrode 146 to isolate the gate 141 and the power supply electrode 146 from other devices to prevent other devices from causing electrical interference to the gate 141 and the power supply electrode 146. At the same time, it can also prevent other devices and water vapor in the air from damaging the gate 141 and the power supply electrode 146, thereby extending the service life of the array substrate 1.

[0102] The insulating layer 142 can also completely cover the gate 141, the power supply electrode 146 and the color resist layer 12. The side of the insulating layer 142 facing away from the color resist layer 12 can be a horizontal plane to reduce the possibility of other components connected to the side of the insulating layer 142 facing away from the color resist layer 12 being broken and the unstable connection with the insulating layer 142 due to the terrain difference on the side of the insulating layer 142 facing away from the substrate 11. This can improve the stability of the connection between other components and the insulating layer 142, thereby improving the manufacturing yield of the array substrate 1 and extending the service life of the array substrate 1.

[0103] The first insulating layer 142a and the second insulating layer 142b can be arranged in the same layer. When the first insulating layer 142a and the second insulating layer 142b are made of the same material, the insulating material can be coated on the side of the color resist layer 12 away from the substrate 11, and the first insulating layer 142a and the second insulating layer 142b can be formed simultaneously through an etching process, thereby simplifying the production process of the array substrate 1 and improving the production efficiency of the array substrate 1.

[0104] However, the present invention is not limited thereto, and the first insulating layer 142a and the second insulating layer 142b may be formed successively through two coating and etching processes respectively. For example, the material of the first insulating layer 142a may be first coated on the side of the gate electrode 141 facing away from the substrate 11, and then the first insulating layer 142a may be obtained through an etching process. Then, the material of the second insulating layer 142b may be coated on the side of the power supply electrode 146 facing away from the substrate 11, and then the second insulating layer 142b may be obtained through an etching process.

[0105] S24 , forming a semiconductor layer 143 on a side of the insulating layer 142 away from the gate 141 .

[0106] S25 , forming a source electrode 144 and a first power supply structure 145 on a side of the semiconductor layer 143 away from the insulating layer 142 , with the source electrode 144 and the first power supply structure 145 spaced apart from each other.

[0107] The transistor may include a gate 141, a first insulating layer 142a, a semiconductor layer 143, a source 144, and a first power supply structure 145. The semiconductor layer 143 is arranged corresponding to the gate 141. By applying an electric field on the gate 141, the distribution of electrons or holes in the semiconductor layer 143 above the insulating layer 142 is controlled, thereby adjusting the current between the source 144 and the first power supply structure 145.

[0108] In one embodiment of the present disclosure, before the step of forming a pixel electrode 16 and a common electrode 17 on a side of the first power supply structure 145 and the second power supply structure 147 facing away from the substrate 11, the manufacturing method may further include: forming a second planar layer 15 on a side of the first power supply structure 145 and the second power supply structure 147 facing away from the color resist layer 12, and forming a first via hole 151 and a second via hole 152 on the second planar layer 15.

[0109] The step of forming a pixel electrode 16 and a common electrode 17 on the side of the first power supply structure 145 and the second power supply structure 147 facing away from the substrate 11 may include: coating an electrode material on the side of the second flat layer 15 facing away from the color resist layer 12, and etching the electrode material to simultaneously obtain the pixel electrode 16 and the common electrode 17, the pixel electrode 16 and the common electrode 17 are arranged in the same layer with intervals, and part of the pixel electrode 16 is mounted on the inner wall of the first via hole 151, and part of the common electrode 17 is mounted on the inner wall of the second via hole 152, the pixel electrode 16 is connected to the first power supply structure 145 through the first via hole 151, and the common electrode 17 is connected to the power supply electrode 146 through the second via hole 152.

[0110] It should be noted that the orthographic projection of the second flat layer 15 on the substrate 11 at least covers the orthographic projection of the second power supply structure 147 on the substrate 11, so that a via hole can be formed on the second flat layer 15, so that the common electrode 17 can be connected to the second power supply structure 147 by being mounted on the inner wall of the via hole.

[0111] like Figure 5 As shown, in another embodiment of the present disclosure, before the step of forming the source 144 and the first power supply structure 145 on the side of the semiconductor layer 143 away from the insulating layer 142, the manufacturing method also includes: forming a pixel electrode 16 on the side of the first insulating layer 142a away from the gate 141.

[0112] Further, such as Figure 5 As shown, a second flat layer 15 is formed on the side of the pixel electrode 16 and the second power supply structure 147 away from the substrate 11, a second via hole 152 is formed on the second flat layer 15, a common electrode material is coated on the side of the second flat layer 15 away from the color resist layer 12, and the common electrode material is etched to obtain a common electrode 17, and a portion of the common electrode 17 is mounted on the inner wall of the second via hole 152 to achieve connection with the power supply electrode 146. At this time, the pixel electrode 16 and the common electrode 17 are arranged in layers and at intervals through the second flat layer 15, which reduces the pixel electrode 16 and the common electrode 17 passing through the color resist layer 12, thereby reducing the spacing between the pixel electrode 16 and the common electrode 17, and increasing the storage capacitance formed by the pixel electrode 16 and the common electrode 17, so as to meet the demand of the array substrate 1 for leakage current during the display cycle, and improve the working stability of the array substrate 1. In addition, when the color resist layer 12 is made of organic material, compared with the related technical solution in which the color resist layer 12 is set between the pixel electrode 16 and the common electrode 17, the color resist layer 12 in the present disclosure is located on the side of the pixel electrode 16 and the common electrode 17 close to the substrate 11, which can reduce the risk of increasing charge residue due to the color resist layer 12 being sandwiched between the electric field.

[0113] The present disclosure provides a display device, which includes any one of the array substrates 1 mentioned above.

[0114] It should be noted that the display device may also include an opposing substrate and a supporting structure. The supporting structure may be arranged on the opposing substrate. After the opposing substrate is opposed to the array substrate 1, the supporting structure abuts between the array substrate 1 and the opposing substrate to support the array substrate 1 and the opposing substrate, and a liquid crystal layer is formed between the array substrate 1 and the opposing substrate, and liquid crystal molecules are filled in the liquid crystal layer, thereby obtaining a display device.

[0115] The present disclosure forms a color resist layer 12 on a substrate 11 first, then forms a first power supply structure 145 and a second power supply structure 147 on a side of the color resist layer 12 away from the substrate 11, forms a pixel electrode 16 on a side of the first power supply structure 145 away from the color resist layer 12, and forms a common electrode 17 on a side of the second power supply structure 147 away from the color resist layer 12. This can reduce the number of pixel electrodes 16 and common electrodes 17 that penetrate the color resist layer 12, thereby reducing the depth of the first via hole 151 and the second via hole 152. Compared with the technical solution in which the via hole penetrates the color resist layer 12, the present disclosure can more easily control the morphology of the via hole, thereby reducing the aperture ratio of the via hole, thereby improving the pixel aperture ratio of the display device. At the same time, by reducing the depth of the via hole, the slope angle of the inner wall of the via hole can also be reduced, thereby reducing the possibility of the pixel electrode 16 and the common electrode 17 mounted on the inner wall of the via hole being broken, thereby improving the manufacturing yield of the display device.

[0116] In addition, the display device may further include a polarizing plate, which may include an upper polarizing plate and a lower polarizing plate, wherein the upper polarizing plate may be located on the side of the liquid crystal layer close to the opposing substrate, and the lower polarizing plate may be located on the side of the liquid crystal layer close to the array substrate 1. The polarizing plate may twist the light, and when the light passes through the polarizing plate, the light whose polarization direction is perpendicular to the transmission axis of the polarizing plate will be absorbed, and the polarized light whose polarization direction is parallel to the transmission axis of the polarizing plate can pass through the polarizing plate. After applying voltage to the liquid crystal layer, an electric field is formed in the liquid crystal layer, and the electric field can change the polarization direction of the light by changing the deflection of the liquid crystal molecules. Therefore, the display device can be controlled to display in a bright state or a dark state by changing the size of the electric field in the liquid crystal layer and the direction of the transmission axis of the upper polarizing plate and the lower polarizing plate.

[0117] It should be noted that the array substrate 1 in the first embodiment can be used to form an IPS (In-Plane Switching) mode display device. In the IPS mode display device, the liquid crystal molecules are in a plane parallel to the substrate 11. When there is no voltage, the light passes through the lower polarizer to form a linear polarization parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. After the voltage is applied, the liquid crystal forms a lateral electric field on the left and right, and the liquid crystal molecules are arranged along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light is in an (elliptical) circular polarization state and can be emitted through the upper polarizer. By using the array substrate 1 in the second embodiment, a display device in FFS (Fringe Field Switching) mode can be formed. The imaging principle of the display device in FFS mode is similar to that of the in-plane switching display device. The difference is that the pixel electrode 16 and the common electrode 17 in the display device in FFS mode are arranged in layers and overlapped through the second flat layer 15, while the pixel electrode 16 and the common electrode 17 in the display device in IPS mode are arranged in the same layer and spaced apart. Compared with the display device in IPS mode, the thickness of the second flat layer 15 can be reduced in the display device in FFS mode to greatly reduce the distance between the pixel electrode 16 and the common electrode 17. When power is turned on, the liquid crystal molecules rotate in a plane parallel to the substrate 11, ensuring that light passes through the short axis of the liquid crystal molecules in all directions, thereby expanding the viewing angle of the display screen of the display device.

[0118] It should also be noted that the array substrate 1 in the present disclosure is not limited to being applicable to display devices of IPS mode and FFS mode, but can also be applicable to display devices of various display modes such as VA (Vertical Alignment) mode.

[0119] In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the feature. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0120] It should be noted that "upper", "lower", "left", "right" and the like are only used for distinction to facilitate description, and do not impose any directional limitation on the embodiments of the present invention. For example, the "upper" may actually be "lower", "left", "right" and other directions. In the present disclosure, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral whole; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium; it may be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0121] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0122] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. An array substrate, characterized in that: include: substrate; The first power supply structure and the second power supply structure are both arranged on the same surface of the substrate; a pixel electrode, located at a side of the first power supply structure away from the substrate and connected to the first power supply structure; a common electrode, the common electrode being connected to the second power supply structure and being located on a side of the second power supply structure away from the substrate, the common electrode and the pixel electrode being spaced apart, the first power supply structure being used to supply power to the pixel electrode, and the second power supply structure being used to supply power to the common electrode, so that an electric field is formed between the pixel electrode and the common electrode; The color resist layer is located between the substrate and the first power supply structure and between the substrate and the second power supply structure to reduce the pixel electrode and the common electrode from penetrating through the color resist layer.

2. The array substrate according to claim 1, characterized in that: The array substrate includes a first flat layer, which is located on a side of the color resist layer away from the substrate, and on a side of the first power supply structure away from the pixel electrode. The first flat layer is also located on a side of the second power supply structure away from the common electrode.

3. The array substrate according to claim 2, characterized in that: The thickness of the color resist layer is in the range of 2um-3um, and the thickness of the first planar layer is in the range of 0.3um-0.4um.

4. The array substrate according to claim 1, characterized in that: The array substrate further includes: A gate, located at a side of the color resist layer away from the substrate; A first insulating layer, located on a side of the gate away from the color resist layer; A semiconductor layer, located on a side of the first insulating layer away from the gate; a source electrode, wherein the source electrode and the first power supply structure are both located on a side of the semiconductor layer away from the first insulating layer, and the source electrode and the first power supply structure are spaced apart from each other; The second power supply structure comprises: A power supply electrode, located on a side of the color resist layer away from the substrate; The second insulating layer is located on a side of the power supply electrode away from the color resist layer.

5. The array substrate according to claim 4, characterized in that: The gate electrode and the power supply electrode are arranged in the same layer, and the first insulating layer and the second insulating layer are arranged in the same layer.

6. The array substrate according to claim 4, characterized in that: The array substrate further includes a second flat layer, the second flat layer at least covers a side of the first power supply structure away from the color resistance layer and a side of the second power supply structure away from the color resistance layer, the pixel electrode and the common electrode are located on a side of the second flat layer away from the substrate, The second planar layer is provided with a first via hole and a second via hole. The pixel electrode is connected to the first power supply structure through the first via hole, and the common electrode is connected to the power supply electrode through the second via hole.

7. The array substrate according to claim 4, characterized in that: The array substrate further includes a second flat layer, the second flat layer at least covers a side of the pixel electrode away from the color resist layer and a side of the second power supply structure away from the color resist layer, the pixel electrode is located between the first insulating layer and the second flat layer, and the pixel electrode is connected to the first power supply structure, the common electrode is located on a side of the second flat layer away from the substrate, The second planar layer is provided with a second via hole, and the common electrode is connected to the power supply electrode through the second via hole.

8. A method for manufacturing an array substrate, characterized in that: The steps of the production method include: forming a color resist layer on one side of the substrate; Forming a first power supply structure and a second power supply structure on a side of the color resist layer away from the substrate; A pixel electrode and a common electrode are formed on the side of the first power supply structure and the second power supply structure away from the substrate, wherein the pixel electrode is connected to the first power supply structure, the common electrode is connected to the second power supply structure, and the pixel electrode and the common electrode are spaced apart.

9. The manufacturing method according to claim 8, characterized in that: Before the step of forming the first power supply structure and the second power supply structure on the side of the color resist layer away from the substrate, the manufacturing method further comprises: forming a first flat layer on the side of the color resist layer away from the substrate; The step of forming a first power supply structure and a second power supply structure on a side of the color resist layer away from the substrate comprises: forming a gate and a power supply electrode on a side of the color resist layer away from the substrate; forming an insulating layer on a side of the gate electrode and the power supply electrode away from the color resist layer; forming a semiconductor layer on a side of the insulating layer away from the gate; A source electrode and a first power supply structure are formed on a side of the semiconductor layer away from the insulating layer, and the source electrode and the first power supply structure are spaced apart.

10. A display device, characterized in that: The display device comprises the array substrate as claimed in any one of claims 1 to 7.

Images