Liquid crystal display device

Abstract

The invention provides a liquid crystal display device which comprises a plurality of pixels, a plurality of gate lines and a plurality of data lines, each pixel comprises a main pixel and a secondary pixel and only comprises two transistors, the first transistor is electrically connected with the secondary pixel, and the second transistor is electrically connected with the main pixel. In the first embodiment, one group of gate lines comprises a first gate line and a second gate line which are electrically connected with the first transistor and the second transistor respectively, and different gray-scale signals are input to the main pixel and the secondary pixel by controlling the switching time sequence of gate line signals and the input time sequence of data line signals. In the second embodiment, one group of data lines comprises a first data line and a second data line which are electrically connected with the secondary pixels and the main pixels respectively, and the two data lines are controlled to input different gray-scale signals to the main pixels and the secondary pixels at the same time, so that different gray-scale signals are input to the main pixels and the secondary pixels. According to the invention, a common electrode is removed and the number of transistors is reduced, so that the aperture opening ratio and the penetration rate are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a liquid crystal display device. Background Art

[0002] In a liquid crystal display panel, transmittance refers to the ratio of the brightness passing through the liquid crystal display panel to the brightness of the backlight source. It is an important optical parameter of the liquid crystal display panel, and its size directly affects the power consumption and display brightness of the entire device.

[0003] In existing liquid crystal display panels, each pixel usually includes three transistors and a common electrode (Sharebar). Although this design can realize the control of the main pixel and the sub-pixel, due to the existence of the common electrode and the three transistors occupying a large area, the pixel aperture ratio is low, resulting in a low transmittance of the liquid crystal display panel.

[0004] Therefore, how to improve the transmittance of a liquid crystal display panel while ensuring the display effect is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a liquid crystal display device, aiming to solve the technical problem of low transmittance of traditional liquid crystal display devices.

[0006] An embodiment of the present application provides a liquid crystal display device, comprising: a display panel, the display panel comprising a plurality of pixels arranged in an array, each of the pixels comprising a primary pixel and a secondary pixel, each of the pixels comprising two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, a second transistor of the two transistors being electrically connected to the primary pixel, the secondary pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of groups of gate lines, a group of the gate lines being electrically connected to a row of the pixels, a group of the gate lines comprising a first gate line and a second gate line, the first gate line being electrically connected to the first transistor of a row of the pixels, the second gate line being electrically connected to the primary pixel of a row of the pixels, The second transistor of the pixel is electrically connected, and the time when the first scanning signal transmitted by the first gate line turns off the first transistor is earlier than the time when the second scanning signal transmitted by the second gate line turns off the second transistor; and multiple data lines, the data lines are electrically connected to the first transistor and the second transistor of one pixel, and the polarities of the data signals transmitted by two adjacent data lines are opposite. The data lines are configured to input a first grayscale signal to the sub-pixel before the first scanning signal turns off the first transistor, and to input a second grayscale signal to the main pixel before the second scanning signal turns off the second transistor, and the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

[0007] In the above liquid crystal display device, the pixel has only two transistors.

[0008] In the above-mentioned liquid crystal display device, the liquid crystal display device also includes: a timing controller, which is configured to receive image data, generate the first grayscale signal and the second grayscale signal according to the image data, and control the first scanning signal transmitted by the first gate line and the second scanning signal transmitted by the second gate line to successively turn off the first transistor and the second transistor, and control the data line to input the first grayscale signal to the sub-pixel before the first transistor is turned off, and input the second grayscale signal to the main pixel before the second transistor is turned off.

[0009] In the above-mentioned liquid crystal display device, the timing controller is configured to generate the first grayscale signal according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal according to the other of the first brightness data and the second brightness data.

[0010] In the above liquid crystal display device, the duration of the data line inputting the first grayscale signal to the sub-pixel before the first transistor is turned off is equal to the duration of the data line inputting the second grayscale signal to the main pixel before the second transistor is turned off.

[0011] The embodiment of the present application also provides a liquid crystal display device, comprising: a display panel, the display panel comprising a plurality of pixels arranged in an array, each of the pixels comprising a primary pixel and a secondary pixel, each of the pixels comprising two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, a second transistor of the two transistors being electrically connected to the primary pixel, the secondary pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of gate lines, one gate line being electrically connected to a row of the pixels, and one gate line being electrically connected to the first transistor and the second transistor of each of the pixels in a row; and a plurality of groups of data lines, one group of the data lines being electrically connected to a column of the pixels; The first data line and the second data line are electrically connected to each sub-pixel of each pixel in a column of pixels, and the second data line is electrically connected to each main pixel of each pixel in a column of pixels. The polarities of data signals transmitted by the first data line and the second data line in a group of data lines are the same, and the polarities of data signals transmitted by two adjacent groups of data lines are opposite. The first data line and the second data line are configured to input a first grayscale signal and a second grayscale signal to the sub-pixel and the main pixel respectively when the scanning signal transmitted by the gate line turns on the first transistor and the second transistor, and the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

[0012] In the above liquid crystal display device, the pixel has only two transistors.

[0013] In the above-mentioned liquid crystal display device, the liquid crystal display device also includes: a timing controller, which is configured to receive image data, generate a first grayscale signal and a second grayscale signal according to the image data, and control the first data line and the second data line to input the first grayscale signal and the second grayscale signal to the main pixel and the sub-pixel of the same column of pixels respectively, wherein the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

[0014] In the above-mentioned liquid crystal display device, the timing controller is configured to generate the first grayscale signal according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal according to the other of the first brightness data and the second brightness data.

[0015] In the above liquid crystal display device, a duration of the first data line inputting the first grayscale signal to the sub-pixel is equal to a duration of the second data line inputting the second grayscale signal to the main pixel.

[0016] Each pixel in the liquid crystal display device of the present invention includes only two transistors, one of which is electrically connected to the main pixel, and the other is electrically connected to the sub-pixel, and the sub-pixels of any two pixels are insulated, and / or the main pixels of any two pixels are insulated, that is, the shared electrode (Sharebar) design in the prior art is eliminated. Since one transistor is reduced and the shared electrode is eliminated, the area occupied by the non-light-transmitting area in the pixel is significantly reduced, thereby improving the aperture ratio of the pixel, and further improving the transmittance of the liquid crystal display device.

[0017] The present invention controls the scanning signals transmitted by the first gate line and the second gate line to turn off the first transistor and the second transistor in turn, and inputs the first grayscale signal to the sub-pixel through the data line before the first transistor is turned off, and inputs the second grayscale signal to the main pixel before the second transistor is turned off, wherein the voltage values ​​of the first grayscale signal and the second grayscale signal are different, so that the main pixel and the sub-pixel can respectively receive different grayscale signals, thereby realizing independent control of the main pixel and the sub-pixel, without relying on a common electrode to realize the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation, and ensuring that the viewing angle of the liquid crystal display device is adjustable.

[0018] Alternatively, the present invention electrically connects the first data line and the second data line in a group of data lines to the sub-pixel and the main pixel of each pixel in a column of pixels, respectively, and controls the first data line and the second data line to input the first grayscale signal and the second grayscale signal with different voltage values ​​to the sub-pixel and the main pixel respectively when the gate line turns on the first transistor and the second transistor, so that the main pixel and the sub-pixel can receive different grayscale signals at the same time, thereby realizing independent control of the main pixel and the sub-pixel without relying on a common electrode to realize the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation, and ensuring that the viewing angle of the liquid crystal display device is adjustable. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the display device provided by the first embodiment and the second embodiment of the present application.

[0020] Figure 2 It is a schematic diagram of the architecture of a display panel in a display device provided in the first embodiment of the present application.

[0021] Figure 3 yes Figure 2 The schematic diagram of the timing relationship between the scan signal and the data signal of the display device shown is shown.

[0022] Figure 4 yes Figure 3 The waveform diagram of the data signal is shown.

[0023] Figure 5 It is a schematic diagram of the architecture of a display panel in a display device provided in the second embodiment of the present application.

[0024] Figure 6 yes Figure 5 The schematic diagram of the timing relationship between the scan signal and the data signal of the display device shown is shown. DETAILED DESCRIPTION

[0025] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0026] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0027] The embodiments of the present application may be combined with each other.

[0028] like Figure 1 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller TCON, a source driving circuit DD and a power management chip (not shown in the figure, the power management chip can be integrated with the timing controller TCON into the same chip). The display panel can be, for example, a liquid crystal display panel.

[0029] The display panel includes a display area and a non-display area. The display area is provided with m×n pixels P arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of scan lines (GL1~GLn), a plurality of data lines (DL1~DLm) and a gate drive circuit GOA. The plurality of scan lines (GL1~GLn) extend along a first direction and are arranged along a second direction, and the plurality of data lines (DL1~DLm) extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit GOA is arranged in the non-display area and is electrically connected to the plurality of scan lines (GL1~GLn). The source drive circuit DD is electrically connected to the plurality of data lines (DL1~DLm) through a flexible circuit board. The timing controller TCON is electrically connected to the gate drive circuit GOA and the source drive circuit DD respectively.

[0030] The display panel includes a thin film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer GI disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer GI, a second metal layer disposed on the semiconductor layer, a passivation layer disposed on the second metal layer, and a pixel electrode disposed on the passivation layer. The first metal layer includes scan lines (GL1~GLn), gate electrodes, etc. The second metal layer includes data lines (DL1~DLm), source electrodes, drain electrodes, etc. The opposing substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0031] Each pixel P includes at least one thin film transistor and a pixel electrode. The gate of the thin film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scan line outputs a high-level scan signal, the thin film transistor is turned on, and the data signal on the data line is transmitted to the pixel electrode through the thin film transistor; when the scan line outputs a low-level scan signal, the thin film transistor is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0032] The gate drive circuit GOA includes n-stage cascaded gate drive units, and each stage of the gate drive unit is electrically connected to a scan line. Under the control of the timing controller TCON, the gate drive unit outputs scan signals in sequence to scan each row of pixels P in the display area line by line. Under the control of the timing controller TCON, the source drive circuit DD generates and outputs data signals according to the image data. The timing controller TCON is used to receive and process external image data and timing signals, generate control signals, and transmit image data to the source drive circuit DD. The power management chip is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode of the liquid crystal display panel, providing a gate drive voltage for the gate drive circuit GOA, and providing a gamma voltage for the source drive circuit DD.

[0033] The specific embodiments of the present invention include a first embodiment and a second embodiment.

[0034] First embodiment:

[0035] like Figure 2 and Figure 3 As shown, this embodiment provides a liquid crystal display device, including a display panel, a plurality of gate lines (G1-G4320) and a plurality of data lines (D1, D2, ...). The display panel is an 8-domain 2G1D architecture.

[0036] The display panel includes a plurality of pixels arranged in an array, each pixel including a primary pixel and a secondary pixel. Each pixel includes two transistors, a first transistor of the two transistors is electrically connected to the secondary pixel, and a second transistor of the two transistors is electrically connected to the primary pixel. The secondary pixels of any two pixels are insulated from each other, and / or the primary pixels of any two pixels are insulated from each other. The display panel does not include a common electrode.

[0037] A group of gate lines is electrically connected to a row of pixels, and the group of gate lines includes a first gate line G1 and a second gate line G2, the first gate line G1 is electrically connected to a first transistor of a row of pixels, the second gate line G2 is electrically connected to a second transistor of a row of pixels, and the time when the first scanning signal transmitted by the first gate line G1 turns off the first transistor is earlier than the time when the second scanning signal transmitted by the second gate line G2 turns off the second transistor. Specifically, the first group of gate lines includes a first gate line G1 and a second gate line G2, the first gate line G1 and the second gate line G2 are electrically connected to the first row of pixels, wherein the first gate line G1 is electrically connected to the first transistor of each pixel in the first row of pixels, and the second gate line G2 is electrically connected to the second transistor of each pixel in the first row of pixels. The second group of gate lines includes a third gate line G3 and a fourth gate line G4, the third gate line G3 and the fourth gate line G4 are electrically connected to the second row of pixels, wherein the third gate line G3 is electrically connected to the first transistor of each pixel in the second row of pixels, and the fourth gate line G4 is electrically connected to the second transistor of each pixel in the second row of pixels. The time when the third scanning signal transmitted by the third gate line G3 turns off the first transistor of the second row of pixels is earlier than the time when the fourth scanning signal transmitted by the fourth gate line G4 turns off the second transistor of the second row of pixels. In addition, the time when the second scanning signal transmitted by the second gate line G2 turns off the second transistor of the first row of pixels is earlier than the time when the third scanning signal transmitted by the third gate line G3 turns off the first transistor of the second row of pixels.

[0038] One data line is electrically connected to the first transistor and the second transistor of one pixel, and the polarities of the data signals transmitted by the two adjacent data lines are opposite, that is, the plurality of data lines include the first data line D1 and the second data line D2, and the polarities of the data signals transmitted by the first data line D1 and the second data line D2 are opposite. Specifically, in a certain time period, the polarity of the data signal transmitted by the first data line D1 is positive, and the polarity of the data signal transmitted by the second data line D2 is negative, and in another time period, the polarity of the data signal transmitted by the first data line D1 is negative, and the polarity of the data signal transmitted by the second data line D2 is positive.

[0039] The data line is configured to input a first grayscale signal 301 to the sub-pixel before the first scan signal turns off the first transistor, and to input a second grayscale signal 302 to the main pixel before the second scan signal turns off the second transistor. The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0040] The display panel further includes a plurality of pixel columns, each column of pixels having the same color. Specifically, the display panel is sequentially arranged with a blue pixel column, a green pixel column and a red pixel column from left to right.

[0041] A pixel has two and only two transistors.

[0042] The liquid crystal display device of this embodiment also includes a timing controller. The timing controller includes preset viewing angle compensation data (View Angle Compensation Table). The timing controller is configured to receive 4k*4k@120Hz image data, and perform differential processing on the image data input to the sub-pixel and the main pixel, that is, the timing controller is configured to generate a first grayscale signal 301 according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate a second grayscale signal 302 according to the other of the first brightness data and the second brightness data, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different. In particular, if Figure 4 As shown, the duration of the first grayscale signal 301 and the second grayscale signal 302 are both 1H.

[0043] The timing controller is also configured to control the first scanning signal transmitted by the first gate line G1 and the second scanning signal transmitted by the second gate line G2 to successively turn off the first transistor and the second transistor, and to control the data line to input the first grayscale signal 301 to the sub-pixel before the first transistor is turned off, and to input the second grayscale signal 302 to the main pixel before the second transistor is turned off.

[0044] The timing controller is configured to divide the time for inputting a data signal to a pixel into a first time period and a second time period. When the first gate line G1 outputs a high level signal, the first data line D1 inputs a first grayscale signal 301 to the sub-pixel of the first row of pixels in the first time period (1H). When the second gate line G2 outputs a high level signal, the first data line D1 inputs a second grayscale signal 302 to the main pixel of the first row of pixels in the second time period (1H). The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0045] The first time period and the second time period have different end times.

[0046] In this embodiment, the timing controller may also be configured to select corresponding viewing angle compensation data from a plurality of preset viewing angle compensation data according to the viewing angle mode selected by the user, and generate the first grayscale signal 301 and the second grayscale signal 302 according to the selected viewing angle compensation data. The timing controller may also be configured to adjust the difference in voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 according to the viewing angle mode selected by the user. Specifically, when the user selects the narrow viewing angle mode (privacy mode), the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a large difference in voltage value, so that the brightness difference between the main pixel and the sub-pixel is large, so that the display effect changes significantly when viewed at a wide viewing angle (the display content will be dimmed or distorted due to the brightness difference when viewed at a wide viewing angle), and the privacy protection effect is achieved. When the user selects the wide viewing angle mode, the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a small difference in voltage value, so that the brightness difference between the main pixel and the sub-pixel is small, so that a good display effect can still be maintained when viewed at a wide viewing angle. For example, in the narrow viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.5 V to 2 V; in the wide viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.1 V to 0.3 V. The timing controller can also be configured to adjust the voltage difference in a gradual manner during the viewing angle mode switching process to avoid sudden changes in the display effect.

[0047] like Figure 3 As shown, the duration of the data line inputting the first grayscale signal 301 to the sub-pixel before the first transistor is turned off is equal to the duration of the data line inputting the second grayscale signal 302 to the main pixel before the second transistor is turned off.

[0048] Specifically, the timing controller is also configured to control the first gate line G1, the second gate line G2, the third gate line G3 and the fourth gate line G4 to output high-level signals in sequence to turn on the first transistor of the first row of pixels, the second transistor of the first row of pixels, the first transistor of the second row of pixels, and the second transistor of the second row of pixels in sequence, and control the first gate line G1, the second gate line G2, the third gate line G3 and the fourth gate line G4 to output low-level signals in sequence to turn off the first transistor of the first row of pixels, the second transistor of the first row of pixels, the first transistor of the second row of pixels, and the second transistor of the second row of pixels in sequence, and control the data line to input four different grayscale signals to the sub-pixels of the first row of pixels, the main pixels of the first row of pixels, the sub-pixels of the second row of pixels, and the main pixels of the second row of pixels in sequence during the period when the first transistor of the first row of pixels is turned on, the second transistor of the first row of pixels is turned on, the first transistor of the second row of pixels is turned on, and the second transistor of the second row of pixels in sequence.

[0049] The timing controller can also be configured to dynamically adjust the timing parameters of the first time period and the second time period according to the change speed of the content to be displayed on the display panel. For example, when the content to be displayed is a static image, the timing controller is configured to extend the duration of the first time period and the second time period so that the main pixel and the sub-pixel have more sufficient charging time, thereby improving the display quality. When the displayed content is a dynamic image, the timing controller is configured to shorten the duration of the first time period and the second time period to increase the display refresh rate and reduce the phenomenon of dynamic blur.

[0050] The timing controller can also be configured to set different charging times for blue pixels, green pixels, and red pixels. Since the human eye has different sensitivities to light of different wavelengths (most sensitive to green light, followed by red light, and least sensitive to blue light), the timing controller is configured to set the charging time of green pixels to T1, the charging time of red pixels to 0.9T1, and the charging time of blue pixels to 0.8T1. Through this differentiated timing control, the driving efficiency can be improved while ensuring the display quality.

[0051] Second embodiment:

[0052] like Figure 5 and Figure 6 As shown, this embodiment provides another liquid crystal display device, including a display panel, a plurality of gate lines (G1-G2160) and a plurality of data lines (D1, D2, D3, D4, ...). The liquid crystal display device is an 8-domain 1G2D architecture.

[0053] The display panel includes a plurality of pixels arranged in an array, each pixel including a primary pixel and a secondary pixel. Each pixel includes two transistors, a first transistor of the two transistors is electrically connected to the secondary pixel, and a second transistor of the two transistors is electrically connected to the primary pixel. The secondary pixels of any two pixels are insulated from each other, and / or the primary pixels of any two pixels are insulated from each other. The display panel does not include a common electrode.

[0054] A gate line is electrically connected to a row of pixels, and a gate line is electrically connected to a first transistor and a second transistor of each pixel in a row of pixels. Specifically, the plurality of gate lines include a first gate line G1 and a second gate line G2. The first gate line G1 is electrically connected to a first row of pixels, and the first gate line G1 is electrically connected to a first transistor and a second transistor of each pixel in the first row of pixels. The second gate line G2 is electrically connected to a second row of pixels, and the second gate line G2 is electrically connected to a first transistor and a second transistor of each pixel in the second row of pixels.

[0055] A group of data lines is electrically connected to a column of pixels, and a group of pixels includes a first data line D1 and a second data line D2, the first data line D1 is electrically connected to the sub-pixel of each pixel in the column of pixels, and the second data line D2 is electrically connected to the main pixel of each pixel in the column of pixels. Specifically, the first group of data lines includes the first data line D1 and the second data line D2, and the first data line D1 and the second data line D2 are electrically connected to the first column of pixels. The second group of data lines includes the third data line D3 and the fourth data line D4, and the third data line D3 and the fourth data line D4 are electrically connected to the second column of pixels. The first data line D1 is electrically connected to the first transistor of each pixel in the first column of pixels, and the second data line D2 is electrically connected to the second transistor of each pixel in the first column of pixels. The third data line D3 is electrically connected to the first transistor of each pixel in the second column of pixels, and the fourth data line D4 is electrically connected to the second transistor of each pixel in the second column of pixels.

[0056] The polarity of the data signals transmitted by the first data line D1 and the second data line D2 in a group of data lines is the same, and the polarity of the data signals transmitted by the two adjacent groups of data lines is opposite. The first data line D1 and the second data line D2 are configured to input the first grayscale signal 301 and the second grayscale signal 302 to the sub-pixel and the main pixel respectively when the scanning signal transmitted by the gate line turns on the first transistor and the second transistor. The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0057] The polarity of the data signals transmitted by the same group of data lines is the same, and the polarity of the data signals transmitted by two adjacent groups of data lines is opposite. Specifically, in a certain time period, the polarity of the data signals transmitted by the first data line D1 and the second data line D2 is positive, and the polarity of the data signals transmitted by the third data line D3 and the fourth data line D4 is negative. In another time period, the polarity of the data signals transmitted by the first data line D1 and the second data line D2 is negative, and the polarity of the data signals transmitted by the third data line D3 and the fourth data line D4 is positive. The grayscale signals transmitted by the same group of data lines are different, that is, the voltage values ​​of the grayscale signals transmitted by the first data line D1 and the second data line D2 are different, and the voltage values ​​of the grayscale signals transmitted by the third data line D3 and the fourth data line D4 are different.

[0058] The display panel further includes a plurality of pixel columns, each column of pixels having the same color. Specifically, the display panel is sequentially arranged with a blue pixel column, a green pixel column and a red pixel column from left to right.

[0059] A pixel has two and only two transistors.

[0060] The liquid crystal display device of this embodiment also includes a timing controller. The timing controller includes preset viewing angle compensation data. The timing controller is configured to receive image data of 4k*4k (resolution)@120Hz (frame rate), generate a first grayscale signal 301 and a second grayscale signal 302 according to the image data and the preset viewing angle compensation data, and control the first data line D1 and the second data line D2 to input the first grayscale signal 301 and the second grayscale signal 302 to the primary pixel and the secondary pixel of the same column of pixels, respectively.

[0061] The timing controller is configured to perform differential processing on the image data to be input to the sub-pixel and the main pixel, that is, to generate a first grayscale signal 301 according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate a second grayscale signal 302 according to the other of the first brightness data and the second brightness data, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different. The timing controller is also configured to control the first gate line G1 to output a high-level signal to turn on the first transistor and the second transistor of the first row of pixels, control the first data line D1 to input the first grayscale signal 301 to the sub-pixel of the first row of pixels, and control the second data line D2 to input the second grayscale signal 302 to the main pixel of the first row of pixels, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0062] The duration of the first data line D1 inputting the first grayscale signal to the sub-pixel is equal to the duration of the second data line D2 inputting the second grayscale signal 302 to the main pixel.

[0063] In this embodiment, the timing controller may also be configured to select corresponding viewing angle compensation data from a plurality of preset viewing angle compensation data according to the viewing angle mode selected by the user, and generate the first grayscale signal 301 and the second grayscale signal 302 according to the selected viewing angle compensation data. The timing controller may also be configured to adjust the difference in voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 according to the viewing angle mode selected by the user. Specifically, when the user selects the narrow viewing angle mode (privacy mode), the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a large difference in voltage value, so that the brightness difference between the main pixel and the sub-pixel is large, so that the display effect changes significantly when viewed at a wide viewing angle (the display content will be dimmed or distorted due to the brightness difference when viewed at a wide viewing angle), and the privacy protection effect is achieved. When the user selects the wide viewing angle mode, the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a small difference in voltage value, so that the brightness difference between the main pixel and the sub-pixel is small, so that a good display effect can still be maintained when viewed at a wide viewing angle. For example, in the narrow viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.5 V to 2 V; in the wide viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.1 V to 0.3 V. The timing controller can also be configured to adjust the voltage difference in a gradual manner during the viewing angle mode switching process to avoid sudden changes in the display effect.

[0064] The timing controller can also be configured to dynamically adjust the timing parameters of the first time period and the second time period according to the change speed of the content to be displayed on the display panel. For example, when the content to be displayed is a static image, the timing controller is configured to extend the duration of the first time period and the second time period so that the main pixel and the sub-pixel have more sufficient charging time, thereby improving the display quality. When the displayed content is a dynamic image, the timing controller is configured to shorten the duration of the first time period and the second time period to increase the display refresh rate and reduce the phenomenon of dynamic blur.

[0065] The timing controller can also be configured to set different charging times for blue pixels, green pixels, and red pixels. Since the human eye has different sensitivities to light of different wavelengths (most sensitive to green light, followed by red light, and least sensitive to blue light), the timing controller is configured to set the charging time of green pixels to T1, the charging time of red pixels to 0.9T1, and the charging time of blue pixels to 0.8T1. Through this differentiated timing control, the driving efficiency can be improved while ensuring the display quality.

[0066] In addition, the timing controller can also be configured to dynamically adjust the voltage range of the signal according to the dynamic range characteristics of the displayed content. For example, when the dynamic range of the displayed content is large, the voltage difference between the two grayscale signals is enlarged; when the dynamic range of the displayed content is small, the voltage difference between the two grayscale signals is reduced to obtain a more delicate grayscale performance.

[0067] Each pixel in the liquid crystal display device of the present invention includes only two transistors, one of which is electrically connected to the main pixel, and the other is electrically connected to the sub-pixel, and the sub-pixels of any two pixels are insulated, and / or the main pixels of any two pixels are insulated, that is, the shared electrode (Sharebar) design in the prior art is eliminated. Since one transistor is reduced and the shared electrode is eliminated, the area occupied by the non-light-transmitting area in the pixel is significantly reduced, thereby improving the aperture ratio of the pixel, and further improving the transmittance of the liquid crystal display device.

[0068] The present invention controls the scanning signals transmitted by the first gate line G1 and the second gate line G2 to turn off the first transistor and the second transistor in turn, and inputs the first grayscale signal 301 to the sub-pixel through the data line before the first transistor is turned off, and inputs the second grayscale signal 302 to the main pixel before the second transistor is turned off, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different, so that the main pixel and the sub-pixel can respectively receive different grayscale signals, thereby realizing independent control of the main pixel and the sub-pixel, without relying on a common electrode to realize the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation, and ensuring that the viewing angle of the liquid crystal display device is adjustable.

[0069] Alternatively, the present invention electrically connects the first data line D1 and the second data line D2 in a group of data lines to the sub-pixel and the main pixel of each pixel in a column of pixels, respectively, and controls the first data line D1 and the second data line D2 to input the first grayscale signal 301 and the second grayscale signal 302 with different voltage values ​​to the sub-pixel and the main pixel respectively when the gate line turns on the first transistor and the second transistor, so that the main pixel and the sub-pixel can receive different grayscale signals at the same time, thereby realizing independent control of the main pixel and the sub-pixel without relying on a common electrode to realize the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation, and ensuring that the viewing angle of the liquid crystal display device is adjustable.

[0070] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A liquid crystal display device, characterized in that: include: A display panel, the display panel comprising a plurality of pixels arranged in an array, each of the pixels comprising a primary pixel and a secondary pixel, each of the pixels comprising two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, a second transistor of the two transistors being electrically connected to the primary pixel, the secondary pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of groups of gate lines, wherein one group of the gate lines is electrically connected to a row of the pixels, the group of the gate lines includes a first gate line and a second gate line, the first gate line is electrically connected to the first transistors of a row of the pixels, the second gate line is electrically connected to the second transistors of a row of the pixels, and the first scanning signal transmitted by the first gate line turns off the first transistor before the second scanning signal transmitted by the second gate line turns off the second transistor; as well as A plurality of data lines are provided, wherein the data lines are electrically connected to the first transistor and the second transistor of one pixel, the polarities of the data signals transmitted by two adjacent data lines are opposite, the data lines are configured to input a first grayscale signal to the sub-pixel before the first scanning signal turns off the first transistor, and to input a second grayscale signal to the main pixel before the second scanning signal turns off the second transistor, and the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

2. The liquid crystal display device according to claim 1, wherein The pixel has and only has two of the transistors.

3. The liquid crystal display device according to claim 1, wherein The liquid crystal display device further includes: A timing controller is configured to receive image data, generate the first grayscale signal and the second grayscale signal according to the image data, control the first scanning signal transmitted by the first gate line and the second scanning signal transmitted by the second gate line to successively turn off the first transistor and the second transistor, and control the data line to input the first grayscale signal to the sub-pixel before the first transistor is turned off, and to input the second grayscale signal to the main pixel before the second transistor is turned off.

4. The liquid crystal display device according to claim 3, wherein: The timing controller is configured to generate the first grayscale signal according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal according to the other of the first brightness data and the second brightness data.

5. The liquid crystal display device according to claim 1, wherein: The duration of the data line inputting the first grayscale signal to the sub-pixel before the first transistor is turned off is equal to the duration of the data line inputting the second grayscale signal to the main pixel before the second transistor is turned off.

6. A liquid crystal display device, characterized in that: include: A display panel, the display panel comprising a plurality of pixels arranged in an array, each of the pixels comprising a primary pixel and a secondary pixel, each of the pixels comprising two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, a second transistor of the two transistors being electrically connected to the primary pixel, the secondary pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of gate lines, one gate line being electrically connected to a row of pixels, and one gate line being electrically connected to the first transistor and the second transistor of each pixel in a row of pixels; as well as A plurality of groups of data lines, wherein one group of the data lines is electrically connected to a column of the pixels, and a group of the pixels includes a first data line and a second data line, wherein the first data line is electrically connected to the sub-pixel of each of the pixels in a column of the pixels, and the second data line is electrically connected to the main pixel of each of the pixels in a column of the pixels, the polarity of the data signals transmitted by the first data line and the second data line in a group of the data lines is the same, and the polarity of the data signals transmitted by two adjacent groups of the data lines is opposite, and the first data line and the second data line are configured to input a first grayscale signal and a second grayscale signal to the sub-pixel and the main pixel respectively when the scanning signal transmitted by the gate line turns on the first transistor and the second transistor, and the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

7. The liquid crystal display device according to claim 6, wherein: The pixel has and only has two of the transistors.

8. The liquid crystal display device according to claim 6, wherein: The liquid crystal display device further comprises: A timing controller is configured to receive image data, generate a first grayscale signal and a second grayscale signal according to the image data, and control the first data line and the second data line to input the first grayscale signal and the second grayscale signal to the main pixel and the sub-pixel of the same column of pixels respectively, wherein the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

9. The liquid crystal display device according to claim 8, wherein: The timing controller is configured to generate the first grayscale signal according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal according to the other of the first brightness data and the second brightness data.

10. The liquid crystal display device according to claim 6, wherein: The duration of the first data line inputting the first grayscale signal to the sub-pixel is equal to the duration of the second data line inputting the second grayscale signal to the main pixel.

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