Liquid crystal display device

Abstract

The present application provides a liquid crystal display device, comprising a plurality of pixels, a plurality of gate lines and a plurality of data lines, each pixel comprising a main pixel and a sub-pixel, and comprising only two transistors, wherein the first transistor is electrically connected to the sub-pixel, and the second transistor is electrically connected to the main pixel. In a first embodiment, a group of gate lines comprises a first gate line and a second gate line, which are electrically connected to the first transistor and the second transistor, respectively, and by controlling the switching timing of the gate line signal and the input timing of the data line signal, different grayscale signals are input to the main pixel and the sub-pixel. In a second embodiment, a group of data lines comprises a first data line and a second data line, which are electrically connected to the sub-pixel and the main pixel, respectively, and by controlling the two data lines to input different grayscale signals to the main pixel and the sub-pixel at the same time, different grayscale signals are input to the main pixel and the sub-pixel. The present application removes the common electrode and reduces the number of transistors, thereby improving the aperture ratio and the transmittance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a liquid crystal display device. Background Art

[0002] In liquid crystal display panels, transmittance refers to the ratio of the brightness passing through the liquid crystal display panel to the brightness of the backlight source. It is an important optical parameter of the liquid crystal display panel, and its size directly affects the power consumption and display brightness of the entire device.

[0003] In existing liquid crystal display panels, each pixel typically includes three transistors and a common electrode (Sharebar). Although this design can achieve control of the main pixel and sub-pixel, the existence of the common electrode and the large area occupied by the three transistors result in a low pixel aperture ratio, which in turn makes the transmittance of the liquid crystal display panel low.

[0004] Therefore, how to improve the transmittance of a liquid crystal display panel while ensuring the display effect is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a liquid crystal display device, aiming to solve the technical problem of low transmittance of traditional liquid crystal display devices.

[0006] An embodiment of the present application provides a liquid crystal display device, comprising: a display panel, the display panel comprising a plurality of pixels arranged in an array, each of the pixels comprising a primary pixel and a secondary pixel, each of the pixels comprising two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, a second transistor of the two transistors being electrically connected to the primary pixel, the secondary pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of groups of gate lines, one group of the gate lines being electrically connected to a row of the pixels, the one group of the gate lines comprising a first gate line and a second gate line, the first gate line being electrically connected to the first transistor of the pixels of the row, the second gate line being electrically connected to the primary pixel of the row The second transistor of the pixel is electrically connected, and the time when the first scanning signal transmitted by the first gate line turns off the first transistor is earlier than the time when the second scanning signal transmitted by the second gate line turns off the second transistor; and multiple data lines, the data lines are electrically connected to the first transistor and the second transistor of one pixel, and the polarities of the data signals transmitted by two adjacent data lines are opposite, and the data lines are configured to input a first grayscale signal to the sub-pixel before the first scanning signal turns off the first transistor, and to input a second grayscale signal to the main pixel before the second scanning signal turns off the second transistor, and the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

[0007] In the above liquid crystal display device, the pixel has only two transistors.

[0008] In the above-mentioned liquid crystal display device, the liquid crystal display device also includes: a timing controller, which is configured to receive image data, generate the first grayscale signal and the second grayscale signal according to the image data, and control the first scanning signal transmitted by the first gate line and the second scanning signal transmitted by the second gate line to successively turn off the first transistor and the second transistor, and control the data line to input the first grayscale signal to the sub-pixel before the first transistor is turned off, and to input the second grayscale signal to the main pixel before the second transistor is turned off.

[0009] In the above-mentioned liquid crystal display device, the timing controller is configured to generate the first grayscale signal based on the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal based on the other of the first brightness data and the second brightness data.

[0010] In the above liquid crystal display device, the duration of the data line inputting the first grayscale signal to the sub-pixel before the first transistor is turned off is equal to the duration of the data line inputting the second grayscale signal to the main pixel before the second transistor is turned off.

[0011] An embodiment of the present application further provides a liquid crystal display device, comprising: a display panel, wherein the display panel comprises a plurality of pixels arranged in an array, each of the pixels comprising a primary pixel and a secondary pixel, each of the pixels comprising two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, a second transistor of the two transistors being electrically connected to the primary pixel, the secondary pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of gate lines, wherein one gate line is electrically connected to a row of the pixels, and one gate line is electrically connected to both the first transistor and the second transistor of each of the pixels in a row; and a plurality of groups of data lines, wherein one group of the data lines is electrically connected to a column of the pixels. connection, a group of pixels includes a first data line and a second data line, the first data line is electrically connected to the sub-pixel of each pixel in a column of pixels, and the second data line is electrically connected to the main pixel of each pixel in a column of pixels, the polarity of the data signals transmitted by the first data line and the second data line in a group of data lines is the same, and the polarity of the data signals transmitted by two adjacent groups of data lines is opposite, the first data line and the second data line are configured to input a first grayscale signal and a second grayscale signal to the sub-pixel and the main pixel respectively when the scanning signal transmitted by the gate line turns on the first transistor and the second transistor, and the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

[0012] In the above liquid crystal display device, the pixel has only two transistors.

[0013] In the above-mentioned liquid crystal display device, the liquid crystal display device also includes: a timing controller, which is configured to receive image data, generate a first grayscale signal and a second grayscale signal based on the image data, and control the first data line and the second data line to input the first grayscale signal and the second grayscale signal to the main pixel and the sub-pixel of the same column of pixels respectively, wherein the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

[0014] In the above-mentioned liquid crystal display device, the timing controller is configured to generate the first grayscale signal based on the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal based on the other of the first brightness data and the second brightness data.

[0015] In the above liquid crystal display device, a duration of the first data line inputting the first grayscale signal to the sub-pixel is equal to a duration of the second data line inputting the second grayscale signal to the main pixel.

[0016] Each pixel in the liquid crystal display device of the present invention contains only two transistors, one of which is electrically connected to the primary pixel and the other to the secondary pixel. The secondary pixels of any two pixels are insulated from each other, and / or the primary pixels of any two pixels are insulated from each other. This eliminates the shared electrode (sharebar) design used in the prior art. By reducing one transistor and eliminating the shared electrode, the area occupied by the non-light-transmitting region in the pixel is significantly reduced, thereby increasing the pixel aperture ratio and, in turn, the transmittance of the liquid crystal display device.

[0017] The present invention controls the scanning signals transmitted by the first gate line and the second gate line to successively turn off the first transistor and the second transistor, and inputs a first grayscale signal to the sub-pixel through the data line before the first transistor is turned off, and inputs a second grayscale signal to the main pixel before the second transistor is turned off, wherein the voltage values ​​of the first grayscale signal and the second grayscale signal are different, so that the main pixel and the sub-pixel can respectively receive different grayscale signals, thereby realizing independent control of the main pixel and the sub-pixel without relying on a common electrode to achieve the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation and ensuring that the viewing angle of the liquid crystal display device is adjustable.

[0018] Alternatively, the present invention electrically connects the first data line and the second data line in a group of data lines to the sub-pixel and the main pixel of each pixel in a column of pixels, respectively, and controls the first data line and the second data line to input the first grayscale signal and the second grayscale signal with different voltage values ​​to the sub-pixel and the main pixel respectively when the gate line turns on the first transistor and the second transistor, so that the main pixel and the sub-pixel can receive different grayscale signals at the same time, thereby realizing independent control of the main pixel and the sub-pixel without relying on a common electrode to achieve the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation, and ensuring that the viewing angle of the liquid crystal display device is adjustable. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the display device provided by the first embodiment and the second embodiment of the present application.

[0020] Figure 2 Schematic diagram of the structure of the display panel in the display device provided in the first embodiment of the present application.

[0021] Figure 3 yes Figure 2 The schematic diagram shows the timing relationship between the scan signal and the data signal of the display device.

[0022] Figure 4 yes Figure 3 The waveform of the data signal is shown.

[0023] Figure 5 2 is a schematic diagram of the structure of a display panel in a display device provided in a second embodiment of the present application.

[0024] Figure 6 yes Figure 5 The schematic diagram shows the timing relationship between the scan signal and the data signal of the display device. DETAILED DESCRIPTION

[0025] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0026] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0027] The embodiments of the present application may be combined with each other.

[0028] like Figure 1 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller TCON, a source driver circuit DD, and a power management chip (not shown in the figure, the power management chip can be integrated into the same chip with the timing controller TCON). The display panel can be, for example, a liquid crystal display panel.

[0029] The display panel includes a display area and a non-display area. The display area is provided with m×n pixels P arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of scan lines (GL1 to GLn), a plurality of data lines (DL1 to DLm), and a gate drive circuit GOA. The plurality of scan lines (GL1 to GLn) extend along a first direction and are arranged along a second direction, and the plurality of data lines (DL1 to DLm) extend along a second direction and are arranged along the first direction, with the first direction being perpendicular to the second direction. The gate drive circuit GOA is provided in the non-display area and is electrically connected to the plurality of scan lines (GL1 to GLn). The source drive circuit DD is electrically connected to the plurality of data lines (DL1 to DLm) via a flexible printed circuit board. The timing controller TCON is electrically connected to the gate drive circuit GOA and the source drive circuit DD, respectively.

[0030] The display panel includes a thin-film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin-film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer GI disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer GI, a second metal layer disposed on the semiconductor layer, a passivation layer disposed on the second metal layer, and a pixel electrode disposed on the passivation layer. The first metal layer includes scan lines (GL1 to GLn) and a gate electrode. The second metal layer includes data lines (DL1 to DLm), a source electrode, a drain electrode, and the like. The opposing substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0031] Each pixel P includes at least one thin-film transistor and a pixel electrode. The gate of the thin-film transistor is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scan line outputs a high-level scan signal, the thin-film transistor turns on, and the data signal on the data line is transmitted to the pixel electrode through the thin-film transistor. When the scan line outputs a low-level scan signal, the thin-film transistor turns off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0032] The gate drive circuit GOA includes n cascaded gate drive units, each of which is electrically connected to a scan line. Under the control of the timing controller TCON, the gate drive units sequentially output scan signals, scanning each row of pixels P in the display area line by line. Under the control of the timing controller TCON, the source drive circuit DD generates and outputs data signals based on image data. The timing controller TCON is used to receive and process external image data and timing signals, generate control signals, and transmit image data to the source drive circuit DD. The power management chip is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode of the liquid crystal display panel, providing a gate drive voltage for the gate drive circuit GOA, and providing a gamma voltage for the source drive circuit DD.

[0033] The specific embodiments of the present invention include a first embodiment and a second embodiment.

[0034] First embodiment:

[0035] like Figure 2 and Figure 3 As shown, this embodiment provides a liquid crystal display device, including a display panel, multiple gate lines (G1-G4320) and multiple data lines (D1, D2, ...). The display panel has an 8-domain 2G1D architecture.

[0036] The display panel includes a plurality of pixels arranged in an array, each pixel including a primary pixel and a secondary pixel. Each pixel includes two transistors, a first transistor of the two transistors being electrically connected to the secondary pixel, and a second transistor of the two transistors being electrically connected to the primary pixel. The secondary pixels of any two pixels are insulated from each other, and / or the primary pixels of any two pixels are insulated from each other. The display panel does not include a common electrode.

[0037] A group of gate lines is electrically connected to a row of pixels, and the group of gate lines includes a first gate line G1 and a second gate line G2. The first gate line G1 is electrically connected to the first transistor of the row of pixels, and the second gate line G2 is electrically connected to the second transistor of the row of pixels. The time when the first scanning signal transmitted by the first gate line G1 turns off the first transistor is earlier than the time when the second scanning signal transmitted by the second gate line G2 turns off the second transistor. Specifically, the first group of gate lines includes the first gate line G1 and the second gate line G2. The first gate line G1 and the second gate line G2 are electrically connected to the first row of pixels, wherein the first gate line G1 is electrically connected to the first transistor of each pixel in the first row of pixels, and the second gate line G2 is electrically connected to the second transistor of each pixel in the first row of pixels. The second group of gate lines includes a third gate line G3 and a fourth gate line G4. The third gate line G3 and the fourth gate line G4 are electrically connected to the second row of pixels, wherein the third gate line G3 is electrically connected to the first transistor of each pixel in the second row of pixels, and the fourth gate line G4 is electrically connected to the second transistor of each pixel in the second row of pixels. The time when the third scanning signal transmitted by the third gate line G3 turns off the first transistors of the pixels in the second row is earlier than the time when the fourth scanning signal transmitted by the fourth gate line G4 turns off the second transistors of the pixels in the second row. In addition, the time when the second scanning signal transmitted by the second gate line G2 turns off the second transistors of the pixels in the first row is earlier than the time when the third scanning signal transmitted by the third gate line G3 turns off the first transistors of the pixels in the second row.

[0038] A data line is electrically connected to the first transistor and the second transistor of a pixel. The polarities of the data signals transmitted by the two adjacent data lines are opposite. That is, the plurality of data lines includes a first data line D1 and a second data line D2. The polarities of the data signals transmitted by the first data line D1 and the second data line D2 are opposite. Specifically, during a certain time period, the polarity of the data signal transmitted by the first data line D1 is positive, and the polarity of the data signal transmitted by the second data line D2 is negative. During another time period, the polarity of the data signal transmitted by the first data line D1 is negative, and the polarity of the data signal transmitted by the second data line D2 is positive.

[0039] The data line is configured to input a first grayscale signal 301 to the sub-pixel before the first scan signal turns off the first transistor, and to input a second grayscale signal 302 to the main pixel before the second scan signal turns off the second transistor. The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0040] The display panel further includes a plurality of pixel columns, each column of pixels having the same color. Specifically, the display panel is sequentially arranged from left to right with a blue pixel column, a green pixel column, and a red pixel column.

[0041] A pixel has exactly two transistors.

[0042] The liquid crystal display device of this embodiment also includes a timing controller. The timing controller includes preset viewing angle compensation data (View Angle Compensation Table). The timing controller is configured to receive 4k*4k@120Hz image data, and perform differential processing on the image data input to the sub-pixel and the main pixel, that is, the timing controller is configured to generate a first grayscale signal 301 according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate a second grayscale signal 302 according to the other of the first brightness data and the second brightness data, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different. In particular, as Figure 4 As shown, the duration of the first grayscale signal 301 and the second grayscale signal 302 are both 1H.

[0043] The timing controller is also configured to control the first scanning signal transmitted by the first gate line G1 and the second scanning signal transmitted by the second gate line G2 to successively turn off the first transistor and the second transistor, and to control the data line to input the first grayscale signal 301 to the sub-pixel before the first transistor is turned off, and to input the second grayscale signal 302 to the main pixel before the second transistor is turned off.

[0044] The timing controller is configured to divide the time during which a data signal is input to a pixel into a first time period and a second time period. When the first gate line G1 outputs a high-level signal, the first data line D1 inputs a first grayscale signal 301 to the sub-pixels of the first row of pixels during the first time period (1H). When the second gate line G2 outputs a high-level signal, the first data line D1 inputs a second grayscale signal 302 to the main pixels of the first row of pixels during the second time period (1H). The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0045] The first time period and the second time period have different end times.

[0046] In this embodiment, the timing controller may be further configured to select corresponding viewing angle compensation data from a plurality of preset viewing angle compensation data according to the viewing angle mode selected by the user, and generate a first grayscale signal 301 and a second grayscale signal 302 according to the selected viewing angle compensation data. The timing controller may also be configured to adjust the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 according to the viewing angle mode selected by the user. Specifically, when the user selects the narrow viewing angle mode (privacy mode), the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a larger voltage difference, resulting in a larger brightness difference between the primary pixel and the secondary pixel, thereby significantly changing the display effect when viewed at a wide viewing angle (the brightness difference may cause the displayed content to become darker or distorted when viewed at a wide viewing angle), thereby achieving a privacy protection effect. When the user selects the wide viewing angle mode, the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a smaller voltage difference, resulting in a smaller brightness difference between the primary pixel and the secondary pixel, thereby maintaining a good display effect when viewed at a wide viewing angle. For example, in narrow viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.5 V to 2 V; in wide viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.1 V to 0.3 V. The timing controller can also be configured to gradually adjust the voltage difference during viewing angle mode switching to avoid sudden changes in display effects.

[0047] like Figure 3 As shown, the duration of the data line inputting the first grayscale signal 301 to the sub-pixel before the first transistor is turned off is equal to the duration of the data line inputting the second grayscale signal 302 to the main pixel before the second transistor is turned off.

[0048] Specifically, the timing controller is also configured to control the first gate line G1, the second gate line G2, the third gate line G3 and the fourth gate line G4 to output high-level signals in sequence to turn on the first transistor of the first row of pixels, the second transistor of the first row of pixels, the first transistor of the second row of pixels, and the second transistor of the second row of pixels in sequence, and control the first gate line G1, the second gate line G2, the third gate line G3 and the fourth gate line G4 to output low-level signals in sequence to turn off the first transistor of the first row of pixels, the second transistor of the first row of pixels, the first transistor of the second row of pixels, and the second transistor of the second row of pixels in sequence, and control the data lines to input four different grayscale signals to the sub-pixels of the first row of pixels, the main pixels of the first row of pixels, the sub-pixels of the second row of pixels, and the main pixels of the second row of pixels in sequence during the period when the first transistor of the first row of pixels is turned on, the second transistor of the first row of pixels is turned on, and the second transistor of the second row of pixels is turned on.

[0049] The timing controller can also be configured to dynamically adjust the timing parameters of the first and second time periods based on the speed at which the content to be displayed on the display panel changes. For example, when the content to be displayed is a static image, the timing controller is configured to extend the duration of the first and second time periods to allow the primary and secondary pixels more time to charge, thereby improving display quality. When the content to be displayed is a dynamic image, the timing controller is configured to shorten the duration of the first and second time periods to increase the display refresh rate and reduce motion blur.

[0050] The timing controller can also be configured to set different charging times for blue pixels, green pixels, and red pixels. Since the human eye has different sensitivities to light of different wavelengths (most sensitive to green light, followed by red light, and least sensitive to blue light), the timing controller is configured to set the charging time of green pixels to T1, the charging time of red pixels to 0.9T1, and the charging time of blue pixels to 0.8T1. Through this differentiated timing control, the driving efficiency can be improved while ensuring display quality.

[0051] Second embodiment:

[0052] like Figure 5 and Figure 6 As shown, this embodiment provides another liquid crystal display device, including a display panel, a plurality of gate lines (G1-G2160) and a plurality of data lines (D1, D2, D3, D4, ...). The liquid crystal display device has an 8-domain 1G2D architecture.

[0053] The display panel includes a plurality of pixels arranged in an array, each pixel including a primary pixel and a sub-pixel. Each pixel includes two transistors, a first transistor of the two transistors being electrically connected to the sub-pixel, and a second transistor of the two transistors being electrically connected to the primary pixel. The sub-pixels of any two pixels are insulated from each other, and / or the primary pixels of any two pixels are insulated from each other. The display panel does not include a common electrode.

[0054] A gate line is electrically connected to a row of pixels, and a gate line is electrically connected to the first transistor and the second transistor of each pixel in the row of pixels. Specifically, the plurality of gate lines include a first gate line G1 and a second gate line G2. The first gate line G1 is electrically connected to a first row of pixels, and the first gate line G1 is electrically connected to the first transistor and the second transistor of each pixel in the first row of pixels. The second gate line G2 is electrically connected to a second row of pixels, and the second gate line G2 is electrically connected to the first transistor and the second transistor of each pixel in the second row of pixels.

[0055] A group of data lines is electrically connected to a column of pixels. The group of pixels includes a first data line D1 and a second data line D2. The first data line D1 is electrically connected to the sub-pixel of each pixel in the column of pixels, and the second data line D2 is electrically connected to the main pixel of each pixel in the column of pixels. Specifically, the first group of data lines includes a first data line D1 and a second data line D2. The first data line D1 and the second data line D2 are electrically connected to the first column of pixels. The second group of data lines includes a third data line D3 and a fourth data line D4. The third data line D3 and the fourth data line D4 are electrically connected to the second column of pixels. The first data line D1 is electrically connected to the first transistor of each pixel in the first column of pixels, and the second data line D2 is electrically connected to the second transistor of each pixel in the first column of pixels. The third data line D3 is electrically connected to the first transistor of each pixel in the second column of pixels, and the fourth data line D4 is electrically connected to the second transistor of each pixel in the second column of pixels.

[0056] The polarity of the data signals transmitted by the first data line D1 and the second data line D2 in a group of data lines is the same, and the polarity of the data signals transmitted by two adjacent groups of data lines is opposite. The first data line D1 and the second data line D2 are configured to input the first grayscale signal 301 and the second grayscale signal 302 to the sub-pixel and the main pixel respectively when the scanning signal transmitted by the gate line turns on the first transistor and the second transistor. The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0057] The data signals transmitted by the same group of data lines have the same polarity, while the data signals transmitted by two adjacent groups of data lines have opposite polarities. Specifically, in a certain time period, the polarity of the data signals transmitted by the first data line D1 and the second data line D2 are both positive, while the polarity of the data signals transmitted by the third data line D3 and the fourth data line D4 are both negative. In another time period, the polarity of the data signals transmitted by the first data line D1 and the second data line D2 are both negative, while the polarity of the data signals transmitted by the third data line D3 and the fourth data line D4 are both positive. The grayscale signals transmitted by the same group of data lines are different, that is, the voltage values ​​of the grayscale signals transmitted by the first data line D1 and the second data line D2 are different, while the voltage values ​​of the grayscale signals transmitted by the third data line D3 and the fourth data line D4 are different.

[0058] The display panel further includes a plurality of pixel columns, each column of pixels having the same color. Specifically, the display panel is sequentially arranged from left to right with a blue pixel column, a green pixel column, and a red pixel column.

[0059] A pixel has exactly two transistors.

[0060] The liquid crystal display device of this embodiment further includes a timing controller. The timing controller includes preset viewing angle compensation data. The timing controller is configured to receive 4k*4k (resolution) @ 120Hz (frame rate) image data, generate a first grayscale signal 301 and a second grayscale signal 302 based on the image data and the preset viewing angle compensation data, and control the first data line D1 and the second data line D2 to input the first grayscale signal 301 and the second grayscale signal 302 to the primary pixel and the secondary pixel in the same column, respectively.

[0061] The timing controller is configured to perform differential processing on image data to be input to the sub-pixels and the primary pixels, namely, to generate a first grayscale signal 301 based on the image data and one of the first luminance data and the second luminance data in the preset viewing angle compensation data, and to generate a second grayscale signal 302 based on the other of the first luminance data and the second luminance data, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different. The timing controller is further configured to control the first gate line G1 to output a high-level signal to turn on the first transistor and the second transistor of the first row of pixels, control the first data line D1 to input the first grayscale signal 301 to the sub-pixels of the first row of pixels, and control the second data line D2 to input the second grayscale signal 302 to the primary pixels of the first row of pixels, wherein the voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different.

[0062] The duration of the first data line D1 inputting the first grayscale signal to the sub-pixel is equal to the duration of the second data line D2 inputting the second grayscale signal 302 to the main pixel.

[0063] In this embodiment, the timing controller may be further configured to select corresponding viewing angle compensation data from a plurality of preset viewing angle compensation data according to the viewing angle mode selected by the user, and generate a first grayscale signal 301 and a second grayscale signal 302 according to the selected viewing angle compensation data. The timing controller may also be configured to adjust the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 according to the viewing angle mode selected by the user. Specifically, when the user selects the narrow viewing angle mode (privacy mode), the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a larger voltage difference, resulting in a larger brightness difference between the primary pixel and the secondary pixel, thereby significantly changing the display effect when viewed at a wide viewing angle (the brightness difference may cause the displayed content to become darker or distorted when viewed at a wide viewing angle), thereby achieving a privacy protection effect. When the user selects the wide viewing angle mode, the timing controller is configured to generate the first grayscale signal 301 and the second grayscale signal 302 with a smaller voltage difference, resulting in a smaller brightness difference between the primary pixel and the secondary pixel, thereby maintaining a good display effect when viewed at a wide viewing angle. For example, in narrow viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.5 V to 2 V; in wide viewing angle mode, the voltage difference between the first grayscale signal 301 and the second grayscale signal 302 can be set to 0.1 V to 0.3 V. The timing controller can also be configured to gradually adjust the voltage difference during viewing angle mode switching to avoid sudden changes in display effects.

[0064] The timing controller can also be configured to dynamically adjust the timing parameters of the first and second time periods based on the speed at which the content to be displayed on the display panel changes. For example, when the content to be displayed is a static image, the timing controller is configured to extend the duration of the first and second time periods to allow the primary and secondary pixels more time to charge, thereby improving display quality. When the content to be displayed is a dynamic image, the timing controller is configured to shorten the duration of the first and second time periods to increase the display refresh rate and reduce motion blur.

[0065] The timing controller can also be configured to set different charging times for blue pixels, green pixels, and red pixels. Since the human eye has different sensitivities to light of different wavelengths (most sensitive to green light, followed by red light, and least sensitive to blue light), the timing controller is configured to set the charging time of green pixels to T1, the charging time of red pixels to 0.9T1, and the charging time of blue pixels to 0.8T1. Through this differentiated timing control, the driving efficiency can be improved while ensuring display quality.

[0066] Furthermore, the timing controller can be configured to dynamically adjust the signal voltage range based on the dynamic range characteristics of the displayed content. For example, when the dynamic range of the displayed content is large, the voltage difference between the two grayscale signals is increased; when the dynamic range of the displayed content is small, the voltage difference between the two grayscale signals is reduced to achieve a more delicate grayscale performance.

[0067] Each pixel in the liquid crystal display device of the present invention contains only two transistors, one of which is electrically connected to the primary pixel and the other to the secondary pixel. The secondary pixels of any two pixels are insulated from each other, and / or the primary pixels of any two pixels are insulated from each other. This eliminates the shared electrode (sharebar) design used in the prior art. By reducing one transistor and eliminating the shared electrode, the area occupied by the non-light-transmitting region in the pixel is significantly reduced, thereby increasing the pixel aperture ratio and, in turn, the transmittance of the liquid crystal display device.

[0068] The present invention controls the scanning signals transmitted by the first gate line G1 and the second gate line G2 to successively turn off the first transistor and the second transistor, and inputs a first grayscale signal 301 to the sub-pixel through the data line before the first transistor is turned off, and inputs a second grayscale signal 302 to the main pixel before the second transistor is turned off. The voltage values ​​of the first grayscale signal 301 and the second grayscale signal 302 are different, so that the main pixel and the sub-pixel can respectively receive different grayscale signals, thereby achieving independent control of the main pixel and the sub-pixel without relying on a common electrode to achieve a voltage difference between the main pixel and the sub-pixel, ensuring that the image displayed by the liquid crystal display device will not have color cast and ensuring that the viewing angle of the liquid crystal display device is adjustable.

[0069] Alternatively, the present invention electrically connects the first data line D1 and the second data line D2 in a group of data lines to the sub-pixel and the main pixel of each pixel in a column of pixels, respectively, and controls the first data line D1 and the second data line D2 to input the first grayscale signal 301 and the second grayscale signal 302 with different voltage values ​​to the sub-pixel and the main pixel respectively when the gate line turns on the first transistor and the second transistor, so that the main pixel and the sub-pixel can receive different grayscale signals at the same time, thereby realizing independent control of the main pixel and the sub-pixel without relying on a common electrode to achieve the voltage difference between the main pixel and the sub-pixel, ensuring that the picture displayed by the liquid crystal display device will not have color deviation, and ensuring that the viewing angle of the liquid crystal display device is adjustable.

[0070] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A liquid crystal display device, characterized in that: include: A display panel comprising a plurality of pixels arranged in an array, each pixel comprising a primary pixel and a sub-pixel, each pixel comprising two transistors, a first transistor of the two transistors being electrically connected to the sub-pixel, and a second transistor of the two transistors being electrically connected to the primary pixel, the sub-pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of groups of gate lines, one group of the gate lines being electrically connected to a row of the pixels, the group of the gate lines comprising a first gate line and a second gate line, the first gate line being electrically connected to the first transistors of the row of the pixels, the second gate line being electrically connected to the second transistors of the row of the pixels, and a first scanning signal transmitted by the first gate line turning off the first transistors before a second scanning signal transmitted by the second gate line turning off the second transistors; as well as a plurality of data lines, one of the data lines being electrically connected to the first transistor and the second transistor of one of the pixels, the polarities of the data signals transmitted by two adjacent data lines being opposite, the data lines being configured to input a first grayscale signal to the sub-pixel before the first scanning signal turns off the first transistor, and to input a second grayscale signal to the main pixel before the second scanning signal turns off the second transistor, the first grayscale signal and the second grayscale signal having different voltage values.

2. The liquid crystal display device according to claim 1, wherein The pixel has and only has two transistors.

3. The liquid crystal display device according to claim 1, wherein The liquid crystal display device further includes: A timing controller is configured to receive image data, generate the first grayscale signal and the second grayscale signal according to the image data, control the first scanning signal transmitted by the first gate line and the second scanning signal transmitted by the second gate line to successively turn off the first transistor and the second transistor, and control the data line to input the first grayscale signal to the sub-pixel before the first transistor is turned off, and to input the second grayscale signal to the main pixel before the second transistor is turned off.

4. The liquid crystal display device according to claim 3, wherein The timing controller is configured to generate the first grayscale signal according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal according to the other of the first brightness data and the second brightness data.

5. The liquid crystal display device according to claim 1, wherein A duration during which the data line inputs a first grayscale signal to the sub-pixel before the first transistor is turned off is equal to a duration during which the data line inputs a second grayscale signal to the main pixel before the second transistor is turned off.

6. A liquid crystal display device, characterized in that: include: A display panel comprising a plurality of pixels arranged in an array, each pixel comprising a primary pixel and a sub-pixel, each pixel comprising two transistors, a first transistor of the two transistors being electrically connected to the sub-pixel, and a second transistor of the two transistors being electrically connected to the primary pixel, the sub-pixels of any two pixels being insulated from each other, and / or the primary pixels of any two pixels being insulated from each other; a plurality of gate lines, one gate line being electrically connected to a row of pixels, and one gate line being electrically connected to the first transistor and the second transistor of each pixel in a row of pixels; as well as A plurality of groups of data lines, one group of the data lines being electrically connected to a column of the pixels, a group of the pixels comprising a first data line and a second data line, the first data line being electrically connected to the sub-pixel of each of the pixels in a column, the second data line being electrically connected to the main pixel of each of the pixels in a column, the first data line and the second data line in a group of the data lines transmitting data signals having the same polarity, and the polarities of the data signals transmitted by two adjacent groups of the data lines being opposite, the first data line and the second data line being configured to input a first grayscale signal and a second grayscale signal to the sub-pixel and the main pixel, respectively, when the first transistor and the second transistor are turned on by a scanning signal transmitted by the gate line, and the voltage values ​​of the first grayscale signal and the second grayscale signal being different.

7. The liquid crystal display device according to claim 6, wherein The pixel has and only has two transistors.

8. The liquid crystal display device according to claim 6, wherein The liquid crystal display device further includes: A timing controller is configured to receive image data, generate a first grayscale signal and a second grayscale signal based on the image data, and control the first data line and the second data line to input the first grayscale signal and the second grayscale signal to the main pixel and the sub-pixel of the same column of pixels, respectively, wherein the voltage values ​​of the first grayscale signal and the second grayscale signal are different.

9. The liquid crystal display device according to claim 8, wherein The timing controller is configured to generate the first grayscale signal according to the image data and one of the first brightness data and the second brightness data in the preset viewing angle compensation data, and to generate the second grayscale signal according to the other of the first brightness data and the second brightness data.

10. The liquid crystal display device according to claim 6, wherein A duration of the first data line inputting the first grayscale signal to the sub-pixel is equal to a duration of the second data line inputting the second grayscale signal to the main pixel.

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