Timing method and device based on FLASH chip and storage medium

Abstract

The invention provides a timing method based on a FLASH chip, which utilizes the principle that the level logic of a storage unit in the FLASH chip is irreversible, that is, the logic '0' in the chip can be changed into the logic '1' only through an erasing mode, and the storage unit of the FLASH chip is erased once during power-on, so that the level logic of the storage unit in the FLASH chip is not reversible. In the subsequent timing process, each bit in the FLASH storage unit serves as the counting scale of the minimum counting time interval and is sequentially written into the logic 0, the total timing time can be obtained by counting the number of the logic 0 in the storage chip, erasing operation is avoided, and the service life of the chip is effectively prolonged. The timing method is simple and effective, does not need to configure a special display, and effectively reduces the project cost. The invention further provides timing equipment based on the FLASH chip and a computer readable storage medium.

Description

Technical Field

[0001] The invention relates to a timing method, a device and a storage medium based on a FLASH chip, and belongs to the field of embedded system timing applications. Background Art

[0002] A timer is a tool or device used to measure time intervals. It is widely used in daily life, scientific research, industrial production, sports events and other fields. Timers can be divided into many types according to their uses and principles, such as mechanical timers, electronic timers, stopwatches, chronographs, etc. In embedded system design, electronic timers are usually used to measure time, but the recorded time must be equipped with a dedicated display to display. Therefore, a new timing method is urgently needed to effectively solve the problem of equipped displays. Summary of the invention

[0003] The present invention aims to provide a timing method based on a FLASH chip. The timing method is simple and effective, does not require configuration of a dedicated display, and effectively reduces project costs.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is: a timing method based on a FLASH chip, the method comprising:

[0005] Step 1, when the device is started, read the feature word in the FLASH chip, if the feature word is a valid feature word, determine that the data stored in the timing base area is credible, and enter step 2; if it is not the valid feature word, the data stored in the timing base area is unreliable, and enter step 3; wherein, the feature word is stored in the feature word area, and is used to determine whether the data stored in the timing base area is credible; the timing base area is used to store the timing base, and the timing base is the number of bits of the FLASH chip that are rewritten from logic "1" to logic "0" when the device is powered on; the feature word area and the timing base area are partitions of the FLASH chip; the valid feature word is a preset value;

[0006] Step 2, sequentially and continuously read the stored data in the timing base area until the last byte of stored data; compare the read stored data with 0x0000 to obtain the first timing base and the second timing base, the first timing base = the number of 0x0000 in the data read in the timing base area * 16, the second timing base = the number of bits in the last byte of stored data that are logic "0", and then go to step 4; wherein the last byte is the last byte in which the bits of the FLASH chip are written with logic "0" when the power is turned on last time;

[0007] Step 3: the first timing base is 0, and the second timing base is 0; proceed to step 4;

[0008] Step 4: add the third timing base to the sum of the first timing base and the second timing base, and the fourth timing base is 0, and then proceed to step 5; wherein the third timing base is the number of minimum timing intervals corresponding to the total time that the device has been powered on before this power-on, and the fourth timing base is used to record the number of minimum timing intervals corresponding to the cumulative power-on time of the device this time, and the minimum timing interval is a preset time interval for timing;

[0009] Step 5, erasing all sectors of the FLASH chip, writing the valid signature into the signature area, and changing the logic "0" of the timing base area into logic "1" by erasing, and proceeding to step 6;

[0010] Step 6, when the minimum timing interval arrives, rewrite the logic "1" of a bit in the timing base area into logic "0", and add 1 to the fourth timing base; repeat step 6 until power is off.

[0011] The FLASH chip needs to be erased before writing data, and the erasing time is usually very long. The present invention utilizes the principle that the logic level of the storage unit in the FLASH chip is irreversible, that is, the logic "0" in the chip can only be changed to logic "1" by erasing. The storage unit of the FLASH chip is erased once when the power is turned on. In the subsequent timing, each bit in the FLASH storage unit is used as the counting scale of the minimum timing time interval, and logic "0" is written in sequence. By counting the number of logic "0" in the storage chip, the total timing time can be obtained.

[0012] According to the embodiments of the present invention, the present invention can be further optimized. The following is the technical solution formed after optimization:

[0013] In one preferred embodiment, step 1 includes: when the device starts, read the characteristic word in the timing sector in the FLASH chip, if the characteristic word in the timing sector is a valid characteristic word, determine that the stored data in the timing base area in the timing sector is credible, and enter step 2; if it is not the valid characteristic word, the stored data in the timing base area in the timing sector is unreliable, and enter step 3; wherein, the timing sector is a sector including the characteristic word area and the timing base area, and the FLASH chip has at least one timing sector. Several timing sectors can be set as timing backups to avoid the loss of counting information due to abnormal power failure during power-on erasing.

[0014] In one preferred embodiment, the method further includes: step 7, according to the third timing base and the fourth timing base, obtaining the total timing time = (the third timing base + the fourth timing base) * the minimum timing interval, and entering step 8; step 8, converting the total timing time into the format required by the communication protocol of the device and outputting it to the outside. The obtained total timing time value is transmitted to the outside through the bus message output, without the need for a display, thereby reducing the project cost.

[0015] Based on the same concept, the present invention also provides a timing device based on a FLASH chip, the device comprising: a memory for storing a computer program; a processor for implementing the steps of the above-mentioned timing method based on a FLASH chip when executing the computer program.

[0016] Based on the same concept, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned timing method based on the FLASH chip are implemented.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: the timing method based on FLASH chip provided by the present invention utilizes the principle that the logic level of the storage unit in the FLASH chip is irreversible, that is, the logic "0" in the chip can only be changed to logic "1" by erasing, and the storage unit of the FLASH chip is erased once when the power is turned on, and each bit in the FLASH storage unit is used as the counting scale of the minimum time interval in the subsequent timing, and the logic "0" is written in sequence, and the total timing time can be obtained by counting the number of logic "0" in the storage chip, and the erasing operation is avoided, which effectively extends the service life of the chip. The timing method is simple and effective, does not need to configure a dedicated display, and effectively reduces the project cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] none DETAILED DESCRIPTION

[0019] The present invention will be described in detail below in conjunction with the embodiments. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0020] Example 1

[0021] This embodiment 1 provides a timing method based on a FLASH chip, which is applicable to embedded systems, such as inertial products. This embodiment 1 takes a 16-bit FLASH bit as an example, and the specific partition design of the timing method is as follows:

[0022] 1. Reserve two FLASH sectors as dual-zone timing backup to avoid loss of counting information due to abnormal power failure during power-on erasing; the storage space of each sector is 1MB.

[0023] 2. The first word space of each sector stores a valid signature word, for example, the valid signature word 0x55ee is written when in use. When not in use or erased, the data stored in the first word space is 0xFFFF, and may also become other values ​​when abnormally damaged. The signature word is used to determine whether the recorded timing data is credible. If the valid signature word recorded in the first word space is different from the preset one (such as 0x55ee preset in the present embodiment 1), it means that the information of this timing sector is unavailable. The size of the first word space can be set according to the specific situation. In the present embodiment 1, the first word space is two bytes.

[0024] 3. The remaining word space of each sector is used to store the timing base value, which is erased only when the device is powered on and is rewritten during the subsequent power-on timing process.

[0025] 4. Each bit in the remaining word space of each sector is used as a counting scale for the minimum timing interval, which is equivalent to a ruler for recording time. When each minimum timing interval arrives, the counting scale, that is, the logic "1" of the bit, is rewritten into logic "0" in turn. That is, the write operation of the FLASH chip can only rewrite the logic "1" into logic "0", avoiding the erase operation and effectively extending the service life of the chip.

[0026] 5. When reading the timing information, the first timing sector shall prevail. Only when the first timing sector is invalid, the timing information of the backup second timing sector shall be read.

[0027] The steps of the timing method provided in this embodiment 1 specifically include:

[0028] S1. Design global variables gTimeBase and gTimeRemainder as timing variables, wherein gTimeBase is the number of minimum timing intervals corresponding to the total power-on time of the inertial group product before the current power-on, and gTimeRemainder is the number of minimum timing intervals corresponding to the accumulated power-on time of the inertial group product during the current power-on; the minimum timing interval is a preset time interval for timing, which is set according to specific usage.

[0029] S2. When the inertial group product is powered on and initialized, first read the first timing sector to determine whether the timing information is valid, that is, whether the feature word is a valid feature word. If it is a valid feature word, sequentially read the storage data of the remaining word space of the first timing sector until the last byte of storage data, compare the read data with 0x0000, obtain TimeA and TimeB, TimeA is the number of 0x0000 in the read storage data * 16, TimeB is the number of bits in the last byte of storage data that are logical "0", return a valid flag, and enter step S4; if it is not a valid feature word, return an invalid flag, and assign TimeA and TimeB to 0, and enter step S4;

[0030] The last byte is the last byte in which the bit of the FLASH chip is written with logic "0" when the power is last turned on;

[0031] S3. If the reading of the first timing sector 1 returns a valid flag, there is no need to read the second timing sector;

[0032] If the invalid flag is returned when reading the first timing sector, the second timing sector is read again, and the reading steps are similar to S2. If the signature of the second timing sector is a valid signature, reliable timing information TimeA and TimeB are obtained, and the process goes to S4; otherwise, TimeA and TimeB are assigned 0, and the process goes to S4. When the timing method is used for the first time in the conventional group product, the signatures of the two timing sectors are not valid signatures, so it is necessary to write valid signatures for subsequent use.

[0033] S4. Obtain the reliable counting information stored in the FLASH chip through S2 and S3, and assign it to the global variable: gTimeBase = gTimeBase + TimeA + TimeB; gTimeRemainder = 0;

[0034] S5, first erase the first timing sector, and write the valid feature word into the first word space in the first timing sector, and change the logic "0" of the remaining word space in the first timing sector into logic "1" by erasing; enter S6;

[0035] Then erase the second timing sector, write the valid signature into the first word space in the second timing sector, and change the logic "0" of the remaining word space in the second timing sector into logic "1" by erasing; the second timing sector is a backup of the first timing sector, and the written data is the same as that of the first timing sector;

[0036] S6. After each counting cycle, that is, when a minimum timing interval arrives, the value of the gTimeRemainder variable is increased by 1, and at the same time, the logic "1" of a bit of the remaining word space in the timing sector is rewritten to logic "0"; repeat S6 until power is cut off.

[0037] The generation and reading of timing information is completed through S1 to S6, and the timing information is stored in the global variables gTimeBase and gTimeRemain of the time function. According to gTimeBase, gTimeRemainder and the minimum timing interval, it is easy to obtain the total timing time and convert it into the format specified by the communication protocol of the inertial group product and output it to the host computer.

[0038] Example 2

[0039] In this embodiment 2, the minimum timing interval is set to 5s. Using the timing method provided in embodiment 1, when the inertial product is powered on for the first time, gTimeBase and gTimeRemainder are both 0. Every 5s, the timing method writes a bit of logic "0" into the FLASH storage chip, and the gTimeRemainder variable is the number of logic "0" written into the FLASH chip; the total timing time T = (gTimeBase + gTimeRemainder) * 5s. When powered on for the second time, gTimeBase is the last recorded power-on time T / 5, and gTimeRemainder starts to accumulate from 0 again, and so on.

[0040] The contents explained in the above embodiments should be understood as these embodiments are only used to more clearly illustrate the present invention, and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the embodiments made by those skilled in the art fall within the scope defined by the claims attached to the present invention.

Claims

1. A timing method based on FLASH chip, characterized in that: The method comprises: Step 1, when the device is started, read the feature word in the FLASH chip, if the feature word is a valid feature word, determine that the data stored in the timing base area is credible, and enter step 2; if it is not the valid feature word, the data stored in the timing base area is unreliable, and enter step 3; wherein, the feature word is stored in the feature word area, and is used to determine whether the data stored in the timing base area is credible; the timing base area is used to store the timing base, and the timing base is the number of bits of the FLASH chip that are rewritten from logic "1" to logic "0" when the device is powered on; the feature word area and the timing base area are partitions of the FLASH chip; the valid feature word is a preset value; Step 2, sequentially and continuously read the stored data in the timing base area until the last byte of stored data; compare the read stored data with 0x0000 to obtain a first timing base and a second timing base, wherein the first timing base = the number of 0x0000 in the data read in the timing base area * 16, and the second timing base = the number of bits in the last byte of stored data that are logic "0", and then proceed to step 4; wherein the last byte is the last byte in which the bits of the FLASH chip are written with logic "0" when the power is turned on last time; Step 3: the first timing base is 0, and the second timing base is 0; proceed to step 4; Step 4: add the third timing base to the sum of the first timing base and the second timing base, and the fourth timing base is 0, and then proceed to step 5; wherein the third timing base is the number of minimum timing intervals corresponding to the total time that the device has been powered on before this power-on, and the fourth timing base is used to record the number of minimum timing intervals corresponding to the cumulative power-on time of the device this time, and the minimum timing interval is a preset time interval for timing; Step 5, erasing all sectors of the FLASH chip, writing the valid signature into the signature area, and changing the logic "0" of the timing base area into logic "1" by erasing, and proceeding to step 6; Step 6, when the minimum timing interval arrives, rewrite the logic "1" of a bit in the timing base area to logic "0", and increase the fourth timing base by 1; repeat step 6 until power is off.

2. The timing method based on FLASH chip according to claim 1, characterized in that: The step 1 comprises: When the device starts, read the signature in the timing sector in the FLASH chip. If the signature in the timing sector is a valid signature, determine that the data stored in the timing base area in the timing sector is credible, and go to step 2; if it is not the valid signature, the data stored in the timing base area in the timing sector is unreliable, and go to step 3; The timing sector is a sector including the feature word area and the timing base area, and the FLASH chip has at least one timing sector.

3. The timing method based on FLASH chip according to claim 1 or 2, characterized in that: The method further comprises: Step 7, according to the third timing base and the fourth timing base, obtain the total timing time = (the third timing base + the fourth timing base) * the minimum timing interval, and proceed to step 8; Step 8: Convert the total time into a format required by the communication protocol of the device and output it to the outside.

4. A timing device based on a FLASH chip, characterized in that: The device comprises: Memory for storing computer programs; A processor, configured to implement the steps of the FLASH chip-based timing method according to any one of claims 1 to 3 when executing the computer program.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the timing method based on a FLASH chip according to any one of claims 1 to 3 are implemented.