Data storage device and non-volatile memory control method

Abstract

The invention relates to a data storage device and a non-volatile memory control method. According to the non-volatile memory control technology, instruction scheduling is carried out at a device end. The disclosed data storage device comprises a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to operate the non-volatile memory with a corresponding host end. The controller is provided with an instruction cache which caches a plurality of instructions sent by a host end. The controller schedules and executes the instructions according to information attached to the cached instructions so as to operate the non-volatile memory. The information comprises a namespace number or / and a function number. Different combined contents of the information have different priorities or processing bandwidths, so that the controller can schedule instructions according to the different combined contents.

Description

Technical Field

[0001] The present invention relates to a control technology of a non-volatile memory. Background Art

[0002] There are many forms of non-volatile memory, such as flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM, spin transfer torque RAM (STT-RAM), etc., which are used for long-term data storage and can be used as storage media to implement a data storage device.

[0003] How to efficiently control non-volatile memory is an important issue in the technical field. Summary of the invention

[0004] The present invention caches instructions on the device side and provides instruction scheduling. The disclosed data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is constructed to correspond to a host side and operate the non-volatile memory. The controller has an instruction cache to cache multiple instructions issued by the host side. The controller schedules the execution of these instructions based on information attached to these cached instructions to operate the non-volatile memory. The information includes a namespace number and / or a function number. Different combinations of the information have different priorities or processing bandwidths for the controller to perform instruction scheduling.

[0005] The above concept is further used to implement a control method of a non-volatile memory.

[0006] The following is a detailed description of the present invention with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A data storage device 100 is illustrated according to one embodiment of the present invention;

[0008] Figure 2A ,as well as Figure 2B Illustrate examples of non-single root input / output virtualization (non-SRIOV);

[0009] Figure 3A ,as well as Figure 3B Illustrate an example of Single Root Input / Output Virtualization (SRIOV) involving multiple hosts;

[0010] Figure 4A ,as well as Figure 4BIllustrate non-SRIOV example - single host 202 only;

[0011] Figure 5A ,as well as Figure 5B Illustrate an example of Single Root Input / Output Virtualization (SRIOV) involving multiple hosts;

[0012] Fig. 6A ,as well as Figure 6B Illustrate an example of non-SRIOV involving multiple hosts 202_1, 202_2; and

[0013] Fig. 7A ,as well as Figure 7B An example of non-single root input / output virtualization (non-SRIOV) is shown, involving multiple hosts 202_1 and 202_2.

[0014]

Explanation of symbols

[0015] 100: Data storage device

[0016] 102: Flash memory

[0017] 104: Controller

[0018] 106: Host side

[0019] 108: Instructions

[0020] 110: Instruction Cache

[0021] 112: Information Identification and Command Scheduling Module

[0022] 114:Timer

[0023] 202, 202_1, 202_2: Host

[0024] 204, 204_1: Entity Function

[0025] 204_2: Virtual Function

[0026] 206…222, 230, 402…406, 602…620, 630, 702: Function blocks

[0027] VM1, VM2: virtual machines DETAILED DESCRIPTION

[0028] The following description lists various embodiments of the present invention. The following description introduces the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the scope of the patent application. The various functional blocks mentioned below can be implemented by a combination of hardware, software, and firmware, and can also include special circuits. The various functional blocks are not limited to being implemented separately, but can also be combined together to share certain functions.

[0029] Non-volatile memory can be Flash Memory, Magnetoresistive RAM, Ferroelectric RAM, Resistive RAM (RRAM), Spin Transfer Torque RAM (STT-RAM), etc., which provide storage media for long-term data preservation. The following discussion specifically takes Flash Memory as an example, but the technology described can also be used on other types of non-volatile memory.

[0030] Nowadays, data storage devices often use flash memory as storage media to realize products such as memory cards, USB flash devices, solid-state drives (SSDs), etc. One application is to use multi-chip packaging to package the flash memory and its controller together, which is called an embedded flash memory module (such as eMMC).

[0031] Data storage devices using flash memory as storage media can be applied to a variety of electronic devices, including smart phones, wearable devices, tablet computers, virtual reality devices, etc. The processor of the electronic device can be regarded as a host, operating the data storage device configured in the electronic device to access the flash memory therein.

[0032] Data storage devices using flash memory as storage media can also be used to build data centers. For example, servers can operate solid-state drive (SSD) arrays to form data centers. The server can be regarded as a host and operate the connected solid-state drive to access the flash memory therein.

[0033] The vehicle-mounted system can also use flash memory to implement data storage devices. Various sensors in the vehicle-mounted system can be regarded as hosts and have the need to access flash memory.

[0034] Flash memory has its own special storage characteristics. The host side issues read and write requests to the flash memory using logical addresses (for example, logical block addresses LBA or global host page numbers GHP, etc.). The logical address needs to be mapped to a physical address in order to correspond to the flash memory physical space. The present invention is applied to namespace technology. Each namespace corresponds to a set of logical addresses, allowing specific software to access. Each namespace has its corresponding namespace identifier (NSID). The flash memory access instruction issued by the host side may be accompanied by a namespace number (NSID) for identification by the device-side controller.

[0035] As for applications where multiple hosts share data storage devices (for example, in-vehicle systems), single root I / O virtualization (SRIOV) technology can be used to achieve high-speed peripheral component interconnect (PCIe) expansion. The data storage device connected to a single PCIe slot can be accessed through a physical channel or an expanded virtual channel, involving virtual machine (VM) technology. The physical channel corresponds to the physical function, and the virtual channel corresponds to the virtual function (VF); each function has its own function number (VF identifier, abbreviated as VFID; the physical function number is VFID0, and the virtual function number starts from VFID1). The flash memory access command issued by the host side can be accompanied by a function number (VFID) for the device-side controller to identify.

[0036] The present invention caches instructions at the device end, and schedules instructions according to information attached to the instructions (such as the aforementioned namespace number NSID and / or function number VFID) to operate the non-volatile memory.

[0037] Figure 1According to one embodiment of the present invention, a data storage device 100 is illustrated, which includes a flash memory 102 and a controller 104 coupled to the flash memory 102. The controller 104 is constructed to operate the flash memory 102 in response to the request of the host end 106. The command 108 issued by the host end 106 is attached with information (such as the aforementioned namespace number NSID and / or function number VFID). The controller 104 caches the command 108 issued by the host end 106 in a command cache 110. The controller 104 further includes an information identification and command scheduling module 112, which schedules the execution of these commands according to the information attached to the commands cached in 110 to operate the flash memory 102. For example, the host end 106 can grant different priorities or processing bandwidths to different combinations of the information; or, the priority or processing bandwidth of each combination of contents can be granted or set by other methods, not limited to being granted by the host end 106. The information identification and command scheduling module 112 can be set in accordance with the host end 106, and can perform command scheduling in accordance with the identified information. The controller 104 can provide a timer 114 to implement processing bandwidth control. Processing bandwidth control can also be implemented in a command counting manner.

[0038] First, we will discuss an example in which the namespace ID (NSID) is used as additional information for a command.

[0039] In one embodiment, different namespace numbers have different priorities. The controller 104 of the device side first executes the instructions with the namespace numbers with higher priorities in the instruction cache 110 before executing the instructions with the namespace numbers with lower priorities in the instruction cache 110 .

[0040] Figure 2A ,as well as Figure 2B An example of non-single root input / output virtualization (non-SRIOV) is illustrated—single host 202 only.

[0041] refer to Figure 2A, the host 202 issues instructions to the device to implement the physical function 204. Before execution, it is cached and scheduled. Each instruction is accompanied by information, including the namespace number (NSID) involved in the instruction. Each namespace number (NSID) has a different priority; for example, this embodiment allows two namespace numbers NSID_A and NSID_B to have different priorities. Regarding the cached instructions, the device uses function block 206 to perform namespace identification, and then uses function block 208 to determine whether the namespace number NSID_A is granted a high priority. If so, the device uses function block 210 to determine whether it is processing an instruction with namespace number NSID_A. If so, the device executes the instruction and operates function block 210 again to determine whether the subsequent instruction is also with namespace number NSID_A. Conversely, the device uses function block 212 to determine whether there is an instruction with namespace number NSID_A cached in other locations of the instruction cache (110). If so, the device uses function block 214 to retrieve a new instruction with namespace number NSID_A from the instruction cache (110), and returns to the previous step to execute it according to the priority configuration. If the instruction cache (110) currently does not have an instruction with namespace number NSID_A, the device uses function block 216 to determine whether it is processing an instruction with namespace number NSID_B. If so, the device executes the instruction and operates function block 212 to check the instruction cache (110) again to ensure that the instruction with namespace number NSID_A takes priority. If 216 determines that there is no instruction with namespace number NSID_B to be processed, the device uses function block 214 to retrieve a new instruction from the instruction cache (110), and returns to the previous step to schedule its execution according to the priority configuration.

[0042] If function block 208 determines that namespace number NSID_A is not granted a high priority, then the corresponding high priority is namespace number NSID_B. The device end uses function block 218 to determine whether it is processing an instruction with namespace number NSID_B. If so, the device end executes the instruction and operates function block 218 again to determine whether the subsequent instruction is also namespace number NSID_B. On the contrary, the device end uses function block 220 to determine whether there is an instruction with namespace number NSID_B cached in other locations of the instruction cache (110). If so, the device end uses function block 222 to newly retrieve an instruction with namespace number NSID_B from the instruction cache (110), and returns to the previous step to execute it according to the priority configuration. If there is currently no instruction with namespace number NSID_B in the instruction cache (110), the device end uses function block 224 to determine whether it is processing an instruction with namespace number NSID_A. If yes, the device executes the command and again checks the command cache (110) at function block 220 to ensure that the command with namespace number NSID_B is prioritized. If 224 determines that there is no command with namespace number NSID_A to process, the device fetches a new command from the command cache (110) at function block 222 and returns to the previous step to schedule its execution according to the priority configuration.

[0043] See also Figure 2B The command issued by the host 202 is converted into a physical function (204), and after completing the namespace identification (206), a namespace priority determination is further performed (230, corresponding to Figure 2A As shown in the figure, the instructions of the namespace number (NSID) with a high priority will be executed before the instructions of the namespace number (NSID) with a low priority will be executed.

[0044] Figure 3A ,as well as Figure 3B Illustrate an example of Single Root Input / Output Virtualization (SRIOV) involving multiple hosts.

[0045] Comparison Figure 2A A single host 202, Figure 3A The two hosts 202_1 and 202_2 respectively issue commands to the device end through the two virtual machines VM1 and VM2, and the device end converts the physical function 204_1 and the virtual function 204_2. Figure 3A The rest of the functional blocks are the same Figure 2A .corresponding Figure 3A , Figure 3B It shows that SRIOV can also execute the instructions of the namespace number (NSID) with a high priority after the instructions of the namespace number (NSID) with a low priority are executed.

[0046] In one implementation, instructions with different namespace IDs (NSIDs) have different processing bandwidths.

[0047] The controller 104 preferentially executes the instruction with a first namespace number in the instruction cache 110 in a first time interval T1, and preferentially executes the instruction with a second namespace number in the instruction cache 110 in a second time interval T2. In one embodiment, the controller 104 of the device divides an execution cycle into the first time interval T1 and the second time interval T2 having a length different from the first time interval T1. Alternatively, two time intervals planned without cutting the execution cycle can also be used as the first time interval T1 and the second time interval T2.

[0048] Figure 4A ,as well as Figure 4B An example of non-single root input / output virtualization (non-SRIOV) is illustrated—single host 202 only.

[0049] refer to Figure 4A , the host 202 issues instructions to the device end to implement the physical function 204. Each instruction is accompanied by information, including the namespace number (NSID) involved in the instruction. Each namespace number (NSID) corresponds to a different processing bandwidth; for example, this embodiment sets the processing bandwidth for two namespace numbers NSID_A and NSID_B, the namespace number NSID_A has a high processing bandwidth, and the namespace number NSID_B has a low processing bandwidth. After the device end performs namespace identification with function block 206, it resets the timer (114) with function block 402. Then, the device end reads the timer 114 with function block 404 to confirm whether it is in the first time interval T1. If so, the device end executes the instruction of the namespace number NSID_A until it exceeds the first time interval T1. Then, the device end reads the timer 114 with function block 406 to confirm whether it is in the second time interval T2 (shorter than the first time interval T1). If so, the device executes the command of the namespace number NSID_B until the second time interval T2 is exceeded, and operates the function block 402 again to reset the timer (114).

[0050] See also Figure 4BAfter the command issued by the host 202 is converted into a physical function (204) and namespace identification (206), the device end repeatedly resets the timer 114 with a function block to count the first time interval T1 and the second time interval T2, so as to execute the command of the command space number NSID_A and NSID_B accordingly. The first time interval T1 is longer than the second time interval T2. The command of the command space number NSID_A obtains a larger processing bandwidth than the command of the command space number NSID_B.

[0051] Figure 5A ,as well as Figure 5B Illustrate an example of Single Root Input / Output Virtualization (SRIOV) involving multiple hosts.

[0052] Comparison Figure 4A A single host 202, Figure 5A The two hosts 202_1 and 202_2 respectively issue commands to the device end through the two virtual machines VM1 and VM2, and the device end converts the physical function 204_1 and the virtual function 204_2. Figure 5A The rest of the functional blocks are the same Figure 4A .corresponding Figure 5A , Figure 5B It shows that SRIOV can also enable the instructions in the command space number NSID_A to obtain a larger processing bandwidth than the instructions in the command space number NSID_B (T1>T2).

[0053] In some cases, if the first time interval T1 has not ended, but there is no command space number NSID_A to be executed, the controller 104 can execute the command space number NSID_B. Similarly, if the second time interval T2 has not ended, but there is no command space number NSID_B to be executed, the controller 104 can execute the command space number NSID_A.

[0054] In one embodiment, the device-side controller 104 uses the number of instructions as the basis for adjusting the processing bandwidth. The controller 104 configures the command space number NSID_A to correspond to the number of instructions N1, and the command space number NSID_B to correspond to the number of instructions N2, N1≠N2. The controller 104 executes N1 instructions of the namespace number NSID_A, and then executes N2 instructions of the namespace number NSID_B, and cycles according to this N1:N2 ratio. If N1 is greater than N2, the instructions of the namespace number NSID_A obtain a larger processing bandwidth than the instructions of the namespace number NSID_B.

[0055] In one embodiment, the device-side controller 104 uses the lower limit of the number of instructions as the basis for adjusting the processing bandwidth. The controller 104 configures the command space number NSID_A to correspond to the lower limit of the number of instructions TH1, and the command space number NSID_B to correspond to the lower limit of the number of instructions TH2, TH1≠TH2. The controller 104 executes the instructions of the namespace number NSID_A to the lower limit of the number of instructions TH1, and then switches to execute the instructions of the namespace number NSID_B, and after the instructions of the namespace number NSID_B are executed to the lower limit of the number of instructions TH2, it switches back to execute the instructions of the namespace number NSID_A, and repeats this cycle. If TH1 is less than TH2, the instructions of the namespace number NSID_A obtain a larger processing bandwidth than the instructions of the namespace number NSID_B.

[0056] The following discusses examples of using a function ID (VFID) as additional information for instructions; such embodiments are all single root input / output virtualization (SRIOV) applications.

[0057] In one embodiment, instructions with different function numbers have different priorities. The controller 104 at the device end first executes instructions with higher priority function numbers in the instruction cache 110 before executing instructions with lower priority function numbers in the instruction cache 110 .

[0058] Fig. 6A ,as well as Figure 6B An example of non-single root input / output virtualization (non-SRIOV) is shown, involving multiple hosts 202_1 and 202_2.

[0059] refer to Fig. 6A, the hosts 202_1 and 202_2 issue instructions to the device side through two virtual machines VM1 and VM2 respectively, and the device side converts the physical function 204_1 and the virtual function 204_2. Each instruction is accompanied by information, including the function number (VFID) defined by the device virtualization. The priority of each function number (VFID) can be determined on the host side; for example, this embodiment sets the priority of two function numbers (function number VFID0 corresponding to virtual machine VM1 and function number VFID1 corresponding to virtual machine VM2). After the device side performs function identification with function block 602, it determines with function block 604 whether the physical function of function number VFID0 is granted high priority. If so, the device side determines with function block 606 whether it is processing a physical function instruction (VFID0). If so, the device side executes the instruction and operates function block 606 again to determine whether the subsequent instruction is also a physical function instruction (VFID0). On the contrary, the device side uses function block 608 to determine whether there is a physical function instruction (VFID0) cached in other locations of the instruction cache (110). If so, the device side uses function block 610 to newly fetch the physical function instruction (VFID0) from the instruction cache (110), and returns to the previous step to execute it according to the priority configuration. If there is no physical function instruction (VFID0) in the instruction cache (110), the device side uses function block 612 to determine whether it is processing a virtual function instruction (VFID1). If so, the device side executes the instruction and operates function block 608 again to check the instruction cache (110) to ensure that the physical function instruction (VFID0) takes priority. If 612 determines that there is no virtual function instruction (VFID1) to be processed, the device side uses function block 610 to newly fetch the instruction from the instruction cache (110), and returns to the previous step to schedule its execution according to the priority configuration.

[0060] If function block 604 determines that the physical function (VFID0) is not granted a high priority, then the corresponding high priority is the virtual function (VFID1). The device end uses function block 614 to determine whether it is processing a virtual function instruction (VFID1). If so, the device end executes the instruction and operates function block 614 again to determine whether the subsequent instruction is also a virtual function instruction (VFID1). On the contrary, the device end uses function block 616 to determine whether there is a virtual function instruction (VFID1) cached in other locations of the instruction cache (110). If so, the device end uses function block 618 to newly retrieve the virtual function instruction (VFID1) from the instruction cache (110), and returns to the previous step to execute it according to the priority configuration. If there is no virtual function instruction (VFID1) in the instruction cache (110), the device end uses function block 620 to determine whether it is processing a physical function instruction (VFID0). If yes, the device executes the instruction and again checks the instruction cache (110) at function block 616 to ensure that the virtual function instruction (VFID1) takes priority. If 620 determines that there is no physical function instruction (VFID0) to process, the device fetches a new instruction from the instruction cache (110) at function block 618 and returns to the previous step to schedule its execution according to the priority configuration.

[0061] See also Figure 6B After the command issued by the host 202_1 / 202_2 is converted into the physical function 204_1 / virtual function 204_2 and the function identification is completed (602), the function priority is determined (630, corresponding to Fig. 6A As shown in the figure, the instructions of the function number (VFID) with a high priority will be executed before the instructions of the function number (VFID) with a low priority will be executed.

[0062] In one implementation, instructions with different VFIDs have different processing bandwidths.

[0063] The controller 104 preferentially executes the instruction with a first function number in the instruction cache 110 in a first time interval T1, and preferentially executes the instruction with a second function number in the instruction cache 110 in a second time interval T2. In one embodiment, the controller 104 of the device side divides an execution cycle into the first time interval T1 and the second time interval T2 whose length is different from the first time interval T1. Alternatively, two time intervals planned without cutting the execution cycle can also be used as the first time interval T1 and the second time interval T2.

[0064] Fig. 7A ,as well as Figure 7B An example of non-single root input / output virtualization (non-SRIOV) is shown, involving multiple hosts 202_1 and 202_2.

[0065] and Figure 5A ,as well as Figure 5B Compared with the example of configuring processing bandwidth based on namespace, Fig. 7A ,as well as Figure 7B Function identification 702 is used. Figure 7B It is clearly shown that the physical function instruction with function number VFID0 obtains a larger processing bandwidth than the virtual function instruction with function number VFID1.

[0066] In some cases, if the first time interval T1 has not expired, but there is no physical function instruction with function number VFID0 to be executed, the controller can execute the virtual function instruction with function number VFID1. Similarly, if the second time interval T2 has not expired, but there is no virtual function instruction with function number VFID1 to be executed, the controller can execute the physical function instruction with function number VFID0.

[0067] In one embodiment, the device-side controller uses the number of instructions as the basis for adjusting the processing bandwidth. The device-side controller configures the function number VFID0 to correspond to the number of instructions N1, and the function number VFID1 to correspond to the number of instructions N2, N1≠N2. The controller 104 executes N1 physical function instructions with the function number VFID0, and then executes N2 virtual function instructions with the function number VFID1, and cycles according to the N1:N2 ratio. If N1 is greater than N2, the physical function instruction with the function number VFID0 obtains a larger processing bandwidth than the virtual function instruction with the function number VFID1.

[0068] In one embodiment, the device-side controller 104 uses the lower limit of the number of instructions as the basis for adjusting the processing bandwidth. The controller 104 configures the function number VFID0 to correspond to the lower limit of the number of instructions TH1, and the function number VFID1 to correspond to the lower limit of the number of instructions TH2, TH1≠TH2. The controller 104 executes the physical function instruction of the function number VFID0 to the lower limit of the number of instructions TH1, and then switches to execute the virtual function instruction of the function number VFID1, and after the virtual function instruction of the function number VFID1 is executed to the lower limit of the number of instructions TH2, it switches back to execute the physical function instruction of the function number VFID0, and repeats this cycle. If TH1 is less than TH2, the physical function instruction of the function number VFID0 obtains a larger processing bandwidth than the virtual function instruction of the function number VFID1.

[0069] In other implementations, the configuration of priority / processing bandwidth is not limited to between physical functions and virtual functions. Different virtual functions may also be configured with different priorities / processing bandwidths. For example, the first virtual function may have a different priority / processing bandwidth from the second virtual function.

[0070] The above concept can be further used to implement a non-volatile memory control method, including: a cache host sends a plurality of instructions for operating a non-volatile memory; and according to information attached to these instructions, the instructions are scheduled to be executed to operate the non-volatile memory. The information includes a namespace ID (NSID) and / or a function ID (VFID). Different combinations of the information have different priorities or processing bandwidths for instruction scheduling.

[0071] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this technology can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached patent application.

Claims

1. A data storage device, comprising: a non-volatile memory; as well as A controller is coupled to the non-volatile memory and configured to operate the non-volatile memory in response to a host request. in: The controller has an instruction cache for caching multiple instructions sent by the host; and The controller schedules the execution of the instructions according to information attached to the cached instructions to operate the non-volatile memory.

2. The data storage device according to claim 1, wherein: The information includes a namespace number; and Each namespace number corresponds to a set of logical addresses, and the host end requests to access the non-volatile memory using the logical addresses.

3. The data storage device according to claim 2, wherein: Different namespace numbers have different precedence; and The controller preferentially executes instructions with namespace numbers having higher priorities in the instruction cache before executing instructions with namespace numbers having lower priorities in the instruction cache.

4. The data storage device according to claim 2, wherein: Instructions with different namespace numbers have different processing bandwidths.

5. The data storage device according to claim 4, wherein: The controller preferentially executes instructions with a first namespace number in the instruction cache in a first time interval, and preferentially executes instructions with a second namespace number in the instruction cache in a second time interval.

6. The data storage device according to claim 1, wherein: This information includes the function number defined by the device virtualization.

7. The data storage device according to claim 6, wherein: Different function numbers have different priorities; and The controller preferentially executes instructions with higher priority function numbers in the instruction cache before executing instructions with lower priority function numbers in the instruction cache.

8. The data storage device according to claim 6, wherein: Instructions with different function numbers have different processing bandwidths.

9. The data storage device as claimed in claim 8, wherein: The controller preferentially executes instructions with a first function number in the instruction cache in a first time interval, and preferentially executes instructions with a second function number in the instruction cache in a second time interval.

10. The data storage device according to claim 1, wherein: The information includes the namespace number and the function number defined by the device virtualization; Each namespace number corresponds to a set of logical addresses, and the host end requests to access the non-volatile memory using the logical addresses; and Different combinations of the information have different priorities or processing bandwidths for the controller to schedule commands accordingly.

11. A non-volatile memory control method, comprising: caching, at the device end, a plurality of instructions issued by the host end to operate a non-volatile memory; and According to information attached to the instructions, the instructions are scheduled to be executed to operate the non-volatile memory.

12. The non-volatile memory control method according to claim 11, wherein: The information includes a namespace number; and Each namespace number corresponds to a set of logical addresses, and the host end requests to access the non-volatile memory using the logical addresses.

13. The non-volatile memory control method according to claim 12, wherein: Also includes: Give different namespace numbers different priorities; and The cached instructions with higher priority namespace numbers are executed first, and then the cached instructions with lower priority namespace numbers are executed.

14. The non-volatile memory control method according to claim 12, wherein: Also includes: Commands with different namespace numbers have different processing bandwidths.

15. The non-volatile memory control method according to claim 14, wherein: Also includes: In a first time interval, cached instructions with a first namespace number are preferentially executed, and in a second time interval, cached instructions with a second namespace number are preferentially executed.

16. The non-volatile memory control method according to claim 11, wherein: This information includes the function number defined by the device virtualization.

17. The non-volatile memory control method according to claim 16, wherein: Also includes: To give different function numbers different priorities; and The cached instructions with higher priority function numbers are executed first, and then the cached instructions with lower priority function numbers are executed.

18. The non-volatile memory control method according to claim 16, wherein: Also includes: Commands with different function numbers have different processing bandwidths.

19. The non-volatile memory control method according to claim 18, wherein: Also includes: The cached instructions with a first function number are preferentially executed in a first time interval, and the cached instructions with a second function number are preferentially executed in a second time interval.

20. The non-volatile memory control method according to claim 11, wherein: The information includes the namespace number and the function number defined by the device virtualization; Each namespace number corresponds to a set of logical addresses, and the host end requests to access the non-volatile memory using the logical addresses; and The non-volatile memory control method grants different combinations of the information with different priorities or processing bandwidths to perform command scheduling.

Images