Data processing method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of storage, and discloses a data processing method and device, computer equipment and a storage medium, the data processing method and device are applied to a reading main core of a hard disk controller, and the hard disk controller further comprises at least one reading standby core; the method comprises the steps that in the read-write operation process of a source data block and a target data block, a first variable value is obtained from a hard disk cache at the first moment, and the first variable value is used for measuring the load capacity of a read main core at the first moment; if the first variable value is a first numerical value at the first moment, a read request message is generated and sent to the at least one read standby core, the read request message is used for indicating the at least one read standby core to start and assisting the read main core in executing read-write operation on the source data block and the target data block, and the first numerical value is used for indicating that the read main core is in a load state. According to the method and the device, the problems that the data reading speed is slow and the service performance is influenced if the read processing core is occupied by other services or the performance is insufficient in the hard disk garbage recycling process can be solved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data processing method, device, computer equipment and storage medium. Background Art

[0002] When a solid state disk (SSD) needs to perform garbage collection (GC), it is usually necessary to first select a source data block with the most garbage data, then read the P2L (Physical-to-Logical) reverse table of the source data block, and identify the garbage data by comparing the read result with the corresponding content of the L2P (Logical-to-Physical) mapping table of the source data block. The data with consistent comparison results is determined as valid data that needs to be moved to the target data block, otherwise, the data with inconsistent comparison results is determined as garbage data to be erased.

[0003] In the related art, when the SSD controller reads valid data, it usually continuously sends read requests to the non-volatile flash controller (NFC) through the GC read processing core in the SSD controller, and the NFC reads the valid data in the source data block, and after the NFC reads, it returns to the GC read processing core, and the GC read processing core sends the read valid data to the GC write processing core, and the GC write processing core rewrites the read valid data to the new target data block according to a certain organizational format. In this SSD garbage collection method, if the GC read processing core is occupied by other services or has insufficient performance, it will cause the GC read processing core to read data slowly, affecting the SSD service performance. Summary of the invention

[0004] In view of this, the present invention provides a data processing method to solve the problem of slow data reading speed and impact on business performance if the read processing core is occupied by other businesses or has insufficient performance during hard disk garbage collection.

[0005] In a first aspect, the present invention provides a data processing method, which is applied to a read main core of a hard disk controller, and the hard disk controller also includes at least one read standby core; the method includes: in the process of reading and writing source data blocks and target data blocks, obtaining a first variable value from the hard disk cache at a first moment, and the first variable is used to measure the load of the read main core at the first moment; if the first variable value at the first moment is a first numerical value, then generating and sending a request read message to at least one read standby core, the request read message is used to indicate that at least one read standby core is started and assists the read main core in performing read and write operations on the source data block and the target data block, and the first numerical value is used to indicate that the read main core is in a load state.

[0006] Based on the method of the first aspect above, the read main core can obtain a first variable value from the hard disk cache at a first moment during the read and write operations on the source data block and the target data block, and if the first variable value at the first moment is a first numerical value, a read request message is generated and sent to at least one read standby core to instruct at least one read standby core to start and assist the read main core in performing read and write operations on the source data block and the target data block.

[0007] Since the value of the first variable is the first value at the first moment, it means that the main read core is in an overloaded state at the first moment. At this time, a request read message is generated and sent to at least one read standby core to start at least one read standby core to assist the main read core in performing read and write operations on the source data block and the target data block. That is, when the main read core performs data processing or the data read and write operation load is large, at least one read standby core is used to share the load of the main read core performing data processing, so as to achieve the goal of load balancing, avoid the problem of slow data reading speed caused by the read processing core being occupied by other services or insufficient performance during the hard disk garbage collection process, and improve the overall performance of hard disk garbage collection.

[0008] In combination with the first aspect, in an optional embodiment, the method also includes: during the read and write operations on the source data block and the target data block, obtaining a first variable value from the hard disk cache at a second moment, the second moment being after the first moment; if the first variable value at the second moment is a second numerical value, sending a stop read message to at least one read standby core, the stop read message is used to indicate that at least one read standby core stops, and the second numerical value is used to indicate that the read main core is in a low load state.

[0009] In the implementation manner of the present invention, when the value of the first variable is the second value at the second moment, it means that the main read core is in a low-load state at the second moment. At this time, a stop-read message is generated and sent to at least one read standby core, so that at least one read standby core stops assisting the main read core in performing read and write operations on the source data block and the target data block. That is, when the main read core performs data processing or data read and write operations with a low load, at least one read standby core is actively stopped, thereby reducing the impact on the business on at least one standby core and improving the response speed of at least one standby core.

[0010] In combination with the first aspect, in an optional embodiment, the hard disk controller also includes a write processing core; performing read and write operations on the source data block and the target data block, including: sending multiple read commands to the flash memory controller in sequence, each read command is used to instruct the flash memory controller to read valid data of at least one address in the source data block, and based on the valid data, generate and return a read information to the read main core; receiving multiple read information returned from the flash memory controller in sequence, and sending the multiple read information to the write processing core in sequence, so that the write processing core writes the valid data to the target data block.

[0011] In the implementation manner of the present invention, read commands may be issued one by one in sequence, and multiple pieces of returned read information may be received in sequence, thereby avoiding high delays caused by issuing a large number of commands at one time and improving overall performance.

[0012] In combination with the first aspect, in an optional implementation, a second variable value is pre-stored in the hard disk cache, and the second variable value is used to indicate the number of times the detected message concurrency being processed by the read main core is greater than or equal to a first threshold; the method also includes: obtaining the second variable value during the read and write operations on the source data block and the target data block; if the second variable value is less than the second threshold, detecting a first number of read commands that have been sent and no read information returned by the flash memory controller is received, and detecting a second number of read messages that have not been sent to the write processing core, the sum of the first number and the second number being the message concurrency; if it is detected that the message concurrency is greater than or equal to the first threshold, increasing the second variable value by one; if it is detected that the message concurrency is less than the first threshold, clearing the second variable value to zero.

[0013] In an embodiment of the present invention, a second variable value is pre-stored on a hard disk to facilitate recording the number of times the detected message concurrency being processed by the read main core is greater than or equal to the first threshold, so as to facilitate subsequent determination of the value of the first variable value based on the second variable value to judge the load status of the read main core.

[0014] In combination with the first aspect, in an optional implementation, the method further includes: if the acquired second variable value is greater than or equal to a second threshold, setting the first variable value to a first value.

[0015] In an embodiment of the present invention, when the recorded detected message concurrency being processed by the read main core is greater than or equal to the first threshold and the number of times is greater than or equal to the second threshold, the load state indicating the read main core is set to the first numerical value corresponding to the high load state, so as to facilitate the subsequent startup of at least one read standby core based on the high load state of the read main core.

[0016] In combination with the first aspect, in an optional implementation, a third variable value is pre-stored in the hard disk cache, and the third variable value is used to indicate the number of times the detected message concurrency being processed by the read main core is less than a third threshold; the third threshold is less than the first threshold; the method also includes: during the read and write operations on the source data block and the target data block, obtaining the third variable value; if the third variable value is less than the second threshold, detecting the message concurrency; if it is detected that the message concurrency is less than the third threshold, adding one to the third variable value; if it is detected that the message concurrency is greater than or equal to the third threshold, clearing the third variable value.

[0017] In an embodiment of the present invention, a third variable value is pre-stored on a hard disk to facilitate recording the number of times the detected message concurrency being processed by the read main core is less than a third threshold value, so as to facilitate subsequent determination of the value of the first variable value based on the third variable value to judge the load status of the read main core.

[0018] In combination with the first aspect, in an optional implementation, the method further includes: if the acquired third variable value is greater than or equal to a second threshold, setting the first variable value to a second value.

[0019] In an embodiment of the present invention, when the number of times the recorded detected message concurrency being processed by the read main core is less than the third threshold is greater than or equal to the second threshold, the load state indicating the read main core is set to a second numerical value corresponding to the low load state, so as to facilitate the subsequent stopping of at least one read standby core based on the low load state of the read main core.

[0020] In a second aspect, the present invention provides a processor, wherein the processor and at least one read spare core belong to a hard disk controller; the processor comprises: an acquisition module, used to acquire a first variable value from a hard disk cache at a first moment during a read and write operation on a source data block and a target data block, the first variable value being used to measure the load of the processor at the first moment; a processing module, used to generate and send a request read message to at least one read spare core if the first variable value at the first moment is a first numerical value, the request read message being used to instruct at least one read spare core to start and assist the processor in performing read and write operations on the source data block and the target data block, the first numerical value being used to indicate that the processor is in an overloaded state.

[0021] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the data processing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0022] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the data processing method of the first aspect or any corresponding embodiment thereof.

[0023] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the data processing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a topological diagram of a data processing system according to an embodiment of the present invention;

[0026] Figure 2 is a flow chart of a data processing method according to an embodiment of the present invention;

[0027] Figure 3 is a flow chart of another data processing method according to an embodiment of the present invention;

[0028] Figure 4 is a structural block diagram of a processor according to an embodiment of the present invention;

[0029] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0031] The embodiment of the present invention is applied to the scenario where garbage collection is required for a solid state drive, especially in the scenario where the SSD controller reads valid data in a source database with the most garbage data.

[0032] Currently, during the garbage collection process of a solid-state drive, when the SSD controller reads valid data, if the GC read processing core is occupied by other services or has insufficient performance, the GC read processing core will read data slowly, affecting the SSD service performance.

[0033] In order to solve the above technical problems, an embodiment of the present invention provides a data processing method, which improves the data reading speed by enabling a read standby core to assist the read main core while the read main core reads valid data.

[0034] Below Figure 1 The method provided in the embodiment of the present application is described by taking the data processing system 100 as an example. Figure 1 It is only a schematic diagram and does not constitute a limitation on the applicable scenarios of the technical solution provided in this application.

[0035] like Figure 1 As shown, Figure 1 is a topological diagram of a data processing system according to an embodiment of the present invention. Figure 1 In the embodiment, the data processing system 100 may include a read main core 101, a read standby core 102, a write processing core 103, a control core 104, a flash memory controller 105 and a hard disk 106. The hard disk 106 includes a source data block 1061 and a target data block 1062.

[0036] The main read core 101, the standby read core 102, the write processing core 103 or the control core 104 in the embodiment of the present invention may be any processing core in the hard disk controller. It is understandable that the hard disk controller may also include more other processing cores.

[0037] The flash memory controller (Nand Flash Control, NFC) 105 in the embodiment of the present invention is used to control the read, write and erase operations of the flash memory particles corresponding to the scheduling source data block or the write data block.

[0038] The source data block 1061 or the target data block 1062 in the embodiment of the present invention may be any data block in the hard disk 106 . The flash memory controller 105 reads data from the source data block 1061 , and the write processing core 103 writes the read data into the target data block 1062 .

[0039] Figure 1 The data processing system 10 shown is only used as an example and is not used to limit the technical solution of the present application. Those skilled in the art should understand that in the specific implementation process, the data processing system 10 can also include other read spare cores, and the number of read spare cores can also be determined according to specific needs without limitation.

[0040] According to an embodiment of the present invention, a data processing method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0041] In this embodiment, a data processing method is provided, which can be used for the above-mentioned read master core. Figure 2 is a flow chart of a data processing method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0042] S201: During a read and write operation on a source data block and a target data block, a first variable value is obtained from a hard disk cache at a first moment.

[0043] The first variable value may also be a gc_multi_flag variable. The first variable value is used to measure the load of the read main core at the first moment. The first variable value may be a first value or a second value. The first value is used to indicate that the read main core is in an overload state. The second value is used to indicate that the read main core is in a low load state. For example, the first value may be 1, and the second value may be 0.

[0044] It can be understood that the first variable value is pre-stored in the hard disk cache.

[0045] In some optional implementations, the read master core sequentially sends multiple read commands to the flash memory controller; sequentially receives multiple read messages returned from the flash memory controller, and sequentially sends the multiple read messages to the write processing core, so that the write processing core writes valid data into the target data block.

[0046] Each read command is used to instruct the flash memory controller to read valid data of at least one address (for example, a multi-plane address) in the source data block, and based on the valid data, generate and return a read information to the read main core.

[0047] Each read message includes a plurality of valid data read.

[0048] For example, Figure 1 For example, when the number of free data blocks in the hard disk 106 is less than a preset threshold, the control core 104 sends a first message to the read master core 101, and the first message is used to instruct the read master core 101 to start the GC read process. The read master core 101 receives the first message and starts to send multiple read commands to the flash controller 105 in sequence; at the same time, it sequentially receives multiple read messages returned from the flash controller 106, and sends the multiple read messages to the write processing core 103 in sequence. The write processing core 103 writes the valid data into the target data block 1062.

[0049] In one example, the read master core receives multiple read messages returned from the flash memory controller, and sends the multiple read messages to the write processing core in sequence, including: the read master core receives multiple read messages returned from the flash memory controller, assembles the valid data included in the multiple read messages into a memory format required by the write processing core, and forwards them to the write processing core according to the memory format.

[0050] The memory format may be a wordline (WL) format. For example, a storage unit on a wordline may be organized into three independent pages.

[0051] S202: If the value of the first variable is the first value at the first moment, generate and send a read request message to at least one read standby core.

[0052] The request read message is used to instruct at least one read standby core to start and assist the read main core in performing read and write operations on the source data block and the target data block. The request read message carries N multi-plane addresses. The N multi-plane addresses are read addresses assigned by the read main core to at least one read standby core.

[0053] The selection of N is related to the allocation method of GC read buff. If the GC read buff is managed by the main read core, N should be as small as possible (for example, N is 2); if the GC read buff is managed by the NFC or spare core, N can be larger (for example, N is 10).

[0054] In one example, the second variable value and the third variable value are pre-stored in the hard disk cache.

[0055] The second variable value is also called the gc_rd_high_press_cnt variable. The second variable value is used to indicate the number of times the detected message concurrency being processed by the read master core is greater than or equal to the first threshold.

[0056] The third variable value is also called the gc_rd_low_press_cnt variable. The third variable value is used to indicate the number of times the detected message concurrency being processed by the read master core is less than the third threshold.

[0057] The third threshold is smaller than the first threshold. The selection of the first threshold and the third threshold is associated with the division of data blocks in the hard disk. If each data block in the hard disk contains N physical luns, the first threshold is 1.5 times the maximum concurrency, that is, N×1.5; the third threshold is one third of the first threshold.

[0058] For example, if each data block in the hard disk contains 128 physical luns, the first threshold is 192; the third threshold is 64.

[0059] In some optional embodiments, the read master core obtains a second variable value during the read and write operations on the source data block and the target data block; if the second variable value is less than a second threshold, detects a first number of read commands that have been sent and read information returned by the flash memory controller that has not been received, and detects a second number of read messages that have not been sent to the write processing core; if it is detected that the message concurrency is greater than or equal to the first threshold, the second variable value is increased by one; if it is detected that the message concurrency is less than the first threshold, the second variable value is cleared to zero.

[0060] The sum of the first number and the second number is the concurrent message volume.

[0061] Exemplarily, during the reading and writing operations on the source data block and the target data block, the read master core periodically obtains the second variable value at a preset interval; if the second variable value is less than the second threshold, the message concurrency is detected, and if it is detected that the message concurrency is less than the first threshold, the second variable value is cleared.

[0062] The preset interval may be set according to actual needs. For example, the preset interval may be the interval at which the read master core sends 10 read commands.

[0063] In some optional implementations, if the second variable value obtained by reading the main core is greater than or equal to the second threshold, the first variable value is set to the first value.

[0064] The second threshold value can be set according to actual needs and is not limited. For example, the second threshold value is 10.

[0065] It can be understood that if the second variable value obtained by the read main core (indicating that the message concurrency is greater than 192 times) is greater than or equal to the second threshold (indicating that it has been detected 10 times in a row), it can be determined that the read main core is continuously in a high load state, and the first variable value corresponding to the load of the read main core can be set to the first value.

[0066] In some optional embodiments, if at least one read standby core receives a request read message sent by a read main core, and based on the N multi-plane addresses carried by the request read message, reads valid data on N multi-plane addresses in the source data block, the read main core obtains the first variable value again at a third moment; if the first variable value at the third moment is the first numerical value, a second request read message is generated and sent to at least one read standby core.

[0067] The second request read message is used to instruct at least one read standby core to continue to assist the read main core in performing read and write operations on the source data block and the target data block. The second request read message carries M multi-plane addresses other than the N multi-plane addresses. The M multi-plane addresses are read addresses that the read main core reassigns to at least one read standby core.

[0068] It can be understood that when the first variable value obtained at the third moment is the first numerical value, it means that the read main core is still in a high-load state. At this time, at least one read standby core has executed the read and write operations corresponding to the read address allocated to the read main core at the first moment. Therefore, it is necessary to resend a second request read message to instruct at least one read standby core to continue to assist the read main core in performing read and write operations on the source data block and the target data block, thereby improving the data reading rate.

[0069] In some optional embodiments, during the read and write operations on the source data block and the target data block, the read main core obtains the first variable value from the hard disk cache at a second moment; if the first variable value is a second value at the second moment, a stop reading message is sent to at least one read standby core.

[0070] The stop reading message is used to instruct at least one read standby core to stop. The second moment is after the first moment.

[0071] It is understandable that after receiving the stop read message, at least one read standby core no longer issues a read command to the flash controller, but still needs to read the valid data from the source data block and return it to the write processing core. During the process of at least one read standby core returning valid data to the write processing core, at least one read standby core needs to put the valid data into the memory format required by the write processing core and return it to the write processing core. If the last valid data returned to the write processing core cannot be put into the memory format, at least one read standby core needs to supplement the "dummy" data to put it into the memory format and return it to the write processing core.

[0072] In some optional embodiments, the read master core obtains the value of a third variable during the read and write operations on the source data block and the target data block; if the value of the third variable is less than the second threshold, the message concurrency is detected; if the message concurrency is detected to be less than the third threshold, the third variable value is increased by one; if the message concurrency is detected to be greater than or equal to the third threshold, the third variable value is cleared.

[0073] Exemplarily, during the read and write operations on the source data block and the target data block, the read master core periodically obtains the value of the third variable at a preset interval; if the value of the third variable is less than the second threshold, the message concurrency is detected; if the message concurrency is detected to be less than the third threshold, the third variable value is increased by one; if the message concurrency is detected to be greater than or equal to the third threshold, the third variable value is cleared.

[0074] In some optional implementations, if the third variable value obtained by reading the main core is greater than or equal to the second threshold, the first variable value is set to the second value.

[0075] It can be understood that if the second variable value obtained by the read main core (indicating that the message concurrency is less than 64 times) is greater than or equal to the second threshold (indicating that it has been detected 10 times in a row), it can be determined that the read main core is continuously in a low load state, and the first variable value corresponding to the load of the read main core can be set to the second value.

[0076] It can be understood that when the read master has initiated GC reads for all flash memory locations of valid data in the source data block and all GC read messages are completed, it is considered that this GC is completed and a new GC process can be initiated for the next selected source data block.

[0077] Based on the above Figure 2 According to the method, during the read and write operations on the source data block and the target data block, the read main core can obtain the first variable value from the hard disk cache at a first moment, and if the first variable value at the first moment is a first value, a request read message is generated and sent to at least one read standby core to instruct the at least one read standby core to start and assist the read main core in performing the read and write operations on the source data block and the target data block.

[0078] Since the value of the first variable is the first value at the first moment, it means that the main read core is in an overloaded state at the first moment. At this time, a request read message is generated and sent to at least one read standby core to start at least one read standby core to assist the main read core in performing read and write operations on the source data block and the target data block. That is, when the main read core performs data processing or the data read and write operation load is large, at least one read standby core is used to share the load of the main read core performing data processing, so as to achieve the goal of load balancing, avoid the problem of slow data reading speed caused by the read processing core being occupied by other services or insufficient performance during the hard disk garbage collection process, and improve the overall performance of hard disk garbage collection.

[0079] In this embodiment, another data processing method is provided. Figure 3 is a flow chart of another data processing method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0080] When the number of free blocks in the hard disk is lower than the GC water level (i.e., the preset threshold), the read master core sends a GC read (i.e., a read command) to the NFC; the NFC returns a GC read completion (i.e., a read message) to the read master core. The read master core reads valid data to fill a WL data and initiates a GC write.

[0081] When the main read core detects that gc_multi_flag=0 and the number of concurrent messages is greater than or equal to 192 for 10 consecutive times, it sends a request for GC read message to at least one read standby core; at least one read standby core sends GC read to NFC; NFC returns the completion of multiple GC reads to at least one read standby core.

[0082] After at least one read standby core completes the request read message, it returns a request GC read completion message to the read main core. At least one read standby core reads valid data to fill a WL data and initiates GC write.

[0083] When the main read core detects that gc_multi_flag=1 and the number of concurrent messages is less than or equal to 64 for 10 consecutive times, it sends a GC read stop request message to at least one read standby core. After at least one read standby core adds dummy data to the last read data, it completes a WL data and initiates GC write.

[0084] In this embodiment, a processor is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0085] This embodiment provides a processor, such as Figure 4 As shown, Figure 4 is a structural block diagram of a processor according to an embodiment of the present invention; the processor and at least one read spare core belong to a hard disk controller; the processor includes:

[0086] The acquisition module 401 is used to acquire a first variable value from the hard disk cache at a first moment during the reading and writing operations on the source data block and the target data block, and the first variable value is used to measure the load of the processor at the first moment.

[0087] Processing module 402 is used to generate and send a request read message to at least one read standby core if the value of the first variable is a first numerical value at a first moment. The request read message is used to indicate that at least one read standby core is started and assists the processor in performing read and write operations on the source data block and the target data block. The first numerical value is used to indicate that the read main core is in an overloaded state.

[0088] In some optional embodiments, the acquisition module 401 is used to obtain the first variable value from the hard disk cache at a second moment during the read and write operations on the source data block and the target data block, and the second moment is after the first moment; the processing module 402 is used to send a stop reading message to at least one read standby core if the first variable value is a second numerical value at the second moment, the stop reading message is used to indicate that at least one read standby core stops, and the second numerical value is used to indicate that the processor is in a low load state.

[0089] In some optional embodiments, the hard disk controller also includes a write processing core; a processing module 402 is specifically used to send multiple read commands to the flash memory controller in sequence, each read command is used to instruct the flash memory controller to read valid data of at least one address in the source data block, and based on the valid data, generate and return a read information to the processor; receive multiple read information returned from the flash memory controller in sequence, and send the multiple read information to the write processing core in sequence, so that the write processing core writes the valid data into the target data block.

[0090] In some optional implementations, a second variable value is pre-stored in the hard disk cache, and the second variable value is used to indicate the number of times the detected message concurrency being processed by the processor is greater than or equal to the first threshold; the acquisition module 401 is also used to acquire the second variable value during the read and write operations on the source data block and the target data block. The processing module 402 is also used to detect the first number of read commands that have been sent and the read information returned by the flash memory controller that has not been received, and the second number of read messages that have not been sent to the write processing core, if the second variable value is less than the second threshold, the sum of the first number and the second number is the message concurrency; if it is detected that the message concurrency is greater than or equal to the first threshold, the second variable value is increased by one; if it is detected that the message concurrency is less than the first threshold, the second variable value is cleared.

[0091] In some optional implementations, the processing module 402 is further configured to set the first variable value to a first value if the acquired second variable value is greater than or equal to a second threshold value.

[0092] In some optional implementations, a third variable value is pre-stored in the hard disk cache, and the third variable value is used to indicate the number of times the detected message concurrency being processed by the processor is less than the third threshold; the third threshold is less than the first threshold; the acquisition module 401 is also used to acquire the third variable value during the read and write operations on the source data block and the target data block. The processing module 402 is also used to detect the message concurrency if the third variable value is less than the second threshold; if the message concurrency is detected to be less than the third threshold, the third variable value is increased by one; if the message concurrency is detected to be greater than or equal to the third threshold, the third variable value is cleared.

[0093] In some optional implementations, the processing module 402 is further configured to set the first variable value to a second value if the acquired third variable value is greater than or equal to a second threshold value.

[0094] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0095] The processor in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0096] The embodiment of the present invention also provides a computer device having the above Figure 4 Processor shown.

[0097] See also Figure 5 , is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: a multi-core processor 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be installed on a common motherboard or in other ways as needed.

[0098] The multi-core processor 10 can process instructions executed within the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, the multi-core processor 10 and / or multiple buses can be used with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, each device providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0099] The multi-core processor 10 includes multiple cores or multiple processing modules, such as Figure 1 The number of control cores, read main cores, write processing cores, read standby cores, etc. shown in the figure can be set according to actual needs, and this embodiment does not impose any limitation on this.

[0100] In addition, the multi-core processor 10 may also include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0101] The memory 20 stores instructions executable by the multi-core processor 10 so that the multi-core processor 10 executes the method shown in the above embodiment.

[0102] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the multi-core processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0103] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0104] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0105] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0106] Part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0107] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A data processing method, characterized in that: The method is applied to a read main core of a hard disk controller, wherein the hard disk controller further comprises at least one read standby core; the method comprises: In the process of reading and writing the source data block and the target data block, a first variable value is obtained from the hard disk cache at a first moment, and the first variable value is used to measure the load of the read main core at the first moment; If the value of the first variable is a first numerical value at the first moment, a request read message is generated and sent to the at least one read standby core, wherein the request read message is used to instruct the at least one read standby core to start and assist the read main core in performing the read and write operations on the source data block and the target data block, and the first numerical value is used to indicate that the read main core is in an overloaded state.

2. The method according to claim 1, characterized in that The method further comprises: In the process of performing the read and write operations on the source data block and the target data block, obtaining the first variable value from the hard disk cache at a second moment, the second moment being after the first moment; If the first variable value is a second value at the second moment, a stop reading message is sent to the at least one read standby core, the stop reading message is used to instruct the at least one read standby core to stop, and the second value is used to indicate that the read main core is in a low load state.

3. The method according to claim 2, characterized in that The hard disk controller further includes a write processing core; the reading and writing operations on the source data block and the target data block include: Sending multiple read commands to the flash memory controller in sequence, each of the read commands is used to instruct the flash memory controller to read valid data of at least one address in the source data block, and based on the valid data, generate and return a piece of read information to the read master core; A plurality of pieces of read information returned from the flash memory controller are received in sequence, and the plurality of pieces of read information are sent in sequence to the write processing core, so that the write processing core writes the valid data into the target data block.

4. The method according to claim 3, characterized in that A second variable value is pre-stored in the hard disk cache, and the second variable value is used to indicate the number of times that the detected message concurrency being processed by the read master core is greater than or equal to a first threshold; The method further comprises: In the process of performing the read and write operations on the source data block and the target data block, obtaining the second variable value; If the second variable value is less than a second threshold, detecting a first number of the read commands that have been sent and the read information that has not been received back by the flash memory controller, and detecting a second number of the read messages that have not been sent to the write processing core, wherein the sum of the first number and the second number is the message concurrency; If it is detected that the concurrent message volume is greater than or equal to the first threshold, the second variable value is increased by one; If it is detected that the concurrent message volume is less than the first threshold, the second variable value is cleared.

5. The method according to claim 4, characterized in that The method further comprises: If the acquired second variable value is greater than or equal to the second threshold, the first variable value is set to the first value.

6. The method according to claim 5, characterized in that A third variable value is pre-stored in the hard disk cache, and the third variable value is used to indicate the number of times that the detected message concurrency being processed by the read main core is less than a third threshold; The third threshold is less than the first threshold; The method further comprises: In the process of performing the read and write operations on the source data block and the target data block, obtaining the third variable value; If the third variable value is less than the second threshold, detecting the concurrent message volume; If it is detected that the concurrent message volume is less than the third threshold, the third variable value is increased by one; If it is detected that the message concurrency is greater than or equal to the third threshold, the third variable value is cleared.

7. The method according to claim 6, characterized in that The method further comprises: If the obtained third variable value is greater than or equal to the second threshold, the first variable value is set to the second value.

8. A processor, characterized in that: The processor and at least one read spare core belong to a hard disk controller; the processor includes: An acquisition module, used for acquiring a first variable value from a hard disk cache at a first moment in a process of performing a read and write operation on a source data block and a target data block, wherein the first variable value is used to measure the load of the processor at the first moment; A processing module, used for generating and sending a request read message to the at least one read standby core if the value of the first variable is a first numerical value at the first moment, wherein the request read message is used to instruct the at least one read standby core to start and assist the processor in performing the read and write operations on the source data block and the target data block, and the first numerical value is used to indicate that the processor is in an overloaded state.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the data processing method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the data processing method according to any one of claims 1 to 7.

Images