Polynomial calculation method and device

Abstract

The embodiment of the invention provides a polynomial calculation method and device, and the method comprises the steps: obtaining a plurality of to-be-calculated polynomials in a polynomial calculation application, dividing the plurality of to-be-calculated polynomials, obtaining a plurality of to-be-calculated groups, and enabling the plurality of to-be-calculated groups to comprise a first to-be-calculated group and a second to-be-calculated group; loading a common variable corresponding to at least one to-be-calculated polynomial in the first to-be-calculated group to at least one first register group, loading a variable coefficient to at least one second register group, and loading a reference variable to at least one third register group, and controlling common variables in the at least one first register group and variable coefficients in the at least one second register group to perform outer product calculation to obtain a first result, and controlling the first result and reference variables in the at least one third register group to perform inner product calculation to obtain a second result. By means of the method, polynomial calculation can be converted into matrix calculation between the register blocks, and the calculation speed is increased.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a polynomial calculation method and device. Background Art

[0002] In mathematics, a polynomial is composed of the sum / difference of multiple monomials, where each monomial is an expression obtained by variables, variable coefficients, and multiplication and exponentiation operations (non-negative integer powers) between them. At present, when calculating polynomials, the result of each monomial is generally calculated first, and then the result of the polynomial is obtained based on the sum / difference of multiple monomials. In the case of a large number of polynomials to be calculated, the above calculation method will cause huge time overhead. How to improve the calculation speed of polynomials is a problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a polynomial calculation method and device for improving the calculation speed of polynomials.

[0004] In a first aspect, the present application provides a polynomial calculation method, which can be executed by a device with a data processing function (such as a computing device) or by a component in the device (such as a processor). Taking a computing device as an example, in this method, a plurality of polynomials to be calculated in a polynomial calculation application are obtained, the plurality of polynomials to be calculated are divided to obtain a plurality of groups to be calculated, each group to be calculated includes at least one polynomial to be calculated, the variable coefficients of at least one polynomial to be calculated in each group to be calculated are the same, the plurality of groups to be calculated include a first group to be calculated, the first group to be calculated is any one of the plurality of groups to be calculated, and the common variables and variable coefficients corresponding to at least one polynomial to be calculated in the first group to be calculated are determined. and reference variables, loading the common variables corresponding to at least one polynomial to be calculated into at least one first register group, loading the variable coefficients corresponding to at least one polynomial to be calculated into at least one second register group, loading the reference variables corresponding to at least one polynomial to be calculated into at least one third register group, controlling the common variables in at least one first register group and the variable coefficients in at least one second register group to perform outer product calculations to obtain the first results corresponding to at least one polynomial to be calculated, controlling the first results corresponding to at least one polynomial to be calculated and the reference variables in at least one third register group to perform inner product calculations to obtain the second results corresponding to at least one polynomial to be calculated. When calculating a large number of polynomials, the above method can be used to convert the polynomial loop calculation into matrix calculations between register groups, thereby improving the calculation speed.

[0005] In one possible design, determining the common variables, variable coefficients, and reference variables corresponding to at least one polynomial to be calculated in the first group to be calculated may include: for a first polynomial in at least one polynomial to be calculated, the first polynomial is any polynomial in the at least one polynomial to be calculated, performing the following steps: extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, wherein the M N-order polynomials correspond one-to-one to the M reference variables, each N-order polynomial includes N common variables and N variable coefficients, the N common variables correspond one-to-one to the N variable coefficients, the N common variables respectively included in the M N-order polynomials are the same, M is a positive integer, N is an integer greater than 1, and based on the M N-order polynomials, determining the N common variables and M*N variable coefficients.

[0006] In a possible design, before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the method may further include: when it is determined that the orders of the monomials included in the first polynomial are discontinuous, the first polynomial is supplemented with the monomials corresponding to the missing orders, and the variable coefficients of the monomials corresponding to the missing orders are zero. Through this design, the supplemented first polynomial can be obtained, wherein the orders of the monomials in the supplemented first polynomial are continuous, which is convenient for subsequent polynomial calculation.

[0007] In a possible design, before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the method may further include: when it is determined that the number of monomials included in the first polynomial is an odd number, supplementing the first polynomial with an odd number of monomials, wherein the coefficients of the variables of the odd number of monomials are all zero. With this design, a supplemented first polynomial may be obtained, wherein the order of the monomials in the supplemented first polynomial is continuous and the number of monomials is an even number, which facilitates subsequent polynomial calculations.

[0008] In a possible design, extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial may include: first taking each N-order adjacent monomial in the first polynomial as a second polynomial to obtain M second polynomials, and then determining the ratio of the k-th variable included in each second polynomial in the M second polynomials to the k-th variable included in the second polynomial with the lowest order as the M reference variables corresponding to the M second polynomials, where k is a non-negative integer less than N, and finally determining the ratio between each second polynomial in the M second polynomials and the corresponding reference variable as the M N-order polynomials. Through this design, a method for obtaining M N-order polynomials and M reference variables is provided.

[0009] In a possible design, loading common variables corresponding to at least one polynomial to be calculated into at least one first register group, loading variable coefficients corresponding to at least one polynomial to be calculated into at least one second register group, and loading reference variables corresponding to at least one polynomial to be calculated into at least one third register group may include: for a first polynomial in at least one polynomial to be calculated, the first polynomial is any polynomial in the at least one polynomial to be calculated, performing the following steps: loading N common variables corresponding to the first polynomial into a first target register group, the first target register group is any one of the at least one first register group; loading M*N variable coefficients corresponding to the first polynomial into a second target register group, the second target register group is any one of the at least one second register group; loading M reference variables corresponding to the first polynomial into a third target register group, the third target register group is any one of the at least one third register group.

[0010] In a possible design, the first target register group includes multiple first registers, each of which includes multiple storage locations; loading N shared variables corresponding to the first polynomial into the first target register group may include: loading the i-th shared variable among the N shared variables into the j-th storage location in the b+i-th first register of the first target register group, where i is an integer ranging from [0, N-1], j is a non-negative integer, and b is a non-negative integer. Through this design, a method for loading shared variables is provided.

[0011] In a possible design, the second target register group includes multiple second registers, each second register includes multiple storage locations; loading M*N variable coefficients corresponding to the first polynomial into the second target register group may include: loading the i-th variable coefficient corresponding to the m-th N-order polynomial among M N-order polynomials into the b+m-th storage location in the b+i-th second register of the second target register group, where m is an integer that ranges from [0, M-1], i is an integer that ranges from [0, N-1], and b is a non-negative integer. Through this design, a method for loading variable coefficients is provided.

[0012] In a possible design, the third target register group includes multiple third registers, each of which includes multiple storage locations; loading M reference variables corresponding to the first polynomial into the third target register group may include: loading the mth reference variable among the M reference variables into the jth storage location in the b+mth third register of the third target register group, where m is an integer ranging from [0, M-1], b is a non-negative integer, and j is a non-negative integer. Through this design, a method for loading reference variables is provided.

[0013] In a possible design, controlling the common variables in at least one first register group and the variable coefficients in at least one second register group to perform outer product calculations to obtain first results corresponding to at least one polynomial to be calculated may include: for a first polynomial in at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, performing the following steps: controlling the common variables in the first target register group and the variable coefficients in the second target register group to perform outer product calculations to obtain a first result corresponding to the first polynomial.

[0014] In a possible design, controlling a first result corresponding to at least one polynomial to be calculated to perform inner product calculation with a reference variable in at least one third register group to obtain a second result corresponding to at least one polynomial to be calculated may include: for a first polynomial in at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, performing the following steps: controlling a first result corresponding to the first polynomial to perform inner product calculation with a reference variable in the third target register group to obtain a second result corresponding to the first polynomial.

[0015] In the second aspect, an embodiment of the present application provides a polynomial calculation device, which has the function of realizing the above-mentioned first aspect and any possible implementation method example of the first aspect. The beneficial effects can be found in the description of the first aspect and will not be repeated here. The function can be implemented by hardware, or the corresponding software can be executed by hardware. The hardware or software includes one or more modules corresponding to the above-mentioned functions. In a possible design, the structure of the device includes an acquisition module and a processing module, which can execute the function of the behavior of the calculation device in the above-mentioned first aspect and any possible implementation method example of the first aspect. Please refer to the detailed description in the method example for details, which will not be repeated here.

[0016] In a third aspect, an embodiment of the present application provides a computing device, which has the function of implementing the computing device behavior in the above-mentioned first aspect and any possible implementation method example of the first aspect. The beneficial effects can be found in the description of the first aspect and will not be repeated here. The structure of the computing device includes a processor and a memory, and the processor is configured to support the device to perform the corresponding functions of the computing device in the method example of the above-mentioned first aspect. The memory is coupled to the processor, which stores the necessary program instructions and data for the communication device. The structure of the communication device also includes a communication interface for communicating with other devices.

[0017] In a fourth aspect, the present application also provides a computer-readable storage medium, which stores instructions, and when the computer-readable storage medium is run on a computer, it enables the computer to execute the method in the above-mentioned first aspect and each possible implementation of the first aspect, or enables the computer to execute the above-mentioned first aspect and each possible implementation of the first aspect.

[0018] In a fifth aspect, the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the above-mentioned first aspect and each possible implementation manner of the first aspect, or enables the computer to execute the above-mentioned first aspect and each possible implementation manner of the first aspect.

[0019] In a sixth aspect, the present application also provides a computer chip, which is connected to a memory, and the chip is used to read and execute a software program stored in the memory, to execute the methods of the above-mentioned first aspect and various possible designs of the first aspect, or to enable a computer to execute the above-mentioned first aspect and various possible implementations of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a flow chart of a polynomial calculation method provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a flow chart of a polynomial calculation method provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of the structure of a first register group provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the structure of a first register group provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of a second register group provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of the structure of a second register group provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of the structure of a third register group provided in an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of the structure of a third register group provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of the structure of a first register group provided in an embodiment of the present application;

[0030] Fig.11 A schematic diagram of the structure of a second register group provided in an embodiment of the present application;

[0031] Fig.12 A schematic diagram of the structure of a third register group provided in an embodiment of the present application;

[0032] Fig.13 A schematic diagram of the structure of a fourth register group provided in an embodiment of the present application;

[0033] Fig.14 A schematic diagram of the structure of a fourth register group provided in an embodiment of the present application;

[0034] Fig.15 A schematic diagram of the structure of a fifth register group provided in an embodiment of the present application;

[0035] Fig.16 A schematic diagram of the structure of a fifth register group provided in an embodiment of the present application;

[0036] Fig.17 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings. The specific operation methods, functional descriptions, etc. in the method embodiments can also be applied to the device embodiments or system embodiments.

[0038] In order to better explain the embodiments of the present application, the relevant terms or technologies in the present application are first explained:

[0039] 1. Row Vector

[0040] A row vector is a 1×p matrix, where p is any positive integer, for example: x = [x1 x2…x p ].

[0041] Column vectors

[0042] A column vector is a q×1 matrix, where q is any positive integer, for example:

[0043] Matrix size / scale

[0044] A p×q matrix is ​​a rectangular array of p rows and q columns. For example:

[0045]

[0046] Each number that makes up the matrix is ​​called an element of the matrix. 11 , A 12 , …, A pq etc. are all elements of matrix A. The subscript (or coordinate) of the element is used to indicate the position of the element in the matrix, which can be the row number (or row coordinate) or column number (or column coordinate) of the element in the matrix. 11 The subscript "11" indicates that the element is located in the first row and first column of matrix A. 21 Indicates that the element is located in the second row and first column of matrix A. In addition, the subscript of the element can also have different forms, such as A 11 It can also be written as A 1，1 , A 21 It can also be written as A 2，1 Etc. Similar details will not be repeated below.

[0047] It should be noted that the row number of the starting row of a matrix is ​​not limited to 1, but can also be other values, such as 0. Similarly, the column number of the starting column of the matrix is ​​not limited to 1, but can also be other data such as 0. For example, if the row number of the starting row and the column number of the starting column of the above matrix are 0 and 0 respectively, then the subscript of the first element in the matrix is ​​"00", indicating that the element is in the 0th row and 0th column of the matrix.

[0048] 4. Matrix addition

[0049] Matrix addition refers to the addition of two matrices of the same size (or the same size, that is, the two matrices have the same number of rows and columns). As shown below, A and B are both p×q matrices, and matrix C=A+B.

[0050]

[0051]

[0052] Similarly, matrix subtraction means subtracting the elements at the same position in two matrices of the same size.

[0053] 5. Matrix multiplication

[0054] For two matrices to be multiplied (such as matrices D and E), the number of columns of D is required to be the same as the number of rows of E. For example, if D is a p×q matrix and E is a q×s matrix, their product will be a p×s matrix. For example:

[0055]

[0056]

[0057] Next, the technical solution provided in the embodiments of the present application is described in detail with reference to the accompanying drawings.

[0058] Figure 1 A schematic diagram of a computing device provided for the present application, the computing device 100 includes: a processor 101, a memory 102. Optionally, the computing device 100 may also include a communication interface 104 and a matrix operator 106, wherein the processor 101, the memory 102, the matrix operator 106 and the communication interface 104 may be interconnected via a communication line 105; the communication line 105 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication line 105 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0059] The processor 101 can be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), an artificial intelligence (AI) chip, a system on chip (SoC) or a complex programmable logic device (CPLD), a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, or one or more integrated circuits for controlling the execution of the program of the present application.

[0060] Please note, Figure 1Only one processor 101 is shown. In actual applications, there may be multiple processors 101. The multiple processors 101 may include multiple processors of the same type or multiple processors of different types. For example, the multiple processors 101 include multiple CPUs. For another example, the multiple processors 101 include at least one CPU and at least one GPU. A CPU has one or more CPU cores. This embodiment does not limit the number of processors 101, the number of CPU cores, etc.

[0061] Specifically, the processor 101 is used to process data access requests from outside the computing device 100 (such as other computing devices, etc.), and is also used to process requests generated inside the computing device 100. For example, the request is a write data request, and the write data request includes a polynomial. After receiving the write data request, the processor 101 can execute the polynomial calculation method provided in the embodiment of the present application, process the polynomial, and save the processed data in the memory 102. For another example, the request can also be a read data request, and the read data request is used to request to read polynomial data, and the polynomial data can include part or all of the polynomial. After receiving the read data request, the processor 101 reads the polynomial data from the memory 102.

[0062] In addition, the processor 101 is also used to perform other data calculations or processing, such as matrix operations, which are not specifically limited. Optionally, the above-mentioned matrix operations can also be assigned to the matrix operator 106 for execution. In some cases, when the processor 101 has multiple cores, or the computing device 100 includes multiple processors 101, or the computing device 100 includes multiple matrix operators 106, multiple cores or multiple processors 101 or multiple matrix operators 106 can perform matrix operations in parallel, which will not be emphasized here.

[0063] The matrix operator 106 can be used to process matrix operations. Please refer to the above introduction to matrix operations, which will not be repeated here. The matrix operator 106 may include but is not limited to: a vector processor (VP), a vector processor system (VPS), a matrix processor, a matrix accelerator, etc., without specific limitation.

[0064] The communication interface 104 uses any transceiver-like device to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), wired access network, etc. For example, to obtain read data request, write data request, etc.

[0065] The memory 102 is used to store data and computer executable program codes. The data includes, but is not limited to, polynomial data, etc. The executable program code may include the program code of the polynomial calculation method provided in the embodiment of the present application, and the processor 101 executes the executable program code to implement the polynomial calculation method provided in the present embodiment. That is, the memory 102 stores computer execution instructions for executing the scheme of the present application, and the execution is controlled by the processor 101. The processor 101 is used to execute the computer execution instructions stored in the memory 102, thereby implementing the polynomial calculation method provided in the above-mentioned embodiment of the present application.

[0066] The memory 102 may exist independently and be connected to the processor via the communication line 105. The memory 102 may also be integrated with the processor. Specifically, the memory 102 may include a memory and may also include a hard disk. The memory refers to an internal memory that directly exchanges data with the processor 101. It can read and write data at any time, and the speed is very fast. It serves as a temporary data storage for the operating system or other running programs. Unlike the memory, the hard disk reads and writes data slower than the memory, and is usually used to store data persistently. In some application scenarios, the processor 101 may temporarily store data in the memory. When the total amount of data in the memory reaches a certain threshold, the processor 101 sends the data stored in the memory to the hard disk for persistent storage. These data may be obtained from an external device, or input by a user, or generated by the computing device 100, and are not specifically limited. Alternatively, the processor 101 reads data from the memory. When the memory misses, the processor 101 reads the data from the hard disk into the memory, and then reads the data from the memory.

[0067] Among them, the memory includes at least two types of memories, for example, the memory can be either a random access memory or a read-only memory (ROM). For example, the random access memory is a dynamic random access memory (DRAM) or a storage class memory (SCM). The memory can also include other random access memories, such as a static random access memory (SRAM), etc. As for the read-only memory, for example, it can be a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), etc. In addition, the memory can also be a dual in-line memory module or a dual in-line memory module (DIMM), that is, a module composed of DRAM. In actual applications, multiple memories and different types of memories can be configured in the computing device 100. This embodiment does not limit the number and type of memory.

[0068] The hard disk can specifically be a disk or other types of storage media, such as a solid-state drive (solid-state drive / solid-state disk, SSD), a hard disk drive (hard disk drive, HDD), a compact disc read-only memory (compact disc read-only memory, CD-ROM) or other optical disk storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0069] It should be noted that Figure 1 The structure of the computing device 100 shown is only an example. In actual applications, the computing device 100 may have more or fewer components. For example, the computing device 100 may also include input / output devices such as a keyboard, a mouse, and a display screen. This embodiment of the present application does not limit this.

[0070] Next, apply to Figure 1 Taking the computing device shown as an example, the polynomial calculation method provided in the embodiment of the present application is introduced in detail.

[0071] Figure 21 is a flow chart corresponding to the polynomial calculation method provided in the embodiment of the present application. The method can be executed by a computing device (such as computing device 100) with data processing capabilities, or a component of the computing device, such as processor 101 or matrix operator 106. For ease of description, the following is an introduction using computing device 100 as an example. Figure 2 As shown, the method includes:

[0072] S201, obtaining a plurality of polynomials to be calculated in a polynomial calculation application.

[0073] In an embodiment of the present application, the polynomial to be calculated includes a basic variable. The polynomial to be calculated includes at least two monomials. The basic variables included in each monomial in the polynomial to be calculated are the same. The polynomial to be calculated can be composed of the sum / difference of at least two monomials, wherein each monomial is an expression obtained by the basic variable, the variable coefficient, and the multiplication and exponentiation operations (non-negative integer powers) between them.

[0074] For example, the polynomial to be calculated is a1x 1 +a2x 2 +a4x 4 , where a1x 1 、a2x 2 and a4x 4 All are monomials, a1, a2 and a4 are variable coefficients, and x is the basic variable. a1, a2, a4 and x can be any known values.

[0075] For the convenience of the following description, when the polynomial to be calculated is composed of the sum / difference of at least two monomials, the polynomial to be calculated can be adjusted so that the adjusted polynomial to be calculated is composed of the sum of at least two monomials. The adjusted polynomial to be calculated is convenient for subsequent polynomial calculation. For example, the polynomial to be calculated is 2x 1 +3x 2 -4x 3 , the polynomial to be calculated can be adjusted, and the adjusted polynomial to be calculated is 2x 1 +3x 2 +(-4x 3 ).

[0076] S202, dividing a plurality of polynomials to be calculated to obtain a plurality of groups to be calculated.

[0077] In the embodiment of the present application, the polynomials to be calculated with the same variable coefficients can be divided into a group to be calculated. Each group to be calculated includes at least one polynomial to be calculated, and at least one polynomial to be calculated in each group to be calculated has the same variable coefficient.

[0078] The multiple groups to be calculated include a first group to be calculated, wherein the first group to be calculated is any group to be calculated among the multiple groups to be calculated, and the following description is taken with the first group to be calculated as an example.

[0079] S203, determining the common variables, the variable coefficients and the reference variables respectively corresponding to at least one polynomial to be calculated in the first to-be-calculated group.

[0080] In an embodiment of the present application, at least one polynomial to be calculated includes a first polynomial, wherein the first polynomial is any polynomial in the at least one polynomial to be calculated, and the first polynomial is used as an example for description below.

[0081] Before determining the common variables, variable coefficients and reference variables corresponding to the first polynomial, it can be determined whether the orders of the monomials included in the first polynomial are continuous. If it is determined that the orders of the monomials included in the first polynomial are discontinuous, the first polynomial is supplemented with the monomials corresponding to the missing orders, and the variable coefficients of the monomials corresponding to the missing orders are zero. It is then determined whether the number of monomials included in the first polynomial is an odd number. If it is determined that the number of monomials included in the first polynomial is an odd number, the first polynomial is supplemented with an odd number of monomials, and the variable coefficients of the odd number of monomials are all zero. After supplementing the odd number of monomials in the first polynomial, the orders of the monomials included in the supplemented first polynomial are still continuous. In the above manner, the supplemented first polynomial can be obtained, wherein the orders of the monomials in the supplemented first polynomial are continuous and the number of monomials is an even number, which is convenient for subsequent polynomial calculation.

[0082] It should be understood that in order to improve the speed of subsequent polynomial calculations, when it is determined that the number of monomials included in the first polynomial is an odd number, a monomial is added to the first polynomial, and the variable coefficient of the added monomial is 0. For the convenience of subsequent discussion, the following description is given by taking the addition of a monomial to the first polynomial as an example.

[0083] For example, if the first polynomial obtained is a1x 1 +a3x 3 , the orders of the two monomials included in the first polynomial are 1 and 3 respectively, so the orders of the above two monomials are not continuous, and the second-order monomial is missing. Therefore, the second-order monomial is used to supplement the first polynomial, and the first polynomial is updated to a1x 1 +a2x 2 +a3x 3 , where a2 is 0.

[0084] The first polynomial a1x 1 +a2x 2 +a3x 3There are 3 monomials in it, and the number of monomials is odd. We can add a1x 1 +a2x 2 +a3x 3 In one case, we can add a1x 1 +a2x 2 +a3x 3 Supplement a0x 0 , the first polynomial is updated to a0x 0 +a1x 1 +a2x 2 +a3x 3 , where a0 is 0. In another case, a1x 1 +a2x 2 +a3x 3 Supplement a4x 4 , the first polynomial is updated to a1x 1 +a2x 2 +a3x 3 +a4x 4 , where a4 is 0.

[0085] When it is determined that the order of the monomials in the first polynomial is continuous and the number of monomials is an even number, the following steps are performed: first, M N-order polynomials and M reference variables corresponding to the M N-order polynomials are extracted from the first polynomial, and then based on the M N-order polynomials, N common variables and M*N variable coefficients are determined, where M is a positive integer and N is an integer greater than 1.

[0086] In the embodiment of the present application, M N-order polynomials and M reference variables corresponding to the M N-order polynomials can be extracted from the first polynomial by the following possible implementations, including: Figure 3 The following steps are shown:

[0087] S301, taking every N adjacent monomials of the first polynomial as a second polynomial, to obtain M second polynomials.

[0088] In the embodiment of the present application, the number of monomials in the first polynomial is N*M, where N can be an integer greater than 1 and is less than the number of monomials in the first polynomial, M is a positive integer, and * represents multiplication, which will not be described in detail below. For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6, set N to 3, based on the above first polynomial, we can get two second polynomials, each of which includes three adjacent monomials of the same order, namely a1x 1 +a2x 2 +a3x 3 , a4x 4 +a5x 5 +a6x 6 .

[0089] In the embodiment of the present application, when the first polynomial is determined, when the value of N is different, the number of second polynomials M obtained is also different. The value of N can be determined by the following two possible implementations.

[0090] In a first possible implementation, a value is randomly selected from the possible values ​​corresponding to N as the value of N.

[0091] For example, if N can take the values ​​2 and 3, then 2 is randomly selected as the value of N.

[0092] In a second possible implementation, the division results corresponding to the possible values ​​of N are determined respectively, wherein the division results include M second polynomials, and when determining the execution times corresponding to different division results, the value corresponding to the division result with the smallest execution time is selected as the value of N. The execution time corresponding to the division result includes the execution time required to obtain the results corresponding to the M second polynomials respectively, and the execution time required to obtain the sum of the M second polynomials.

[0093] Among the M second polynomials, the result of each second polynomial is obtained by inner product calculation, so the execution time required to obtain the result of each second polynomial is the time corresponding to the inner product calculation. The sum of the M second polynomials requires M-1 accumulations, so the execution time required to obtain the sum of the M second polynomials is the time corresponding to the M-1 accumulation calculations. Specifically, the execution time to obtain the sum of the M second polynomials is equal to (M-1)*the time corresponding to the accumulation calculation.

[0094] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 , the number of monomials in the first polynomial is 6, and the value of N can be 2 or 3. The duration corresponding to the first inner product calculation is set to t1, the first inner product calculation can be understood as the inner product calculation of two 2×2 matrices, the duration corresponding to the second inner product calculation is t2, the second inner product calculation can be understood as the inner product calculation of two 3×3 matrices, and the duration corresponding to the cumulative calculation is t3.

[0095] When the value of N is 2, the first polynomial is divided to obtain a first division result, which includes three second polynomials, namely, a1x 1 +a2x 2 , a3x 3 +a4x 4 , a5x 5 +a6x 6 The result of each second polynomial is obtained by inner product calculation, so the execution time required to obtain the result of each second polynomial is t1, and the execution time required to obtain the results of the above three second polynomials is 3*t1. The sum of the three second polynomials requires two accumulation calculations, so the execution time to obtain the sum of the three second polynomials is 2*t3. Therefore, the execution time corresponding to the first partition result is equal to 3*t1+2*t3.

[0096] When N is 3, the first polynomial is divided to obtain a second division result, which includes two second polynomials, namely a1x 1 +a2x 2 +a3x 3 and a4x 4 +a5x 5 +a6x 6 The result of each second polynomial is obtained by inner product calculation, so the execution time required to obtain the result of each second polynomial is t2, and the execution time required to obtain the results of the above two second polynomials is 2*t2. The sum of the two second polynomials requires one accumulation, so the execution time to obtain the sum of the two second polynomials is t3. Therefore, the execution time corresponding to the second partition result is equal to 2*t2+t3.

[0097] The execution time corresponding to the first division result is 3*t1+2*t3, and the execution time corresponding to the second division result is 2*t2+t3. Based on the comparison of the above two execution times, if 3*t1+2*t3 is less than 2*t2+t3, then the value of N is 2; if 3*t1+2*t3 is greater than 2*t2+t3, then the value of N is 3; if 3*t1+2*t3 is equal to 2*t2+t3, then the value of N can be either 2 or 3.

[0098] S302, determining the ratio of the kth variable included in each of the M second polynomials to the kth variable included in the second polynomial with the lowest order as M reference variables corresponding to the M second polynomials; k is a non-negative integer less than N.

[0099] S303: Determine the ratio between each second polynomial in the M second polynomials and the corresponding reference variable as M N-order polynomials.

[0100] In the embodiment of the present application, based on Figure 3 From the steps in , it can be seen that the first polynomial can be decomposed into M N-order polynomials and M reference variables, where the M N-order polynomials correspond to the M reference variables one by one.

[0101] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 , the number of monomials in the first polynomial is 6, set N to 2, and obtain 3 second polynomials from the first polynomial, namely a1x 1 +a2x 2 , a3x 3 +a4x 4 , a5x 5 +a6x 6 Each second polynomial includes two variables, the 0th variable and the 1st variable, that is, the value of k is 0 or 1. Among them, the second polynomial with the lowest order is a1x 1 +a2x 2 .

[0102] In the embodiment of the present application, the value of k is 0 or 1. The following explanation is based on the value of k being 0. For the 0th second polynomial a1x 1 +a2x 2 , the 0th variable in the second polynomial is x 1 , the second lowest polynomial a1x 1 +a2x 2 The 0th variable in the 1 , then the reference variable corresponding to the 0th second polynomial is x 1 / x 1 = 1. The 0th second polynomial a1x 1 +a2x 2 The ratio a1x to the corresponding reference variable 1 1 +a2x 2 , as the 0th 2nd order polynomial.

[0103] For the first second polynomial a3x 3 +a4x 4 , the 0th variable x in the second polynomial 3 , the second lowest polynomial a1x 1 +a2x 2 The 0th variable in the 1 , then the reference variable corresponding to the first second polynomial is x 3 / x1 =x 2 . Substitute the first second polynomial a3x 3 +a4x 4 The corresponding reference variable x 2 The ratio between a3x 1 +a4x 2 , as the first 2nd order polynomial.

[0104] For the second second polynomial a5x 5 +a6x 6 , the 0th variable x in the second polynomial 5 , the second lowest polynomial a1x 1 +a2x 2 The 0th variable in the 1 , then the reference variable corresponding to the second second polynomial is x 5 / x 1 =x 4 . Substitute the second polynomial a5x 5 +a6x 6 The corresponding reference variable x 4 The ratio between a5x 1 +a6x 2 , as the second 2nd order polynomial.

[0105] In summary, from the first polynomial a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 The three second-order polynomials extracted are a1x 1 +a2x 2 , a3x 1 +a4x 2 , a5x 1 +a6x 2 , the three reference variables corresponding to the three second-order polynomials are 1, x 2 and x 4 So the first polynomial a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 It can be broken down into the following structure.

[0106] a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x5 +a6x 6

[0107] =1*(a1x 1 +a2x 2 )+x 2 *(a3x 1 +a4x 2 )+x 4 *(a5x 1 +a6x 2 )

[0108] In the embodiment of the present application, each N-order polynomial includes N common variables and N variable coefficients, the N common variables correspond to the N variable coefficients one-to-one, and the N common variables included in the M N-order polynomials are the same.

[0109] Based on the above example, each 2nd order polynomial includes 2 common variables x 1 and x 2 , the 0th 2nd order polynomial includes 2 common variables x 1 and x 2 , the coefficients of the two common variables are a1 and a2. The first 2nd order polynomial includes two common variables x 1 and x 2 , the coefficients of the two common variables are a3 and a4. The second 2nd order polynomial includes the common variable x 1 and x 2 , the variable coefficients corresponding to the two common variables are a5 and a6 respectively.

[0110] S204, loading the common variables corresponding to the at least one polynomial to be calculated into at least one first register group, loading the variable coefficients corresponding to the at least one polynomial to be calculated into at least one second register group, and loading the reference variables corresponding to the at least one polynomial to be calculated into at least one third register group.

[0111] For a first polynomial in at least one polynomial to be calculated, perform the following steps:

[0112] N common variables corresponding to the first polynomial are loaded into a first target register group, where the first target register group is any one of at least one first register group; M*N variable coefficients corresponding to the first polynomial are loaded into a second target register group, where the second target register group is any one of at least one second register group; M reference variables corresponding to the first polynomial are loaded into a third target register group, where the third target register group is any one of at least one third register group.

[0113] In an embodiment of the present application, the first register group includes a plurality of first registers, each of which includes a plurality of storage locations. Generally speaking, the first register group includes 8 first registers. Each first register can store 512 bits (binary digit, bit) of data. It is assumed that each first register includes 8 storage locations, so each storage location in the first register can store 64 bits of data. The first register can be a scalable vector extension (SVE) register.

[0114] like Figure 4 As shown, for the convenience of the following description, each first register in the first register group may be numbered, and the eight first registers are numbered V0, V1, V2, V3, V4, V5, V6, and V7, respectively. Each storage position in each first register may also be numbered, and the eight storage positions of each first register are numbered 0, 1, 2, 3, 4, 5, 6, and 7, respectively. Each storage position in the first register group may be initialized with 0.

[0115] In a possible implementation, loading the N common variables corresponding to the first polynomial into the first target register group can be implemented by the following steps: loading the i-th common variable among the N common variables into the j-th storage position in the b+i-th first register of the first target register group, where i is an integer ranging from [0, N-1], j is a non-negative integer, and b is a non-negative integer. In the embodiment of the present application, since the first register group includes 8 first registers, each of which includes 8 storage positions, the value range of b+i is any integer in [0, 7], and the value range of j is any integer in [0, 7].

[0116] In the embodiment of the present application, the loading method of the N common variables corresponding to the first polynomial may include the following methods.

[0117] For the 0th shared variable corresponding to the first polynomial, the 0th shared variable may be loaded in the following manner. For example, the 0th shared variable may be directly obtained from the N shared variables, and the 0th shared variable may be loaded into the first target register group.

[0118] For other shared variables except the 0th shared variable corresponding to the first polynomial, other shared variables can be loaded in the following two possible ways. One possible way is to directly obtain other shared variables from the N shared variables and load them into the first target register group. Another possible way is to calculate based on the 0th shared variable in the first target register group to obtain other shared variables. For example, if the 0th shared variable is x 1 , other common variables are x2 , in x 1 After loading into the first target register group, calculation is performed in the first target register group to convert x 1 *x 1 As a common variable x 2 , and the obtained x 2 Add to the first target register set.

[0119] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 , and its corresponding three second-order polynomials are a1x 1 +a2x 2 , a3x 1 +a4x 2 and a5x 1 +a6x 2 The three reference variables corresponding to the three second-order polynomials are 1, x 2 and x 4 .

[0120] The three second-order polynomials all include two common variables x 1 and x 2 , the 0th common variable is x 1 , the first common variable is x 2 , set j = 0, b = 0, such as Figure 5 As shown, the 0th shared variable x 1 Load into the 0th storage location of the 0th (0+0=0)th first register of the first target register group, and set the first shared variable x 2 Loaded to the 0th storage position in the 1st (0+1=1)th first register of the first target register group, wherein the 0th first register is the first register V0, and the 1st first register is the first register V1.

[0121] It should be understood that the shared variables in each storage position in the b+ith first register of the first target register group should have the same corresponding variable coefficients. In the case where the variable coefficients corresponding to the shared variables are the same, the shared variables with the same variable coefficients can be loaded into different storage positions of the same first register. For example, the 0th storage position in the 0th first register of the first target register group stores the shared variable x 1 , the corresponding variable coefficient is a1, and the first storage position in the 0th first register of the first target register group stores the common variable y 1 , the corresponding variable coefficient is still a1, and the total variable x1 and 1 The corresponding variable coefficients are the same.

[0122] In an embodiment of the present application, the second register group includes a plurality of second registers, each of which includes a plurality of storage locations. Generally speaking, the second register group includes 8 second registers. Each second register can store 512 bits of data. It is assumed that each second register includes 8 storage locations, so each storage location in the second register can store 64 bits of data. The second register can be a scalable matrix extension (SME) register.

[0123] like Figure 6 As shown, for the convenience of the following description, each second register in the second register group can be numbered, and the eight second registers are numbered e0, e1, e2, e3, e4, e5, e6, and e7. Each storage position in each second register can also be numbered, and the eight storage positions in each second register are numbered 0, 1, 2, 3, 4, 5, 6, and 7. Each storage position in the second register group can be initialized with 0. In order to facilitate a more intuitive understanding of the calculation of the polynomial in the following text, each second register in the second register group adopts Figure 6 The second registers in the second register group may also be arranged in other ways, which are not limited here.

[0124] In a possible implementation, loading the M*N variable coefficients corresponding to the first polynomial into the second target register group can be achieved by the following steps: loading the i-th variable coefficient corresponding to the m-th N-order polynomial among the M N-order polynomials into the b+m-th storage position in the b+i-th second register of the second target register group, where m is an integer that ranges from [0, M-1], i is an integer that ranges from [0, N-1], and b is a non-negative integer. In the embodiment of the present application, since the second register group includes 8 second registers, each second register includes 8 storage positions, the value range of b+i is any integer in [0, 7], and the value range of b+m is any integer in [0, 7].

[0125] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 , and its corresponding three second-order polynomials are a1x 1 +a2x 2 , a3x 1 +a4x 2and a5x 1 +a6x 2 The variable coefficients corresponding to the three second-order polynomials are a1, a2, a3, a4, a5 and a6 respectively.

[0126] Set b = 0, such as Figure 7 As shown, the 0th 2nd order polynomial a1x 1 +a2x 2 The corresponding variable coefficients are a1 and a2, the 0th variable coefficient in the 0th second-order polynomial is a1, and the 1st variable coefficient is a2. When m=0, i=0, the 0th variable coefficient a1 in the 0th second-order polynomial is loaded to the 0th (0+0=0)th storage position in the 0th (0+0=0)th second register of the second target register group; when m=0, i=1, the first variable coefficient a2 in the 0th second-order polynomial is loaded to the 0th (0+0=0)th storage position in the 1st (0+1=0)th second register of the second target register group. Among them, the 0th second register is the second register e0, and the 1st second register is the second register e1.

[0127] The first 2nd order polynomial a3x 1 +a4x 2 The corresponding variable coefficients are a3 and a4, the 0th variable coefficient in the first second-order polynomial is a3, and the 1st variable coefficient is a4. When m=1 and i=0, the 0th variable coefficient a3 in the first second-order polynomial is loaded to the 1st (0+1=1) storage position in the 0th (0+0=0)th second register of the second target register group; when m=1 and i=1, the first variable coefficient a4 in the first second-order polynomial is loaded to the 1st (0+1=1) storage position in the 1st (0+1=0)th second register of the second target register group. Among them, the 0th second register is the second register e0, and the 1st second register is the second register e1.

[0128] The second 2nd order polynomial a5x 1 +a6x 2The corresponding variable coefficients are a5 and a6, the 0th variable coefficient in the second second-order polynomial is a5, and the 1st variable coefficient is a6. When m=2, i=0, the 0th variable coefficient a5 in the second second-order polynomial is loaded to the 2nd (0+2=0)th storage position in the 0th (0+0=0)th second register of the second target register group; when m=2, i=1, the first variable coefficient a6 in the second second-order polynomial is loaded to the 2nd (0+2=2)th storage position in the 1st (0+1=0)th second register of the second target register group. Among them, the 0th second register is the second register e0, and the 1st second register is the second register e1.

[0129] In an embodiment of the present application, the third register group includes a plurality of third registers, each of which includes a plurality of storage locations. Generally speaking, the third register group includes 8 third registers. Each third register can store 512 bits of data. It is assumed that each third register includes 8 storage locations, so each storage location in the third register can store 64 bits of data. The third register can be an SVE register.

[0130] like Figure 8 As shown, for the convenience of the following description, each third register in the third register group may be numbered, and the eight third registers are numbered U0, U1, U2, U3, U4, U5, U6, and U7, respectively. Each storage position in each third register may also be numbered, and the eight storage positions of each third register are numbered 0, 1, 2, 3, 4, 5, 6, and 7, respectively. Each storage position in the third register group may be initialized with 0.

[0131] In a possible implementation, loading the M reference variables corresponding to the first polynomial into the third target register group can be implemented by the following steps: loading the mth reference variable among the M reference variables into the jth storage position in the b+mth third register of the third target register group, where m is an integer ranging from [0, M-1], b is a non-negative integer, and j is a non-negative integer. In the embodiment of the present application, since the third register group includes 8 third registers, each of which includes 8 storage positions, the value range of b+m is any integer in [0, 7], and the value range of j is any integer in [0, 7].

[0132] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 , and its corresponding three second-order polynomials are a1x 1+a2x 2 , a3x 1 +a4x 2 and a5x 1 +a6x 2 The three reference variables corresponding to the three second-order polynomials are 1, x 2 and x 4 .

[0133] Set j = 0, b = 0, such as Fig. 9 As shown, when m=0, the 0th reference variable 1 is loaded into the 0th storage position in the 0th (0+0=0)th third register of the third target register group, wherein the 0th third register is the third register U0.

[0134] When m=1, the first reference variable x 2 Loaded to the 0th storage position in the 1st (0+1=1)th third register of the third target register group, wherein the 1st third register is the third register U1.

[0135] When m=2, the second reference variable x 4 Loaded to the 0th storage position in the 0th (0+2=2)th third register of the third target register group, wherein the 2nd third register is the third register U2.

[0136] In the case of obtaining multiple first polynomials, the above method can be used to determine N common variables, M*N variable coefficients, and M reference variables corresponding to each first polynomial, and the N common variables corresponding to each first polynomial are loaded into the first target register group, the M*N variable coefficients corresponding to each first polynomial are loaded into the second target register group, and the M reference variables corresponding to each first polynomial are loaded into the third target register group.

[0137] Take 24 first polynomials as an example, the 0th to 7th first polynomials are respectively

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144]

[0145]

[0146] Among them, x0, x1, x2, x3, x4, x5, x6 and x7 are basic variables with different values.

[0147] Taking the 0th first polynomial as an example, the 0th first polynomial can be expressed as follows:

[0148]

[0149] The 0th first polynomial includes three 2nd order polynomials, and the three reference variables corresponding to the three 2nd order polynomials are 1, and The common variables included in the three second-order polynomials are and The three second-order polynomials include variable coefficients a1, a2, a3, a4, a5 and a6.

[0150] The method of obtaining the reference variables, common variables and variable coefficients of the 1st to 7th first polynomials is similar to the method of obtaining the reference variables, common variables and variable coefficients of the 0th first polynomial, and will not be repeated here.

[0151] The 8th to 15th first polynomials are

[0152]

[0153]

[0154]

[0155]

[0156]

[0157]

[0158]

[0159]

[0160] Among them, y0, y1, y2, y3, y4, y5, y6 and y7 are basic variables with different values.

[0161] Taking the 8th first polynomial as an example, the 8th first polynomial can be expressed as follows:

[0162]

[0163] The 8th first polynomial includes two 2nd-order polynomials, and the two reference variables corresponding to the two 2nd-order polynomials are 1 and The common variables included in the two second-order polynomials are and The two 2nd order polynomials include variable coefficients b1, b2, b3 and b4.

[0164] The method of obtaining the reference variables, common variables and variable coefficients of the 9th to 15th first polynomials is similar to the method of obtaining the reference variables, common variables and variable coefficients of the 8th first polynomial, and will not be repeated here.

[0165] The 16th to 23rd first polynomials are

[0166]

[0167]

[0168]

[0169]

[0170]

[0171]

[0172]

[0173]

[0174] Among them, z0, z1, z2, z3, z4, z5, z6 and z7 are basic variables with different values.

[0175] Taking the 16th first polynomial as an example, the 16th first polynomial can be expressed as follows:

[0176]

[0177] The 16th first polynomial includes two third-order polynomials, and the two reference variables corresponding to the two third-order polynomials are 1 and The common variables included in the two third-order polynomials are and The two third-order polynomials include variable coefficients c1, c2, c3, c4, c5 and c6.

[0178] like Fig.10 As shown, the common variables corresponding to the above 24 first polynomials are added to the first target register group, such as Fig.11As shown, the variable coefficients corresponding to the above 24 first polynomials are loaded into the second target register group, such as Fig.12 As shown, the reference variables corresponding to the above 24 first polynomials are loaded into the third target register group.

[0179] S205: Control the common variables in at least one first register group to perform outer product calculations with the coefficients of the variables in at least one second register group to obtain first results respectively corresponding to at least one polynomial to be calculated.

[0180] For a first polynomial in at least one polynomial to be calculated, the common variables in the first target register group and the coefficients of the variables in the second target register group are controlled to perform outer product calculation to obtain a first result corresponding to the first polynomial.

[0181] In an embodiment of the present application, the first result corresponding to the first polynomial can be stored in a fourth target register group. The fourth target register group includes a plurality of fourth registers, each of which includes a plurality of storage locations. Generally speaking, the fourth register group includes 8 fourth registers. Each fourth register can store 512 bits of data. It is assumed that each fourth register includes 8 storage locations, so each storage location in the fourth register can store 64 bits of data. The fourth register can be an SVE register.

[0182] like Fig.13 As shown, for the convenience of the following description, each fourth register in the fourth register group may be numbered, and the eight fourth registers are numbered W0, W1, W2, W3, W4, W5, W6, and W7, respectively. Each storage position in each fourth register may also be numbered, and the eight storage positions of each fourth register are numbered 0, 1, 2, 3, 4, 5, 6, and 7, respectively. Each storage position in the fourth register group may be initialized with 0.

[0183] Specifically, the mth first result among the M first results corresponding to the first polynomial can be loaded into the jth storage position in the b+mth fourth target register, where m is an integer ranging from [0, M-1], b is a non-negative integer, and j is a non-negative integer. In the embodiment of the present application, since the fourth register group includes 8 fourth registers, each of which includes 8 storage positions, the value range of b+m is any integer in [0, 7], and the value range of j is any integer in [0, 7].

[0184] In a possible implementation, an outer product is calculated between the b-th storage position of each first register in the first target register group and the q-th storage position of each second register in the second target register group to obtain a first result corresponding to the first polynomial, where b is an integer that ranges from [0, 7], and q is an integer that ranges from [0, 7].

[0185] The 24 first polynomials mentioned above are used to illustrate that the common variables corresponding to the 24 first polynomials are stored in Fig.10 The first target register group shown in FIG. 1 , the variable coefficients corresponding to the 24 first polynomials are stored in Fig.11 The second target register group shown in FIG. 1 illustrates how to obtain first results corresponding to 24 first polynomials respectively by performing outer product calculations based on the common variables in the first target register group and the variable coefficients in the second target register group. The first results corresponding to the 24 first polynomials respectively are stored in the following manner: Fig.14 In the fourth target register set shown.

[0186] The outer product of the 0th storage position of each first register in the first target register group and the 0th storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 0th fourth destination register 0th storage location.

[0187] The outer product of the 0th storage position of each first register in the first target register group and the 1st storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 1st fourth destination register storage location 0.

[0188] The outer product of the 0th storage position of each first register in the first target register group and the 2nd storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 2nd fourth destination register storage location 0.

[0189] The outer product of the 0th storage position of each first register in the first target register group and the 3rd storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 3rd fourth destination register storage location 0.

[0190] The outer product of the 0th storage position of each first register in the first target register group and the 4th storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 4th destination register storage location 0.

[0191] The outer product of the 0th storage position of each first register in the first target register group and the 5th storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 5th fourth destination register storage location 0.

[0192] The outer product of the 0th storage position of each first register in the first target register group and the 6th storage position of each second register in the second target register group is calculated, and the first result is obtained as follows: And the first result Load into the 6th fourth destination register storage location 0.

[0193] An outer product is calculated for the 0th storage position of each first register in the first target register group and the 7th storage position of each second register in the second target register group, a first result of 0 is obtained, and the first result 0 is loaded into the 0th storage position of the 7th fourth target register.

[0194] The above steps are repeated for the 1st to 7th storage locations of each first register in the first target register group, and are not described in detail here.

[0195] S206, controlling the first result corresponding to at least one polynomial to be calculated to perform inner product calculation with at least one reference variable in the third register group to obtain a second result corresponding to at least one polynomial to be calculated.

[0196] For a first polynomial in at least one polynomial to be calculated, a first result corresponding to the first polynomial is controlled to perform an inner product calculation with a reference variable in a third target register group to obtain a second result corresponding to the first polynomial.

[0197] In an embodiment of the present application, the second result of the first polynomial can be stored in a fifth target register group. The fifth target register group includes a plurality of fifth registers, each of which includes a plurality of storage locations. Generally speaking, the fifth register group includes 8 fifth registers. Each fifth register can store 512 bits of data. It is assumed that each fifth register includes 8 storage locations, so each storage location in the fifth register can store 64 bits of data. The fifth register can be an SVE register.

[0198] like Fig.15As shown, for the convenience of the following description, each fifth register in the fifth register group may be numbered, and the eight fifth registers are numbered Z0, Z1, Z2, Z3, Z4, Z5, Z6, and Z7, respectively. Each storage position in each fifth register may also be numbered, and the eight storage positions of each fifth register are numbered 0, 1, 2, 3, 4, 5, 6, and 7, respectively. Each storage position in the fifth register group may be initialized with 0.

[0199] It should be understood that before performing the inner product calculation, the number of first results corresponding to the first polynomial and the number of reference variables need to be determined. In the embodiment of the present application, the number of first results corresponding to the first polynomial is M, and the number of reference variables is M. Before the inner product calculation, the number of first results corresponding to the first polynomial and the number of reference variables can be saved in the sixth target register group.

[0200] by Fig.12 The third target register set shown, Fig.14 Taking the fourth target register group shown in FIG. 1 as an example, it is explained how to perform inner product calculation on the first result in the fourth target register group and the reference variable in the third target register group to obtain 24 second results of the first polynomial. Among them, the second results of the 24 first polynomials are stored in Fig.16 The fifth target register set is shown.

[0201] Determine that the number of first temporary values ​​corresponding to the 0th first polynomial is 3, the number of reference variables is 3, and the inner product is calculated between the 0th storage position of the fourth register W0-W2 in the fourth target register group and the 0th storage position of the third register U0-U2 in the third target register group, and the second result of the first polynomial is obtained as follows: And the second result of the first polynomial Load into storage location 0 in register 0 in target register set 5.

[0202] The calculation process of the second results corresponding to the 1st to 7th first polynomials is similar to the calculation process of the second result of the 0th first polynomial, and will not be described in detail here.

[0203] Determine that the number of first temporary values ​​corresponding to the 8th first polynomial is 2, the number of reference variables is 2, and the inner product is calculated between the 0th storage position of the fourth register W3-W4 in the fourth target register group and the 0th storage position of the third register U3-U4 in the third target register group, and the second result of the first polynomial is obtained as follows: And the second result of the first polynomial Load into storage location 0 in destination register number 1 in the fifth register bank.

[0204] The calculation process of the second results corresponding to the 9th to 15th first polynomials is similar to the calculation process of the second result of the 8th first polynomial, and will not be described in detail here.

[0205] Determine that the number of first temporary values ​​corresponding to the 16th first polynomial is 2, the number of reference variables is 2, and the inner product is calculated between the 0th storage position of the fourth register W5-W6 in the fourth target register group and the 0th storage position of the third register U5-U6 in the third target register group, and the second result of the first polynomial is obtained as follows: And the second result of the first polynomial Load into storage location 0 in register number 2 of fifth register in fifth destination register set.

[0206] The calculation process of the second results corresponding to the 17th to 23rd first polynomials is similar to the calculation process of the second result of the 16th first polynomial, and will not be described in detail here.

[0207] When calculating a large number of polynomials, the above method can be used to convert the polynomial loop calculation into matrix calculation between register groups, thereby improving the calculation speed.

[0208] Based on the same inventive concept as the method embodiment, the embodiment of the present application also provides a polynomial calculation device, which is used to perform the above Figure 2 The method of the method embodiment. Fig.17 As shown, the polynomial calculation device 1700 includes an acquisition module 1701 and a processing module 1702. Specifically, in the polynomial calculation device 1700, each module is connected through a communication path. In an application scenario, the memory 102 stores executable program code, and the processor 101 executes the executable program code to respectively implement the functions of the aforementioned acquisition module 1701 and the processing module 1702, thereby implementing the polynomial calculation method provided in this embodiment.

[0209] The acquisition module 1701 is used to acquire multiple polynomials to be calculated in a polynomial calculation application.

[0210] The processing module 1702 is configured to divide a plurality of polynomials to be calculated to obtain a plurality of groups to be calculated, each group to be calculated includes at least one polynomial to be calculated, at least one polynomial to be calculated in each group to be calculated is of the same type, and the plurality of groups to be calculated include a first group to be calculated, which is any group to be calculated in the plurality of groups to be calculated; determine a common variable, a variable coefficient, and a reference variable respectively corresponding to at least one polynomial to be calculated in the first group to be calculated, at least one polynomial to be calculated in the first group to be calculated corresponds to the same variable coefficient; load the common variables respectively corresponding to at least one polynomial to be calculated into at least one first register group, load the variable coefficient respectively corresponding to at least one polynomial to be calculated into at least one second register group, and load the reference variable respectively corresponding to at least one polynomial to be calculated into at least one third register group; control the common variables in at least one first register group to perform outer product calculation with the variable coefficients in at least one second register group to obtain a first result respectively corresponding to at least one polynomial to be calculated; control the first result respectively corresponding to at least one polynomial to be calculated to perform inner product calculation with the reference variables in at least one third register group to obtain a second result respectively corresponding to at least one polynomial to be calculated.

[0211] In a possible implementation, when the processing module 1702 determines the common variables, variable coefficients and reference variables corresponding to at least one polynomial to be calculated in the first group to be calculated, it can include: for a first polynomial in at least one polynomial to be calculated, the first polynomial is any polynomial in the at least one polynomial to be calculated, performing the following steps: extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the M N-order polynomials corresponding one-to-one to the M reference variables, each N-order polynomial including N common variables and N variable coefficients, the N common variables corresponding one-to-one to the N variable coefficients, the N common variables respectively included in the M N-order polynomials are the same, M is a positive integer, and N is an integer greater than 1; based on the M N-order polynomials, determining N common variables and M*N variable coefficients.

[0212] In one possible implementation, before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the processing module 1702 is also used to, when it is determined that the orders of the monomials included in the first polynomial are discontinuous, supplement the first polynomial with monomials corresponding to the missing orders, and the variable coefficients of the monomials corresponding to the missing orders are zero.

[0213] In one possible implementation, before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the processing module 1702 is also used to, when it is determined that the number of monomials included in the first polynomial is an odd number, add an odd number of monomials to the first polynomial, and the variable coefficients of the odd number of monomials are all zero.

[0214] In a possible implementation, when the processing module 1702 extracts M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, it is specifically used to: take every N-order adjacent monomial in the first polynomial as a second polynomial to obtain M second polynomials; determine the ratio of the k-th variable included in each second polynomial in the M second polynomials to the k-th variable included in the second polynomial with the lowest order as the M reference variables corresponding to the M second polynomials; k is a non-negative integer less than N; determine the ratio between each second polynomial in the M second polynomials and the corresponding reference variable as the M N-order polynomials.

[0215] In a possible implementation, when the processing module 1702 loads the common variables corresponding to at least one polynomial to be calculated into at least one first register group, loads the variable coefficient corresponding to at least one polynomial to be calculated into at least one second register group, and loads the reference variable corresponding to at least one polynomial to be calculated into at least one third register group, it may include: for a first polynomial in at least one polynomial to be calculated, the first polynomial is any polynomial in the at least one polynomial to be calculated, performing the following steps: loading N common variables corresponding to the first polynomial into a first target register group, the first target register group is any one of the at least one first register group; loading M*N variable coefficients corresponding to the first polynomial into a second target register group, the second target register group is any one of the at least one second register group; loading M reference variables corresponding to the first polynomial into a third target register group, the third target register group is any one of the at least one third register group.

[0216] In a possible implementation, the first target register group includes multiple first registers, each of which includes multiple storage locations; when the processing module 1702 loads N shared variables corresponding to the first polynomial into the first target register group, it is specifically used to: load the i-th shared variable among the N shared variables into the j-th storage position in the b+i-th first register of the first target register group, where i is an integer that ranges from [0, N-1], j is a non-negative integer, and b is a non-negative integer.

[0217] In a possible implementation, the second target register group includes multiple second registers, each second register includes multiple storage locations; when the processing module 1702 loads the M*N variable coefficients corresponding to the first polynomial into the second target register group, it is specifically used to: load the i-th variable coefficient corresponding to the m-th N-order polynomial among the M N-order polynomials into the b+m-th storage position in the b+i-th second register of the second target register group, where m is an integer that ranges from [0, M-1], the value of i is an integer that ranges from [0, N-1], and b is a non-negative integer.

[0218] In a possible implementation, the third target register group includes multiple third registers, each third register includes multiple storage locations; when the processing module 1702 loads the M reference variables corresponding to the first polynomial into the third target register group, it is specifically used to: load the mth reference variable among the M reference variables into the jth storage position in the b+mth third register of the third target register group, where m is an integer ranging from [0, M-1], b is a non-negative integer, and j is a non-negative integer.

[0219] In a possible implementation, when the processing module 1702 controls the common variables in at least one first register group and the variable coefficients in at least one second register group to perform outer product calculations to obtain first results corresponding to at least one polynomial to be calculated, the processing module 1702 is specifically configured to: for a first polynomial in at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, perform the following steps: control the common variables in the first target register group and the variable coefficients in the second target register group to perform outer product calculations to obtain a first result corresponding to the first polynomial.

[0220] In a possible implementation, the processing module 1702 controls the first result corresponding to at least one polynomial to be calculated to perform inner product calculation with the reference variable in the at least one third register group to obtain the second result corresponding to the at least one polynomial to be calculated, and is specifically used to: for a first polynomial in the at least one polynomial to be calculated, the first polynomial is any polynomial in the at least one polynomial to be calculated, perform the following steps: control the first result corresponding to the first polynomial to perform inner product calculation with the reference variable in the third target register group to obtain the second result corresponding to the first polynomial.

[0221] The present application also provides a computer program product including instructions. The computer program product may be a software or program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the above Figure 2For the method of the embodiment, please refer to the relevant description above and will not be repeated here.

[0222] The present application also provides a computer-readable storage medium. The computer-readable storage medium may be any available medium that can be stored by a computing device or a data storage device that includes one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to perform the above Figure 2 The method implemented in the embodiment has been described above and will not be described again here.

[0223] Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0224] Those of ordinary skill in the art will appreciate that the various digital numbers such as the first and second involved in this application are only for the convenience of description, and are not used to limit the scope of the embodiments of this application, and also represent the order of precedence. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one" refers to one or more. At least two refers to two or more. "At least one", "any one" or similar expressions refer to any combination of these items, including any combination of single items (individuals) or plural items (individuals). For example, at least one item (individuals, kinds) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. "Multiple" refers to two or more, and other quantifiers are similar. In addition, when the singular forms “a,” “an,” and “the” appear, they do not mean “one or only one,” but rather “one or more than one,” unless the context clearly dictates otherwise. For example, “a device” means one or more of such devices.

[0225] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0226] The various illustrative logic units and circuits described in the embodiments of the present application can be implemented or operated by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or the design of any combination of the above functions. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any traditional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration to implement.

[0227] The steps of the method or algorithm described in the embodiments of the present application can be directly embedded in the software unit executed by the hardware, the processor, or a combination of the two. The software unit can be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM or other storage media of any form in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Alternatively, the storage medium can also be integrated into the processor. The processor and the storage medium can be arranged in an ASIC.

[0228] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0229] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, a person skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A polynomial calculation method, characterized in that: The method comprises: Obtaining multiple polynomials to be calculated in a polynomial calculation application; Dividing the multiple polynomials to be calculated to obtain multiple groups to be calculated, each group to be calculated includes at least one polynomial to be calculated, at least one polynomial to be calculated in each group to be calculated has the same variable coefficient, the multiple groups to be calculated include a first group to be calculated, and the first group to be calculated is any group to be calculated in the multiple groups to be calculated; Determine the common variables, variable coefficients and reference variables respectively corresponding to at least one polynomial to be calculated in the first to-be-calculated group; Loading the common variables respectively corresponding to the at least one polynomial to be calculated into at least one first register group, loading the variable coefficients respectively corresponding to the at least one polynomial to be calculated into at least one second register group, and loading the reference variables respectively corresponding to the at least one polynomial to be calculated into at least one third register group; Controlling the common variables in the at least one first register group to perform outer product calculations with the coefficients of the variables in the at least one second register group to obtain first results respectively corresponding to the at least one polynomial to be calculated; The first results respectively corresponding to the at least one polynomial to be calculated are controlled to perform inner product calculations with reference variables in the at least one third register group to obtain second results respectively corresponding to the at least one polynomial to be calculated.

2. The method according to claim 1, characterized in that The determining of the common variables, the variable coefficients and the reference variables respectively corresponding to at least one polynomial to be calculated in the first to-be-calculated group includes: For a first polynomial in the at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, perform the following steps: Extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the M N-order polynomials corresponding to the M reference variables one-to-one, each of the N-order polynomials including N common variables and N variable coefficients, the N common variables corresponding to the N variable coefficients one-to-one, the M N-order polynomials respectively including the same N common variables, M being a positive integer, and N being an integer greater than 1; Based on the M N-order polynomials, N common variables and M*N variable coefficients are determined.

3. The method according to claim 2, characterized in that Before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the method further includes: When it is determined that the orders of the monomials included in the first polynomial are discontinuous, the first polynomial is supplemented with monomials corresponding to the missing orders, and the variable coefficients of the monomials corresponding to the missing orders are zero.

4. The method according to claim 2 or 3, characterized in that Before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the method further includes: When it is determined that the number of monomials included in the first polynomial is an odd number, an odd number of monomials are supplemented to the first polynomial, and the variable coefficients of the odd number of monomials are all zero.

5. The method according to claim 2, characterized in that The extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial includes: Taking every N adjacent monomials of the first polynomial as a second polynomial, to obtain M second polynomials; Determine the ratio of the kth variable included in each of the M second polynomials to the kth variable included in the second polynomial with the lowest order as the M reference variables corresponding to the M second polynomials; k is a non-negative integer less than N; The ratio between each second polynomial in the M second polynomials and the corresponding reference variable is determined as the M N-order polynomials.

6. The method according to claim 2, characterized in that The method of loading the common variables respectively corresponding to the at least one polynomial to be calculated into at least one first register group, loading the variable coefficients respectively corresponding to the at least one polynomial to be calculated into at least one second register group, and loading the reference variables respectively corresponding to the at least one polynomial to be calculated into at least one third register group comprises: For a first polynomial in the at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, perform the following steps: Loading N common variables corresponding to the first polynomial into a first target register group, where the first target register group is any one of the at least one first register group; Loading M*N variable coefficients corresponding to the first polynomial into a second target register group, where the second target register group is any one of the at least one second register group; The M reference variables corresponding to the first polynomial are loaded into a third target register group, where the third target register group is any one of the at least one third register group.

7. The method according to claim 6, characterized in that The first target register set includes a plurality of first registers, each first register includes a plurality of storage locations; The step of loading the N common variables corresponding to the first polynomial into a first target register group includes: Loading the i-th shared variable among the N shared variables into the j-th storage position in the b+i-th first register of the first target register group, wherein i is an integer ranging from [0, N-1], j is a non-negative integer, and b is a non-negative integer.

8. The method according to any one of claims 6-7, characterized in that: The second target register set includes a plurality of second registers, each second register includes a plurality of storage locations; The step of loading the M*N variable coefficients corresponding to the first polynomial into the second target register group includes: The i-th variable coefficient corresponding to the m-th N-order polynomial among the M N-order polynomials is loaded into the b+m-th storage position in the b+i-th second register of the second target register group, wherein m is an integer ranging from [0, M-1], the value of i is an integer ranging from [0, N-1], and b is a non-negative integer.

9. The method according to any one of claims 6 to 8, characterized in that: The third target register set includes a plurality of third registers, each third register includes a plurality of storage locations; The step of loading the M reference variables corresponding to the first polynomial into a third target register group includes: The mth reference variable of the M reference variables is loaded into the jth storage position of the b+mth third register of the third target register group, wherein m is an integer ranging from [0, M-1], b is a non-negative integer, and j is a non-negative integer.

10. The method according to claim 6, characterized in that The controlling the common variables in the at least one first register group to perform outer product calculations on the coefficients of the variables in the at least one second register group to obtain first results respectively corresponding to the at least one polynomial to be calculated includes: For a first polynomial in the at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, perform the following steps: Controlling the common variables in the first target register group and the coefficients of the variables in the second target register group to perform outer product calculation to obtain a first result corresponding to the first polynomial.

11. The method according to claim 10, characterized in that The controlling the first result corresponding to the at least one polynomial to be calculated to perform inner product calculation with the reference variable in the at least one third register group to obtain the second result corresponding to the at least one polynomial to be calculated, comprises: For a first polynomial in the at least one polynomial to be calculated, where the first polynomial is any polynomial in the at least one polynomial to be calculated, perform the following steps: Controlling a first result corresponding to the first polynomial to perform an inner product calculation with a reference variable in the third target register group to obtain a second result corresponding to the first polynomial.

12. A polynomial calculation device, characterized in that: The polynomial calculation device comprises an acquisition module and a processing module: The acquisition module is used to acquire multiple polynomials to be calculated in the polynomial calculation application; The processing module is used to divide the multiple polynomials to be calculated to obtain multiple groups to be calculated, each group to be calculated includes at least one polynomial to be calculated, at least one polynomial to be calculated in each group to be calculated is of the same type, the multiple groups to be calculated include a first group to be calculated, and the first group to be calculated is any group to be calculated in the multiple groups to be calculated; The processing module is further used to determine the common variables, variable coefficients and reference variables respectively corresponding to at least one polynomial to be calculated in the first to-be-calculated group, wherein at least one polynomial to be calculated in the first to-be-calculated group corresponds to the same variable coefficient; The processing module is further configured to load the common variables respectively corresponding to the at least one polynomial to be calculated into at least one first register group, load the variable coefficients respectively corresponding to the at least one polynomial to be calculated into at least one second register group, and load the reference variables respectively corresponding to the at least one polynomial to be calculated into at least one third register group; The processing module is further used to control the common variables in the at least one first register group and the variable coefficients in the at least one second register group to perform outer product calculations to obtain first results respectively corresponding to the at least one polynomial to be calculated; The processing module is further used to control the first results respectively corresponding to the at least one polynomial to be calculated to perform inner product calculations with the reference variables in the at least one third register group to obtain second results respectively corresponding to the at least one polynomial to be calculated.

13. A computing device, characterized in that: The device includes a processor and a memory; The memory is used to store computer program instructions; The processor executes and calls the computer program instructions in the memory to perform the method according to any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that: When the computer-readable storage medium is executed by a storage device, the storage device executes the method according to any one of claims 1 to 11.

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