Intermediate expression-based two-stage instruction translation method, system and equipment and medium

Abstract

The invention relates to the technical field of computer hardware CPU (Central Processing Unit) instruction translation, and discloses a two-stage instruction translation method, system and equipment based on intermediate expression and a medium, which are used for assisting in finishing starting and running of an application program on a source CPU on a target computer by translating an instruction in a source CPU instruction set into an instruction sequence corresponding to a CPU instruction set of the target computer. The method has the characteristics of front-end and rear-end decoupling of instruction translation, cross-platform multiplexing of translation codes and the like, and can perform flexible combination processing between translation front-end codes and rear-end translation codes, so that the reusability of the instruction translation codes is improved, and the development time of the instruction translation codes is shortened; particularly, the problem that translation codes cannot be reused due to a one-step translation method of direct translation between CPU instruction sets can be solved.

Description

Technical Field

[0001] The invention relates to the technical field of computer hardware CPU instruction translation, and discloses a two-stage instruction translation method, system, device and medium based on intermediate expression. Background Art

[0002] When running an application on a computer, no matter what high-level language the application is coded in, it will eventually be converted into an instruction sequence in the corresponding CPU instruction set (i.e., program binary file) by a compiler, and then deployed on the computer to start running. When a program binary file generated for a certain CPU instruction set is started on another CPU, it is necessary to translate instructions between the two CPU instruction sets. The traditional instruction translation method is to directly translate and convert between the two CPU instruction sets (i.e., one-step translation method). The one-step translation method is only applicable to instruction translation between two specific CPU instruction sets. Once the source CPU instruction set or the target CPU instruction set changes, the original translation code cannot be reused at all. Summary of the invention

[0003] The purpose of the present invention is to provide a two-stage instruction translation method, system, device and medium based on intermediate expression, which can flexibly combine the translation front-end code and the back-end translation code, improve the reusability of the instruction translation code, and shorten the development time of the instruction translation code; in particular, it can solve the problem of non-reusability of the translation code caused by the one-step translation method of direct translation between CPU instruction sets.

[0004] In order to achieve the above technical effects, the technical solution adopted by the present invention is:

[0005] The two-stage instruction translation method based on intermediate expression includes:

[0006] Translate all source CPU instructions in the original application binary file into corresponding instruction sequences in the intermediate expression pseudo instruction set to form an application instruction file represented by the intermediate expression pseudo instruction set;

[0007] All pseudo instructions in the application instruction file represented by the intermediate expression pseudo instruction set are translated into corresponding instruction sequences in the target CPU instruction set to form an application instruction file represented by the target CPU instruction set.

[0008] Furthermore, the intermediate expression pseudo-instruction set includes arithmetic instructions, logical instructions, shift instructions, jump instructions, memory instructions and other instructions; the other instructions include assignment instructions, sign extension instructions, zero extension instructions, 16-bit byte exchange instructions, 32-bit byte exchange instructions, and 64-bit byte exchange instructions.

[0009] Furthermore, the arithmetic instructions include addition instructions, subtraction instructions, negation instructions, multiplication instructions, division instructions, and remainder instructions; the logic instructions include logic and instructions, logic or instructions, logic exclusive or instructions, logic not instructions, logic not and instructions, logic exclusive or not instructions, logic not and instructions, logic not or instructions, logic not or instructions, clear instructions, and set instructions; the shift instructions include left shift instructions, unsigned right shift instructions, signed right shift instructions, circular left shift instructions, and circular right shift instructions; the jump instructions include absolute jump instructions and conditional jump instructions; the memory instructions include 8-bit memory load instructions, 16-bit memory load instructions, 32-bit memory load instructions, 64-bit memory load instructions, 8-bit memory assignment instructions, 16-bit memory assignment instructions, 32-bit memory assignment instructions, 64-bit memory assignment instructions, and memory barrier instructions.

[0010] In order to achieve the above technical effects, the present invention also provides a two-stage instruction translation system based on intermediate expression, which is used to implement the two-stage instruction translation method based on intermediate expression, including:

[0011] A first translation module is used to translate all source CPU instructions in the original application binary file into corresponding instruction sequences in the intermediate expression pseudo instruction set to form an application instruction file represented by the intermediate expression pseudo instruction set;

[0012] The second translation module is used to translate all pseudo instructions in the application instruction file represented by the intermediate expression pseudo instruction set into corresponding instruction sequences in the target CPU instruction set to form an application instruction file represented by the target CPU instruction set.

[0013] Furthermore, in the first translation module and the second translation module, the intermediate expression pseudo-instruction set includes arithmetic instructions, logical instructions, shift instructions, jump instructions, memory instructions and other instructions; the other instructions include assignment instructions, sign extension instructions, zero extension instructions, 16-bit byte exchange instructions, 32-bit byte exchange instructions, and 64-bit byte exchange instructions.

[0014] Further, in the first translation module and the second translation module, the arithmetic instructions include addition instructions, subtraction instructions, negation instructions, multiplication instructions, division instructions, and remainder instructions; the logic instructions include logic and instructions, logic or instructions, logic exclusive or instructions, logic not instructions, logic not and instructions, logic exclusive or not instructions, logic not and instructions, logic not or instructions, logic not or instructions, clear instructions, and set instructions; the shift instructions include left shift instructions, unsigned right shift instructions, signed right shift instructions, circular left shift instructions, and circular right shift instructions; the jump instructions include absolute jump instructions and conditional jump instructions; the memory instructions include 8-bit memory load instructions, 16-bit memory load instructions, 32-bit memory load instructions, 64-bit memory load instructions, 8-bit memory assignment instructions, 16-bit memory assignment instructions, 32-bit memory assignment instructions, 64-bit memory assignment instructions, and memory barrier instructions.

[0015] To achieve the above technical effects, the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the two-stage instruction translation method based on intermediate expression when executing the computer program.

[0016] In order to achieve the above technical effects, the present invention also provides a computer-readable storage medium, which stores a computer program for executing the two-stage instruction translation method based on intermediate expression.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention assists in completing the startup and operation of the application on the source CPU on the target computer by translating the instructions in the source CPU instruction set into the instruction sequence corresponding to the target computer CPU instruction set. It has the characteristics of decoupling the front-end and back-end of instruction translation, and the translation code is reusable across platforms. It can perform flexible combination processing between the translation front-end code and the back-end translation code, thereby improving the reusability of the instruction translation code and shortening the development time of the instruction translation code. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the two-stage instruction translation method based on intermediate expression in the embodiment

[0019] Figure 2 It is a flow chart of a two-stage instruction translation method based on intermediate expression in an embodiment;

[0020] Figure 3 It is a structural block diagram of a two-stage instruction translation system based on intermediate expression in an embodiment;

[0021] Among them, 1. The first translation module; 2. The second translation module. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with the embodiments and drawings. However, it should not be understood that the scope of the above subject matter of the present invention is limited to the following embodiments, and all technologies realized based on the content of the present invention belong to the scope of the present invention.

[0023] Example

[0024] See also Figure 1-Figure 3 , a two-stage instruction translation method based on intermediate expression, including:

[0025] Translate all source CPU instructions in the original application binary file into corresponding instruction sequences in the intermediate expression pseudo instruction set to form an application instruction file represented by the intermediate expression pseudo instruction set;

[0026] All pseudo instructions in the application instruction file represented by the intermediate expression pseudo instruction set are translated into corresponding instruction sequences in the target CPU instruction set to form an application instruction file represented by the target CPU instruction set.

[0027] In this embodiment, the translation engine used for the front-end translation can be determined according to the source CPU instruction set, and the source CPU instruction sequence can be translated into an equivalent intermediate expression pseudo-instruction sequence by the front-end translation engine. According to the target CPU instruction set, the translation engine used for the back-end translation can be determined, and the intermediate expression pseudo-instruction sequence can be translated into an equivalent target CPU instruction sequence by the back-end translation engine. The present invention assists in completing the startup and operation of the application on the source CPU on the target computer by translating the instructions in the source CPU instruction set into the instruction sequence corresponding to the target computer CPU instruction set. It has the characteristics of decoupling the front-end and back-end of the instruction translation, and the cross-platform reusable translation code. It can perform flexible combination processing between the translation front-end code and the back-end translation code, improve the reusability of the instruction translation code, and shorten the development time of the instruction translation code; in particular, it can solve the problem of non-reusable translation code caused by the one-step translation method of direct translation between CPU instruction sets.

[0028] In this embodiment, the intermediate expression pseudo-instruction set includes arithmetic instructions, logical instructions, shift instructions, jump instructions, memory instructions and other instructions; the other instructions include assignment instructions, sign extension instructions, zero extension instructions, 16-bit byte exchange instructions, 32-bit byte exchange instructions, and 64-bit byte exchange instructions.

[0029] In this embodiment, the arithmetic instructions include addition instructions, subtraction instructions, negation instructions, multiplication instructions, division instructions, and remainder instructions; the logic instructions include logical and instructions, logical or instructions, logical exclusive or instructions, logical not instructions, logical not and instructions, logical exclusive or not instructions, logical not and instructions, logical not or instructions, logical not or instructions, clear instructions, and set instructions; the shift instructions include left shift instructions, unsigned right shift instructions, signed right shift instructions, circular left shift instructions, and circular right shift instructions; the jump instructions include absolute jump instructions and conditional jump instructions; the memory instructions include 8-bit memory load instructions, 16-bit memory load instructions, 32-bit memory load instructions, 64-bit memory load instructions, 8-bit memory assignment instructions, 16-bit memory assignment instructions, 32-bit memory assignment instructions, 64-bit memory assignment instructions, and memory barrier instructions.

[0030] Based on the same inventive concept, this embodiment also provides a two-stage instruction translation system based on intermediate expression, including:

[0031] A first translation module is used to translate all source CPU instructions in the original application binary file into corresponding instruction sequences in the intermediate expression pseudo instruction set to form an application instruction file represented by the intermediate expression pseudo instruction set;

[0032] The second translation module is used to translate all pseudo instructions in the application instruction file represented by the intermediate expression pseudo instruction set into corresponding instruction sequences in the target CPU instruction set to form an application instruction file represented by the target CPU instruction set.

[0033] Based on the same inventive concept, this embodiment also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the two-stage instruction translation method based on intermediate expression when executing the computer program. The present invention can be implemented in the form of software and run on a target computer, thereby reducing the amount of code and solving the problem of non-reusability of translation code caused by the one-step translation method of direct translation between CPU instruction sets.

[0034] Specifically, the computer device may be a computer terminal, a server or a similar computing device.

[0035] Based on the same inventive concept, this embodiment also provides a computer-readable storage medium, which stores a computer program for executing the two-stage instruction translation method based on intermediate expression.

[0036] Specifically, computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer-readable storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0037] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A two-stage instruction translation method based on intermediate expression, characterized in that: include: Translate all source CPU instructions in the original application binary file into corresponding instruction sequences in the intermediate expression pseudo instruction set to form an application instruction file represented by the intermediate expression pseudo instruction set; All pseudo instructions in the application instruction file represented by the intermediate expression pseudo instruction set are translated into corresponding instruction sequences in the target CPU instruction set to form an application instruction file represented by the target CPU instruction set.

2. The two-stage instruction translation method based on intermediate expression according to claim 1 is characterized in that: The intermediate expression pseudo-instruction set includes arithmetic instructions, logical instructions, shift instructions, jump instructions, memory instructions and other instructions; the other instructions include assignment instructions, sign extension instructions, zero extension instructions, 16-bit byte exchange instructions, 32-bit byte exchange instructions, and 64-bit byte exchange instructions.

3. The two-stage instruction translation method based on intermediate expression according to claim 1 is characterized in that: The arithmetic instructions include addition instructions, subtraction instructions, negation instructions, multiplication instructions, division instructions, and remainder instructions; the logic instructions include logic and instructions, logic or instructions, logic exclusive or instructions, logic not instructions, logic not and instructions, logic exclusive or not instructions, logic not and instructions, logic not or instructions, logic not or instructions, clear instructions, and set instructions; the shift instructions include left shift instructions, unsigned right shift instructions, signed right shift instructions, circular left shift instructions, and circular right shift instructions; the jump instructions include absolute jump instructions and conditional jump instructions; the memory instructions include 8-bit memory load instructions, 16-bit memory load instructions, 32-bit memory load instructions, 64-bit memory load instructions, 8-bit memory assignment instructions, 16-bit memory assignment instructions, 32-bit memory assignment instructions, 64-bit memory assignment instructions, and memory barrier instructions.

4. A two-stage instruction translation system based on intermediate expression, used to implement the two-stage instruction translation method based on intermediate expression according to any one of claims 1 to 3, characterized in that: include: A first translation module is used to translate all source CPU instructions in the original application binary file into corresponding instruction sequences in the intermediate expression pseudo instruction set to form an application instruction file represented by the intermediate expression pseudo instruction set; The second translation module is used to translate all pseudo instructions in the application instruction file represented by the intermediate expression pseudo instruction set into corresponding instruction sequences in the target CPU instruction set to form an application instruction file represented by the target CPU instruction set.

5. The two-stage instruction translation system based on intermediate expression according to claim 4 is characterized in that: In the first translation module and the second translation module, the intermediate expression pseudo-instruction set includes arithmetic instructions, logical instructions, shift instructions, jump instructions, memory instructions and other instructions; the other instructions include assignment instructions, sign extension instructions, zero extension instructions, 16-bit byte exchange instructions, 32-bit byte exchange instructions, and 64-bit byte exchange instructions.

6. The two-stage instruction translation system based on intermediate expression according to claim 4 is characterized in that: In the first translation module and the second translation module, the arithmetic instructions include addition instructions, subtraction instructions, negation instructions, multiplication instructions, division instructions, and remainder instructions; the logic instructions include logic and instructions, logic or instructions, logic exclusive or instructions, logic not instructions, logic not and instructions, logic exclusive or not instructions, logic not and instructions, logic not or instructions, logic not or instructions, clear instructions, and set instructions; the shift instructions include left shift instructions, unsigned right shift instructions, signed right shift instructions, circular left shift instructions, and circular right shift instructions; the jump instructions include absolute jump instructions and conditional jump instructions; the memory instructions include 8-bit memory load instructions, 16-bit memory load instructions, 32-bit memory load instructions, 64-bit memory load instructions, 8-bit memory assignment instructions, 16-bit memory assignment instructions, 32-bit memory assignment instructions, 64-bit memory assignment instructions, and memory barrier instructions.

7. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the two-stage instruction translation method based on intermediate expression described in any one of claims 1 to 3 is implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program for executing the intermediate expression-based two-stage instruction translation method according to any one of claims 1 to 3.

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