High-reliability chip boot method and chip

Abstract

This invention relates to a highly reliable chip boot method and chip. It includes: for any target chip to be booted, at least one boot module is installed within the target chip; when booting the target chip, the Flash memory is configured to at least be in continuous read mode; subsequently, the boot module is controlled to enter an instruction read and execute operation state; for any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module; for any boot instruction returned via the on-chip bus, the boot module immediately parses the boot instruction, and after parsing, initiates a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request. This invention can improve the reliability and efficiency of chip booting, and also saves the area of ​​the target chip.

Description

Technical Field

[0001] This invention relates to a chip startup method and a chip, and more particularly to a highly reliable chip startup method and chip. Background Technology

[0002] With the rapid development of the semiconductor industry, microelectronics, and electronic information technology, the market and users have increasingly higher demands for the reliability, security, flexibility, and compatibility of chip systems. As is well known, using a chip requires a startup process, but this is not a simple matter. Chip startup is a complex process; whether the chip can start stably and successfully is crucial to its subsequent usability. If startup fails, the chip cannot be used. Therefore, the chip startup operation plays a vital role.

[0003] Currently, chips generally employ only one boot mode: booting the chip through a single method or mechanism. Specifically, the chip boot program is stored in Flash memory. After the chip powers on and resets, the MCU moves the boot program from Flash to main memory and then jumps to the specified memory address to execute it. The boot program includes initializing various components, such as clearing registers, configuring specific values ​​for some function registers, resetting and configuring the clocks of various components, initializing the PCIe card and training and linking the connection, training the HBM, configuring internal modules and peripheral interfaces, booting the kernel, and loading the operating system. Therefore, chip booting involves many operations, requiring a flexible and reliable design with strong compatibility.

[0004] For SPI (Serial Peripheral Interface) type Flash memory, accessing the Flash requires configuring both the SPI controller and the Flash memory. Only after configuration can the Flash be operated according to the configured settings. Flash operations include reading, writing, and erasing. Since the configuration program is embedded in the MCU's ROM and cannot be modified, an error in the embedded program will prevent the chip from booting, resulting in a boot failure.

[0005] As explained above, once a chip is fabricated, the firmware in the ROM cannot be modified. However, chip fabrication is extremely costly in terms of both capital and time. Therefore, before fabrication, both the MCU and the firmware in the ROM must be thoroughly verified to ensure their correctness. If errors occur after fabrication, the chip will fail to boot, resulting in significant financial and time losses, and potentially even causing the entire chip project to fail. Currently, because there is only one method for chip booting, it is relatively simple and rigid, lacking flexibility and making it difficult to guarantee effective chip booting. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a highly reliable chip startup method and chip, which can improve the reliability and startup efficiency of chip startup.

[0007] According to the technical solution provided by the present invention, a highly reliable chip boot method is provided, the chip boot method comprising:

[0008] For any target chip to be booted, a boot module is provided at least within the target chip, wherein the boot module is adapted to be connected to the Flash memory storing the boot program via an on-chip bus;

[0009] When booting the target chip, the Flash memory must be configured in continuous read mode at least. Afterward, the boot module is controlled to enter the instruction read and execution operation state, where...

[0010] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a boot configuration execution request corresponding to the instruction read request;

[0011] For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module;

[0012] For any boot command returned via the on-chip bus, the boot module immediately parses the boot command and then sends a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request.

[0013] When the on-chip bus returns a stop command, the boot module enters a stopped working state.

[0014] The Flash memory is connected to the on-chip bus via a QSPI controller, whereby...

[0015] When the Flash memory is configured to continuous read mode by the QSPI controller, the Flash memory is configured to at least four-wire fast continuous read mode via the boot module or Jtag interface. After configuring the Flash memory to four-wire fast continuous read mode, the QSPI controller is configured to Xip mode.

[0016] When the Flash memory is configured to four-wire fast continuous read mode via the Jtag interface, the boot module is in a reset state.

[0017] The instruction read and execution request initiated by the boot module to the on-chip bus is a serial protocol request, in which...

[0018] When the boot module initiates an instruction read and execution request to the on-chip bus, it can only initiate the next instruction read request or startup configuration execution request to the on-chip bus after receiving the boot instruction read response returned by the on-chip bus.

[0019] When the instruction read execution request initiated by the boot module to the on-chip bus is a boot configuration execution request, the boot module can only initiate the next instruction read request or boot configuration execution request to the on-chip bus after receiving the boot configuration execution response returned by the on-chip bus.

[0020] 4. The high-reliability chip boot method according to claim 3, characterized in that: the instruction read execution request includes a request validity identifier signal xx2yy_req_valid, a request address xx2yy_req_addr, a request data xx2yy_req_data, a request write granularity status signal xx2yy_req_strb, a request type signal xx2yy_req_type, and a request read granularity status signal xx2yy_req_rsize;

[0021] When the request type signal xx2yy_req_type is in the first valid level state, the instruction read execution request is an instruction read request;

[0022] When the request type signal xx2yy_req_type is in the second valid level state, the instruction read execution request is the start configuration execution request.

[0023] The responses to the startup configuration execution and startup command reading are as follows:

[0024] This includes the response validity flag yy2xx_ack_valid, the response data yy2xx_ack_data, and the response exception flag yy2xx_ack_excp, among which,

[0025] For any startup configuration execution response and startup command read response, once the response validity flag yy2xx_ack_valid is valid, the response data yy2xx_ack_data and the response exception flag yy2xx_ack_excp are retained until the request validity flag xx2yy_req_valid in the next command read execution request is valid.

[0026] The boot instructions stored in the Flash memory also include the NOP empty instruction, SETBASEH instruction, SETBASEL instruction, DELAY instruction, SETW instruction, WR.1 instruction, WR.2 instruction, WR.4 instruction, and / or WR.8 instruction, among which...

[0027] After receiving and parsing the NOP empty instruction, the boot module initiates a next instruction read request to the on-chip bus after the next clock cycle based on the data in the NOP empty instruction.

[0028] After receiving and parsing the SETBASEH instruction, the boot module obtains the high-order base address of the write I / O device.

[0029] After receiving and parsing the SETBASEL instruction, the boot module obtains the low-order base address of the write I / O device.

[0030] After receiving and parsing the DELAY instruction, the boot module counts and waits until the count value corresponds to the delay time in the DELAY instruction. After that, the boot module sends a request to the on-chip bus to read the next instruction.

[0031] After receiving and parsing the SETW command, the boot module performs continuous write operations on the chip components connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0032] After receiving and parsing the WR.1 command, the boot module performs a write operation of 1 byte at a time on the chip component connected to the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0033] After receiving and parsing the WR.2 command, the boot module performs a 2-byte write operation on the chip component connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0034] After receiving and parsing the WR.4 instruction, the boot module performs a 4-byte write operation on the chip component connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0035] After receiving and parsing the WR.8 command, the boot module performs an 8-byte write operation on the chip component connected to the on-chip bus and waits for the boot configuration execution response returned by the on-chip bus.

[0036] If the target chip cannot boot from the boot module, the Jtag interface is used to configure the chip components within the target chip until the boot requirements of the target chip are met.

[0037] A high-reliability chip, wherein the chip is started using the chip startup method described above, the chip comprising:

[0038] Flash memory, which stores at least the boot program, and is connected to the on-chip bus via the Qspi controller;

[0039] The boot module, connected to the on-chip bus, can configure the Flash memory in four-wire fast continuous read mode. After configuring the Flash memory in four-wire fast continuous read mode, the QSPI controller can be configured in Xip mode.

[0040] When the control chip starts up, the control boot module enters the instruction reading and execution operation state, where...

[0041] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a boot configuration execution request corresponding to the instruction read request;

[0042] For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module;

[0043] For any boot command returned via the on-chip bus, the boot module immediately parses the boot command and then sends a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request.

[0044] When the on-chip bus returns a stop command, the boot module enters a stopped working state.

[0045] The boot module includes a configuration unit and a read / execute unit, wherein...

[0046] When the configuration chip starts up, the external MCU unit cancels the reset of the boot module. Then, the configuration unit in the boot module configures the Flash memory to four-wire fast continuous read mode and the QSPI controller to Xip mode via the on-chip bus. Alternatively, the external MCU unit controls the boot module to be in a reset state. Then, at least through the JTAG interface, the Flash memory is configured to four-wire fast continuous read mode and the QSPI controller is configured to Xip mode.

[0047] When the Flash memory is configured in four-wire fast continuous read mode and the QSPI controller is in Xip mode, the MCU unit cancels the boot module reset to at least configure the read execution unit to enter the instruction read execution operation state.

[0048] The advantages of this invention are as follows: A boot module is set up within the target chip. The boot module is connected to the QSPI controller via the on-chip bus. The QSPI controller is configured to enter Xip mode and the Flash memory to enter four-wire fast continuous read mode via the boot module or the JTAG interface. Subsequently, the boot program in the Flash memory can be read quickly and continuously. The boot module parses the read boot instructions and writes data to the chip components connected to the on-chip bus, achieving chip component initialization and configuration. This eliminates program transfer time and shortens chip startup time. Furthermore, the boot module or the JTAG interface can be used to control the startup of the target chip, improving the reliability and efficiency of chip startup. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of one embodiment of the chip startup method of the present invention.

[0050] Figure 2 This is a flowchart of another embodiment of the present invention where the chip does not use the boot module to start.

[0051] Figure 3 This is a schematic diagram of an embodiment of the boot module of the present invention working in conjunction with the on-chip bus and Flash memory.

[0052] Figure 4 This is a schematic diagram of the state machine corresponding to the boot module of the present invention.

[0053] Figure 5 This is a schematic diagram of an embodiment of the instruction read execution request and startup configuration execution response of the present invention. Detailed Implementation

[0054] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0055] To improve the reliability and efficiency of chip startup, this invention provides a highly reliable chip startup method. Specifically, the chip startup method includes:

[0056] For any target chip to be booted, a boot module is provided at least within the target chip, wherein the boot module is adapted to be connected to the Flash memory storing the boot program via an on-chip bus;

[0057] When booting the target chip, the Flash memory must be configured in continuous read mode at least. Afterward, the boot module is controlled to enter the instruction read and execution operation state, where...

[0058] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a boot configuration execution request corresponding to the instruction read request;

[0059] For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module;

[0060] For any boot command returned via the on-chip bus, the boot module immediately parses the boot command and then sends a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request.

[0061] When the on-chip bus returns a stop command, the boot module enters a stopped working state.

[0062] It should be understood that the chip boot method of the present invention is specifically for booting a target chip. The type of target chip, etc., can be determined according to actual application requirements, and will not be elaborated here. When booting the target chip, a boot module should be set up at least within the target chip. After setting up the boot module within the target chip, the boot module can be used to control the boot of the target chip. Compared with the prior art, the area of ​​the boot module can be smaller than the area of ​​the logic module used for booting the target chip in the prior art, thereby reducing the area of ​​the target chip and lowering its cost. In addition, since the boot module is dedicated to booting the target chip, the boot efficiency of the target chip can be improved.

[0063] Figure 3The diagram illustrates one embodiment of the connection between the boot module and the on-chip bus within the target chip. As shown, the boot module should be connected to the on-chip bus. Subsequently, the boot module can be connected to the Flash memory via the on-chip bus to read the boot program stored in the Flash memory. It should be understood that the boot program in the Flash memory should be compatible with the target chip. For example, a corresponding boot program can be designed according to the type of the target chip and burned into the Flash memory. The boot program in the Flash memory generally consists of several boot instructions. These boot instructions can be used to initialize and configure the chip components within the target chip. It should be noted that the initialization and configuration of the chip components is mainly for the purpose of initializing the target chip's boot process; for details, please refer to the description of chip boot configuration in the background section above.

[0064] To enable rapid booting of the target chip, the Flash memory should be configured in continuous read mode. Only when the Flash memory is configured in continuous read mode can the boot module be controlled to enter the instruction read and execution operation state. The method for configuring the Flash memory in continuous read mode can be selected according to actual needs; an example is given below.

[0065] In one embodiment of the present invention, the Flash memory is connected to the on-chip bus via a QSPI controller, wherein,

[0066] When the Flash memory is configured to continuous read mode by the QSPI controller, the Flash memory is configured to at least four-wire fast continuous read mode via the boot module or Jtag interface. After the Flash memory is configured to four-wire fast continuous read mode, the QSPI controller is configured to Xip mode.

[0067] When the Flash memory is configured to four-wire fast continuous read mode via the Jtag interface, the boot module is in a reset state.

[0068] Figure 3The diagram illustrates an embodiment where a Flash memory is connected to an on-chip bus via a QSPI (Queued SPI) controller. In this case, the Flash memory should meet the QSPI operating mode to be compatible with the QSPI controller. The Flash memory, QSPI controller, and on-chip bus can adopt existing common forms. For example, the Flash memory should at least meet the four-wire fast continuous read mode. When the Flash memory is configured in four-wire fast continuous read mode, it is four times faster than ordinary Flash data reading and can read continuously. Therefore, data can be read from the Flash memory quickly, which greatly improves the startup efficiency of the target chip and greatly shortens the startup time of the target chip.

[0069] It should be noted that when configuring a Flash memory to enter four-wire fast continuous read mode, Flash commands should generally be used to configure the Flash memory. The configuration method will differ depending on the type of Flash memory. For a given Flash memory, mode configuration can be achieved through different methods in conjunction with the QSPI controller. The configuration method should be related to the type of Flash memory. For example, after determining the type of Flash memory, the boot module can configure the Flash memory mode via the on-chip bus and QSPI controller, or the JTAG interface can be used in conjunction with the on-chip bus and QSPI controller. The specific method and process for configuring the Flash memory to enter four-wire fast continuous read mode are consistent with existing technologies and will not be elaborated here.

[0070] In practice, when configuring the Flash memory to four-wire fast continuous read mode, first configure the Flash memory to four-wire fast continuous read mode, and then configure the QSPI controller to Xip (Execute In Place) mode.

[0071] As explained above, during the design phase of the target chip, once the type of Flash memory is determined, the boot module is generally also determined accordingly; that is, the boot module should be related to the type of Flash memory within the target chip. However, during the tape-out phase, if the type of Flash memory within the target chip changes, the boot module will become incompatible with the Flash memory. Consequently, the boot module cannot configure the Flash memory, meaning it cannot configure the Flash memory for four-wire fast continuous read mode.

[0072] When the type of Flash memory changes, causing the boot module to be unable to configure the Flash memory, the boot program in the Flash memory is still consistent with the design phase. Therefore, the boot instructions in the Flash memory can still be read and parsed by the boot module. That is, when the Flash memory is configured in four-wire fast continuous read mode, the boot module can read the boot instructions in the Flash memory via the on-chip bus, and then parse the boot instructions returned by the on-chip bus.

[0073] When the aforementioned Flash memory type changes, in one embodiment of the present invention, the Flash memory can be configured to enter a four-wire fast continuous read mode via the Jtag interface. Specifically, when configuring the Flash memory to enter the four-wire fast continuous read mode via the Jtag interface, an external MCU can be used to operate the Jtag, thereby configuring the Flash memory through the Jtag interface to enable the Flash memory to enter the four-wire fast continuous read mode. Specifically, when configuring the Flash memory using the Jtag interface, the operating mode configuration of the Flash memory should be implemented according to the Flash memory configuration method. As can be seen from the above description, the Flash memory mode can be configured via Flash commands, and the Flash commands used for configuration can be obtained from the Flash memory's manual, etc. Similar to the above method of using the boot module to put the Flash memory into four-wire fast continuous read mode, when configuring the Flash memory into four-wire fast continuous read mode via the JTAG interface, the QSPI controller should also be configured into Xip mode. The method and process of configuring the QSPI controller into Xip mode can generally be consistent with existing technologies, depending on the type of QSPI controller and its datasheet, and will not be elaborated here.

[0074] When configuring the Flash memory to enter the four-wire fast continuous read mode via the JTAG interface, the boot module should be in a non-working state. If the boot module is in a reset state, specifically, when the target chip starts up, it must first be reset. At this time, the boot module should also be reset under the boot module reset control signal i_boot_rst_n. After the boot module reset is canceled, the boot module can enter the working state and can enter the instruction read and execute operation state. When the boot module is in a reset state, the boot module reset control signal i_boot_rst_n should be in an invalid state. At this time, the boot module is in a non-working state.

[0075] It should be noted that when configuring the Flash memory to enter four-wire fast continuous read mode via the boot module, the boot module will enter the instruction read execution operation state after the Flash memory enters four-wire fast continuous read mode. However, when configuring the Flash memory to enter four-wire fast continuous read mode via the JTAG interface, the boot module should be configured to change from the reset state to the unreset state after the Flash memory enters four-wire fast continuous read mode, and then enter the instruction read execution operation state after unreset. Of course, as can be seen from the above, the QSPI controller should also be configured to enter Xip mode before the boot module enters the instruction read execution operation state.

[0076] Since initialization and configuration of the chip components are required, after entering the instruction read / execution operation state, the boot module should initiate an instruction read / execution request to the on-chip bus, and based on the instruction read / execution request, first read the boot instruction from the Flash memory, and then perform initialization and configuration of the chip components based on the read boot instruction. In specific implementation, each instruction read / execution request should include the instruction read request and / or the corresponding boot configuration execution request.

[0077] For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module. Specifically, according to the instruction read request, the Flash memory returns the boot instruction to the on-chip bus via the QSPI controller. Afterwards, the on-chip bus generates a boot instruction read response and returns it to the boot module; that is, the returned boot instruction is returned to the boot module in the form of a boot instruction read response. Therefore, an instruction read request specifically refers to a request to read the boot instruction from the Flash memory. In practice, when the boot program is burned into the Flash memory, the storage address of each boot instruction in the Flash memory can be determined. Therefore, based on the type of the target chip and the boot requirements, the boot module can generate a corresponding instruction read request, and the corresponding boot instruction can be read based on the generated instruction read request.

[0078] In practice, after entering the instruction read / execution state, the boot module uses a given address as the starting address and reads the boot instruction corresponding to that starting address via the on-chip bus. Subsequently, for the next instruction read request, the boot module updates the address corresponding to the previous instruction read request to obtain a new address. For example, it might add 4 to the address corresponding to the previous instruction read request to obtain the new address. Then, based on the new address, it reads the boot instruction corresponding to the new address via the on-chip bus, thus reading the boot instruction at the corresponding address from the Flash memory. It is understandable that the specific update method when obtaining the new address is related to the storage settings of the boot instruction in the Flash memory; the specific method of updating the new address is determined by whether it can effectively read the corresponding boot instruction.

[0079] After reading the boot command returned by the boot command on the on-chip bus, the boot module immediately parses the boot command. During the parsing of the boot command, the main task is to obtain the corresponding instruction information. After that, the boot module generates a boot configuration execution request based on the parsing of the boot command. The generated boot configuration execution request should be used to configure the chip components connected to the on-chip bus via the on-chip bus. Specifically, the boot configuration of the chip components is to initialize the corresponding chip components.

[0080] In practice, multiple boot instructions in the Flash memory can be read one by one through multiple instruction read requests. Then, the corresponding boot instruction is executed based on the boot configuration execution request. When the boot instruction returned by the on-chip bus is a stop state instruction, the boot module enters the stop working state. At this time, it means that the boot module has completed the configuration or initialization of the chip components of the target chip.

[0081] As can be seen from the above description, when booting the target chip, it is not necessary to move the boot program in the Flash memory to the ROM and then jump to the ROM for execution. Instead, it is directly read from the Flash memory and executed directly by the boot module. After executing one boot instruction, the next boot instruction is read. This saves the time of program transfer and shortens the boot time of the target chip.

[0082] In one embodiment of the present invention, the instruction read and execution request initiated by the boot module to the on-chip bus is a serial protocol request, wherein,

[0083] When the boot module initiates an instruction read and execution request to the on-chip bus, it can only initiate the next instruction read request or startup configuration execution request to the on-chip bus after receiving the boot instruction read response returned by the on-chip bus.

[0084] When the instruction read execution request initiated by the boot module to the on-chip bus is a boot configuration execution request, the boot module can only initiate the next instruction read request or boot configuration execution request to the on-chip bus after receiving the boot configuration execution response returned by the on-chip bus.

[0085] It is understandable that when the instruction read execution request is a serial protocol request, the above state can be satisfied: one boot instruction is executed before the next boot instruction is read, thereby improving the reliability of the target chip's boot process; when a boot failure occurs, the boot process of the target chip can be traced.

[0086] In practice, the chip boot process where the boot module configures the Flash memory to enter the four-wire fast continuous read mode is called the self-boot mode, while the chip boot process where the Flash memory is configured to enter the four-wire fast continuous read mode via the JTAG interface is called the semi-interactive boot mode. The following section will combine... Figure 1 and Figure 3 Examples are given for the auto-start mode and the semi-interactive start mode.

[0087] Specifically, the boot module detects the external input mode control signal i_boot_mcu_sel to determine the type of boot mode selected by the target chip, and then decides whether to skip the configuration part of the boot module. Specifically, if the mode control signal i_boot_mcu_sel is 0, the self-boot mode is selected, and the boot module configures the Flash memory to enter the four-wire fast continuous read mode and configures the QSPI controller to enter the Xip mode. After that, the boot module is controlled to enter the instruction read and execute operation state. If the mode control signal i_boot_mcu_sel is 1, the semi-interactive boot mode is selected, and the Flash memory is configured to enter the four-wire fast continuous read mode through the JTAG interface and the QSPI controller is configured to enter the Xip mode. After that, the boot module is controlled to enter the instruction read and execute operation state.

[0088] Depend on Figure 1 It can be seen that when the target chip starts up in self-boot mode, the boot process includes:

[0089] Step 1: Inform the boot module that this boot is in auto-boot mode by setting the mode control signal i_boot_mcu_sel = 0. Then, check the reset status control signal i_boot_rst_n loaded onto the boot module. When i_boot_rst_n is 0, it indicates a reset state, and the boot module is in a non-working state. When i_boot_rst_n is 1, it indicates that the reset state has been removed, and the boot module should enter the working state.

[0090] Depend on Figure 1 It can be seen that when i_boot_rst_n is 1, then proceed to step 2; otherwise, maintain the current state. Figure 1 The original state of the contents shall be maintained.

[0091] Step 2: Configure the boot module to enter the four-wire fast continuous read mode for the Flash memory, and configure the QSPI controller to enter the Xip mode.

[0092] Step 3: The boot module enters the instruction read and execute operation state;

[0093] Step 4: The boot module sends a read request to the on-chip bus;

[0094] Step 5: The on-chip bus sends the read request to the QSPI controller;

[0095] Step 6: The QSPI controller sends the request to the Flash memory;

[0096] Step 7: The Flash memory returns the read data to the QSPI controller according to the command;

[0097] Step 8: The QSPI controller returns the read data to the on-chip bus;

[0098] Step 9: The on-chip bus returns the read data to the boot module;

[0099] Step 10: The boot module executes instructions based on the type of read data instruction, typically by sending a write request to the on-chip bus.

[0100] Step 11: The on-chip bus sends the write request information to the corresponding chip component. The chip component is mounted on the on-chip bus. Of course, the chip component can also be mounted on the on-chip bus through a relay component. The connection status between the chip component and the on-chip bus is based on whether the chip component can be accessed through the on-chip bus.

[0101] Step 12: The chip component returns a write response to the on-chip bus;

[0102] Step 13: The on-chip bus returns a write response to the boot module;

[0103] Step 14: The boot module receives the write response, and one instruction is executed.

[0104] Step 15: Start executing again from step 4); until the stop state instruction is executed, the boot module finishes running, enters the stop state, and no longer performs any operations.

[0105] As explained above, the instruction read request is a read request, which mainly reads the boot instruction from the Flash memory, while the boot configuration execution request is a write request, which mainly writes the data related to the boot instruction into the corresponding chip component.

[0106] Depend on Figure 1 It can be seen that when the target chip boots based on the semi-interactive boot mode, the boot process includes:

[0107] Step 20: Inform the boot module that this boot is in semi-interactive boot mode by setting the mode control signal i_boot_mcu_sel = 1. Then, check the reset status control signal i_boot_rst_n loaded into the boot module. If i_boot_rst_n is 1, proceed to step 21; otherwise, maintain the current state. Figure 1 The original state of the contents shall be maintained.

[0108] Step 21: Configure the external MCU to enter the four-wire fast continuous read mode of the Flash memory through the Jtag interface, and configure the Qspi controller to enter the Xip mode.

[0109] Step 22: Cancel the reset of the boot module and configure the boot module to enter the instruction read and execute operation state;

[0110] Step 23: The boot module sends a read request to the on-chip bus;

[0111] Step 24: The on-chip bus sends the read request to the QSPI controller;

[0112] Step 25: The QSPI controller sends the request to the Flash memory;

[0113] Step 26: The Flash memory returns the read data to the QSPI controller according to the command;

[0114] Step 27: The QSPI controller returns the read data to the on-chip bus;

[0115] Step 28: The on-chip bus returns the read data to the boot module;

[0116] Step 29: The boot module executes instructions based on the type of read data instruction, typically by sending a write request to the on-chip bus.

[0117] Step 30: The on-chip bus sends the write request information to the corresponding chip components, which are mounted on the on-chip bus.

[0118] Step 31: The chip component returns a write response to the on-chip bus;

[0119] Step 32: The on-chip bus returns a write response to the boot module;

[0120] Step 33: The boot module receives the write response, and one instruction is executed.

[0121] Step 34: Restart from step 23) and continue execution until the stop state instruction is reached. The boot module has finished running and enters the stop state, where it will no longer perform any operations.

[0122] Furthermore, if the target chip cannot boot from the boot module, the Jtag interface is used to configure the chip components within the target chip until the boot requirements of the target chip are met.

[0123] It is understandable that after the target chip is fabricated, errors may occur in the boot module. In this case, the boot module cannot read the boot instructions from the Flash memory and execute the driver for the target chip, meaning the target chip cannot boot based on the boot module. To enable the target chip to boot, in practice, an external MCU can be used to configure the chip components within the target chip via a JTAG interface until the boot requirements of the target chip are met.

[0124] As explained above, after the boot program is stored in the Flash memory, the chip components within the target chip can be configured using the JTAG interface, depending on the type of the target chip. Specifically, configuring the chip components refers to completing the initialization process described above. The method and process of initializing the chip components within the target chip using the JTAG interface can be consistent with existing technologies, focusing on enabling the target chip to boot; details will not be elaborated here. It should be noted that the JTAG interface operates at a relatively low clock frequency; therefore, the boot speed of the target chip is slower using this method.

[0125] It should be noted that when there are no errors in the boot module, but the type of Flash memory used in the tape-out stage is different from the type of Flash memory used in the design stage, the above-mentioned semi-automatic interactive boot mode should be used for the target chip.

[0126] In one embodiment of the present invention, the instruction read execution request includes a request validity identifier signal xx2yy_req_valid, a request address xx2yy_req_addr, a request data xx2yy_req_data, a request write granularity status signal xx2yy_req_strb, a request type signal xx2yy_req_type, and a request read granularity status signal xx2yy_req_rsize;

[0127] When the request type signal xx2yy_req_type is in the first valid level state, the instruction read execution request is an instruction read request;

[0128] When the request type signal xx2yy_req_type is in the second valid level state, the instruction read execution request is the start configuration execution request.

[0129] Specifically, the request validity flag xx2yy_req_valid primarily indicates the validity status of the instruction read and execute request. Figure 5 The document illustrates an embodiment where the request validity flag signal xx2yy_req_valid is active high. Specifically, when the request validity flag signal xx2yy_req_valid is active, the on-chip bus will confirm the existence of a valid instruction read / execution request. Subsequently, the instruction read / execution request can be sent to the Flash memory via the QSPI controller.

[0130] To improve performance, the data width of the request data xx2yy_req_data should be at least 32 bits. Of course, the data width of the request data xx2yy_req_data can also be 64 bits. The address width of the request address xx2yy_req_addr and the data width of the request data xx2yy_req_data can generally be selected according to actual needs, based on meeting the interaction requirements between the boot module and the Flash memory, as well as the chip components connected to the on-chip bus. For example, the address width of the request address xx2yy_req_addr can be 32 bits. Figure 5 The image shows an embodiment where the address width of the request address xx2yy_req_addr and the data width of the request data xx2yy_req_data are both 32 bits.

[0131] The request type signal xx2yy_req_type is used to identify the request type of the read execution request in the instruction, such as whether the read execution request is a write request or a read request. Figure 5 The diagram illustrates one embodiment where a high level indicates a write request for the instruction read execution request, and a low level indicates a read request for the instruction read execution request. Figure 5 In the above context, when the request type signal xx2yy_req_type is high and the request validity flag signal xx2yy_req_valid is valid, the instruction read execution request can be determined to be a valid write request. Other cases can be found in the following references. Figure 5 As explained here, examples will not be provided one by one.

[0132] When the instruction read execution request is a write request, the write request granularity is set via the write granularity status signal xx2yy_req_strb. Furthermore, the write granularity status signal xx2yy_req_strb can be omitted within the instruction read execution request itself. If the instruction read execution request type is fixed as a read request, the write granularity status signal xx2yy_req_strb can be omitted. When the instruction read execution request includes the write granularity status signal xx2yy_req_strb, its data width can be one-eighth of the data width of xx2yy_req_data. If the data width of the requested data xx2yy_req_data is at least 32 bits, the width of the write granularity status signal xx2yy_req_strb can be 4 bits. Figure 5 As shown.

[0133] When the request type is a read request, the granularity of the read request can be set via the read granularity status signal `xx2yy_req_rsize`. Furthermore, the read granularity status signal `xx2yy_req_rsize` can be omitted within an instruction read execution request. For example, if the request type of the instruction read execution request is fixed as a write request, the read granularity status signal `xx2yy_req_rsize` can be omitted. When the instruction read execution request includes the read granularity status signal `xx2yy_req_rsize`, its size can be 2 bits. In this case, a read granularity status signal `xx2yy_req_rsize` of 00 indicates a 1-byte read; read granularity status signals `xx2yy_req_rsize` of 01, 10, and 11 indicate 2-byte, 4-byte, and 8-byte reads, respectively.

[0134] In practical implementation, a corresponding instruction read and execute request can be generated based on the request requirements of the boot module. The content of the instruction read and execute request can be set in the manner described above. For example, the target object connected via the on-chip bus can be determined based on the request address xx2yy_req_addr.

[0135] Figure 5 The document also illustrates one embodiment of the startup configuration execution response. Figure 5In the diagram, yy2xx_ack_valid is the response validity flag signal. The validity of the response information of the current target object can be identified by using the response validity flag signal yy2xx_ack_valid. When the response validity flag signal yy2xx_ack_valid is high, it indicates that the response information of the target object is valid; otherwise, it is invalid.

[0136] Figure 5 In this context, yy2xx_ack_excp is a response exception flag. When a response exception occurs, the response exception flag yy2xx_ack_excp is in a valid state. Figure 5 In this context, the exception response flag yy2xx_ack_excp is active high; that is, when an exception occurs, the exception response flag yy2xx_ack_excp is high. Furthermore, Figure 5 In this context, clk is the clock signal, and rst_n is the reset signal.

[0137] As can be seen from the above description, when the boot module reads the boot instruction from the Flash memory, the on-chip bus returns the boot instruction to the boot module with a boot instruction read response. Specifically, the boot instruction read response and the boot configuration execution response have the same format. For details on the boot instruction read response, please refer to the above description of the boot configuration execution response, which will not be repeated here.

[0138] In practice, for any startup configuration execution response and startup instruction read response, once the response validity flag yy2xx_ack_valid is valid, the response data yy2xx_ack_data and the response exception flag yy2xx_ack_excp are retained until the request validity flag xx2yy_req_valid in the next instruction read execution request is valid.

[0139] In one embodiment of the present invention, the boot instructions stored in the Flash memory further include NOP (no null) instructions, SETBASEH instructions, SETBASEL instructions, DELAY instructions, SETW instructions, WR.1 instructions, WR.2 instructions, WR.4 instructions, and / or WR.8 instructions, wherein...

[0140] After receiving and parsing the NOP empty instruction, the boot module initiates a next instruction read request to the on-chip bus after the next clock cycle based on the data in the NOP empty instruction.

[0141] After receiving and parsing the SETBASEH instruction, the boot module obtains the high-order base address of the write I / O device.

[0142] After receiving and parsing the SETBASEL instruction, the boot module obtains the low-order base address of the write I / O device.

[0143] After receiving and parsing the DELAY instruction, the boot module counts and waits until the count value corresponds to the delay time in the DELAY instruction. After that, the boot module sends a request to the on-chip bus to read the next instruction.

[0144] After receiving and parsing the SETW command, the boot module performs continuous write operations on the chip components connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0145] After receiving and parsing the WR.1 command, the boot module performs a write operation of 1 byte at a time on the chip component connected to the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0146] After receiving and parsing the WR.2 command, the boot module performs a 2-byte write operation on the chip component connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0147] After receiving and parsing the WR.4 instruction, the boot module performs a 4-byte write operation on the chip component connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus.

[0148] After receiving and parsing the WR.8 command, the boot module performs an 8-byte write operation on the chip component connected to the on-chip bus and waits for the boot configuration execution response returned by the on-chip bus.

[0149] In practical implementation, when designing the boot program, the corresponding boot program can be generated using the aforementioned boot instructions based on the type of the target chip. Each boot instruction can be used to initialize the chip components. The following example illustrates the boot instructions with a data width of 32 bits. It is understood that the boot module operates under a clock signal. Therefore, for a given boot module, its clock cycle can be determined. When the boot instruction is a NOP (no-op) instruction, the boot module can initiate a next instruction read request to the on-chip bus in the next clock cycle.

[0150] Specifically, in all startup instructions, the lower 8 bits (7:0) are the opcode, i.e. the instruction type; Inst is an abbreviation for instruction, Inst0 is the first instruction (32-bit user-defined instruction), Inst1 represents the second instruction (32-bit write data), and Inst2 represents the third instruction (32-bit write data).

[0151]

[0152]

[0153]

[0154] In the table above, the NOP instruction is the NOP empty instruction, and the STOP instruction is the stop state instruction. The NOP empty instruction, the stop state instruction, the SETBASEH instruction, and the SETBASEL instruction each contain one instruction. The SETW instruction can contain three instructions. For example, in the SETW instruction, Inst0 is the first instruction, Inst1 is the second instruction, and Inst2 is the third instruction. Other cases can be referred to here for explanation, and will not be listed and explained one by one here.

[0155] Figure 4 The image shows an embodiment of the state machine for the boot module's operating state. The following section will discuss this in conjunction with... Figure 4 The working status of the boot module is described in detail.

[0156] IDLE state: The IDLE state is the initial state after the boot module is reset. If it is in auto-boot mode, i.e., boot_mcu_sel is 0, after releasing the boot reset, when the configuration part of the boot module finishes running, it will give a prompt signal spi_done=1, and then enter the READ_INST0 state in the next cycle; if it is in semi-interactive boot mode, i.e., boot_mcu_sel is 1, and after releasing the reset, it will enter the READ_INST0 state in the next cycle.

[0157] READ_INST0 state: Read instruction 1 state. The boot module initiates a read request to the on-chip bus to read the boot instruction in the Flash memory. As can be seen from the above description, depending on the boot instruction, some may require reading instruction 2 or instruction 2 and instruction 3. Specifically, the boot instruction read back here is the write data to be written to the chuck component.

[0158] WAIT_INST0 state: waiting for the response data returned by the Flash memory, which is instruction 1, i.e. the aforementioned start instruction.

[0159] READ_DATA1 state: If writing 1 byte, 2 bytes, or 4 bytes, instruction 2 is required, which means writing the lower 4 bytes of data;

[0160] WAIT_DATA1 state: waiting for instruction 2, that is, waiting to write data;

[0161] READ_DATA2 status: If writing 8 bytes, instruction 3 is required, which means writing the high 4 bytes of data;

[0162] WAIT_DATA2 state: waiting for instruction 3, which is the high 4 bytes of writing data;

[0163] WRITE state: After the boot module receives the returned boot command and write data, the boot module initiates a write request to the on-chip bus to write the data into the register of the chip component connected to the on-chip bus;

[0164] WRITE_RESP state: waiting for write response; if there is no response exception and the write is complete, it will jump to READ_INST0 state to read the next instruction; if there is no response exception and the write is not complete, it will jump back to READ_DATA1 to read the data to be written.

[0165] ERROR state: An error state that occurs when an abnormal response is received in any of the waiting states; and it remains in this state indefinitely.

[0166] STOP state: When the read-back instruction is a STOP instruction, the system will jump to this state and remain in this state.

[0167] DELAY state: When the startup instruction read is a DELAY instruction, it will jump to this state and keep counting. When the count reaches the value in the DELAY instruction, it will jump to the READ_ISNT0 state to read the next instruction. Otherwise, it will continue to remain in this state.

[0168] based on Figure 4 As can be seen from the above description, the boot module operates according to the state machine described above, which enables the target chip to be started.

[0169] From the above description, a highly reliable chip of the present invention can be obtained. Specifically, the chip is started using the chip startup method described above, and the chip includes:

[0170] Flash memory, which stores at least the boot program, and is connected to the on-chip bus via the Qspi controller;

[0171] The boot module, connected to the on-chip bus, can configure the Flash memory in four-wire fast continuous read mode. After configuring the Flash memory in four-wire fast continuous read mode, the QSPI controller can be configured in Xip mode.

[0172] When the control chip starts up, the control boot module enters the instruction reading and execution operation state, where...

[0173] After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a boot configuration execution request corresponding to the instruction read request;

[0174] For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module;

[0175] For any boot command returned via the on-chip bus, the boot module immediately parses the boot command and then sends a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request.

[0176] When the on-chip bus returns a stop command, the boot module enters a stopped working state.

[0177] Specifically, the chip refers to the target chip mentioned above. In addition, there is usually an MCU unit outside the chip, which can take the form of a commonly used MCU. The functions of the Flash memory and boot module within the chip, and their cooperation in enabling the chip to boot, are explained in the above description.

[0178] In one embodiment of the present invention, the boot module includes a configuration unit and a read / execute unit, wherein,

[0179] The boot module includes a configuration unit and a read / execute unit, wherein...

[0180] When the configuration chip starts up, the external MCU cancels the reset of the boot module. Then, the configuration unit in the boot module configures the Flash memory to four-wire fast continuous read mode and the QSPI controller to Xip mode via the on-chip bus. Alternatively, the external MCU unit controls the boot module to be in a reset state. Then, at least through the JTAG interface, the Flash memory is configured to four-wire fast continuous read mode and the QSPI controller is configured to Xip mode.

[0181] When the Flash memory is configured in four-wire fast continuous read mode and the QSPI controller is in Xip mode, the MCU unit cancels the boot module reset to at least configure the read execution unit to enter the instruction read execution operation state.

[0182] Figure 3 The diagram illustrates one embodiment of the boot module. As shown, the boot module should include a configuration unit and a read execution unit. The configuration unit uses the on-chip bus to configure the Flash memory in four-wire fast continuous read mode and the QSPI controller in Xip mode. The method and process of configuring the Flash memory in four-wire fast continuous read mode can be found in the above description and will not be repeated here. Furthermore, as described above, the Flash memory can also be configured in four-wire fast continuous read mode and the QSPI controller can be configured in Xip mode via the JTAG interface.

[0183] Specifically, the read execution unit enters the instruction read execution operation state, which means that the read execution unit performs the corresponding read execution operation in the instruction read execution operation state. The specific process of the instruction read execution operation state can be referred to the above description, and will not be repeated here.

Claims

1. A highly reliable chip boot method, characterized in that, The chip startup method includes: For any target chip to be booted, a boot module is set in at least the target chip, wherein the boot module is connected to the QSPI controller via an on-chip bus, and the QSPI controller is adapted to be connected to the Flash memory storing the boot program. When booting the target chip, the Flash memory must be configured in continuous read mode at least. Afterward, the boot module is controlled to enter the instruction read and execution operation state, where... After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a boot configuration execution request corresponding to the instruction read request; For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module; For any boot command returned via the on-chip bus, the boot module immediately parses the boot command and then sends a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request. When the on-chip bus returns a stop command, the boot module enters a stop working state. When the Flash memory is configured to continuous read mode by the QSPI controller, the Flash memory is configured to at least four-wire fast continuous read mode via the boot module or Jtag interface. After configuring the Flash memory to four-wire fast continuous read mode, the QSPI controller is configured to Xip mode. When the Flash memory is configured to four-wire fast continuous read mode via the Jtag interface, the boot module is in a reset state.

2. The high-reliability chip startup method according to claim 1, characterized in that: The instruction read and execution request initiated by the boot module to the on-chip bus is a serial protocol request, in which... When the boot module initiates an instruction read and execution request to the on-chip bus, it can only initiate the next instruction read request or startup configuration execution request to the on-chip bus after receiving the boot instruction read response returned by the on-chip bus. When the instruction read execution request initiated by the boot module to the on-chip bus is a boot configuration execution request, the boot module can only initiate the next instruction read request or boot configuration execution request to the on-chip bus after receiving the boot configuration execution response returned by the on-chip bus.

3. The high-reliability chip startup method according to claim 2, characterized in that: The instruction read execution request includes a request validity identifier signal xx2yy_req_valid, a request address xx2yy_req_addr, a request data xx2yy_req_data, a request write granularity status signal xx2yy_req_strb, a request type signal xx2yy_req_type, and a request read granularity status signal xx2yy_req_rsize; When the request type signal xx2yy_req_type is in the first valid level state, the instruction read execution request is an instruction read request; When the request type signal xx2yy_req_type is in the second valid level state, the instruction read execution request is the start configuration execution request.

4. The high-reliability chip startup method according to claim 3, characterized in that: The responses to the startup configuration execution and startup command reading are as follows: This includes the response validity flag yy2xx_ack_valid, the response data yy2xx_ack_data, and the response exception flag yy2xx_ack_excp, among which, For any startup configuration execution response and startup command read response, once the response validity flag yy2xx_ack_valid is valid, the response data yy2xx_ack_data and the response exception flag yy2xx_ack_excp are retained until the request validity flag xx2yy_req_valid in the next command read execution request is valid.

5. The high-reliability chip startup method according to claim 2, characterized in that: The boot instructions stored in the Flash memory also include the NOP empty instruction, SETBASEH instruction, SETBASEL instruction, DELAY instruction, SETW instruction, WR.1 instruction, WR.2 instruction, WR.4 instruction, and / or WR.8 instruction, among which... After receiving and parsing the NOP empty instruction, the boot module initiates a next instruction read request to the on-chip bus after the next clock cycle based on the data in the NOP empty instruction. After receiving and parsing the SETBASEH instruction, the boot module obtains the high-order base address of the write I / O device. After receiving and parsing the SETBASEL instruction, the boot module obtains the low-order base address of the write I / O device. After receiving and parsing the DELAY instruction, the boot module counts and waits until the count value corresponds to the delay time in the DELAY instruction. After that, the boot module sends a request to the on-chip bus to read the next instruction. After receiving and parsing the SETW command, the boot module performs continuous write operations on the chip components connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus. After receiving and parsing the WR.1 command, the boot module performs a write operation of 1 byte at a time on the chip component connected to the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus. After receiving and parsing the WR.2 command, the boot module performs a 2-byte write operation on the chip component connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus. After receiving and parsing the WR.4 instruction, the boot module performs a 4-byte write operation on the chip component connected to the on-chip bus via the on-chip bus, and waits for the boot configuration execution response returned by the on-chip bus. After receiving and parsing the WR.8 command, the boot module performs an 8-byte write operation on the chip component connected to the on-chip bus and waits for the boot configuration execution response returned by the on-chip bus.

6. The high-reliability chip startup method according to any one of claims 1 to 5, characterized in that: If the target chip cannot boot from the boot module, the Jtag interface is used to configure the chip components within the target chip until the boot requirements of the target chip are met.

7. A highly reliable chip, characterized in that, The chip is started using the chip startup method according to any one of claims 1 to 6, and the chip comprises: Flash memory, which stores at least the boot program, and is connected to the on-chip bus via the Qspi controller; The boot module, connected to the on-chip bus, can configure the Flash memory in four-wire fast continuous read mode. After configuring the Flash memory in four-wire fast continuous read mode, the QSPI controller can be configured in Xip mode. When the control chip starts up, the control boot module enters the instruction reading and execution operation state, where... After entering the instruction read and execute operation state, the boot module initiates an instruction read and execute request to the on-chip bus, wherein the instruction read and execute request includes an instruction read request and / or a boot configuration execution request corresponding to the instruction read request; For any instruction read request, the on-chip bus reads the boot instruction at the corresponding address from the Flash memory based on the instruction read request, and returns the read boot instruction to the boot module; For any boot command returned via the on-chip bus, the boot module immediately parses the boot command and then sends a corresponding boot configuration execution request to the on-chip bus to perform boot configuration on the chip components connected to the on-chip bus based on the boot configuration execution request. When the on-chip bus returns a stop command, the boot module enters a stopped working state.

8. The high-reliability chip according to claim 7, characterized in that, The boot module includes a configuration unit and a read / execute unit, wherein... When the configuration chip starts up, the external MCU unit cancels the reset of the boot module. Then, the configuration unit in the boot module configures the Flash memory to four-wire fast continuous read mode and the QSPI controller to Xip mode via the on-chip bus. Alternatively, the external MCU unit controls the boot module to be in a reset state. Then, at least through the JTAG interface, the Flash memory is configured to four-wire fast continuous read mode and the QSPI controller is configured to Xip mode. When the Flash memory is configured in four-wire fast continuous read mode and the QSPI controller is in Xip mode, the MCU unit cancels the boot module reset to at least configure the read execution unit to enter the instruction read execution operation state.

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