Master device, module detection method and computer readable medium

Abstract

The invention discloses a master device, a module detection method and a computer readable medium. The primary device comprises: a single wire interface SWi (602) for single wire connection to a secondary device; and a processor (608) configured to selectively connect the SWI (602) to a supply voltage during a charging phase and to connect the SWI (602) to the voltage detection circuit (606) during a subsequent sampling phase during which the voltage detection circuit (606) detects one or more voltages at the SWI (602); and determining whether the SWI module is present in the secondary device based on the detected one or more voltages.

Description

Technical Field

[0001] Various aspects of the present disclosure are generally directed to a single wire interface connection between a primary device and a secondary device, wherein a single wire interface (SWI) allows both charging of a secondary device by a primary device and data exchange between the primary device and the secondary device. Background Art

[0002] In certain applications, it may be preferable to utilize SWI to connect a master device to a slave device. SWI may provide a simple and inexpensive connection between devices, particularly when compared to more complex multi-wire bus connections. Despite the simplicity of a single wire, a single-wire connection may allow power transfer between devices (e.g., the master device charges the slave device) as well as data transfer between devices. For example, SWI may allow a master device to connect a slave device to a supply voltage for a module or component of the slave device to perform one or more operations. Typically, these one or more operations end with the slave device sending data to the master device, during which the master device disconnects from the supply voltage so that the voltage across the SWI may be selectively increased or decreased for data transfer. With respect to data transfer, SWI may allow, for example, bidirectional, half-duplex serial communication between a master device and a slave device.

[0003] A master device may be configured to connect to a variety of slave devices, and even configured within a specific model or type of slave device, and various configurations may exist. Therefore, the master device may need to perform one or more detection operations on the slave device, such as when connecting to the slave device via SWI. Specifically, the master device may need to determine whether its newly connected slave device includes one or more modules or features. Ideally, such determinations should be performed quickly using only pre-existing components on the master and slave devices and with minimal communication overhead. Summary of the invention

[0004] According to an embodiment of the present disclosure, a master device includes: a single-wire interface SWI for single-wire connection to a slave device; and a processor, which is configured to: selectively connect the SWI to a supply voltage during a charging phase and connect the SWI to a voltage detection circuit during a subsequent sampling phase, wherein during the sampling phase, the voltage detection circuit detects one or more voltages at the SWI; and determine whether a SWI module exists in the slave device based on the detected one or more voltages.

[0005] According to an embodiment of the present disclosure, a module detection method includes: selectively connecting a single-wire interface SWI to a supply voltage during a charging phase and connecting the SWI to a voltage detection circuit during a subsequent sampling phase, during which the voltage detection circuit detects one or more voltages at the SWI; and determining whether a SWI module exists in a secondary device based on the detected one or more voltages.

[0006] According to an embodiment of the present disclosure, a non-transitory computer-readable medium includes instructions, which, when executed, cause a processor to perform the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the accompanying drawings, the same reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the exemplary principles of the present disclosure. In the following description, various exemplary embodiments of the present disclosure are described with reference to the following drawings, in which:

[0008] Figure 1 depicts a simplified configuration of primary and secondary devices;

[0009] Figure 2 depicts the voltage across SWI during and after the charging phase;

[0010] Figure 3 depicts multiple voltage measurements taken for the charging phase, sampling phase, and steady-state phase;

[0011] Figure 4 For a slave device without a SWI module, the charging phase, the sampling phase, and the steady-state phase are depicted with respect to the voltage across the SWI;

[0012] Figure 5 depicts an exemplary voltage measurement as performed by an analog-to-digital converter (ADC);

[0013] Figure 6 depicts a master device including a SWI for single-wire connection to a slave device;

[0014] Figure 7 A first method of detecting a SWI module within a secondary device is described;

[0015] Figure 8 A second method of detecting a SWI module within a secondary device is described;

[0016] Fig. 9 A third method of detecting a SWI module in a secondary device is described;

[0017] Fig.10depicts an optional configuration in which a processor detects a SWI module based on samples acquired over a plurality of sampling phases;

[0018] Fig.11 An exemplary flow chart depicting the process described herein;

[0019] Fig.12 A method for detecting a SWI module through SWI is described; and

[0020] Fig.13 Determination of a faulty component (eg, an energy storage device) is depicted. DETAILED DESCRIPTION

[0021] The following detailed description refers to the accompanying drawings that show, by way of illustration, exemplary details and embodiments in which aspects of the disclosure may be practiced.

[0022] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations or designs.

[0023] Throughout the drawings, it should be noted that unless otherwise described, the same reference numbers are used to depict the same or similar elements, features, and structures.

[0024] The phrases "at least one" and "one or more" may be understood to include numerical quantities greater than or equal to one (e.g., one, two, three, four, [...], etc.). The phrase "at least one of..." with respect to a group of elements may be used herein to mean at least one element of the group consisting of these elements. For example, the phrase "at least one of..." with respect to a group of elements may be used herein to mean a selection of: one of the listed elements, one of a plurality of listed elements, a plurality of individual listed elements, or a plurality of individual listed elements.

[0025] The words "plurality" and "multiple" in the specification and claims expressly refer to quantities greater than one. Thus, any phrase that expressly invokes the aforementioned words to refer to a plurality of elements (e.g., "plurality [elements]," "multiple [elements]") expressly refers to more than one of the elements. For example, the phrase "plurality" may be understood to include a numerical quantity greater than or equal to two (e.g., two, three, four, five, [...], etc.).

[0026] The phrases "group", "set", "collection", "series", "sequence", "grouping", etc. in the specification and claims, if any, refer to a quantity equal to or greater than one, i.e., one or more. The terms "proper subset", "reduced subset" and "smaller subset" refer to a subset of a set that is not equal to the set, illustratively, to a subset of a set that contains fewer elements than the set.

[0027] As used herein, the term "data" may be understood to include information in any suitable analog or digital form, such as provided as a file, a portion of a file, a collection of files, a signal or stream, a portion of a signal or stream, a collection of signals or streams, etc. In addition, the term "data" may also be used to refer to a reference to information, such as in the form of a pointer. However, the term "data" is not limited to the above examples, and may take various forms to represent any information understood in the art.

[0028] For example, the term "processor" or "controller" used in this article can be understood as any type of technical entity that allows processing data. Data can be processed according to one or more specific functions performed by a processor or controller. In addition, the processor or controller used in this article can be understood as any type of circuit, such as any type of analog or digital circuit. The processor or controller can therefore be or include an analog circuit, a digital circuit, a mixed signal circuit, a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an integrated circuit, an application-specific integrated circuit (ASIC), etc. or any combination thereof. Any other type of implementation of each function described in more detail below can also be understood as a processor, a controller or a logic circuit. It should be understood that any two (or more) of the processors, controllers or logic circuits described in detail herein can be implemented as a single entity or the like with equivalent functions, and conversely, any single processor, controller or logic circuit described in detail herein can be implemented as two (or more) separate entities or the like with equivalent functions.

[0029] As used herein, "memory" is understood to be a computer-readable medium (e.g., a non-transitory computer-readable medium) in which data or information can be stored for retrieval. Thus, references to "memory" included herein may be understood to refer to volatile or non-volatile memory, including random access memory ("RAM"), read-only memory ("ROM"), flash memory, solid-state storage devices, magnetic tape, hard drives, optical drives, 3D XPoint TMetc. or any combination thereof. In this document, registers, shift registers, processor registers, data buffers, etc. are also included in the term "memory". The term "software" refers to any type of executable instructions, including firmware.

[0030] Unless explicitly stated, the term "transmitting" includes both direct transmission (point-to-point) and indirect transmission (via one or more intermediate points). Similarly, the term "receiving" includes direct reception and indirect reception. The term "communication" includes one or both of sending and receiving, i.e., one-way communication or two-way communication in one or both of the incoming and outgoing directions. The term "computing" includes "direct" computations via mathematical expressions / formulas / relationships as well as "indirect" computations via lookups or hash tables and other array indexing or searching operations.

[0031] Figure 1 A simplified configuration of a master device 102 and a slave device 104 is depicted. In the figure, the master device 102 and the slave device 104 are connected via a single wire interface (SWI) 105. The master device 102 may include an analog-to-digital converter (ADC) 106 (also referred to herein as a voltage detection circuit), which is connected to the SWI 105 during a sampling phase. The master device 102 may also include a general purpose input output unit (GPIO) 108 (e.g., such as a GPIO pin on a microcontroller), which is connected to the SWI 105 during a charging phase. The master device 102 may also include a voltage source (e.g., VCC) 110. The master device 102 may be configured to selectively connect the slave device 104 to the ADC 106 or the GPIO 108, such as by Figure 1 The switch depicted in , the switch may be implemented using any switching technology, whether transistor-based or otherwise, without limitation.

[0032] As described above, GPIO 108 as used herein may describe an input / output port characterized by being able to provide an additional supply voltage (e.g., different from the supply voltage of voltage source 110). In some configurations, ADC 106 and / or GPIO 108 may optionally be a module (e.g., a function, connection, pin, etc.) within a control device (such as a microcontroller). GPIO 108 may be considered a "strong" voltage source that may be used to selectively supply a predetermined voltage to SWI 105. As will be described in more detail, the voltage supplied by GPIO 108 may be relatively constant, independent of the current draw on SWI 105 (assuming the current draw is within the tolerance range of the GPIO / corresponding microcontroller), while the voltage supplied by voltage source 110 (e.g., VCC) may depend on the corresponding current draw, at least due to ohmic resistor 112. As will be described herein, these characteristics may be utilized to detect the presence or absence of SWI module 122 in slave device 104. As will be described in more detail herein, the voltage of the voltage source 110 and the voltage of the GPIO 108 can be selected based on a given implementation, and the principles and methods described herein can function over a wide range of parameters. The values ​​of the open circuit voltage of the GPIO 108 and the open circuit voltage of the voltage source 110 can be the same. Alternatively, the values ​​of the open circuit voltage of the GPIO 108 and the open circuit voltage of the voltage source 110 can be different. The relationship of the open circuit voltage of the GPIO 108 to the open circuit voltage of the voltage source 110 may affect the measurement threshold, for example, for determining whether the SWI module 122 is present. Those skilled in the art will understand how to set the relevant threshold voltage based on the voltage of the GPIO 108 and the voltage of the voltage source 110 and the expected current, capacitance, and resistance of the ohmic resistor as described herein.

[0033] In some implementations, voltage source 110 is used to power SWI module 122 and may be different from one or more other supply voltages that may be used to power device 120 itself (such as via one or more additional pins), which may include but are not limited to push-pull strong / weak voltage sources as further described herein.

[0034] SWI 105 can also be configured to selectively operate as a communication link between a primary device (102) and a secondary device (104). Figure 1105. The necessary switch network for selectively connecting to the voltage source 110 is not depicted. The connection to the voltage source 110 can be configured with an ohmic resistor 112. When the SWI module 122 is connected to the voltage source 110 via the SWI 105, current can flow. The current flowing in this way will cause a voltage drop across the ohmic resistor 112, and thus the ohmic resistor 112 can reduce the voltage level to be provided to the auxiliary device 104 via the SWI 105. In some implementations, the ohmic resistor helps to implement an open-drain output architecture in the auxiliary device 104.

[0035] The auxiliary device 104 can be any type of device capable of communicating using SWI, such as SWI 105. Non-limiting examples of such auxiliary devices 104 include mobile phones, printers, and / or water dispensers or water filtration systems. The auxiliary device 104 can be configured with any of a variety of components 120. Component 120 can be any component that achieves a specific purpose. Although any type of component can be used as component 120 in accordance with the present disclosure, non-limiting examples of such components include batteries, water filters, ink cartridges, etc. Because component 120 can generally be a battery, for simplicity, in most of the remainder of the present disclosure, component 120 may be described as a battery. However, such reference to batteries is for simplicity and is not intended to be limiting. Those skilled in the art will understand that the teachings described herein regarding SWI module detection are applicable to various SWI module types and are not limited to modules for batteries.

[0036] In certain configurations, it may be desirable to ensure that the component 120 meets a certain level of security or authenticity. That is, it may be desirable to ensure that the component 120 is an original component or is otherwise approved or certified by the manufacturer. To this end, and returning to the example where the component 120 is a battery, it may be desirable to ensure that the battery is an original or genuine battery. To this end, the various components 120 may be configured with a SWI module 122, which may be configured to perform verification or authentication functions for the component 120, for example, via SWI 105. Although the SWI module 122 is described herein as performing verification or authentication functions, the purpose of the SWI module may not include or be limited to verification or authentication. As described herein, it is more important to determine whether the component 120 is equipped with a SWI module 122 rather than the specific purpose or function of the SWI module 122 itself.

[0037] The SWI module 122 can utilize any of a variety of strategies to notify the primary device 102 that the component 120 within the secondary device 104 is authentic. For example, the SWI module 122 can utilize one or more cryptographic processes to provide a secret code to the primary device 102, wherein the secret code proves to the primary device 102 that the component 120 within the secondary device 104 is authentic.

[0038] The SWI module 122 may not be ubiquitous in all components 120 or slave devices 104, and therefore it may be necessary or advantageous for the primary device to detect whether the SWI module 122 is present within the slave device 104. As described above, it is desirable to perform this detection quickly with minimal communication overhead using only pre-existing components on the primary device 102 and the slave device 104.

[0039] The SWI module 122 may be conductively connected to an element 124, which may be generally understood as an energy storage device and may be configured, for example, as a capacitor. The element 124 may be configured to perform any of the following operations: receive and store charge from the SWI 105 (e.g., from the GPIO 108), power the SWI module 122, or smooth variations in the voltage across the SWI 105. The charge itself may be discharged or consumed by the SWI module 122.

[0040] When the master device 102 is connected to the slave device 104, the master device 102 may need to determine whether the SWI module 122 for the component 120 is present in the slave device 104. On a practical level, the presence of the SWI module 122 may require the master device 102 to participate in various communication steps that the master device 102 would not participate in if the slave device 104 did not have the SWI module 122. Therefore, the master device 102 may determine whether the slave device 104 includes the SWI module 122 when connected to the slave device 104.

[0041] Because SWI 105 allows at least half-duplex communication between the master device 102 and the slave device 104, in theory the master device 102 and the slave device 104 can participate in such a communication protocol: in this communication protocol, the master device 102 sends a request to the slave device 104, asking it to indicate whether the SWI module 122 exists, and the slave device responds accordingly. However, existing devices may not be configured for such a communication protocol, and enabling such communication may require software or even hardware updates. In contrast, the process for detecting the presence of the SWI module 122 as described herein requires less system memory, and the process can be executed faster than using a more complex communication protocol. Relatedly, the process as described herein reduces or eliminates the need for software and / or hardware updates, thereby reducing the total product cost. Therefore, it can be expected that the master device 102 detects the presence of the SWI module 122 not using an explicit communication protocol but using a detection process as described herein.

[0042] The master device 102 may more simply use one or more voltage measurements over the SWI 105 to detect the presence of the SWI module 122 within the slave device 104. Various pre-established protocols (e.g., software detection) may optionally be performed when the master device 102 connects with the slave device 104 via the SWI 105 (e.g., one or more power-on or boot-up activities). Thereafter, the master device 102 may selectively connect the SWI module 122 (if present) to the GPIO 108 via the SWI 105 during what will be described herein as a charging phase, during which power from the GPIO 108 will power the SWI module 122 and the element 124 will be charged. Figure 2 The voltage across SWI is depicted during a charging phase and a subsequent sampling phase, which will be described below.

[0043] That is, during the charging phase, the master device 102 connects the SWI 105 to the GPIO 108, which provides a supply voltage (which may be equal to or different from the voltage source 110) at the SWI 105. If the SWI module 122 and the element 124 are present, the element 124 is charged to a voltage equal to or close to the voltage at the GPIO 108 during the charging phase. Regardless of whether the SWI module 122 is present, it is expected that the voltage on the SWI 105 during the charging phase is close to or equal to the voltage of the GPIO 108.

[0044] After the charging phase, the master device 102 enters a sampling phase. During the sampling phase, the master device 102 disconnects the SWI 105 from the GPIO 108 and selectively connects the SWI 105 to the ADC 106. The ADC 106 can be configured to measure the voltage at the SWI 105 multiple times during the sampling phase. In this way, the ADC can be understood as a voltage detection circuit or a voltage measurement circuit. During the sampling phase, the SWI module 122 continues to be connected to the voltage source 110 via the SWI 105. If the SWI module 122 is present, the SWI module 122 typically begins to perform one or more operations that require current drawing during the sampling phase. Since the SWI module 122 causes a current draw on the SWI 105 from the voltage supply at the voltage source 110 (the SWI 105 is no longer connected to the GPIO 108, and thus the voltage source 110 defines the minimum voltage across the SWI 105 taking into account any voltage drop across its ohmic resistor), the current utilized by the SWI module 122 flows through the ohmic resistor 112, thereby creating a voltage drop compared to the voltage source 110. That is, the voltage provided to the SWI 105 by the master device 102 during the sampling phase is expected to be lower than the voltage of the voltage source 110 (e.g., VCC).

[0045] like Figure 1 As shown, the SWI module 122 can be connected to one or more passive components (components, capacitors) 124, which can be configured to store the charge received through the SWI 105 during the charging phase. The reduction in voltage provided by the master device 102 to the slave device 104 through the SWI 105 due to the voltage drop across the ohmic resistor 112 as described above causes at least a partial discharge of the component 124 (e.g., a capacitor), which causes the voltage across the SWI 105 to gradually decrease, and the rate of change of the voltage across the SWI 105 is largely determined by the amount of current drawn by the SWI module 122, the resistance of the ohmic resistor 112 (e.g., ohms), and the ability of the component 124 to store energy (e.g., the capacitance of the capacitor). The gradual decrease in voltage due to the above factors quickly reaches a steady state, in which a balance is reached between the current drawn by the SWI module 122 and the voltage drop caused by the discharge of the component 124.

[0046] Figure 3 Depicted are multiple voltage measurements taken at the ADC 106 for a charging phase 302 , a sampling phase 304 , and a steady-state phase 306 when a slave device 104 having a SWI module 122 is attached to the master device 102 via the SWI 105 .

[0047] In the charging phase 302, the slave device 104 is connected to the master device 102 via the SWI 105, and in particular to the voltage source 110 and the GPIO 108. In the charging phase 302, the SWI module 122 is in an idle state, during which the SWI module 122 draws only a small (e.g., very small, negligible) current, or may even draw no current. A charge may occur on the SWI 105 via the GPIO 108, and therefore the voltage across the SWI 105 is at or close to the voltage of the GPIO 108. For example, if the voltage at the GPIO 108 is 1.8V, the voltage across the SWI 105 will also be close to 1.8V. As can be seen from the charging phase 302, the voltage across the SWI 105 can remain relatively constant throughout the charging phase.

[0048] In the sampling phase 304, the slave device 104 continues to be connected to the master device 102 via the SWI 105. During the sampling phase 304, the master device disconnects the SWI 105 from the GPIO 108 and selectively connects the SWI 105 to the ADC 106. The SWI module 122 (if present) draws current from the voltage source 110 (the voltage source 110 and the GPIO 108 may have the same open circuit voltage, but alternatively, the GPIO may have a voltage slightly higher than VCC, such as in the case where the GPIO subsystem uses a power supply different from VCC without otherwise changing the principles and methods disclosed herein) through the SWI 105, which produces a voltage drop across the ohmic resistor 112. As a result, the ADC 106 measures a voltage across the SWI 105 that is less than the voltage of the voltage source 110. At the same time, the element 124 begins to discharge, which results in a gradual transition from the supply voltage to the steady-state voltage (e.g., curve). At any time during the sampling phase, the magnitude of the difference between the voltage across SWI 105 and the supply voltage (based on GPIO 108 ) depends on the resistance of ohmic resistor 112 , the current draw of SWI module 122 (or any other component or combination of components of the slave device), and the capacitance of element 124 .

[0049] During this sampling phase, ADC 106 makes one or more measurements of the voltage across SWI 105. These one or more measurements reflect one or more instantaneous voltages at various points along the curve where the voltage across SWI 105 transitions from the supply voltage at GPIO 108 to a steady-state voltage.

[0050] During the subsequent steady-state phase 306, an equilibrium state has been reached in which the current draw of the auxiliary device 104 is relatively constant and at least some of the charge in the element 124 has been discharged. Figure 3 It can be seen that the voltage across the SWI 105 remains constant or relatively constant during the steady-state phase 306 .

[0051] Figure 4 A charging phase 402, a sampling phase 404, and a steady-state phase 406 are depicted with respect to the voltage across the SWI 105, wherein the slave device 104 does not include the SWI module 122 and therefore draws little current during the sampling phase. Figure 3Similarly, SWI 105 is connected to GPIO 108. It would generally be expected that the voltage measured across SWI 105 during the charging phase would be equal to or substantially similar to the voltage at GPIO 108. Moving to the sampling phase 404, it would be expected that the slave device 104 lacking the SWI module 122 would draw no current (or perhaps only a very small current) during the sampling phase 404, so that almost no voltage drop would occur across the ohmic resistor 112. Therefore, it would be expected that the voltage across SWI 105 during the sampling phase 404 would be equal to or very close to the voltage of the voltage source 110 (note that SWI 105 is not connected to GPIO 108 during the sampling phase 404). Relatedly, because the absence of SWI module 122 implies the absence of capacitor 124, it would be expected that the transition between the GPIO voltage and the voltage of the voltage source 110 would have little to no curve change (assuming there is a difference; if there is no difference, the voltage will not change). Transitioning to the steady state phase 406 , and similarly, since the slave device 104 is not drawing current, the voltage across the SWI 105 remains constant during the steady state phase 406 .

[0052] In view of the above, and relying on the voltage measurements made by the ADC during the sampling phase, the processor of the master device 102 can determine whether the SWI module 122 is present in the slave device 104 . Figure 5 Depicted are exemplary voltage measurements 502, 504, and 506 performed by the ADC. Although only three voltage measurements are labeled, and each of these voltage measurements is performed at the beginning of the sampling phase, it can be seen from the image that more voltage measurements can be made and that voltage measurements can be performed at any point during the sampling phase. Similarly, as will be shown, less than three samples (e.g., 1 sample or 2 samples) may also be used.

[0053] Figure 6 Depicted Figure 1The main device 600 includes a SWI 602 for single-line connection to a slave device. The main device 600 also includes a processor 608, which is configured to: selectively connect the SWI 602 to a supply voltage (e.g., the voltage of the GPIO 108) during a charging phase and connect the SWI 602 to a voltage detection circuit 606 during a subsequent sampling phase, during which the voltage detection circuit 606 detects one or more voltages at the SWI 602; and determine whether there is a SWI module in the slave device based on the detected one or more voltages. The main device may also include a voltage supply circuit 607 and a voltage detection circuit 606, which may be configured to supply a supply voltage. The main device may also include a microcontroller or an application processor (such as a mobile application processor in a mobile phone), wherein the voltage supply circuit and the voltage detection circuit are configured as part of the microcontroller or the application processor. In some embodiments, the processor 608 may also form part of the microcontroller or the application processor. Alternatively, the voltage supply circuit and the voltage detection circuit may also be located in different components.

[0054] When determining whether a SWI module is present in a secondary device based on one or more detected voltages, as will be described in more detail with respect to the first method, the second method, and the third method, the processor 608 may also be optionally configured to generate a signal indicating the presence of a SWI module based on a single voltage measurement result, or based on a difference between a first voltage measurement result in a plurality of voltage measurements and one or more second voltage measurements in the plurality of voltage measurements. The difference may correspond to a difference between a supply voltage and a steady-state voltage. Conversely, the processor 608 may also be configured to generate a signal indicating the absence of a SWI module based on a single voltage measurement result, or when the difference between a first voltage measurement result in a plurality of voltage measurements and a second voltage measurement result in a plurality of voltage measurements is close to zero.

[0055] Alternatively, the processor 608 determining whether the SWI module 122 is present in the slave device may include the processor 608 determining a sum of a plurality of voltage measurements. In this manner, the processor 608 may be configured to generate a signal indicating that the SWI module is not present when the sum of the plurality of voltage measurements is equal to the supply voltage multiplied by the amount of the plurality of voltage measurements. Similarly, the processor 608 may be configured to generate a signal indicating that the SWI module is present when the sum of the plurality of voltage measurements is less than the supply voltage multiplied by the amount of the plurality of voltage measurements.

[0056] As described above, the processor may detect the SWI module 122 (eg, determine the presence or absence of the SWI module) using one of at least three different methods. Additionally, two of these methods may be used to detect a failure or absence of a capacitor coupled to the SWI module 122 .

[0057] Figure 7 A first method of detecting a SWI module within a slave device is depicted. In this figure, the processor can detect the SWI module 122 based on the difference between two voltage measurements from the ADC. In this manner, the processor evaluates a first voltage measurement 702 acquired at or shortly after the beginning of the sampling phase 304, and a second voltage measurement 704 acquired after the first voltage measurement 702 (e.g., toward the end of the sampling phase 506). In this manner, the processor determines the difference between the first voltage measurement 702 and the second voltage measurement 704, which will be referred to herein as ΔV. In general, if ΔV is equal to or close to the difference between the supply voltage and the steady-state voltage (e.g., assuming that the supply voltage and the steady-state voltage are not equal, such as at least Figure 2 , Figure 3 and Figure 5 , and based on the voltage drop across the ohmic resistor 112 due to the current drawn from the voltage source 110), the presence of the SWI module 122 is detected. Accordingly, the processor may optionally send a signal indicating the presence of the SWI module 122. Conversely, if ΔV is equal to or close to 0V (e.g., see Figure 4 ), it is detected that the SWI module 122 does not exist. In this case, the processor may optionally send a signal indicating that the SWI module 122 does not exist.

[0058] As an optional extension of this first method, the processor may also detect additional information about the auxiliary device based on ΔV and the second voltage measurement 704. Specifically, if ΔV is equal to or close to 0V and the second voltage measurement 704 is equal to the voltage at the voltage source 110, then the absence of the SWI module 122 is detected. In addition, if ΔV is equal to or close to 0V and the second voltage measurement 704 is equal to or close to a steady-state voltage (the steady-state voltage is less than the voltage at the voltage source 110), then the presence of the SWI module 122 is detected (a lower steady-state voltage is reached only if the SWI module 122 is present and current is drawn through the ohmic resistor); however, ΔV being equal to or close to 0 indicates that the first voltage measurement 702 is also at a steady-state voltage, which may indicate that the component (e.g., capacitor 124) is defective. In this manner, the processor may send one or more error signals indicating that the capacitor is defective, such error signals may be audible signals, visual signals (e.g., light), warnings on a display, or other signals. If ΔV is equal to or close to the difference between the supply voltage and the steady-state voltage, and if the second voltage measurement 704 is equal to or close to the steady-state voltage, then the SWI module 122 is detected and the functionality of the element 124 is verified. It should be explicitly noted that, depending on how close the second voltage measurement 704 is acquired to the end of the sampling phase, the voltage across the SWI may not have reached the steady-state voltage, and thus the second voltage measurement 704 may only be close to the steady-state voltage. Therefore, the tolerance of the second voltage measurement 704 (e.g., above a predetermined range of the steady-state voltage) must be considered. Finally, if the second voltage measurement 704 is below the steady-state voltage (e.g., below an expected or predetermined steady-state voltage), the processor may determine that the SWI module 122 is present but is operating at a current greater than its expected current, which may indicate a SWI module 122 failure.

[0059] In a second method for determining the presence or absence of the SWI module 122, the processor may detect the SWI module 122 based on a single measurement result 802 acquired during the sampling phase. According to the second method, the processor then compares the single measurement result with a predetermined threshold. A measured voltage greater than the predetermined threshold indicates the absence of the SWI module 122, while a measured voltage less than the predetermined threshold indicates the presence of the SWI module 122. In this case, the predetermined threshold may be an expected steady-state voltage, or a value between the GPIO voltage and the expected steady-state voltage.

[0060] In other words, using this second method, a single voltage measurement can be made to obtain a certain confidence level regarding the presence or absence of the SWI module 122. It should also be noted that this single measurement method (e.g., the second method) can be performed using a specific measurement timing (e.g., a duration after connecting the SWI to a voltage detection circuit (such as an ADC), a duration after the start of a sampling phase, etc.), because the voltage during the sampling phase is closely related not only to the question of whether the SWI module 122 is present, but also to the timing of the measurement relative to the start of the sampling phase.

[0061] At least through Fig. 9 A third method for determining the presence or absence of the SWI module 122 is depicted. In this way, the processor considers multiple and preferably more than two voltage measurements during the sampling phase. These multiple measurements can generally be understood as measuring or approximating the area under the curve in the sampling phase. The voltage or, alternatively, the corresponding steps of the ADC can be added, and the sum of these voltages or levels provides information about the presence or absence of the SWI module 122.

[0062] This can be best demonstrated by a non-limiting example. In an exemplary configuration, which is provided for illustrative purposes only and is not intended to be limiting, the supply voltage at the GPIO 108 and the voltage at the voltage source 110 are each 1.8V, and the steady-state voltage is 1.66V. In addition, in this exemplary configuration, the pull-up ohmic resistor is configured to be 680 ohms, and the capacitor / element is configured to have 2.2μF. If the SWI module 122 is present, the SWI module 122 is expected to draw a current of 150μA±some value, which may be, for example, 5%, as described above, which results in a steady-state voltage of approximately 1.66V taking into account the 680 ohm resistor. A value greater than the buffer value that is higher than the expected current draw can be selected as the threshold for overcurrent of the SWI module 122. Using the values ​​in this illustrative example, it can be assumed that 200μA is selected as the overcurrent value, so that a current draw equal to or greater than 200μA indicates that the SWI module 122 is overcurrent, thereby indicating a SWI module 122 failure. The threshold for determining overcurrent can be selected based on the expected maximum current for a given implementation. That is, in this illustrative example, which is provided for illustrative purposes only and is not intended to be limiting, the SWI module 122 can draw a current of 150μA±5%, up to 200μA, exceeding which current draw would be considered an overcurrent. Of course, a current draw within the higher normal range (in this example, the current draw is closer to 200μA) will result in a steady-state voltage of less than 1.66V because the current draw will result in a larger voltage drop across the ohmic resistor 112. However, it should be expressly noted that these values ​​are given for illustrative purposes only and are not intended to be limiting.

[0063] In addition, in this exemplary configuration, a 10-bit ADC is used to obtain 16 samples of the voltage across the SWI during the sampling phase (an ADC with higher or lower resolution can be used, and the number of samples can be greater or less than 16). The 10-bit ADC produces 1024 sample levels, so assuming that the highest sample level 1024 is assigned to the voltage source 1.8V, and assuming linear resolution, the steady-state voltage of 1.66V will correspond to level 944. Since 1024--944=80, the difference between the maximum sample level (1024) and the actual sample level (as low as 944) can be determined for each sampled voltage. This difference will be referred to as ΔS (e.g., level difference) in this article. ΔS can be added for each of the 16 samples during the sampling phase. Therefore, the sum of the ΔS values ​​can be as high as 1280 (80*16 samples=1280). If the sum is equal to 1280, no change in the voltage of the voltage source is detected, and the SWI module 122 does not exist. However, at least some tolerance should be considered, and thus a slightly lower number (eg, 1024) may be selected such that a sum within the threshold range of 1024 to 1280 indicates that the SWI module 122 is not present.

[0064] Continuing with this analysis, additional thresholds may be selected to define a range indicating that the SWI module 122 is present and the element 124 is functioning properly, which in this exemplary configuration may be 512 to 1024. In this manner, if the sum of the ΔS of the 16 samples is within the range of 512 to 1024, the SWI module 122 is detected and the element 124 is functioning properly.

[0065] Additionally, a lower threshold may be selected to define a range indicating that the SWI module 122 is present but the element 124 is faulty, which in this exemplary configuration may be less than 512. Thus, if the sum of the ΔS of the 16 samples is less than 512, the presence of the SWI module 122 is detected; however, the element 124 may be considered faulty.

[0066] Finally, additional information can be obtained by analyzing the absolute levels corresponding to the ADC measurements. Specifically, if any level corresponding to the voltage measurement is below the level corresponding to the steady-state voltage (or if the voltage measurement is less than the steady-state voltage), it can be assumed that the SWI module 122 is present, but the SWI module 122 is drawing a current greater than expected and may be malfunctioning. In this manner, if any single voltage is detected below level 944, a malfunction will be assumed.

[0067] The above considerations related to the third approach for this exemplary configuration can be summarized as follows:

[0068]

[0069]

[0070] It is emphasized again that the above exemplary configuration is intended for illustrative purposes only and should not be construed as limiting. Based on the above disclosure, those skilled in the art will understand that the expected voltage drop of the active SWI module 122 on the ohmic resistor and the remaining values ​​can be adjusted accordingly and also taking into account any differences in supply voltage, number of samples, sampling resolution, etc. In other words, the principles and methods reflected in this example can be implemented using different ohmic resistors (e.g., having a different resistance than that used in this article), different VCC values, different types of auxiliary devices, etc. Changes in any of these features may require changes in some or all of the other features; however, based on the teachings herein, the technician will understand how to relate these features to each other and how to select thresholds or related values ​​based on the values ​​of the remaining features.

[0071] The first, second and third methods have been described above with respect to calculations performed in a single sampling phase. In an alternative configuration, Fig.10 As depicted, the processor may be configured to determine the presence or absence of the SWI module 122 based on samples acquired in multiple sampling phases. In the figure, a first charging phase 1002 and a first sampling phase 1003 are depicted, followed by a second charging phase 1004 and a second sampling phase 1005, followed by a third charging phase 1006 and a third sampling phase 1007. In this manner, the processor may perform any of the above determinations with respect to the first method, the second method, or the third method, and repeat these determinations for each sampling phase in a plurality of sampling phases (e.g., 1003, 1005, 1007, etc.). In the figure, three consecutive phase groups are depicted for purposes of illustration; however, any two or more consecutive sampling phases may be used, and the depiction of three consecutive sampling phases is not intended to be limiting. In this manner, the results of multiple consecutive determinations may be averaged or weighted relative to each other. This use of multiple consecutive determinations can reduce the risk of a single erroneous calculation, such as caused by delayed start or completion of the charging phase, delayed start or completion of the sampling phase, jitter, electrostatic interference, or any other source of interference that may negatively affect the ADC's voltage measurement results.

[0072] Fig.11An optional flow chart of the process described herein is depicted. In the flow chart, a master device initiates startup of a slave device 1102. The startup process and the process of achieving startup can vary widely from device to device and are generally beyond the scope of the SWI module detection described herein. After startup, the master device can issue a SWI power-down signal, followed by a charging phase 1104, in which the SWI is connected to a general purpose input output (GPIO) and the master device configures the GPIO to a strong push-pull setting 1104. The master device can then begin a sampling phase and begin sampling the voltage on the SWI after selectively connecting the SWI to the ADC instead of the GPIO 1106. Depending on the method used, and in particular whether multiple samples are required, the master device can continue to sample the voltage on the SWI during the sampling phase 1108. Based on the measurement results, the master device determines whether a SWI module is present or not in the slave device 1110. Optionally, as at least in Fig. 9 As described in , the measuring step may be repeated so that a final determination of the presence or absence of the SWI module in the slave device is performed based on multiple sampling phases.

[0073] Fig.12 A method of detecting through SWI is depicted. The method includes: selectively connecting the SWI to a supply voltage during a charging phase and connecting the SWI to a voltage detection circuit during a subsequent sampling phase, during which the voltage detection circuit detects one or more voltages at the SWI 1202; and determining whether a SWI module is present in a secondary device based on the detected one or more voltages 1204.

[0074] Fig.13 Detection of a failed element 124 (e.g., a capacitor) is depicted in accordance with one aspect of the present disclosure. If an element 124 fails, it is expected that the element will not store the energy provided during the charging phase. In this manner, Fig.13 During the charging phase 1302, the voltage along SWI is equal to or very close to the GPIO voltage. However, upon entering the sampling phase 1304, SWI is disconnected from GPIO and quickly reaches the steady-state voltage. A slave device with a failed component 124 will typically reach the steady-state voltage faster than a slave device with a properly functioning capacitor because the cycle of capacitor discharge typically raises the voltage at SWI to greater than the steady-state voltage. In the event of a component 124 failure, such as Fig.13 As depicted in , it can be seen that the steady-state voltage is reached almost immediately after disconnecting the SWI from the GPIO. Therefore, the sampling phase 1304 is almost entirely performed at the steady-state voltage. The steady-state phase 1306 will also be understood to be performed at the steady-state voltage.

[0075] Based on the foregoing, either the first method or the third method may be used to detect a failed component 124. (The second method involves only a single measurement and is generally insufficient to make this determination.) In the first method, the difference between the two voltage measurements will be equal to or close to 0V (thereby indicating that both measurements during the sampling phase 1304 were made at or near a steady-state voltage). Using the third method, if the sum of the voltage measurements during the sampling phase 1304 is equal to or close to the steady-state voltage multiplied by the number of samples, this may indicate a failed component 124.

[0076] The ADC may be any type of analog-to-digital converter, including but not limited to a successive approximation ADC, a delta-sigma ADC, a dual slope ADC, a pipeline ADC, or a flash ADC.

[0077] If the processor determines that the SWI module 122 is present or absent, the processor may optionally be configured to send a signal indicating the determination. That is, the processor may send a signal indicating that the SWI module 122 is detected or absent. Similarly, if the processor determines that the SWI module 122 is faulty (e.g., according to method one or method two, based on the voltage measured in the sampling phase being lower than the expected steady-state voltage), the processor may optionally be configured to send a signal indicating that the SWI module 122 is faulty.

[0078] If the measurement indicates that the voltage in the sampling phase quickly reaches a steady-state voltage without an expected discharge curve of the component / capacitor, the processor may also be configured to send a signal indicating a component / capacitor failure. Alternatively or additionally, such a failure of the component / capacitor may be detected if the difference between a first voltage measurement in the plurality of voltage measurements and a second voltage measurement in the plurality of voltage measurements is close to or equal to zero.

[0079] In the foregoing, the SWI module 122 is generally referred to as a "module" to indicate that the principles and methods disclosed herein can be widely applied to a variety of different modules that perform a variety of different functions. Such modules can include, but are not limited to, communication modules (baseband modems, transceivers, etc.), cryptographic modules, security modules, etc. In particular, the SWI module 122 can be or include a battery verification module, which can be connected to the battery of the auxiliary device and can be configured to send one or more signals to the main device to verify the battery (e.g., confirm, approve, indicate its authenticity, etc.).

[0080] The timing of the charging phase, the sampling phase, and the steady-state phase may vary depending on the implementation. As described above, one or more startup processes may be required before starting the SWI module detection steps described herein. The duration of the startup depends on the given device and its configuration, and the startup can be of any duration without limitation. In an exemplary configuration, the startup can be less than 500ms. The startup can directly enter the charging phase, which may be very short. The charging phase only needs to last for the time required to charge the component / capacitor to the supply voltage. During the startup phase, a large amount of communication may occur between the main device and the auxiliary device, which may result in the charging or partial charging of the component / capacitor. After the startup phase is completed, a short charge is performed. Optionally, it may be necessary or desirable that the SWI is maintained at the supply voltage during this period and the capacitor is charged. Assuming that there is a SWI module in the auxiliary device, the subsequent sampling phase may have the duration necessary to stabilize the voltage on the SWI to the steady-state voltage. In an exemplary configuration, the duration of the sampling phase may be about 3ms. Depending on, for example, the difference between the steady-state voltage and the supply voltage and the capacitance of the component / capacitor, the measurement period may be longer or shorter than 3ms, but is not limited to this.

[0081] In some configurations, ADS 106 and GPIO 108 can be configured as part of the same microcontroller. Alternatively, either or both of ADS 106 or GPIO 108 can be configured externally to the master device 102. In this way, the master device can selectively connect SWI 105 to an external ADS 106 and / or to an external strong supply voltage (e.g., similar to GPIO 108).

[0082] In an optional alternative configuration, either or both of the ADC 106 or GPIO 108 may be configured as part of the auxiliary device 120. In this manner, the auxiliary device may connect the SWI 105 to a strong supply voltage located in the auxiliary device 104 during the charging phase (e.g., similar to the GPIO 108) and / or connect the SWI 105 to the ADC during the sampling phase (similar to the ADC 106).

[0083] Additional aspects of the disclosure will be described by way of examples.

[0084] In Example 1, the master device includes: a SWI for single-line connection to a slave device; a voltage supply circuit configured to connect the SWI to a supply voltage during a charging phase and a subsequent sampling phase, wherein the charging phase is used to charge elements of the slave device; a voltage detection circuit configured to generate multiple voltage measurement results of the voltage at the SWI during the sampling phase; and a processor configured to determine whether a SWI module is present in the slave device based on the multiple voltage measurement results.

[0085] In Example 2, the master device of Example 1, wherein the processor is configured to: during the sampling phase, when the plurality of voltage measurements transition from a supply voltage to a steady-state voltage lower than the supply voltage, generate a signal indicating detection of the SWI module.

[0086] In Example 3, the master device of Example 1 or 2, wherein the processor is further configured to: during the sampling phase, when the plurality of voltage measurements remain at the supply voltage, generate a signal indicating that the SWI module is not present.

[0087] In Example 4, according to a main device described in any one of Examples 1 to 3, wherein the processor determines whether a SWI module exists in the auxiliary device based on multiple voltage measurement results, including: the processor determines a difference between a first voltage measurement result among the multiple voltage measurement results and a second voltage measurement result among the multiple voltage measurement results.

[0088] In Example 5, according to the main device described in Example 4, the processor is further configured to: generate a signal indicating the presence of the SWI module when the difference between a first voltage measurement result among the multiple voltage measurement results and a second voltage measurement result among the multiple voltage measurement results corresponds to the difference between the supply voltage and the steady-state voltage, and wherein the processor is further configured to: generate a signal indicating the absence of the SWI module when the difference between the first voltage measurement result among the multiple voltage measurement results and the second voltage measurement result among the multiple voltage measurement results is approximately zero.

[0089] In Example 6, according to any one of Examples 1 to 5, the processor determines whether the SWI module exists in the slave device based on the multiple voltage measurement results, including: the processor determines the sum of the multiple voltage measurement results.

[0090] In Example 7, the master device of Example 6, wherein the processor is configured to generate a signal indicating that the SWI module is not present when a sum of the plurality of voltage measurements is equal to a supply voltage multiplied by an amount of the plurality of voltage measurements.

[0091] In Example 8, the master device of Example 6 or 7, wherein the processor is configured to generate a signal indicating the presence of the SWI module when a sum of the plurality of voltage measurements is less than a supply voltage multiplied by the plurality of voltage measurements.

[0092] In Example 9, according to any one of Examples 1 to 8, the voltage supply circuit includes an ohmic resistor, and the ohmic resistor is configured to: when a slave device having a SWI module is connected to the master device via SWI, generate a voltage drop corresponding to the difference between the supply voltage and the steady-state voltage.

[0093] In Example 10, the master device of Example 9, wherein the steady-state voltage corresponds to the supply voltage minus a voltage drop across the ohmic resistor based on a current draw of the SWI module.

[0094] In Example 11, the host device according to any one of Examples 1 to 10, wherein the voltage detection circuit includes an analog-to-digital converter.

[0095] In Example 12, the master device of Example 11, wherein the analog-to-digital converter is a successive approximation analog-to-digital converter.

[0096] In Example 13, according to any one of Examples 10 to 12, the master device, wherein the analog-to-digital converter is configured to have a resolution of multiple levels for detecting between the supply voltage and the steady-state voltage.

[0097] In Example 14, according to a main device described in any one of Examples 1 to 13, the processor is further configured to: send a signal indicating a SWI module failure when a voltage measurement result among multiple voltage measurement results is lower than a first predetermined threshold, or when the sum of the multiple voltage measurement results is lower than a second predetermined threshold.

[0098] In Example 15, the master device of Example 14, wherein the first predetermined threshold is a steady-state voltage, or wherein the second predetermined threshold is a steady-state voltage multiplied by a number of measurements of the plurality of voltage measurements.

[0099] In Example 16, according to a main device described in any one of Examples 1 to 15, the processor is further configured to: send a signal indicating a component failure of the auxiliary device if the difference between a first voltage measurement result among multiple voltage measurement results and a second voltage measurement result among the multiple voltage measurement results is close to or equal to zero.

[0100] In Example 17, the main device according to any one of Examples 1 to 16, wherein the element of the auxiliary device is a capacitor.

[0101] In Example 18, the primary device according to any one of Examples 1 to 17, wherein the secondary device includes a battery, and wherein the SWI module is a battery authentication SWI module.

[0102] In Example 19, a master device according to any one of Examples 1 to 18, wherein the master device is configured to perform multiple SWI module determinations, wherein each SWI module determination in the multiple SWI module determinations includes: the voltage supply circuit connects the SWI to a supply voltage for charging elements of the auxiliary device during a charging phase; and the voltage detection circuit generates multiple voltage measurement results of the voltage at the SWI during a sampling phase; and wherein the processor is configured to determine whether the SWI module exists in the auxiliary device based on the multiple SWI module determinations.

[0103] In Example 20, a method for detection through SWI includes: connecting the SWI to a supply voltage during a charging phase and a subsequent sampling phase, wherein the charging phase is used to charge components of an auxiliary device; generating multiple voltage measurement results of the voltage at the SWI during the sampling phase; and determining whether a SWI module is present in the auxiliary device based on the multiple voltage measurements.

[0104] In Example 21, the method of Example 20 further includes: during the sampling phase, when the plurality of voltage measurements transition from the supply voltage to a steady-state voltage lower than the supply voltage, generating a signal indicating that the SWI module is detected.

[0105] In Example 22, the method of Example 20 or 21 further includes: during the sampling phase, when the plurality of voltage measurements remain at the supply voltage, generating a signal indicating that the SWI module is not present.

[0106] In Example 23, according to the method described in any one of Examples 20 to 22, determining whether a SWI module exists in the auxiliary device based on multiple voltage measurement results includes: determining a difference between a first voltage measurement result among the multiple voltage measurement results and a second voltage measurement result among the multiple voltage measurement results.

[0107] In Example 24, the method according to Example 23 further includes: generating a signal indicating the presence of a SWI module when the difference between a first voltage measurement result among a plurality of voltage measurement results and a second voltage measurement result among a plurality of voltage measurement results corresponds to a difference between a supply voltage and a steady-state voltage, and generating a signal indicating the absence of a SWI module when the difference between a first voltage measurement result among a plurality of voltage measurement results and a second voltage measurement result among a plurality of voltage measurement results is approximately zero.

[0108] In Example 25, according to the method of any one of Examples 20 to 24, determining whether a SWI module exists in the slave device based on the plurality of voltage measurement results comprises: determining a sum of the plurality of voltage measurement results.

[0109] In Example 26, the method of Example 25 further includes generating a signal indicating that the SWI module is not present when a sum of the plurality of voltage measurements is equal to the supply voltage multiplied by an amount of the plurality of voltage measurements.

[0110] In Example 27, the method of Example 25 or 26 further includes generating a signal indicating the presence of the SWI module when a sum of the plurality of voltage measurements is less than an amount of the supply voltage multiplied by the plurality of voltage measurements.

[0111] In Example 28, according to any one of Examples 20 to 27, the steady-state voltage corresponds to the supply voltage minus a voltage drop across the ohmic resistor based on the current draw of the SWI module.

[0112] In Example 29, the method according to any one of Examples 20 to 28 further includes performing one or more voltage measurements using an analog-to-digital converter.

[0113] In Example 30, the method of Example 29 is performed, wherein the analog-to-digital converter is a successive approximation analog-to-digital converter.

[0114] In Example 31, according to a method according to any one of Examples 28 to 30, the analog-to-digital converter is configured to have a resolution of multiple levels for detecting between the supply voltage and the steady-state voltage.

[0115] In Example 32, the method according to any one of Examples 20 to 31 further includes: sending a signal indicating a SWI module failure when a voltage measurement result among multiple voltage measurement results is lower than a first predetermined threshold, or when the sum of the multiple voltage measurement results is lower than a second predetermined threshold.

[0116] In Example 33, the method of Example 32 is described, wherein the first predetermined threshold is the steady-state voltage, or wherein the second predetermined threshold is the steady-state voltage multiplied by the number of measurements of the plurality of voltage measurements.

[0117] In Example 34, the method according to any one of Examples 20 to 33 further includes: if the difference between a first voltage measurement result among the multiple voltage measurement results and a second voltage measurement result among the multiple voltage measurement results is close to or equal to zero, sending a signal indicating a component failure of the auxiliary device.

[0118] In Example 35, according to a method described in any one of Examples 20 to 34, the element of the auxiliary device is a capacitor.

[0119] In Example 36, according to any one of Examples 20 to 35, the auxiliary device includes a battery, and wherein the SWI module is a battery verification SWI module.

[0120] In Example 37, the method according to any one of Examples 20 to 36 further includes performing multiple SWI module determinations, wherein each SWI module determination in the multiple SWI module determinations includes: the voltage supply circuit connects the SWI to a supply voltage for charging elements of the auxiliary device during a charging phase; generates multiple voltage measurement results of the voltage at the SWI during a sampling phase; and determines whether a SWI module exists in the auxiliary device based on the multiple SWI module determinations.

[0121] In Example 38, a computer-readable medium includes instructions that, if executed, cause one or more processors to perform the following operations: connect the SWI to a supply voltage during a charging phase and a subsequent sampling phase, wherein the charging phase is used to charge components of an auxiliary device; generate multiple voltage measurements of the voltage at the SWI during the sampling phase; and determine whether a SWI module is present in the auxiliary device based on the multiple voltage measurements.

[0122] In Example 39, according to the computer readable medium of Example 38, the instructions are further configured to cause one or more processors to perform the following operations: during the sampling phase, when multiple voltage measurement results transition from the supply voltage to a steady-state voltage lower than the supply voltage, generate a signal indicating that the SWI module is detected.

[0123] In Example 40, according to the computer readable medium of Example 38 or 39, the instructions are further configured to cause the one or more processors to perform the following operations: during the sampling phase, when the plurality of voltage measurements remain at the supply voltage, generating a signal indicating that the SWI module is not present.

[0124] In Example 41, according to a computer readable medium described in any one of Examples 38 to 40, determining whether a SWI module exists in a slave device based on multiple voltage measurement results includes: determining a difference between a first voltage measurement result in the multiple voltage measurement results and a second voltage measurement result in the multiple voltage measurement results.

[0125] In Example 42, according to the computer-readable medium described in Example 41, the instructions are further configured to cause one or more processors to perform the following operations: when the difference between a first voltage measurement result among the multiple voltage measurement results and a second voltage measurement result among the multiple voltage measurement results corresponds to the difference between the supply voltage and the steady-state voltage, generate a signal indicating that the SWI module exists, and when the difference between the first voltage measurement result among the multiple voltage measurement results and the second voltage measurement result among the multiple voltage measurement results is approximately zero, generate a signal indicating that the SWI module does not exist.

[0126] In Example 43, the computer readable medium of any one of Examples 38 to 42, wherein determining whether a SWI module is present in the slave device based on a plurality of voltage measurements comprises determining a sum of the plurality of voltage measurements.

[0127] In Example 44, according to the computer readable medium of Example 43, the instructions are further configured to cause the one or more processors to perform the following operations: when the sum of the multiple voltage measurements is equal to the supply voltage multiplied by the amount of the multiple voltage measurements, generate a signal indicating that the SWI module is not present.

[0128] In Example 45, according to the computer-readable medium described in Example 43 or 44, the instructions are further configured to cause one or more processors to perform the following operations: when the sum of the multiple voltage measurement results is less than the supply voltage multiplied by the multiple voltage measurement results, generate a signal indicating the presence of the SWI module.

[0129] In Example 46, the computer readable medium of any one of Examples 38 to 45, wherein the steady state voltage corresponds to the supply voltage minus a voltage drop across the ohmic resistor based on a current draw of the SWI module.

[0130] In Example 47, according to the computer readable medium of any one of Examples 38 to 46, the instructions are further configured to cause the one or more processors to perform the following operations: perform one or more voltage measurements using an analog-to-digital converter.

[0131] In Example 48, according to a computer readable medium described in any one of Examples 38 to 47, the instructions are also configured to cause one or more processors to perform the following operations: when a voltage measurement result among multiple voltage measurement results is lower than a first predetermined threshold, or when the sum of the multiple voltage measurement results is lower than a second predetermined threshold, a signal indicating a SWI module failure is sent.

[0132] In Example 49, the computer readable medium of Example 48, wherein the first predetermined threshold is the steady state voltage, or wherein the second predetermined threshold is the steady state voltage multiplied by the number of measurements of the plurality of voltage measurements.

[0133] In Example 50, according to a computer-readable medium described in any one of Examples 38 to 49, the instructions are also configured to cause one or more processors to perform the following operations: if the difference between a first voltage measurement result among a plurality of voltage measurement results and a second voltage measurement result among the plurality of voltage measurement results is close to or equal to zero, a signal indicating a component failure of an auxiliary device is sent.

[0134] In Example 51, according to a computer-readable medium described in any one of Examples 38 to 50, the instructions are further configured to cause one or more processors to perform operations to perform multiple SWI module determinations, wherein each SWI module determination in the multiple SWI module determinations includes: the voltage supply circuit connects the SWI to a supply voltage for charging elements of an auxiliary device during a charging phase; generates multiple voltage measurement results of the voltage at the SWI during a sampling phase; and determines whether a SWI module exists in the auxiliary device based on the multiple SWI module determinations.

[0135] In Example 1a, the master device includes: a SWI for single-line connection to a slave device; and a processor configured to selectively connect the SWI to a supply voltage during a charging phase and to connect the SWI to a voltage detection circuit during a subsequent sampling phase, during which the voltage detection circuit detects one or more voltages at the SWI; and determine whether a SWI module is present in the slave device based on the detected one or more voltages.

[0136] In Example 2a, the master device according to Example 1a further includes a voltage supply circuit and a voltage detection circuit, the voltage supply circuit being configured to supply a power supply voltage.

[0137] In Example 3a, the host device of Example 2a further includes a microcontroller, wherein the voltage supply circuit and the voltage detection circuit are configured as part of the microcontroller.

[0138] In Example 4a, the host device of Example 3a, wherein the voltage supply circuit is a general purpose input output port of a microcontroller.

[0139] In Example 5a, a main device according to any one of Examples 1a to 4a, wherein the processor determines whether a SWI module exists in the auxiliary device, including: the processor is configured to generate a signal indicating that the SWI module is detected when the difference between two voltages detected during the sampling phase is outside a certain range, and the processor is configured to generate a signal indicating that the SWI module does not exist when the difference between two voltages detected during the sampling phase is within the range.

[0140] In Example 6a, a main device according to any one of Examples 1a to 4a, wherein the processor determines whether a SWI module exists in the auxiliary device, including: the processor is configured to generate a signal indicating that the SWI module is detected when a voltage detected during a sampling phase is within a predetermined range, and is configured to generate a signal indicating that the SWI module does not exist when a voltage detected during the sampling phase is outside a predetermined range.

[0141] In Example 5a1, the main device according to Example 5a, wherein generating a signal indicating that the SWI module is detected when the difference between two voltages detected during a sampling phase is outside a predetermined range includes: a processor receiving first data representing a first detection voltage and receiving second data representing a second detection voltage; determining a difference between the first detection voltage and the second detection voltage; and determining that the difference is outside a predetermined range.

[0142] In Example 5a2, a master device according to Example 5a1, wherein, in a hypothetical example provided for illustrative purposes only and not intended to be limiting, the first detection voltage is 1.73V, the second detection voltage is 1.66V, and the predetermined range is a difference of 50mV to 90mV.

[0143] In Example 5a3, a master device according to Example 5a or 5a1, wherein generating a signal indicating that the SWI module is detected when the difference between two voltages detected during a sampling phase is within a predetermined range includes: a processor receiving first data representing a first detection voltage and receiving second data representing a second detection voltage; determining a difference between the first detection voltage and the second detection voltage; and determining that the difference is within a predetermined range.

[0144] In Example 5a4, the master device of Example 5a3, wherein, in a hypothetical example provided for illustrative purposes only and not intended to be limiting, the first detection voltage is 1.72V, the second detection voltage is 1.70V, and the predetermined range is a difference of 50mV to 90mV.

[0145] In Example 7a, a main device according to any one of Examples 1a to 6a, wherein the one or more voltages detected at the SWI are multiple detected voltages, and wherein the processor determines whether a SWI module exists in the auxiliary device, including the processor being configured to: generate a signal indicating that the SWI module is detected when the sum of the multiple detected voltages is less than a predetermined tolerance of a power supply voltage multiplied by the amount of multiple voltage measurement results, and generate a signal indicating that the SWI module does not exist when the sum of the multiple detected voltages is equal to the power supply voltage multiplied by the amount of multiple voltage measurement results or is within a predetermined tolerance of the power supply voltage multiplied by the amount of multiple voltage measurement results.

[0146] In Example 8a, a master device according to any one of Examples 1a to 7a, wherein the voltage detection circuit includes an analog-to-digital converter; and wherein the analog-to-digital converter is configured to have a resolution of multiple levels for detecting between a supply voltage and a steady-state voltage.

[0147] In Example 9a, according to a main device described in any one of Examples 1a to 8a, the processor is further configured to: send a signal indicating a SWI module failure when a voltage measurement result among multiple voltage measurement results indicates an overcurrent, wherein the overcurrent refers to a current on the SWI exceeding a predetermined maximum current threshold.

[0148] In Example 10a, the primary device according to any one of Examples 1a to 9a, wherein the circuit for providing the supply voltage and / or the ADC is located in the secondary device.

[0149] In Example 11a, according to a main device described in any one of Examples 1a to 10a, the processor is further configured to: send a signal indicating a failure of an energy storage device of the auxiliary device if the difference between a first voltage measurement result during a sampling phase and a second voltage measurement result during the sampling phase is equal to or close to 0V, or if the sum of the voltage measurement results obtained during the sampling phase is equal to or close to the steady-state voltage multiplied by the number of samples obtained.

[0150] In Example 12a, the primary device of any one of Examples 1a to 11a, wherein the secondary device includes a battery, and wherein the SWI module is a battery verification module.

[0151] In Example 13a, a master device according to any one of Examples 1a to 12a, wherein the master device is configured to perform multiple module determinations, wherein each module determination in the multiple module determinations includes configuring the processor to: selectively connect the SWI to a supply voltage during a charging phase and connect the SWI to a voltage detection circuit during a subsequent sampling phase, during which the voltage detection circuit detects one or more voltages at the SWI; and determine whether a SWI module exists in the slave device based on the detected one or more voltages.

[0152] In Example 14a, a method for module detection includes: selectively connecting a single-wire interface SWI to a supply voltage during a charging phase and connecting the SWI to a voltage detection circuit during a subsequent sampling phase, during which the voltage detection circuit detects one or more voltages at the SWI; and determining whether a SWI module exists in a secondary device based on the detected one or more voltages.

[0153] In Example 15a, according to the method described in Example 14a, determining whether a SWI module exists in the auxiliary device includes: when the difference between two voltages detected during the sampling phase is outside a certain range, generating a signal indicating that the SWI module is detected, and when the difference between the two voltages detected during the sampling phase is within the range, generating a signal indicating that the SWI module does not exist.

[0154] In Example 16a, according to a method described in any one of Examples 14a to 15a, determining whether a SWI module exists in the auxiliary device includes: when a voltage detected during a sampling phase is less than a predetermined threshold, generating a signal indicating that the SWI module is detected, and when a voltage detected during the sampling phase is greater than a predetermined threshold, generating a signal indicating that the SWI module does not exist.

[0155] In Example 17a, according to a method described in any one of Examples 14a to 16a, wherein the one or more voltages detected at the SWI are multiple detection voltages, and wherein determining whether a SWI module exists in the auxiliary device includes: when the sum of the multiple detection voltages is less than a predetermined tolerance of a power supply voltage multiplied by the amount of multiple voltage measurement results, generating a signal indicating that the SWI module is detected, and when the sum of the multiple detection voltages is equal to the power supply voltage multiplied by the amount of multiple voltage measurement results or is within a predetermined tolerance of the power supply voltage multiplied by the amount of multiple voltage measurement results, generating a signal indicating that the SWI module does not exist.

[0156] In Example 18a, the method according to any one of Examples 14a to 17a further includes: when a voltage measurement result among the multiple voltage measurement results indicates an overcurrent, sending a signal indicating a SWI module failure, wherein the overcurrent refers to a current on the SWI exceeding a predetermined maximum current threshold.

[0157] In Example 19a, according to a method according to any one of Examples 14a to 18a, the circuit for providing the supply voltage and / or the ADC is located in a secondary device.

[0158] In Example 20a, the method according to any one of Examples 14a to 19a further includes: if the difference between a first voltage measurement result obtained during the sampling phase and a second voltage measurement result obtained during the sampling phase is equal to or close to 0V, or if the sum of the voltage measurement results obtained during the sampling phase is equal to or close to the steady-state voltage multiplied by the number of samples obtained, sending a signal indicating a failure of the energy storage device of the auxiliary device.

[0159] In Example 21a, the method according to any one of Examples 14a to 20a further includes the master device performing multiple module determinations, wherein each module determination in the multiple module determinations includes: selectively connecting the SWI to the supply voltage during the charging phase and connecting the SWI to the voltage detection circuit during the subsequent sampling phase, during the sampling phase, the voltage detection circuit detects one or more voltages at the SWI; and determining whether a SWI module exists in the slave device based on the detected one or more voltages.

[0160] In Example 22a, a non-transitory computer readable medium includes instructions that, if executed, cause a processor to perform the method of Examples 14a to 21a.

[0161] In Example 1c, a device for detecting a single-wire interface SWI module includes a processor configured to: selectively connect the SWI to a supply voltage during a charging phase and connect the SWI to a voltage detection circuit during a subsequent sampling phase; receive an output of the voltage detection circuit, the output representing one or more voltages detected at the SWI during the sampling phase; and determine whether a SWI module exists in a secondary device based on the detected one or more voltages.

[0162] In Example 2c, according to the main device described in Example 1c, wherein the processor determines whether a SWI module exists in the auxiliary device, including: the processor is configured to generate a signal indicating that the SWI module is detected when the difference between two voltages detected during the sampling phase is outside a certain range, and the processor is configured to generate a signal indicating that the SWI module does not exist when the difference between two voltages detected during the sampling phase is within the range.

[0163] In Example 3c, according to the main device described in Example 1c, wherein the processor determines whether a SWI module exists in the auxiliary device, including: the processor is configured to generate a signal indicating that the SWI module is detected when the voltage detected during the sampling phase is less than a predetermined threshold, and is configured to generate a signal indicating that the SWI module does not exist when the voltage detected during the sampling phase is greater than a predetermined threshold.

[0164] In Example 4c, a main device according to any one of Examples 1c to 3c, wherein the one or more voltages detected at the SWI are multiple detection voltages, and wherein the processor determines whether a SWI module exists in the auxiliary device, including the processor being configured to: when the sum of the multiple detection voltages is less than a predetermined tolerance of a power supply voltage multiplied by the amount of multiple voltage measurement results, generate a signal indicating that the SWI module is detected, and when the sum of the multiple detection voltages is equal to the power supply voltage multiplied by the amount of multiple voltage measurement results or is within a predetermined tolerance of the power supply voltage multiplied by the amount of multiple voltage measurement results, generate a signal indicating that the SWI module does not exist.

[0165] In Example 5c, a main device according to any one of Examples 1c to 4c, wherein the voltage detection circuit includes an analog-to-digital converter; and wherein the analog-to-digital converter is configured to have a resolution of multiple levels for detecting between a supply voltage and a steady-state voltage.

[0166] In Example 6c, according to a main device described in any one of Examples 1c to 5c, the processor is further configured to: send a signal indicating a SWI module failure when a voltage measurement result among multiple voltage measurement results indicates an overcurrent, wherein the overcurrent refers to a current on the SWI exceeding a predetermined maximum current threshold.

[0167] In Example 7c, according to a main device described in any one of Examples 1c to 6c, the processor is further configured to send a signal indicating a failure of an energy storage device of the auxiliary device if the difference between a first voltage measurement result obtained during a sampling phase and a second voltage measurement result obtained during the sampling phase is equal to or close to 0V, or if the sum of the voltage measurement results during the sampling phase is equal to or close to the steady-state voltage multiplied by the number of samples obtained.

[0168] In Example 8c, a master device according to any one of Examples 1c to 7c, wherein the master device is configured to perform multiple module determinations, wherein each module determination in the multiple module determinations includes configuring the processor to: selectively connect the SWI to a supply voltage during a charging phase and connect the SWI to a voltage detection circuit during a subsequent sampling phase, during which the voltage detection circuit detects one or more voltages at the SWI; and determine whether a SWI module exists in the slave device based on the detected one or more voltages.

[0169] Although the above description and drawings may depict components as separate elements, those skilled in the art will appreciate the various possibilities of combining or integrating discrete components into a single component. This may include combining two or more circuits to form a single circuit, mounting two or more circuits to a common chip or base to form an integrated component, executing discrete software components on a common processor core, etc. Conversely, the skilled person will recognize the possibility of separating a single component into two or more discrete components, such as separating a single circuit into two or more separate circuits, separating a chip or base into discrete components originally provided thereon, separating a software component into two or more parts and executing each part on a separate processor core, etc.

[0170] It should be understood that the implementation of the method described in detail herein is illustrative in nature, and is therefore understood to be implemented in a corresponding device. Similarly, it should be understood that the implementation of the device described in detail herein is understood to be implemented as a corresponding method. Therefore, it should be understood that the device corresponding to the method described in detail herein may include one or more components configured to perform each aspect of the related method.

[0171] All acronyms defined in the above description additionally apply to all claims included herein.

Claims

1. A master device, comprising: A single-wire interface SWI (602) for single-wire connection to a slave device; as well as A processor (608) configured to: selectively connecting the SWI (602) to a supply voltage during a charging phase and connecting the SWI (602) to a voltage detection circuit (606) during a subsequent sampling phase, wherein during the sampling phase, the voltage detection circuit (606) detects one or more voltages at the SWI (602); as well as A determination is made as to whether a SWI module (122) is present in the slave device based on the detected one or more voltages.

2. The master device according to claim 1, further comprising a voltage supply circuit (607) and the voltage detection circuit (606), the voltage supply circuit (607) being configured to supply the supply voltage.

3. The host device according to claim 2 further comprises a microcontroller, wherein: The processor (608), the voltage supply circuit (607) and the voltage detection circuit (606) are configured as part of the microcontroller.

4. The master device according to claim 3, wherein: The voltage supply circuit (607) is a general purpose input and output port of the microcontroller.

5. The main device according to any one of claims 1 to 4, wherein: The processor (608) determines whether the SWI module (122) exists in the auxiliary device, including: the processor (608) is configured to generate a signal indicating that the SWI module (122) is detected when the difference between the two voltages detected during the sampling phase is outside a certain range, and the processor (608) is configured to generate a signal indicating that the SWI module (122) does not exist when the difference between the two voltages detected during the sampling phase is within the range.

6. The master device according to any one of claims 1 to 4, wherein: The processor (608) determines whether the SWI module (122) exists in the auxiliary device, including: the processor (608) is configured to generate a signal indicating that the SWI module (122) is detected when the voltage detected during the sampling phase is less than a predetermined threshold, and is configured to generate a signal indicating that the SWI module (122) does not exist when the voltage detected during the sampling phase is greater than the predetermined threshold.

7. The main device according to any one of claims 1 to 4, wherein: The one or more voltages detected at the SWI (602) are multiple detected voltages, and wherein the processor (608) determines whether the SWI module (122) is present in the auxiliary device, including: the processor (608) is configured to generate a signal indicating that the SWI module (122) is detected when the sum of the multiple detected voltages is less than a predetermined tolerance of the supply voltage multiplied by the amount of the multiple voltage measurement results, and to generate a signal indicating that the SWI module (122) is not present when the sum of the multiple detected voltages is equal to the supply voltage multiplied by the amount of the multiple voltage measurement results or is within a predetermined tolerance of the supply voltage multiplied by the amount of the multiple voltage measurement results.

8. The master device according to any one of claims 1 to 7, wherein: The voltage detection circuit (606) includes an analog-to-digital converter; and wherein the analog-to-digital converter is configured to have a resolution for detecting multiple levels between the supply voltage and a steady-state voltage.

9. The master device according to any one of claims 1 to 8, wherein: The processor (608) is further configured to send a signal indicating a fault in the SWI module (122) when a voltage measurement in a plurality of voltage measurements indicates an overcurrent, wherein the overcurrent refers to a current on the SWI (602) exceeding a predetermined maximum current threshold.

10. The master device according to any one of claims 1 to 9, wherein: The circuit for providing the supply voltage and / or the voltage detection circuit (606) including an analog-to-digital converter is located in the auxiliary device.

11. The master device according to any one of claims 1 to 10, wherein: The processor (608) is also configured to send a signal indicating a failure of the energy storage device of the auxiliary device if the difference between a first voltage measurement result obtained during the sampling phase and a second voltage measurement result obtained during the sampling phase is equal to or close to 0V, or if the sum of the voltage measurements obtained during the sampling phase is equal to or close to the steady-state voltage multiplied by the number of samples obtained.

12. The master device according to any one of claims 1 to 11, wherein: The auxiliary device includes a battery, and wherein the SWI module (122) is a battery verification module.

13. The master device according to any one of claims 1 to 12, wherein: The master device is configured to perform multiple module determinations, wherein each module determination in the multiple module determinations includes configuring the processor to: selectively connecting the SWI (602) to the supply voltage during the charging phase and connecting the SWI (602) to the voltage detection circuit (606) during a subsequent sampling phase, during which the voltage detection circuit (606) detects one or more voltages at the SWI (602); and A determination is made as to whether the SWI module (122) is present in the slave device based on the detected one or more voltages.

14. A module detection method, comprising: selectively connecting a single wire interface (SWI) (602) to a supply voltage during a charging phase and connecting the SWI (602) to a voltage detection circuit (606) during a subsequent sampling phase, during which the voltage detection circuit (606) detects one or more voltages at the SWI (602); as well as A determination is made as to whether a SWI module (122) is present in the slave device based on the detected one or more voltages.

15. A non-transitory computer readable medium comprising instructions which, if executed, cause a processor to perform the method according to claim 14.

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