Data transmission system, verification method, and slave device
By introducing a mechanism for verifying write operations in the data transmission system, the problem that traditional circuit design cannot verify the correctness of slave device registers is solved, and the effect of avoiding unexpected operation errors is achieved.
Patent Information
- Application Number
- CN202311318810.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-12
- Publication Date
- 2025-04-15
AI Technical Summary
Traditional circuit design lacks a check mechanism and cannot verify whether the registers of the slave device have been correctly set, resulting in unpredictable operational errors in the slave device.
A data transmission system is designed, including a master control device and a slave device. The main control device outputs a write command, which contains control data. The slave device performs a write operation, stores control data in the address of the data register, and generates corresponding verification data. The master control device uses verification data to verify the write operation.
By verifying the write operation, unexpected operation errors can be avoided and the slave device's registers are correctly set.
Smart Images
Figure CN119829488A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a data transmission technology, and more particularly to a data transmission system and verification method capable of verifying a write operation. Background Art
[0002] In communication protocols with a master-slave relationship, such as the Media-Independent Interface, Serial Peripheral Interface, and Inter-Integrated Circuit BUS, the master device controls the behavior of the slave device by reading and writing operations on the registers of the slave device. However, conventional circuit designs do not provide a check mechanism to verify whether the registers of the slave device have been correctly set, which makes it easy for the slave device to have unexpected operation errors. Summary of the invention
[0003] The present disclosure provides a data transmission system, which includes a master control device and a slave device. The master control device is used to output a write instruction, and the write instruction includes control data. The slave device includes a data register coupled to the master control device. When the slave device receives the write instruction, the slave device is used to perform a write operation to store the control data at an address of the data register according to the write instruction. The slave device is used to generate verification data corresponding to the write operation according to the control data and the address. The master control device is used to verify the write operation using the verification data.
[0004] The present disclosure provides a verification method, which includes the following steps: a master control device outputs a write instruction to a slave device, and the write instruction includes control data; a write operation is performed by the slave device to store the control data at the address of a data register of the slave device according to the write instruction; the slave device generates verification data corresponding to the write operation according to the control data and the address; and the master control device uses the verification data to verify the write operation.
[0005] The present disclosure provides a slave device, which is used to receive a write instruction output by a master control device, and the write instruction includes control data. The slave device includes a data register, a processor, and a parity check circuit. The processor is used to perform a write operation to store the control data at the address of the data register according to the write instruction. The parity check circuit is used to perform a first parity operation using the control data and the previous slave end data parity value to generate a current slave end data parity value. The parity check circuit is also used to perform a second parity operation using the address and the previous slave end address parity value to generate a current slave end address parity value. The processor is used to output the current slave end data parity value and the current slave end address parity value to the master control device. The first parity operation is the same as or different from the second parity operation.
[0006] One of the advantages of the above-mentioned data transmission system and verification method is that the writing operation can be verified to avoid unexpected operation errors. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 It is a simplified functional block diagram of a data transmission system according to an embodiment of the present disclosure.
[0008] Figure 2 FIG. 4 is a schematic diagram of a frame format according to an embodiment of the present disclosure.
[0009] Figure 3 The figure is a flow chart of a verification method according to an embodiment of the present disclosure.
[0010] Figure 4 FIG. 4 is a simplified functional block diagram of a parity check circuit according to an embodiment of the present disclosure.
[0011] Figure 5 FIG. 4 is a simplified functional block diagram of a parity check circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0012] The following will illustrate the embodiments of the present disclosure in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.
[0013] Figure 1 The simplified functional block diagram of a data transmission system 100 according to an embodiment of the present disclosure is shown. The data transmission system 100 includes a master device 110 and a slave device 120 coupled to each other. The master device 110 reads or writes the slave device 120 through a data line DL, thereby controlling the slave device 120. The master device 110 is also used to provide a clock signal to the slave device 120 through a clock line CK to synchronize data transmission between the master device 110 and the slave device 120. In some embodiments, the master device 110 and the slave device 120 are a media access control (MAC) device and a physical layer (PHY) device, respectively, and the data line DL and the clock line CK are respectively an MDIO signal line and an MDC signal line in a media-independent interface.
[0014] However, the present disclosure is not limited to the above. The master device 110 and the slave device 120 can be any suitable electronic device that can communicate through a communication protocol having a master-slave relationship. In some embodiments, the data line DL includes a MOSI signal line and a MISO signal line in a serial peripheral interface (Serial Peripheral Interface), and the clock line CK is an SCK signal line in the serial peripheral interface. In other embodiments, the data line DL and the clock line CK are respectively the SDA signal line and the SCL signal line in an integrated circuit bus (Inter-Integrated Circuit BUS).
[0015] Please refer to Figure 2 ,in Figure 2 FIG. 4 is a schematic diagram of the MDIO Clause 45 frame format according to an embodiment of the present disclosure. The MDIO Clause 45 frame format includes a preamble field PRE, a start of frame field ST, an operation code field OP, a port address field PRTAD, a device address field DEVAD, a turnaround time field TA, and an address / data field REG_DATA. A person skilled in the art can understand the purpose of each field in the MDIO Clause 45 frame format, and for the sake of brevity, the relevant description is omitted here.
[0016] The master device 110 includes a processor 111, a data register 113, a parity check circuit 115, and a counter 117 coupled to each other. The master device 110 is used to output a write instruction WIS to the slave device 120 through a data line DL. The write instruction WIS has a frame format of MDIO clause 45, and the address / data field REG_DATA of the write instruction WIS includes control data CDA or address RAD (shown in FIG. Figure 4 ), but the present disclosure is not limited thereto. In other embodiments, the write instruction WIS may have any frame format that complies with the communication protocol used by the master device 110 and the slave device 120.
[0017] The slave device 120 includes a processor 121, a data register 123, a parity check circuit 125, an address register 127, and a counter 129, which are coupled to each other. The processors 111 and 121 are coupled to each other via a data line DL and a clock line CK. When the processor 121 of the slave device 120 receives a write instruction WIS from the processor 111 of the master device 110, the slave device 120 is used to perform a write operation to store the control data CDA in the address RAD of the data register 123 according to the write instruction WIS. The control data CDA is used to control the behavior of the slave device 120. The slave device 120 is used to use the content of the device address field DEVAD of the write instruction WIS to search for the corresponding address RAD, and the relevant content will be described later in conjunction with Figure 3 The slave device 120 is further configured to generate verification data VDA corresponding to the write operation according to the control data CDA and the address RAD, and to transmit the verification data VDA to the master device 110. The master device 110 is configured to use the verification data VDA to verify whether the write operation is correctly performed, that is, whether the control data CDA has been correctly written into the data register 123, or whether the content of the control data CDA has been changed.
[0018] Figure 3 1 is a flow chart of a verification method 300 according to an embodiment of the present disclosure. The data transmission system 100 is used to execute the verification method 300 to verify whether the write operation is correctly executed. If the master device 110 does not output the write instruction WIS to the slave device 120, or the slave device 120 determines that the instruction it receives is not the write instruction WIS, then the data transmission system 100 may not execute the verification method 300. It should be understood that the verification method 300 may include a method that is different from the method described above. Figure 3 More or fewer steps may be shown, and the steps in verification method 300 may be performed in any suitable order.
[0019] In step S310, the processor 111 of the master device 110 outputs a write command WIS to the slave device 120. As mentioned above, the write command WIS includes the control data CDA.
[0020] In step S320, when the processor 121 of the slave device 120 determines that the received instruction is a write instruction WIS, the processor 121 performs a write operation to store the control data CDA at the address RAD of the data register 123 according to the write instruction WIS. Figure 2 The frame start field ST and the operation code field OP are used to determine the type of the received instruction, and the corresponding relationship is shown in Table 1 below.
[0021] Table 1
[0022]
[0023]
[0024] It is worth mentioning that the master device 110 can output an "addressing instruction" to the slave device 120 before outputting the read instruction or the write instruction WIS. The address / data field REG_DATA of the "addressing instruction" includes the address RAD. When the processor 121 determines that the instruction it has received is an "addressing instruction" based on the frame start field ST and the operation code field OP, the processor 121 will store the address RAD in the address / data field REG_DATA in the address register 127. In detail, the multiple addresses of the address register 127 correspond to multiple device types. The processor 121 can store the address RAD recorded in the address / data field REG_DATA of the "addressing instruction" in a corresponding one of the multiple addresses of the address register 127 based on the device type recorded in the device address field DEVAD of the "addressing instruction".
[0025] Next, when the processor 121 receives the read instruction or the write instruction WIS, the processor 121 searches the address register 127 using the device type recorded in the device address field DEVAD of the write instruction WIS to obtain the address RAD previously specified by the "addressing instruction", and further uses this address RAD to perform a read operation or a write operation on the data register 123. In other words, the processor 121 searches the corresponding address RAD from the address register 127 according to the read instruction or the write instruction WIS.
[0026] In addition, the master device 110 can send the "addressing command" to the slave device 120 only once, and continuously send the "addressing command after reading" in subsequent operations without sending the "addressing command" again. When the slave device 120 receives the "addressing command after reading", it will automatically start the reading operation from the adjacent address.
[0027] Please refer to Figure 4 ,in Figure 4 FIG. 1 is a simplified functional block diagram of the parity check circuit 125 according to an embodiment of the present disclosure. In step S330, when the processor 121 performs a write operation, the parity check circuit 125 generates verification data VDA corresponding to the write operation according to the control data CDA and the address RAD, and the processor 121 is used to transmit the verification data VDA to the main control device 110.
[0028] Specifically, step S330 includes step S332 and step S334. In step S332, the parity check circuit 125 is used to perform a first parity operation (e.g., an XOR operation) using the control data CDA and the previous slave data parity value Pre_DD to generate the current slave data parity value Cu_DD. The parity check circuit 125 is also used to update the previous slave data parity value Pre_DD using the current slave data parity value Cu_DD, that is, the parity check circuit 125 will use the current slave data parity value Cu_DD as the previous slave data parity value Pre_DD in the next first parity operation.
[0029] In step S334, the parity check circuit 125 is used to search the address register 127 using the device type recorded in the device address field DEVAD of the write instruction WIS to obtain the address RAD previously specified by the "address instruction". The parity check circuit 125 is used to perform a second parity operation (e.g., an XOR operation) using the address RAD and the previous slave address parity value Pre_DA to generate the current slave address parity value Cu_DA. The parity check circuit 125 is also used to update the previous slave address parity value Pre_DA using the current slave address parity value Cu_DA, that is, the parity check circuit 125 will use the current slave address parity value Cu_DA as the previous slave address parity value Pre_DA in the next second parity operation.
[0030] The first parity operation and the second parity operation may be the same or different. In some embodiments, at least one of the first parity operation and the second parity operation may be a checksum operation.
[0031] The verification data VDA includes the current slave data parity value Cu_DD and the current slave address parity value Cu_DA, that is, the processor 121 is used to output the current slave data parity value Cu_DD and the current slave address parity value Cu_DA to the master device 110. In some embodiments, the counter 129 of the slave device 120 is used to count the number of executions of the write operation (or the number of times the processor 121 receives the write instruction WIS), and the verification data VDA also includes the number of executions of the write operation, that is, the processor 121 is also used to output the number of executions of the write operation to the master device 110.
[0032] Please refer to Figure 5 ,in Figure 5FIG. 1 is a simplified functional block diagram of a parity check circuit 115 according to an embodiment of the present disclosure. In step S340, the master device 110 uses the verification data VDA to verify whether the write operation is correctly performed. Since the control data CDA and the address RAD are both transmitted from the master device 110 to the slave device 120, the control data CDA and the address RAD are known information to the master device 110.
[0033] Specifically, step S340 includes steps S342 to S346. In step S342, the parity check circuit 115 is used to perform the aforementioned first parity operation (e.g., XOR operation) using the control data CDA and the previous master data parity value Pre_HD to generate the current master data parity value Cu_HD. The parity check circuit 115 is also used to update the previous master data parity value Pre_HD using the current master data parity value Cu_HD, that is, the parity check circuit 115 will use the current master data parity value Cu_HD as the previous master data parity value Pre_HD in the next first parity operation.
[0034] In step S344, the parity check circuit 115 is used to perform the aforementioned second parity operation (e.g., XOR operation) using the address RAD and the previous master address parity value Pre_HA to generate the current master address parity value Cu_HA. The parity check circuit 115 is also used to update the previous master address parity value Pre_HA using the current master address parity value Cu_HA, that is, the parity check circuit 115 will use the current master address parity value Cu_HA as the previous master address parity value Pre_HA in the next second parity operation.
[0035] In step S346, the processor 111 is used to compare the current slave data parity value CU_DD in the verification data VDA with the current master data parity value Cu_HD. The processor 111 is also used to compare the current slave address parity value Cu_DA in the verification data VDA with the current master address parity value Cu_HA. If the processor 111 determines that the current slave data parity value CU_DD is the same as the current master data parity value Cu_HD, and the current slave address parity value Cu_DA is the same as the current master address parity value Cu_HA, the processor 111 determines that the slave device 120 has correctly performed the write operation.
[0036] On the other hand, if the processor 111 determines that the current slave data parity value CU_DD is different from the current master data parity value Cu_HD, or the current slave address parity value Cu_DA is different from the current master address parity value Cu_HA, the processor 111 determines that the slave device 120 does not correctly perform the write operation. In this case, the processor 111 can perform a preset operation, wherein the preset operation can be a command to retransmit the relevant write operation, such as an "addressing command", a "add address after reading command" and / or a write command WIS, but the present disclosure is not limited thereto. In some embodiments, when it is determined that the write operation is not correctly performed, the processor 111 can perform any suitable operation.
[0037] In some embodiments, the counter 117 of the master device 110 is used to count an output number of the write instruction WIS. The processor 111 further compares the output number of the write instruction WIS with the execution number of the write operation in the verification data VDA in step S346. If so, the processor 111 determines that the slave device 120 has correctly executed the write operation. Otherwise, the processor 111 determines that the slave device 120 has not correctly executed the write operation.
[0038] In some embodiments, the parity check circuit 115 may be replaced by a software module having the same function, that is, the processor 111 may execute the software module to implement steps S342 - 346 .
[0039] It is worth mentioning that the data transmission system 100 and the verification method 300 of the present disclosure can communicate using any suitable communication protocol with a master-slave relationship, and are not limited to using the frame format of MDIO clause 45 for communication. In some embodiments, if the data transmission system 100 uses the frame format of MDIO clause 22 for communication, or uses an integrated circuit bus for communication, the address register 127 of the slave device 120 can be omitted. In the case where the address register 127 is omitted, the processor 121 of the slave device 120 and the parity check circuit 125 can directly obtain the address RAD and the control data CDA from the write instruction WIS in steps S320-S340 to perform the write operation, the first parity operation, and the second parity operation.
[0040] In other embodiments, the data transmission system 100 uses a serial peripheral interface for communication. Since the serial peripheral interface does not have an addressing instruction, the address register 127 of the slave device 120 can be omitted, and the master device 110 and the slave device 120 can omit the second parity operation in steps S334 and S344. In other words, the verification data VDA may not include the current slave address parity value Cu_DA, and the processor 111 of the master device 110 may not compare whether the current slave address parity value Cu_DA is the same as the current master address parity value Cu_HA in step S346.
[0041] In summary, the data transmission system 100 and the verification method 300 can determine whether an unexpected event occurs when writing the control data CDA, thereby preventing the data transmission system 100 from having unexpected operation errors.
[0042] Certain words are used in the specification and the scope of the patent application to refer to specific components. However, those with ordinary knowledge in the relevant technical field should understand that the same component may be referred to by different terms. The specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "include" mentioned in the specification and the scope of the patent application is an open-ended term, so it should be interpreted as "include but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second element through other elements or connection means.
[0043] The description method of "and / or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes the meaning of the plural term.
[0044] The above are only preferred embodiments of the present disclosure. Various modifications and equivalent changes may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.
[0045]
Explanation of symbols
[0046] 100:Data transmission system
[0047] 110: Main control device
[0048] 111: Processor
[0049] 113: Data register
[0050] 115:Parity check circuit
[0051] 117: Counter
[0052] 120: Slave device
[0053] 121: Processor
[0054] 123: Data register
[0055] 125:Parity check circuit
[0056] 127: Address register
[0057] 129: Counter
[0058] CK: Clock line
[0059] DL: Data line
[0060] WIS: Write Instruction
[0061] VDA: Validation Data
[0062] PRE: Previous text field
[0063] ST: frame start field
[0064] OP: Operation code field
[0065] PRTAD:Port Address Field
[0066] DEVAD: Device address field
[0067] TA: Turnaround time column
[0068] REG_DATA: Address / Data Field
[0069] 300: Verification method
[0070] S310~S346: Steps
[0071] CDA: Control Data
[0072] RAD:Address
[0073] Cu_DD: Current slave data parity value
[0074] Pre_DD: previous slave data parity value
[0075] Cu_DA: Current slave address parity value
[0076] Pre_DA: previous slave address parity value
[0077] Cu_HD: Current master data parity value
[0078] Pre_HD: The previous master data parity value
[0079] Cu_HA: Current master address parity value
[0080] Pre_HA: previous master address parity value
Claims
1. A data transmission system, comprising: a main control device, configured to output a write instruction, wherein the write instruction includes a control data; and a slave device, comprising a data register, coupled to the master device, wherein when the slave device receives the write instruction, the slave device is configured to perform a write operation to store the control data at an address of the data register according to the write instruction, wherein the slave device is used to generate a verification data corresponding to the write operation according to the control data and the address, The master control device is used to verify the write operation using the verification data.
2. The data transmission system according to claim 1, wherein: The slave device is used for: Performing a first parity operation using the control data and a previous slave data parity value to generate a current slave data parity value; as well as A second parity operation is performed using the address and a previous slave address parity value to generate a current slave address parity value, The verification data includes the current slave data parity value and the current slave address parity value, and the first parity operation is the same as or different from the second parity operation.
3. The data transmission system according to claim 2, wherein: The slave device is used to calculate an execution number of the write operation, wherein the verification data further includes the execution number.
4. The data transmission system according to claim 2, wherein: The main control device is used for: Using the control data and a previous master data parity value to perform the first parity operation to generate a current master data parity value; and The second parity operation is performed using the address and a previous master control end address parity value to generate a current master control end address parity value, The master control device is used to compare the current slave data parity value with the current master data parity value, and compare the current slave address parity value with the current master address parity value, so as to verify the write operation.
5. The data transmission system according to claim 4, wherein: The slave device is used to calculate an execution number of the write operation, wherein the verification data further includes the execution number, The main control device is used for calculating an output number of the write instruction, and the main control device is used for comparing the execution number with the output number to verify the write operation.
6. A verification method comprising: Outputting a write command from a master device to a slave device, wherein the write command includes a control data; Performing a write operation by the slave device to store the control data at an address of a data register of the slave device according to the write instruction; Generate verification data corresponding to the write operation by the slave device according to the control data and the address; as well as The write operation is verified by the master device using the verification data.
7. The verification method according to claim 6, wherein: Generating the verification data according to the control data and the address includes: By means of the slave device, a first parity operation is performed using the control data and a previous slave data parity value to generate a current slave data parity value; as well as By the slave device, a second parity operation is performed using the address and a previous slave address parity value to generate a current slave address parity value, The verification data includes the current slave data parity value and the current slave address parity value, and the first parity operation is the same as or different from the second parity operation.
8. The verification method according to claim 7, wherein: Verifying the write operation using the verification data includes: By means of the master control device, the control data and a previous master control end data parity value are used to perform the first parity operation to generate a current master control end data parity value; The master control device uses the address and a previous master control end address parity value to perform the second parity operation to generate a current master control end address parity value, The master device compares the current slave data parity value with the current master data parity value, and compares the current slave address parity value with the current master address parity value to verify the write operation.
9. The verification method according to claim 8, wherein: Generating the verification data according to the control data and the address further comprises: Calculating an execution number of the write operation by the slave device, wherein the verification data further includes the execution number, Wherein verifying the write operation using the verification data further comprises: Calculating an output frequency of the write instruction by the main control device; and The main control device compares the execution number with the output number to verify the write operation.
10. A slave device, for receiving a write instruction output by a master device, wherein the write instruction comprises a control data, and the slave device comprises: A data register; a processor, configured to execute a write operation to store the control data at an address of the data register according to the write instruction; and a parity check circuit for performing a first parity operation using the control data and a previous slave data parity value to generate a current slave data parity value, and for performing a second parity operation using the address and a previous slave address parity value to generate a current slave address parity value, wherein the processor is used to output the current slave data parity value and the current slave address parity value to the master control device, The first parity operation is the same as or different from the second parity operation.