Gearbox module of Ethernet 10GBASE-R PCS

Abstract

The invention relates to chip design, in particular to a Gearbox module of Ethernet 10GBASE-R PCS, which comprises a write depth pointer generation component, a write width pointer generation component, a write data control component and a data FIFO component which are positioned in a write clock domain, and a read depth pointer generation component, a read width pointer generation component and a read data control component which are positioned in a read clock domain, the write depth pointer generation component is used for generating a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component; the write width pointer generation component is used for generating a write width pointer pointing to a transverse bit position where write data is written in the data FIFO component; according to the technical scheme provided by the invention, the defect that seamless butt joint between an internal data bus of an Ethernet 10GBASE-R PCS and a data interface of a physical medium connection sub-layer PMA is difficult to realize through a Gearbox module in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to chip design, in particular to a Gearbox module of Ethernet 10GBASE-RPCS. Background Art

[0002] According to the definition in Chapter 49 of the IEEE 802.3 protocol, the physical coding sublayer 10GBASE-RPCS (Physical Coding Sublayer) is located between the coordination sublayer Reconciliation and the physical medium attachment sublayer PMA (Physical Medium Attachment). The physical coding sublayer 10GBASE-RPCS is interconnected with the upper coordination sublayer Reconciliation through the XGMII (10Gigabit Media Independent Interface) interface, and is interconnected with the lower physical medium attachment sublayer PMA through the XSBI (10Gigabit SixteenBit Interface) interface. Figure 4 shown.

[0003] The typical hardware structure of the physical coding sublayer 10GBASE-RPCS data transmission is as follows: Figure 5 As shown, it mainly includes 64B / 66B encoding module, scrambling module and Gearbox module. The 64B / 66B encoding module converts the 32-bit data received through the XGMII interface into 66-bit wide blocks, and after scrambling by the scrambling module, sends it to the Gearbox module. The Gearbox module converts the 66-bit wide data into 16-bit wide data (xsbi_tx_data[15:0]), and finally sends it to the physical medium connection sublayer PMA through the XSBI interface. The two clocks rpcs_tx_clk and xsbi_tx_clk used for data transmission are both provided by the physical medium connection sublayer PMA and are of the same source. For the standard 32-bits XGMII interface and 16-bits XSBI interface, the frequencies of the two clocks rpcs_tx_clk and xsbi_tx_clk are 312.5MHz and 644.53125MHz respectively.

[0004] In actual design, the data bus at the XGMII interface is designed to be in the standard 32bits×312.5MHz mode, and is also designed to be in the 64bits×156.25MHz mode, with a transmission rate of 10Gbps. After passing through the 64B / 66B encoding module, the transmission rate becomes 10.3125Gbps. In order to facilitate data processing, the internal data bus of the physical coding sublayer 10GBASE-RPCS is generally designed to be in the 33bits×312.5MHz or 66bits×156.25MHz mode. In general, the data interface of the physical medium connection sublayer PMA adopts the 20bits×515.625MHz mode in addition to the standard XSBI mode, i.e., the 16bits×644.53125MHz mode, and the transmission rate is also 10.3125Gbps.

[0005] Therefore, it is very important to design a flexible and universal Gearbox module to achieve seamless connection between the internal data bus of Ethernet 10GBASE-RPCS and the data interface of the physical medium attachment sublayer PMA. Summary of the invention

[0006] 1. Technical issues to be resolved

[0007] In view of the above-mentioned shortcomings of the prior art, the present invention provides a Gearbox module for Ethernet 10GBASE-RPCS, which can effectively overcome the defect of the prior art that it is difficult to achieve seamless connection between the internal data bus of Ethernet 10GBASE-RPCS and the data interface of the physical medium attachment sublayer PMA through the Gearbox module.

[0008] (II) Technical solution

[0009] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0010] The Gearbox module of Ethernet 10GBASE-RPCS includes a write depth pointer generation component, a write width pointer generation component, a write data control component and a data FIFO component located in the write clock domain, and a read depth pointer generation component, a read width pointer generation component and a read data control component located in the read clock domain;

[0011] A write depth pointer generation component, used to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component;

[0012] A write width pointer generation component, used to generate a write width pointer pointing to a lateral bit position where write data is written in the data FIFO component;

[0013] The write data control component writes the write data into the data FIFO component according to the write start bit position pointed to by the write depth pointer and the write width pointer;

[0014] Data FIFO component, used to store data;

[0015] A read depth pointer generating component, used to generate a read depth pointer pointing to a longitudinal position of read data read from the data FIFO component;

[0016] A read width pointer generating component, used to generate a read width pointer pointing to a horizontal bit position of read data read from the data FIFO component;

[0017] The read data control component reads and stores the read data from the data FIFO component according to the read start bit position pointed to by the read depth pointer and the read width pointer;

[0018] Among them, the write clock domain and the read clock domain are of the same origin.

[0019] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data writing process of the gearbox module includes:

[0020] In the initial state, the write start bit position is Cycle0 (0, 0), the write depth pointer and the write width pointer are both 0, and the data FIFO component is empty;

[0021] Cycle1(1,3) is the write start bit position after the first group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 1, and the write width pointer is incremented by 3 and updated to 3.

[0022] Cycle2 (2, 6) is the write start bit position after the second group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 2, and the write width pointer is incremented by 3 and updated to 6.

[0023] After the ninth group of 33 bits of write data is written into the data FIFO component, Cycle9(3,27) is the write start bit position of the tenth group of 33 bits of write data into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 3, and the write width pointer is incremented by 3 and updated to 27.

[0024] Cycle10(5,0) is the write start bit position after the tenth group of 33-bit write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 2 and updated to 5, and the write width pointer is incremented by 3 and updated to 0.

[0025] Cycle11(0,3) is the write start bit position after the eleventh group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 0, and the write width pointer is incremented by 3 and updated to 3.

[0026] After the above process is repeated, we get:

[0027] After every ten groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the write width pointer is incremented by 3, and after counting to 27, it loops back to 0, that is, modulo 30 addition.

[0028] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data reading process of the gearbox module includes:

[0029] In the initial state, the read start bit position is Cycle0 (0, 0), the read depth pointer and the write width pointer are both 0, and data is stored in the data FIFO component;

[0030] Cycle1 (0, 20) is the read start bit position after the first group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer remains unchanged and remains at 0. The read width pointer is updated to 20 after adding 20.

[0031] Cycle2 (1, 10) is the read start bit position after the second group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 1 after incrementing by 1, and the read width pointer is updated to 10 after incrementing by 20.

[0032] Cycle3(2,0) is the read start bit position after the third group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 2 after adding 1, and the read width pointer is updated to 0 after adding 20.

[0033] After the above process is repeated, we get:

[0034] After every 30 bits of read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 20, and after counting to 10, it loops back to 0, that is, modulo 30 addition.

[0035] Preferably, the write data bit width of the gearbox module is 33 bits, the write clock frequency is 312.5 MHz, the read data bit width of the gearbox module is 20 bits, and the read clock frequency is 515.625 MHz;

[0036] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0037] To facilitate read operations, the width of the data FIFO component is set to 30 bits.

[0038] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode, and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode:

[0039] 1) During the data writing process of the Gearbox module:

[0040] After every 32 groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the write width pointer is incremented by 1, and after counting to 31, it is looped back to 0, that is, modulo 32 addition;

[0041] 2) During the data reading process of the Gearbox module:

[0042] After every two groups of 16-bit read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16 in steps, and after counting to 16, it is looped back to 0, that is, modulo 32 addition.

[0043] Preferably, the write data bit width of the gearbox module is 33 bits, the write clock frequency is 312.5 MHz, the read data bit width of the gearbox module is 16 bits, and the read clock frequency is 644.53125 MHz;

[0044] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0045] To facilitate read operations, the width of the data FIFO component is set to 32 bits.

[0046] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in the 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in the 20 bits × 515.625 MHz mode:

[0047] 1) During the data writing process of the Gearbox module:

[0048] After every ten groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the write width pointer is incremented by 6, and after counting to 54, it is looped back to 0, that is, modulo 60 addition;

[0049] 2) During the data reading process of the Gearbox module:

[0050] After every three groups of 20 bits of read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 20 in steps, and after counting to 40, it is looped back to 0, that is, modulo 60 addition.

[0051] Preferably, the write data bit width of the gearbox module is 66 bits, the write clock frequency is 156.25 MHz, the read data bit width of the gearbox module is 20 bits, and the read clock frequency is 515.625 MHz;

[0052] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0053] To facilitate read operations, the width of the data FIFO component is set to 60 bits.

[0054] Preferably, when the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode, and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode:

[0055] 1) During the data writing process of the Gearbox module:

[0056] After every 32 groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the write width pointer is incremented by 2, and after counting to 62, it is looped back to 0, that is, modulo 64 addition;

[0057] 2) During the data reading process of the Gearbox module:

[0058] After every four groups of 16-bit read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16 steps, and after counting to 48, it is looped back to 0, that is, modulo 64 addition.

[0059] Preferably, the write data bit width of the gearbox module is 66 bits, the write clock frequency is 156.25 MHz, the read data bit width of the gearbox module is 16 bits, and the read clock frequency is 644.53125 MHz;

[0060] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0061] To facilitate read operations, the width of the data FIFO component is set to 64 bits.

[0062] (III) Beneficial effects

[0063] Compared with the prior art, the Gearbox module of Ethernet 10GBASE-R PCS provided by the present invention designs a flexible and universal Gearbox module based on a FIFO structure of two-dimensional read and write pointers, supports conversion of 33bits×312.5MHz or 66bits×156.25MHz mode into 16bits×644.53125MHz or 20bits×515.625MHz mode, and realizes seamless connection between the internal data bus of Ethernet 10GBASE-R PCS and the data interface of the physical medium attachment sublayer PMA. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 It is a schematic diagram of the hardware structure of the present invention;

[0066] Figure 2 It is a schematic diagram of the data writing process of the Gearbox module when the internal data bus of the physical coding sublayer 10GBASE-R PCS in the present invention is in the 33bits×312.5MHz mode and the data interface of the physical medium attachment sublayer PMA is in the 20bits×515.625MHz mode;

[0067] Figure 3 It is a schematic diagram of the data reading process of the Gearbox module when the internal data bus of the physical coding sublayer 10GBASE-R PCS in the present invention is in the 33bits×312.5MHz mode and the data interface of the physical medium attachment sublayer PMA is in the 20bits×515.625MHz mode;

[0068] Figure 4 It is a schematic diagram of the architecture position of the existing physical coding sublayer 10GBASE-RPCS;

[0069] Figure 5 The figure is a schematic diagram of the hardware structure of the existing physical coding sublayer 10GBASE-R PCS data transmission. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] Ethernet 10GBASE-R PCS Gearbox module, such as Figure 1 As shown, it includes a write depth pointer generation component, a write width pointer generation component, a write data control component and a data FIFO component located in the write clock domain, and a read depth pointer generation component, a read width pointer generation component and a read data control component located in the read clock domain;

[0072] A write depth pointer generation component, used to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component;

[0073] A write width pointer generation component, used to generate a write width pointer pointing to a lateral bit position where write data is written in the data FIFO component;

[0074] The write data control component writes the write data into the data FIFO component according to the write start bit position pointed to by the write depth pointer and the write width pointer;

[0075] Data FIFO component, used to store data;

[0076] A read depth pointer generating component, used to generate a read depth pointer pointing to a longitudinal position of read data read from the data FIFO component;

[0077] A read width pointer generating component, used to generate a read width pointer pointing to a horizontal bit position of read data read from the data FIFO component;

[0078] The read data control component reads and stores the read data from the data FIFO component according to the read start bit position pointed to by the read depth pointer and the read width pointer;

[0079] Among them, the write clock domain and the read clock domain are of the same origin.

[0080] ①33bits×312.5MHz mode converted to 20bits×515.625MHz mode

[0081] like Figure 2 As shown in the figure, when the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data writing process of the gearbox module includes:

[0082] In the initial state, the write start bit position is Cycle0 (0, 0), the write depth pointer and the write width pointer are both 0, and the data FIFO component is empty;

[0083] Cycle1(1,3) is the write start bit position after the first group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 1, and the write width pointer is incremented by 3 and updated to 3.

[0084] Cycle2 (2, 6) is the write start bit position after the second group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 2, and the write width pointer is incremented by 3 and updated to 6.

[0085] After the ninth group of 33 bits of write data is written into the data FIFO component, Cycle9(3,27) is the write start bit position of the tenth group of 33 bits of write data into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 3, and the write width pointer is incremented by 3 and updated to 27.

[0086] Cycle10(5,0) is the write start bit position after the tenth group of 33-bit write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 2 and updated to 5, and the write width pointer is incremented by 3 and updated to 0.

[0087] Cycle11(0,3) is the write start bit position after the eleventh group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 0, and the write width pointer is incremented by 3 and updated to 3.

[0088] After the above process is repeated, we get:

[0089] After every ten groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1. After counting to 5, it loops back to 0, that is, modulo 6 addition, (5+1)mod6=0; the write width pointer is incremented by 3, and after counting to 27, it loops back to 0, that is, modulo 30 addition, (27+3)mod30=0.

[0090] like Figure 3 As shown in the figure, when the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data reading process of the gearbox module includes:

[0091] In the initial state, the read start bit position is Cycle0 (0, 0), the read depth pointer and the write width pointer are both 0, and data is stored in the data FIFO component;

[0092] Cycle1 (0, 20) is the read start bit position after the first group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer remains unchanged and remains at 0. The read width pointer is updated to 20 after adding 20.

[0093] Cycle2 (1, 10) is the read start bit position after the second group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 1 after incrementing by 1, and the read width pointer is updated to 10 after incrementing by 20.

[0094] Cycle3(2,0) is the read start bit position after the third group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 2 after adding 1, and the read width pointer is updated to 0 after adding 20.

[0095] After the above process is repeated, we get:

[0096] After every 30 bits of read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition, (5+1)mod6=0; the read width pointer is incremented in steps of 20, and after counting to 10, it loops back to 0, that is, modulo 30 addition, (10+20)mod30=0.

[0097] Among them, the write data bit width of the Gearbox module is 33 bits, the write clock frequency is 312.5MHz, the read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625MHz;

[0098] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0099] To facilitate read operations, the width of the data FIFO component is set to 30 bits.

[0100] ②33bits×312.5MHz mode converted to 16bits×644.53125MHz mode

[0101] When the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode:

[0102] 1) During the data writing process of the Gearbox module:

[0103] After every 32 groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the write width pointer is incremented by 1, and after counting to 31, it is looped back to 0, that is, modulo 32 addition;

[0104] 2) During the data reading process of the Gearbox module:

[0105] After every two groups of 16-bit read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16 in steps, and after counting to 16, it is looped back to 0, that is, modulo 32 addition.

[0106] Among them, the write data bit width of the Gearbox module is 33 bits, the write clock frequency is 312.5MHz, the read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125MHz;

[0107] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0108] To facilitate read operations, the width of the data FIFO component is set to 32 bits.

[0109] ③66bits×156.25MHz mode converted to 20bits×515.625MHz mode

[0110] When the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode:

[0111] 1) During the data writing process of the Gearbox module:

[0112] After every ten groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the write width pointer is incremented by 6, and after counting to 54, it is looped back to 0, that is, modulo 60 addition;

[0113] 2) During the data reading process of the Gearbox module:

[0114] After every three groups of 20 bits of read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 20 in steps, and after counting to 40, it is looped back to 0, that is, modulo 60 addition.

[0115] Among them, the write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25MHz, the read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625MHz;

[0116] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0117] To facilitate read operations, the width of the data FIFO component is set to 60 bits.

[0118] ④66bits×156.25MHz mode converted to 16bits×644.53125MHz mode

[0119] When the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode:

[0120] 1) During the data writing process of the Gearbox module:

[0121] After every 32 groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the write width pointer is incremented by 2, and after counting to 62, it is looped back to 0, that is, modulo 64 addition;

[0122] 2) During the data reading process of the Gearbox module:

[0123] After every four groups of 16-bit read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16 steps, and after counting to 48, it is looped back to 0, that is, modulo 64 addition.

[0124] Among them, the write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25MHz, the read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125MHz;

[0125] To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6.

[0126] To facilitate read operations, the width of the data FIFO component is set to 64 bits.

[0127] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. Ethernet 10GBASE-RPCS Gearbox module, characterized by: It includes a write depth pointer generation component, a write width pointer generation component, a write data control component and a data FIFO component located in the write clock domain, and a read depth pointer generation component, a read width pointer generation component and a read data control component located in the read clock domain; A write depth pointer generation component, used to generate a write depth pointer pointing to a longitudinal position where write data is written in the data FIFO component; A write width pointer generation component, used to generate a write width pointer pointing to a lateral bit position where write data is written in the data FIFO component; The write data control component writes the write data into the data FIFO component according to the write start bit position pointed to by the write depth pointer and the write width pointer; Data FIFO component, used to store data; A read depth pointer generating component, used to generate a read depth pointer pointing to a longitudinal position of read data read from the data FIFO component; A read width pointer generating component, used to generate a read width pointer pointing to a horizontal bit position of read data read from the data FIFO component; The read data control component reads and stores the read data from the data FIFO component according to the read start bit position pointed to by the read depth pointer and the read width pointer; Among them, the write clock domain and the read clock domain are of the same origin.

2. The Ethernet 10GBASE-RPCS Gearbox module according to claim 1, characterized in that: When the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data writing process of the gearbox module includes: In the initial state, the write start bit position is Cycle0 (0, 0), the write depth pointer and the write width pointer are both 0, and the data FIFO component is empty; Cycle1(1,3) is the write start bit position after the first group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 1, and the write width pointer is incremented by 3 and updated to 3. Cycle2 (2, 6) is the write start bit position after the second group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 2, and the write width pointer is incremented by 3 and updated to 6. After the ninth group of 33 bits of write data is written into the data FIFO component, Cycle9(3,27) is the write start bit position of the tenth group of 33 bits of write data into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 3, and the write width pointer is incremented by 3 and updated to 27. Cycle10(5,0) is the write start bit position after the tenth group of 33-bit write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 2 and updated to 5, and the write width pointer is incremented by 3 and updated to 0. Cycle11 (0,3) is the write start bit position after the eleventh group of 33 bits of write data is written into the data FIFO component. At this time, the write depth pointer is incremented by 1 and updated to 0, and the write width pointer is incremented by 3 and updated to 3. After the above process is repeated, we get: After every ten groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the write width pointer is incremented by 3, and after counting to 27, it loops back to 0, that is, modulo 30 addition.

3. The Ethernet 10GBASE-RPCS Gearbox module according to claim 2, characterized in that: When the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode, the data reading process of the gearbox module includes: In the initial state, the read start bit position is Cycle0 (0, 0), the read depth pointer and the write width pointer are both 0, and data is stored in the data FIFO component; Cycle1 (0, 20) is the read start bit position after the first group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer remains unchanged and remains at 0. The read width pointer is updated to 20 after adding 20. Cycle2 (1, 10) is the read start bit position after the second group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 1 after incrementing by 1, and the read width pointer is updated to 10 after incrementing by 20. Cycle3(2,0) is the read start bit position after the third group of 20 bits of read data is read from the data FIFO component. At this time, the read depth pointer is updated to 2 after adding 1, and the read width pointer is updated to 0 after adding 20. After the above process is repeated, we get: After every 30 bits of read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it loops back to 0, that is, modulo 6 addition; the read width pointer is incremented in steps of 20, and after counting to 10, it loops back to 0, that is, modulo 30 addition.

4. The Ethernet 10GBASE-RPCS Gearbox module according to claim 3, characterized in that: The write data bit width of the Gearbox module is 33 bits, and the write clock frequency is 312.5MHz. The read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625MHz. To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 30 bits.

5. The Ethernet 10GBASE-RPCS Gearbox module according to claim 3, characterized in that: When the internal data bus of the physical coding sublayer 10GBASE-RPCS is in 33 bits × 312.5 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode: 1) During the data writing process of the Gearbox module: After every 32 groups of 33-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it loops back to 0, i.e., modulo 6 addition; The increment step of the write width pointer is 1, and after counting to 31, it loops back to 0, i.e., modulo 32 addition; 2) During the data reading process of the Gearbox module: After every two groups of 16-bit read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16 in steps, and after counting to 16, it is looped back to 0, that is, modulo 32 addition.

6. The Ethernet 10GBASE-R PCS Gearbox module according to claim 5, characterized in that: The write data bit width of the Gearbox module is 33 bits, and the write clock frequency is 312.5MHz. The read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125MHz. To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 32 bits.

7. The Ethernet 10GBASE-R PCS Gearbox module according to claim 3, characterized in that: When the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 20 bits × 515.625 MHz mode: 1) During the data writing process of the Gearbox module: After every ten groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it loops back to 0, i.e., modulo 6 addition; The increment step of the write width pointer is 6, and after counting to 54, it loops back to 0, i.e., modulo 60 addition; 2) During the data reading process of the Gearbox module: After every three groups of 20 bits of read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 20 in steps, and after counting to 40, it is looped back to 0, that is, modulo 60 addition.

8. The Ethernet 10GBASE-R PCS Gearbox module according to claim 7, characterized in that: The write data bit width of the Gearbox module is 66 bits, the write clock frequency is 156.25MHz, the read data bit width of the Gearbox module is 20 bits, and the read clock frequency is 515.625MHz; To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 60 bits.

9. The Ethernet 10GBASE-R PCS Gearbox module according to claim 3, characterized in that: When the internal data bus of the physical coding sublayer 10GBASE-R PCS is in 66 bits × 156.25 MHz mode and the data interface of the physical medium attachment sublayer PMA is in 16 bits × 644.53125 MHz mode: 1) During the data writing process of the Gearbox module: After every 32 groups of 66-bit write data are written into the data FIFO component, the write depth pointer is incremented by 2, and the remaining increment steps are all 1, and after counting to 5, it loops back to 0, i.e., modulo 6 addition; The increment step of the write width pointer is 2, and after counting to 62, it loops back to 0, i.e., modulo 64 addition; 2) During the data reading process of the Gearbox module: After every four groups of 16-bit read data are read out from the data FIFO component, the read depth pointer is incremented by 1, and after counting to 5, it is looped back to 0, that is, modulo 6 addition; the read width pointer is incremented by 16 steps, and after counting to 48, it is looped back to 0, that is, modulo 64 addition.

10. The Ethernet 10GBASE-R PCS Gearbox module according to claim 9, characterized in that: The write data bit width of the Gearbox module is 66 bits, and the write clock frequency is 156.25MHz. The read data bit width of the Gearbox module is 16 bits, and the read clock frequency is 644.53125MHz. To prevent overflow, the spacing between the write depth pointer and the read depth pointer needs to be guaranteed. When the write depth pointer is 2, data reading starts, and the depth of the data FIFO component is set to 6. To facilitate read operations, the width of the data FIFO component is set to 64 bits.

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