Reliability Evaluation Method for Automotive Chips Based on the Competition Failure of Multiple Failure Mechanisms

Abstract

The present application relates to the technical field of automotive chips, and discloses a reliability evaluation method for automotive chips based on competing failures of multiple failure mechanisms. The method includes conducting single failure mechanism evaluation tests to obtain acceleration factors and failure rates, constructing an acceleration factor matrix and a failure rate matrix to calculate a proportion coefficient matrix, and constructing a multi-mechanism competing failure matrix to calculate the comprehensive failure rate and the mean life time to evaluate its reliability. The present application realizes the comprehensive consideration of the competing relationships of multiple failure mechanisms. Through scientific and reasonable test and calculation methods, it can accurately evaluate the comprehensive failure rate and the mean life time of automotive chips under complex stress environments, effectively overcomes the limitations of traditional separate evaluations of each failure mechanism, provides a more accurate and more practical working condition-compliant evaluation means for the reliability evaluation of automotive chips, meets the stringent requirements of the automotive industry for the reliability evaluation of chips, and improves the reliability guarantee level of automotive chips in the design, production, and application links.

Description

Technical Field

[0001] This application relates to the technical field of automotive chips, and specifically, to a method for evaluating the reliability of automotive chips based on competing failures with multiple failure mechanisms. Background Art

[0002] With the booming development of the intelligent vehicle industry, as a core component, the technology and reliability of automotive chips have attracted much attention. The working environment of automotive chips is complex, facing challenges such as high and low temperatures, high voltage stress, etc. Failures often occur due to the combined effects of multiple failure mechanisms such as hot carrier injection (HCI), negative bias temperature instability (NBTI), time-dependent dielectric breakdown (TDDB), and electromigration (EM). Moreover, the failure rates of these failure mechanisms are similar, and they compete with each other, affecting the reliability of the chips.

[0003] The inventors found in the research of the prior art that there are defects in the evaluation of the reliability of automotive chips, mostly separately conducting individual tests and evaluations on each failure mechanism. This defect does not carry out comprehensive stress tests and calculations, and cannot fully reflect the true reliability of the chips in complex environments, making it difficult to meet the strict requirements of the automotive industry for chip reliability evaluation.

[0004] Chinese Patent No. CN119493981A discloses a method for predicting the performance level of chips. Although this patent can predict the performance level of chips, it only relies on chip attribute parameters and models for prediction, without considering the failure mechanisms in the actual operation of automotive chips. It ignores the influence of multiple failure mechanisms such as HCI and NBTI on chip reliability, and does not conduct relevant tests to obtain data. The evaluation dimension is single, and it cannot accurately evaluate the reliability of automotive chips under complex working conditions, making it difficult to meet the needs of the automotive industry.

[0005] In summary, there is an urgent need for a new technical solution for evaluating the reliability of automotive chips based on competing failures with multiple failure mechanisms to solve the above technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a method for evaluating the reliability of automotive chips based on competing failures with multiple failure mechanisms to solve the technical problems raised in the above background art.

[0007] To achieve the above purpose, this application discloses the following technical solutions: A method for evaluating the reliability of automotive chips based on competing failures with multiple failure mechanisms, including the following steps:

[0008] S1: Based on the preset IEC standard and the corresponding same failure criterion, conduct the first batch of single failure mechanism evaluation tests under different stress conditions to obtain a single acceleration factor and the corresponding single failure rate. The acceleration factor is used to characterize the influence of stress on the failure process;

[0009] S2: Based on the acceleration factor and the failure rate, construct the corresponding acceleration factor matrix and failure rate matrix, and calculate the obtained proportion coefficient matrix. The proportion coefficient matrix is used to characterize the proportion relationship of multiple failure mechanisms in the comprehensive failure rate, and the proportion coefficient matrix is also used to calculate the comprehensive failure rate of automotive chips;

[0010] S3: Based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix, construct a multi-mechanism competition failure matrix, which is used to calculate the comprehensive failure rate and the corresponding average life time to evaluate its reliability.

[0011] Preferably, in S1, the first batch of single failure mechanism evaluation tests include selecting MOS devices on the same process line and from the same batch of wafer runs as test samples, and selecting corresponding MOS devices for the corresponding failure mechanism evaluation tests for multiple failure mechanisms. The multiple failure mechanisms include hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect and electromigration effect.

[0012] Preferably, the method for selecting corresponding MOS devices for multiple failure mechanisms is as follows:

[0013] Select NMOS devices for the hot carrier effect;

[0014] Select PMOS devices for the negative bias temperature instability effect;

[0015] Select large-area MOS capacitors for the time-dependent dielectric breakdown effect;

[0016] Select interconnect metal lines for the electromigration effect.

[0017] Preferably, in S1, obtain a single acceleration factor and the corresponding single failure rate, specifically:

[0018] Obtain the hot carrier effect acceleration factor and the corresponding hot carrier effect failure rate for the hot carrier effect;

[0019] Obtain the negative bias temperature instability effect acceleration factor and the corresponding negative bias temperature instability effect failure rate for the negative bias temperature instability effect;

[0020] Obtain the time-dependent dielectric breakdown effect acceleration factor and the corresponding time-dependent dielectric breakdown effect failure rate for the time-dependent dielectric breakdown effect;

[0021] Obtain the electromigration effect acceleration factor and the corresponding electromigration effect failure rate for the electromigration effect.

[0022] Preferably, in S2, based on the acceleration factor and the failure rate, construct the corresponding acceleration factor matrix and failure rate matrix, specifically:

[0023] Construct an acceleration factor matrix based on the hot carrier effect acceleration factor, the negative bias temperature instability effect acceleration factor, the time-dependent dielectric breakdown effect acceleration factor, and the electromigration effect acceleration factor , where is the number corresponding to different stress conditions. Based on this acceleration factor matrix , obtain the corresponding failure rate matrix , and this failure rate matrix is obtained based on the single failure mechanism evaluation test of the first batch.

[0024] Preferably, in S2, the calculated proportion coefficient matrix is based on the acceleration factor matrix and the failure rate matrix to calculate the proportion coefficient matrix , and this calculation is specifically .

[0025] Preferably, in S3, the multi-mechanism competition failure matrix constructed based on the acceleration factor matrix, the proportion coefficient matrix, and the failure rate matrix is , where is the number of the new batch.

[0026] Preferably, the calculation method of the comprehensive failure rate is as follows:

[0027] Obtain the preset hot carrier effect weight factor , the negative bias temperature instability effect weight factor , the time-dependent dielectric breakdown effect weight factor , and the electromigration effect weight factor . Based on the failure rate matrix, obtain the corresponding hot carrier effect failure rate , the negative bias temperature instability effect failure rate , the time-dependent dielectric breakdown effect failure rate , and the electromigration effect failure rate . The calculation of the comprehensive failure rate is:

[0028]

[0029] where is the calculated comprehensive failure rate.

[0030] Preferably, in S3, the average life time is calculated by using the average life time formula, and the average life time formula is:

[0031]

[0032] Among them, is the calculated average lifetime.

[0033] Preferably, when calculating the failure rate of a new batch, each failure mechanism is tested with far fewer test samples than those in the first batch to obtain new acceleration factors under different stress conditions. Based on the multi-mechanism competing failure matrix, the corresponding new failure rate matrix is obtained, and based on this new failure rate matrix, the new comprehensive failure rate and the new average lifetime are calculated.

[0034] Beneficial effects: The method for evaluating the reliability of automotive chips based on multi-failure mechanism competing failures of the present application uses the preset IEC standard and the same failure criterion to conduct the first batch of single-failure mechanism evaluation tests, obtains individual acceleration factors and failure rates, then constructs a matrix and calculates the correlation coefficient, realizing the competition relationship of multiple failure mechanisms comprehensively considering the effects of hot carriers, negative bias temperature instability, time-dependent dielectric breakdown, and electromigration. Through scientific and reasonable test and calculation methods, it can accurately evaluate the comprehensive failure rate and average lifetime of automotive chips in complex stress environments, effectively overcoming the limitations of traditional separate evaluation of each failure mechanism, providing a more accurate and practical evaluation method for the reliability evaluation of automotive chips, meeting the strict requirements of the automotive industry for chip reliability evaluation, and improving the reliability guarantee level of automotive chips in the design, production, and application links. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 It is a flowchart of the method for evaluating the reliability of automotive chips based on multi-failure mechanism competing failures provided by the embodiments of the present application. Detailed Embodiments

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0038] In this text, the term "comprising" is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a series of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0039] This embodiment discloses a Figure 1 method for evaluating the reliability of automotive chips based on multi-failure mechanism competing failures as shown below, including the following steps:

[0040] S1: Based on a preset IEC standard and corresponding identical failure criteria, conduct the first batch of single-failure mechanism evaluation tests under different stress conditions to obtain a single acceleration factor and the corresponding single failure rate. The acceleration factor is used to characterize the influence of stress on the failure process.

[0041] S2: Based on the acceleration factor and the failure rate, construct the corresponding acceleration factor matrix and failure rate matrix, and calculate the proportion coefficient matrix. The proportion coefficient matrix is used to characterize the proportion relationship of multi-failure mechanisms in the comprehensive failure rate, and the proportion coefficient matrix is also used to calculate the comprehensive failure rate of automotive chips.

[0042] S3: Based on the acceleration factor matrix, the proportion coefficient matrix, and the failure rate matrix, construct a multi-mechanism competing failure matrix. The multi-mechanism competing failure matrix is used to calculate the comprehensive failure rate and the corresponding average lifetime to evaluate its reliability.

[0043] It should be noted that the IEC standard in this embodiment is an existing standard for the fields of electrical engineering and electronic engineering. Different stress conditions specifically refer to different voltage and different temperature conditions in this embodiment. In a simple example, the corresponding identical failure criteria mean that the failure criteria for hot carrier effect and negative bias temperature instability effect are set as a 10% threshold voltage degradation after a 10,000 s stress test, the failure criteria for electromigration effect are set as a 10% interconnection line resistance degradation after a 10,000 s stress test, and the failure criteria for time-dependent dielectric breakdown effect are set as MOS capacitor breakdown after a 10,000 s stress test.

[0044] With the above, this embodiment uses the preset IEC standard and the same failure criterion to conduct the first batch of single failure mechanism evaluation tests, obtains individual acceleration factors and failure rates, then constructs a matrix and calculates the correlation coefficient, realizing the competitive relationship of multiple failure mechanisms comprehensively considering hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect, and electromigration effect. Through scientific and reasonable test and calculation methods, it can accurately evaluate the comprehensive failure rate and average life time of automotive chips in complex stress environments, effectively overcoming the limitations of traditional separate evaluation of each failure mechanism, providing a more accurate and practical evaluation method for the reliability evaluation of automotive chips, meeting the strict requirements of the automotive industry for chip reliability evaluation, and improving the reliability guarantee level of automotive chips in the design, production, and application links.

[0045] Specifically, in S1, the first batch of single failure mechanism evaluation tests include selecting MOS devices fabricated on the same process line and in the same batch as test samples, and selecting corresponding MOS devices for corresponding failure mechanism evaluation tests for multiple failure mechanisms, which include hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect, and electromigration effect.

[0046] With the above, this embodiment uses the method of selecting MOS devices fabricated on the same process line and in the same batch as test samples, and selecting specific MOS devices for different failure mechanisms, realizing the reduction of test errors caused by process differences. Devices on the same process line and batch have high consistency in process parameters, which can ensure that more comparable and accurate data can be obtained when conducting failure mechanism evaluation tests such as hot carrier effect and negative bias temperature instability effect. Selecting suitable MOS devices for different failure mechanisms can give full play to the device characteristics, making the test results more truly reflect the impact of failure mechanisms on the reliability of automotive chips, thereby improving the accuracy and reliability of the entire reliability evaluation method and laying a solid foundation for subsequent accurate calculation and evaluation.

[0047] Specifically, the method of selecting corresponding MOS devices for multiple failure mechanisms is as follows:

[0048] Select NMOS devices for the hot carrier effect;

[0049] Select PMOS devices for the negative bias temperature instability effect;

[0050] Select large-area MOS capacitors for the time-dependent dielectric breakdown effect;

[0051] Select interconnect metal lines for the electromigration effect.

[0052] Through the above, this embodiment realizes the improvement of the pertinence and effectiveness of the test. Different types of MOS devices have uniqueness in their responses to specific failure mechanisms. NMOS devices are more sensitive to the hot carrier effect and can capture the performance changes of the chip under this effect more accurately; PMOS devices show more obvious characteristics for the negative bias temperature instability effect. Through this targeted selection, when conducting a single failure mechanism evaluation test, more accurate acceleration factors and failure rates can be obtained, so that in the subsequent process of constructing a matrix and calculating the comprehensive failure rate, the impacts of various failure mechanisms on the reliability of automotive chips can be evaluated more precisely, and the credibility of the evaluation results can be improved.

[0053] Specifically, in S1, a single acceleration factor and the corresponding single failure rate are obtained, specifically:

[0054] For the hot carrier effect, a hot carrier effect acceleration factor and the corresponding hot carrier effect failure rate are obtained;

[0055] For the negative bias temperature instability effect, a negative bias temperature instability effect acceleration factor and the corresponding negative bias temperature instability effect failure rate are obtained;

[0056] For the time-dependent dielectric breakdown effect, a time-dependent dielectric breakdown effect acceleration factor and the corresponding time-dependent dielectric breakdown effect failure rate are obtained;

[0057] For the electromigration effect, an electromigration effect acceleration factor and the corresponding electromigration effect failure rate are obtained.

[0058] Through the above, this embodiment realizes the refined analysis of each failure mechanism by obtaining the corresponding acceleration factors and failure rates for each failure mechanism respectively. By obtaining the corresponding data one by one for the hot carrier effect, negative bias temperature instability effect, etc., the influence degree of each failure mechanism on the failure process of automotive chips under different stress conditions can be clearly grasped. These detailed data provide an accurate basis for the subsequent construction of the acceleration factor matrix and failure rate matrix, enabling a more accurate reflection of the roles of various failure mechanisms in the comprehensive situation when calculating the proportion coefficient matrix and comprehensive failure rate, avoiding errors caused by general analysis, and thus improving the accuracy of the reliability evaluation of automotive chips, providing strong support for the optimized design and quality control of automotive chips.

[0059] Specifically, in S2, a corresponding acceleration factor matrix and failure rate matrix are constructed based on the acceleration factors and failure rates, specifically:

[0060] An acceleration factor matrix is constructed based on the hot carrier effect acceleration factor, negative bias temperature instability effect acceleration factor, time-dependent dielectric breakdown effect acceleration factor, and electromigration effect acceleration factor , where is the number corresponding to different stress conditions. Based on this acceleration factor matrix , the corresponding failure rate matrix is obtained . This failure rate matrix is obtained based on the single failure mechanism evaluation test of the first batch.

[0061] Through the above, this embodiment constructs an acceleration factor matrix by using the acceleration factors of multiple failure mechanisms such as hot carrier effect and negative bias temperature instability effect, and obtains the failure rate matrix based on this, realizing the systematic integration of complex failure mechanism data. The acceleration factor matrix is numbered by different stress conditions, and the acceleration factors of multiple failure mechanisms are arranged in an orderly manner, clearly showing the acceleration situation of each failure mechanism under different stresses; the failure rate matrix corresponds to it, reflecting the corresponding failure rate data. This matrix form is convenient for subsequent calculation of the proportion coefficient matrix and the comprehensive failure rate, making the entire evaluation process more organized and standardized, improving the evaluation efficiency and accuracy, and providing an efficient data processing and analysis method for the reliability evaluation of automotive chips.

[0062] Specifically, in S2, the calculated proportion coefficient matrix is based on the acceleration factor matrix and the failure rate matrix to calculate the proportion coefficient matrix . This calculation is specifically .

[0063] Through the above, this embodiment uses the method of multiplying the inverse matrix of the acceleration factor matrix by the failure rate matrix to calculate the proportion coefficient matrix, realizing the quantification of the proportion relationship of each failure mechanism in the comprehensive failure rate, so as to accurately obtain the proportion coefficients of the hot carrier effect, negative bias temperature instability effect, etc. in the comprehensive failure rate. These coefficients are key parameters for evaluating the reliability of automotive chips. They clarify the contribution degree of each failure mechanism to the overall reliability of the chip, helping engineers understand the main reasons for chip failure, and thus taking targeted measures in the chip design, manufacturing and application processes to improve the reliability and stability of the chip.

[0064] Specifically, in S3, the multi-mechanism competition failure matrix constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix is , where is the number of the new batch.

[0065] In a simple example, the construction of the multi-mechanism competition failure matrix in this embodiment is as follows:

[0066] Under the experimental conditions of voltage and temperature , the acceleration factor of the HCI effect obtained is , and the acceleration factor of the NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is , the failure rate is ;

[0067] Under the experimental conditions of voltage and temperature , the acceleration factor of the HCI effect obtained is , the acceleration factor of the NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is , the failure rate is ;

[0068] Under the experimental conditions of voltage and temperature , the acceleration factor of the HCI effect obtained is , the acceleration factor of the NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is , the failure rate is ;

[0069] Under the experimental conditions of voltage and temperature , the acceleration factor of the HCI effect obtained is , the acceleration factor of the NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is , the failure rate is ;

[0070] Then the obtained acceleration factor matrix is , and the failure rate matrix is . Based on this, using to calculate and obtain . Based on this to conduct the reliability assessment of a new batch.

[0071] Through the above, this embodiment constructs a multi-mechanism competition failure matrix by using the acceleration factor matrix and the proportion coefficient matrix, and realizes the rapid calculation of the failure rate of the new batch of chips in the way of distinguishing by the new batch number. When evaluating a new batch of chips, only need to obtain the new acceleration factor, combine with the existing proportion coefficient matrix, and the new failure rate matrix can be quickly obtained through the multi-mechanism competition failure matrix. This method greatly reduces the workload of the new batch test, shortens the evaluation cycle, and at the same time ensures the accuracy and consistency of the evaluation results. It not only improves the evaluation efficiency but also reduces the cost, enabling the reliability assessment of automotive chips to better meet the needs of mass production and rapid iteration.

[0072] Specifically, the calculation method of the comprehensive failure rate is as follows:

[0073] Obtain the preset hot carrier effect weight factor , negative bias temperature instability effect weight factor , time-dependent dielectric breakdown effect weight factor and electromigration effect weight factor , and obtain the corresponding hot carrier effect failure rate based on the failure rate matrix , negative bias temperature instability effect failure rate , time-dependent dielectric breakdown effect failure rate and electromigration effect failure rate , and the calculation of the comprehensive failure rate is:

[0074]

[0075] wherein, is the calculated comprehensive failure rate.

[0076] It should be noted that the method for obtaining the weight factor in this embodiment can be but is not limited to being obtained through chip foundry companies or international relevant literature, and in this embodiment, .

[0077] In a simple example, the hot carrier effect weight factor obtained through chip foundry companies or international relevant literature is 0.3, the negative bias temperature instability effect weight factor is 0.25, the time-dependent dielectric breakdown effect weight factor is 0.2, and the electromigration effect weight factor is 0.25;

[0078] After the first batch of single failure mechanism evaluation tests, the hot carrier effect failure rate is 100, the negative bias temperature instability effect failure rate is 80, the time-dependent dielectric breakdown effect failure rate is 60, and the electromigration effect failure rate is 70;

[0079] According to the comprehensive failure rate calculation formula, substituting the data, the comprehensive failure rate can be obtained as 79.5.

[0080] Furthermore, in a simple example, when the obtained comprehensive failure rate is 79.5, the calculated average lifetime is 1.26*10 7 .

[0081] Through the above, this embodiment realizes the comprehensive consideration of the influence of multiple failure mechanisms on the reliability of automotive chips by obtaining preset weight factors and calculating the comprehensive failure rate in combination with the failure rate matrix. Different failure mechanisms such as the hot carrier effect and the negative bias temperature instability effect have different degrees of influence on the chip reliability. By presetting weight factors, it is possible to reasonably allocate the weights of each failure mechanism in the calculation of the comprehensive failure rate according to the actual situation. After multiplying the failure rates of each failure mechanism by the corresponding weight factors and then accumulating them, the obtained comprehensive failure rate can more truly reflect the reliability status of automotive chips under the combined action of multiple failure mechanisms, providing a more accurate quantitative index for the quality assessment and reliability prediction of automotive chips.

[0082] Specifically, in S3, the average lifetime is calculated using the average lifetime formula, and the average lifetime formula is:

[0083]

[0084] Where, is the calculated average lifetime.

[0085] Through the above, this embodiment realizes the conversion of the comprehensive failure rate into an intuitive life index of automotive chips using the average lifetime formula. The average lifetime is an important parameter for measuring the reliability of automotive chips. Through this formula, the comprehensive failure rate obtained from complex calculations can be converted into an easy-to-understand time value. This enables engineers, manufacturers, and users to more intuitively understand the expected service life of automotive chips, providing an important reference basis in aspects such as chip selection, product design, and maintenance plan formulation, helping to improve the reliability and stability of automotive products and reduce the usage risk.

[0086] Specifically, when calculating the failure rate of a new batch, each failure mechanism conducts tests on far fewer test samples than the first batch, obtains new acceleration factors under different stress conditions, obtains the corresponding new failure rate matrix based on the multi-mechanism competition failure matrix, and calculates the new comprehensive failure rate and new average lifetime based on this new failure rate matrix.

[0087] Through the above, this embodiment realizes the efficient and low-cost evaluation of the reliability of new batch automotive chips by conducting a small number of tests on each failure mechanism of the new batch to obtain new acceleration factors, then calculating the new failure rate matrix based on the multi-mechanism competition failure matrix, and further calculating the new comprehensive failure rate and average lifetime. Compared with the large-scale tests of the first batch, only a small number of tests are required for the new batch, greatly reducing the test cost and time. At the same time, based on the existing matrix and calculation method, the accuracy and coherence of the evaluation are ensured. This method enables the rapid reliability evaluation of different batch products during the production process of automotive chips, timely discovery and solution of potential problems, and improvement of production efficiency and product quality.

[0088] In summary, the reliability evaluation method of automotive chips based on multi-failure mechanism competing failures in this embodiment uses the preset IEC standard and the same failure criterion to conduct the first batch of single-failure mechanism evaluation tests, obtains individual acceleration factors and failure rates, then constructs a matrix and calculates the correlation coefficient, realizing the competition relationship of multiple failure mechanisms that comprehensively consider hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect, and electromigration effect. Through scientific and reasonable test and calculation methods, it can accurately evaluate the comprehensive failure rate and average life time of automotive chips in complex stress environments, effectively overcoming the limitations of traditional separate evaluation of each failure mechanism, providing a more accurate and practical working condition-compliant evaluation means for the reliability evaluation of automotive chips, meeting the stringent requirements of the automotive industry for chip reliability evaluation, and improving the reliability guarantee level of automotive chips in the design, production, and application links.

[0089] In the embodiments provided in this application, it should be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, code, or any appropriate combination thereof. For hardware implementation, the processor can be implemented in one or more of the following units: application specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, or other electronic units designed to implement the functions described herein, or a combination thereof. For software implementation, part or all of the processes of the embodiments can be completed by a computer program instructing the relevant hardware. When implemented, the above program can be stored in a computer-readable storage medium or transmitted as one or more instructions or codes on a computer-readable storage medium. The computer-readable storage medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available medium that can be accessed by a computer. The computer-readable storage medium can include, but is not limited to, RAM, ROM, EEPROM, CD-ROM, or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer.

[0090] Finally, it should be noted that the above are only preferred embodiments of the present application and are not used to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A reliability evaluation method for automotive chips based on competing failures with multiple failure mechanisms, characterized in that, It includes the following steps: S1: Based on the preset IEC standard and the corresponding same failure criterion, conduct the first batch of single failure mechanism evaluation tests under different stress conditions to obtain a single acceleration factor and the corresponding single failure rate. The acceleration factor is used to characterize the influence of stress on the failure process; S2: Based on the acceleration factor and the failure rate, construct the corresponding acceleration factor matrix and failure rate matrix, and calculate the obtained proportion coefficient matrix. The proportion coefficient matrix is used to characterize the proportion relationship of multiple failure mechanisms in the comprehensive failure rate, and the proportion coefficient matrix is also used to calculate the comprehensive failure rate of automotive chips; S3: Based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix, construct a multi-mechanism competing failure matrix. The multi-mechanism competing failure matrix is used to calculate the comprehensive failure rate and the corresponding mean life time to evaluate its reliability; In S2, based on the acceleration factor and the failure rate, construct the corresponding acceleration factor matrix and failure rate matrix, specifically: Construct an acceleration factor matrix based on the hot carrier effect acceleration factor, the negative bias temperature instability effect acceleration factor, the time-dependent dielectric breakdown effect acceleration factor, and the electromigration effect acceleration factor , where is the number corresponding to different stress conditions. Based on this acceleration factor matrix , the corresponding failure rate matrix is obtained. This failure rate matrix is obtained based on the first batch of single failure mechanism evaluation tests; In S2, the calculated proportion coefficient matrix is based on the acceleration factor matrix and the failure rate matrix to calculate the proportion coefficient matrix , and the specific calculation is ; In S3, the multi-mechanism competing failure matrix constructed based on the acceleration factor matrix, the proportion coefficient matrix, and the failure rate matrix is , where is the number of the new batch; The calculation method of the comprehensive failure rate is: Obtain the preset hot carrier effect weight factor , negative bias temperature instability effect weight factor , time-dependent dielectric breakdown effect weight factor and electromigration effect weight factor , and obtain the corresponding hot carrier effect failure rate based on the failure rate matrix , negative bias temperature instability effect failure rate , time-dependent dielectric breakdown effect failure rate and electromigration effect failure rate , and the calculation of the comprehensive failure rate is as follows: ； Among them, is the calculated comprehensive failure rate.

2. The reliability evaluation method of automotive chips based on multi-failure mechanism competing failures according to claim 1, characterized in that In S1, the first batch of single failure mechanism evaluation tests include selecting MOS devices with the same process line and the same batch of wafer runs as test samples, and selecting corresponding MOS devices for corresponding failure mechanism evaluation tests for multiple failure mechanisms. The multiple failure mechanisms include hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect, and electromigration effect.

3. The reliability evaluation method of automotive chips based on multi-failure mechanism competing failures according to claim 2, characterized in that The method of selecting corresponding MOS devices for multiple failure mechanisms is: Select NMOS devices for the hot carrier effect; Select PMOS devices for the negative bias temperature instability effect; Select large-area MOS capacitors for the time-dependent dielectric breakdown effect; Select interconnect metal lines for the electromigration effect.

4. The reliability evaluation method of automotive chips based on multi-failure mechanism competing failures according to claim 2, wherein, In S1, obtain a single acceleration factor and the corresponding single failure rate, specifically: Obtain the hot carrier effect acceleration factor and the corresponding hot carrier effect failure rate for the hot carrier effect; Obtain the negative bias temperature instability effect acceleration factor and the corresponding negative bias temperature instability effect failure rate for the negative bias temperature instability effect; Obtain the time-dependent dielectric breakdown effect acceleration factor and the corresponding time-dependent dielectric breakdown effect failure rate for the time-dependent dielectric breakdown effect; Obtain the electromigration effect acceleration factor and the corresponding electromigration effect failure rate for the electromigration effect.

5. The reliability evaluation method for automotive chips based on competing failures with multiple failure mechanisms according to claim 1, characterized in that In S3, the calculation of the mean life time is carried out using the mean life time formula. The mean life time formula is: ； Among them, is the calculated average lifetime.

6. The reliability evaluation method for automotive chips based on multi-failure mechanism competing failures according to claim 1, characterized in that When calculating the failure rate of a new batch, each failure mechanism conducts tests on test samples that are much smaller than those of the first batch, obtains new acceleration factors under different stress conditions, obtains the corresponding new failure rate matrix based on the multi-mechanism competing failure matrix, and calculates the new comprehensive failure rate and the new mean life time based on this new failure rate matrix.

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