Digital circuit for realizing large-scale SVD (Singular Value Decomposition) calculation

Abstract

The invention discloses a digital circuit design for realizing large-scale SVD (Singular Value Decomposition). The design consists of three parts, namely a matrix column storage module, a parallel selection module and a Jacobian rotation calculation module. According to the scheme, the Hisenberg matrix calculation is performed on the original input matrix, so that the occupation of input storage resources is reduced. Then, through a multi-path selection (mux) mode, SVD rotation solving is carried out on eight matrix column vectors at the same time in each processing period, and the parallel calculation degree of SVD calculation is improved; and finally, point product calculation of a large-scale matrix column vector is realized through a PE processing module, and solving of a rotation angle and right singular value calculation in SVD decomposition are completed. According to the method, multiple SVD sub-algorithms are achieved through the same digital circuit design framework, the repeated utilization rate of hardware resources is increased, the SVD calculation parallelism degree is improved in a multi-path selection mode, and excessive access of a circuit to a storage unit is reduced.

Description

Technical Field

[0001] The present invention relates to the fields of digital signal processing and digital circuit design, and in particular to a digital circuit structure for implementing singular value decomposition (SVD), aiming to improve data processing efficiency and computing speed through parallel computing technology. Background Art

[0002] At present, Singular Value Decomposition (SVD) is an important matrix decomposition method with wide applications in modern science and engineering. SVD decomposes a matrix into the product of three matrices, which can effectively reveal the characteristic structure of the original matrix. It is widely used in signal noise reduction and feature extraction, image compression, data analysis and machine learning.

[0003] Singular value decomposition (SVD) decomposes a matrix A into the product of three matrices. The column vectors of the U matrix are the eigenvectors of the column space of A, V T The row vectors of the matrix are the eigenvectors of the row space of A, and the ∑ diagonal matrix contains the eigenvalues ​​of the A matrix:

[0004] A=U∑V T

[0005] Hardware acceleration methods for SVD can generally be divided into two types: implementation based on Jacobi rotation and hardware implementation based on HouseHolder transformation. The former gradually approaches the diagonalization result in an iterative manner, and each rotation only affects the local matrix elements, which can ensure high numerical stability. However, this step-by-step iterative method requires multiple rotations to reach convergence. This results in a large number of iterations and a long calculation time when processing large-scale matrices; the latter Householder transformation can greatly reduce the number of calculation steps, but it requires the storage of multiple reflection matrices and intermediate results, which will take up a lot of storage resources in the case of large-scale matrices, and parallel calculations are difficult.

[0006] In summary, the problems of implementing SVD decomposition of high-dimensional matrices with digital circuits include:

[0007] 1. Limited storage resources. For large input matrices (such as high-dimensional large-scale data), the required digital circuit resources increase significantly, which may lead to insufficient hardware storage resources. Or the hardware storage resources are insufficient because of excessive storage of intermediate matrices.

[0008] 2. Limited computing resources. The decomposition of large-scale matrices requires a large number of computing units, such as multipliers and adders. Although modern hardware has highly parallel computing capabilities, due to limited logic unit resources, when the matrix size increases, the computing units used for parallel processing on the hardware may not be sufficient, limiting the degree of computational parallelism and affecting overall performance.

[0009] 3. Many iterations SVD usually requires multiple iterations to converge, which makes the calculation process very time-consuming and places high demands on the efficiency of the hardware.

[0010] Technical problems solved by the invention and purpose of the invention

[0011] Singular value decomposition has a wide range of applications in modern science and engineering. A large number of matrix operations involved in SVD (such as matrix multiplication, rotation, iteration, etc.) can be performed in parallel in digital circuits, greatly reducing the calculation time. Although there are many advantages to implementing SVD through digital circuits, hardware implementation also faces challenges in insufficient storage / computing resources and long iterative calculation time in SVD operations on high-dimensional matrices.

[0012] In order to achieve high-dimensional large-scale data SVD decomposition under limited hardware storage and computing resources, the present invention proposes a digital circuit architecture design scheme for resource reuse. The architecture can be implemented under limited computing and storage resources:

[0013] (1) Reduce the dimension of the intermediate matrix, thereby reducing the use of hardware storage resources. By implementing the Heisenberg matrix multiplication calculation, the dimension of the original input matrix can be reduced. The Heisenberg matrix multiplication calculation H = A of the dimension m × n matrix A T A, get the Heisenberg matrix of n×n dimension, and then perform subsequent calculations. The same circuit framework is used to complete the Heisenberg matrix calculation and SVD decomposition. The former reduces the SVD input from m×n dimension size to n×n dimension size (m>>n), greatly reducing the storage resources required for the matrix.

[0014] (2) Improve the parallelism of SVD decomposition calculations. By designing a MUX multiplexer with configurable input data flow direction, different combinations of column vectors are selected to achieve matrix parallelism. The flow direction of the data flow is processed through a simple MUX module. In this design, the MUX multiplexer is composed of 4 smaller groups of 2input, 2output muxes, and a single data flow channel is used internally to achieve the above effect, greatly reducing the complexity of the design. JacobiRotation calculation;

[0015] (3) Improve the reuse of SVD decomposition computing resources. By designing a parameter-configurable vector processing module PE (processing element), it is possible to achieve: (3.1) dot product calculations of column vectors of different lengths; (3.2) Jacobi Rotation angle calculations of matrices; (3.3) SVD right singular value calculations; BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following briefly introduces the drawings required to be used in the embodiment of the present invention.

[0017] Figure 1 1 is a circuit overall framework diagram of the SVD parallel computing circuit provided in an embodiment of the present invention;

[0018] Figure 2 It is a framework diagram of a PE computing unit of an SVD parallel computing circuit provided in an embodiment of the present invention; DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] The implementation plan is divided into three steps:

[0021] Step 1: Implement Heisenberg matrix calculation;

[0022] Step 2: parallel SVD decomposition through a multiplexer MUX;

[0023] First is the calculation implementation of the Heisenberg matrix:

[0024] (1.1) Configuration Configure the Config register module in the framework to control the framework to perform Heisenberg matrix multiplication calculations, the purpose of which is to reduce the matrix dimensions that need to be processed. Perform Heisenberg matrix multiplication calculation H=A on the A matrix of dimension m×n T A, get the Heisenberg matrix of n×n dimension;

[0025] (1.2) The PC-side algorithm determines which 8 column vectors of the original matrix should be transferred to the 8 vector storage RAMs in the PL side through the AXI-FULL protocol. The storage size of each RAM is 4KB (which can be adjusted according to the vector size).

[0026] (1.3) The column vector elements stored in the Matrix Vector RAM are transmitted through the RX transmission module based on the data stream transmission method of the AXI-STREAM protocol, which divides the column vector into multiple sub-column vectors.

[0027] (2) The multiplexer module MUX receives the parameter configuration information from the control register Config and determines the flow direction of the column vector, and determines to which PE vector processing module the column vector should be sent for subsequent processing.

[0028] (3) The PE module is a vector processing module. It receives the Heisenberg matrix calculation from Config. This module only starts Figure 2 The column vector calculation submodule in the Matrix Rotation module implements the dot multiplication calculation of the column vector through a multiplication accumulation tree.

[0029] After configuring the circuit to complete the calculation of the Heisenberg matrix, we get a Heisenberg matrix of n×n dimensions. The subsequent SVD decomposition uses this Heisenberg matrix as input:

[0030] (1.1) First, configure the Config register module in the framework to control the framework to perform parallel SVD, the purpose of which is to reduce the matrix dimension to be processed. Perform Heisenberg matrix multiplication H=A on the m×n matrix A. T A, get the Heisenberg matrix of n×n dimension;

[0031] (1.2) The PS end selects The selected column vector is transferred to the matrix RAM of PL through the axi-full protocol. The column vector elements in are transmitted through the RX transmission module based on the data stream transmission method of the AXI-STREAM protocol, and the column vector is divided into multiple sub-column vectors for transmission.

[0032] (2.1) MUX receives the configuration information from the Config module and selects the data flow. The data flow is as follows: in the first calculation, (1, 2) (3, 4) (5, 6) (7, 8) are selected and transmitted to the PE module for calculation. In the second calculation, (1, 4) (2, 5) (4, 7) (5, 8) vector groups are selected for calculation. This process is repeated to complete the calculation of all vector combinations in pairs.

[0033] (2.2) In general designs, the MUX multiplexer module will use an 8-input, 8-output design. However, for an input data stream with a data width of 16*8bit, this will make the internal combinational logic of the multiplexer complex and difficult to design. In this design, the MUX multiplexer is composed of 4 smaller groups of 2input, 2output muxes, and a single data stream channel is used internally to achieve the above effect, greatly reducing the complexity of the design.

[0034] (3) Starting the PE module is a SinCos Rotation angle calculation submodule and a Matrix Rotation matrix rotation calculation submodule in a vector processing module, which realizes the solution of the diagonal matrix elements and the solution of the right singular value matrix.

Claims

1. A SVD parallel computing design method for digital circuit implementation, characterized in that The following three parts: (P1): The specific structure of the parallel computing multiplexer MUX; (P2): Specific design structure of vector processing module PE; (P3): Specific configuration method of vector processing module PE; 2. The specific structure of the parallel computing multiplexer MUX according to claim 1 is characterized in that: 2.1 Contents of P1: The MUX multiplexer is composed of 4 groups of 2-input, 2-output minMUX, and uses a single data stream channel internally to achieve Combinations: (1, 2) (3, 4) (5, 6) (7, 8), (1, 4) (2, 5) (4, 7) (5, 8) and other combinations. 2.2 Contents of P2: The PE vector processor module consists of two sub-modules: SinCos Calculation and Matrix Rotation. The former consists of a sub-vector multiplication accumulation tree module and a trigonometric function calculation module, which can realize the dot multiplication calculation of multi-element vectors and the solution of vector rotation angles. The latter consists of a rotation parameter storage table, a vector multiplication module, and a read-hot code generation module. This module obtains the rotation angle in the rotation parameter table to construct a 2×2 rotation matrix, obtains the matrix eigenvalues ​​by calculating with the original vector matrix, and obtains the right singular value matrix by calculating with the one-hot code matrix. 2.3 Contents of P3: In the Heisenberg matrix calculation, the PE module only turns on the vector calculation submodule to perform dot multiplication on the two column vectors selected by the MUX. The result is then sent to the PE2M module and then transmitted back to the memory through the TX module in the form of a data stream. In the SVD calculation, the PE module needs to perform vector calculation on the two column vectors A and B selected by the MUX, and then obtain the rotation angle matrix H through the trigonometric function calculation module. Then, two one-hot code vectors C and D are generated according to the vector selection method. The matrix eigenvalue is obtained by recalculating the original two vectors and H, and the generated one-hot code vector and H are calculated to obtain the right singular matrix.

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